List of Nets Files that Include

          a Connection to FPGA U1
     ---------------------------------


                                 Original Rev.  20-Oct-2015
                                  Current Rev.  23-Nov-2016 GTH->MGT


This file is simply a list of all of the nets files in this
directory that include a connection to the Hub's UltraScale
FPGA component U1.


            File Name                           Notes
   ----------------------------------     --------------------

   bank_0_and_bank_65_config_mem_nets     Configuration Nets


   combined_data_distribution_nets        GTH/GTY

   hub_all_other_mgt_nets                 GTH/GTY

   mgt_fanout_channel_nets                GTH/GTY

      Note: The FPGA pinout in  mgt_fanout_channel_nets  comes
            from  /Build_GTH_Readout_Nets/gth_fanout_to_hub_fpga_nets



   hardware_address_to_rod_nets           3V3 and 1V8 Banks

   led_lemo_translator_driver_nets        1V8 Bank

   minipod_pow_gnd_ctrl_no_conn_nets      3V3 Bank

   rod_to_from_hub_spare_nets             1V8 Bank

   switch_chips_all_other_nets            3V3 Bank

   ultra_fpga_power_ground_nets           All power and ground

   ultra_fpga_to_phys_chips_nets          1V8 Bank

   ultra_no_connect_pins_nets             Package no conn pins

   power_supply_all_other_nets            System Monitor Reference and Power/Gnd
                                          ROD Power Control - 1V8 Bank

   jtag_and_associated_nets               JTAG
                                          ROD_Preset_B - 1V8 Bank

   clock_generation_nets                  25 MHz Logic Clock Input - Ethernet Clock
                                          48 MHz Reference Clk Input from Other Hub
                                          48 MHz Reference Clk Output to 48 MHz PLL
                                          48 MHz Logic Clock Input
                                         320 MHz Logic Clock Input
                                         320 MHz MGT Reference Clock Inputs  8x
                                          Lock Detect Inputs from 48 & 320 MHz PLLs

   i2C_sensor_bus_nets                    Sensor I2C Bus  to FPGA SysMon
                                          Sensor I2C Bus  to FPGA I2C Master Port
                                          Enables to the 3x I2C Buffer/Translators