# # # Bank 0 and Bank 65 Configuration Memory Nets # # This is the Key In Net List file for the Hub Module # ------------------------------------------------------ # # # Original Rev. 21-Sept-2015 # Most Recent Rev. 14-Dec-2015 # # # This file holds the Nets involved with Bank 0 of the # UltraScale FPGA and the associated Configuration # Flash Memory. # # Note: This file contains fixed pin connections to the # UltraScale FPGA. # # # Configuration Flash Memory # ---------------------------- # # This is a single 2 Gbit Micron MT28GU01GAAA1EGC-0SIT # device in a 64 pin 1mm BGA package that is mounted on # the top side of the PCB. # # # Power Ground and ByPass Caps for the Configuration Memory # NET 'BULK_1V8' U25-A4 U25-A6 U25-D5 NET 'BULK_1V8' U25-D6 U25-G4 U25-H3 NET 'GROUND' U25-B2 U25-H2 U25-H4 U25-H6 NET 'BULK_1V8' C1801-1 C1802-1 C1803-1 NET 'GROUND' C1801-2 C1802-2 C1803-2 NET 'BULK_1V8' C1804-1 C1805-1 C1806-1 C1807-1 NET 'GROUND' C1804-2 C1805-2 C1806-2 C1807-2 # # Data Lines between the Configuration Flash Memory and BANKS 0 & 65 # NET 'FLASH_D00' U25-F2 U1-AM14 # D00_MOSI_0 NET 'FLASH_D01' U25-E2 U1-AK14 # D01_DIN_0 NET 'FLASH_D02' U25-G3 U1-AF16 # D02_0 NET 'FLASH_D03' U25-E4 U1-AH14 # D03_0 NET 'FLASH_D04' U25-E5 U1-BE19 # IO_L22P_T3U_N6_DBC_AD0P_D04_65 NET 'FLASH_D05' U25-G5 U1-BF19 # IO_L22N_T3U_N7_DBC_AD0N_D05_65 NET 'FLASH_D06' U25-G6 U1-BD18 # IO_L21P_T3L_N4_AD8P_D06_65 NET 'FLASH_D07' U25-H7 U1-BE18 # IO_L21N_T3L_N5_AD8N_D07_65 NET 'FLASH_D08' U25-E1 U1-BE17 # IO_L20P_T3L_N2_AD1P_D08_65 NET 'FLASH_D09' U25-E3 U1-BF17 # IO_L20N_T3L_N3_AD1N_D09_65 NET 'FLASH_D10' U25-F3 U1-BD17 # IO_L19P_T3L_N0_DBC_AD9P_D10_65 NET 'FLASH_D11' U25-F4 U1-BD16 # IO_L19N_T3L_N1_DBC_AD9N_D11_65 NET 'FLASH_D12' U25-F5 U1-BC20 # IO_L18P_T2U_N10_AD2P_D12_65 NET 'FLASH_D13' U25-H5 U1-BC19 # IO_L18N_T2U_N11_AD2N_D13_65 NET 'FLASH_D14' U25-G7 U1-BA19 # IO_L17P_T2U_N8_AD10P_D14_65 NET 'FLASH_D15' U25-E7 U1-BB19 # IO_L17N_T2U_N9_AD10N_D15_65 # # Address Lines from BANK 65 to the Configuration Flash Memory # NET 'FLASH_A00' U25-A1 U1-BA21 # IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 NET 'FLASH_A01' U25-B1 U1-BB21 # IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 NET 'FLASH_A02' U25-C1 U1-BB18 # IO_L15P_T2L_N4_AD11P_A02_D18_65 NET 'FLASH_A03' U25-D1 U1-BC18 # IO_L15N_T2L_N5_AD11N_A03_D19_65 NET 'FLASH_A04' U25-D2 U1-AY20 # IO_L14P_T2L_N2_GC_A04_D20_65 NET 'FLASH_A05' U25-A2 U1-BA20 # IO_L14N_T2L_N3_GC_A05_D21_65 NET 'FLASH_A06' U25-C2 U1-AY19 # IO_L13P_T2L_N0_GC_QBC_A06_D22_65 NET 'FLASH_A07' U25-A3 U1-AY18 # IO_L13N_T2L_N1_GC_QBC_A07_D23_65 NET 'FLASH_A08' U25-B3 U1-AV20 # IO_L12P_T1U_N10_GC_A08_D24_65 NET 'FLASH_A09' U25-C3 U1-AW20 # IO_L12N_T1U_N11_GC_A09_D25_65 NET 'FLASH_A10' U25-D3 U1-AW18 # IO_L11P_T1U_N8_GC_A10_D26_65 NET 'FLASH_A11' U25-C4 U1-AW17 # IO_L11N_T1U_N9_GC_A11_D27_65 NET 'FLASH_A12' U25-A5 U1-AV21 # IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 NET 'FLASH_A13' U25-B5 U1-AW21 # IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 NET 'FLASH_A14' U25-C5 U1-AU18 # IO_L9P_T1L_N4_AD12P_A14_D30_65 NET 'FLASH_A15' U25-D7 U1-AV18 # IO_L9N_T1L_N5_AD12N_A15_D31_65 NET 'FLASH_A16' U25-D8 U1-AT21 # IO_L8P_T1L_N2_AD5P_A16_65 NET 'FLASH_A17' U25-A7 U1-AU21 # IO_L8N_T1L_N3_AD5N_A17_65 NET 'FLASH_A18' U25-B7 U1-AT19 # IO_L7P_T1L_N0_QBC_AD13P_A18_65 NET 'FLASH_A19' U25-C7 U1-AU19 # IO_L7N_T1L_N1_QBC_AD13N_A19_65 NET 'FLASH_A20' U25-C8 U1-AR20 # IO_L6P_T0U_N10_AD6P_A20_65 NET 'FLASH_A21' U25-A8 U1-AT20 # IO_L6N_T0U_N11_AD6N_A21_65 NET 'FLASH_A22' U25-G1 U1-AR19 # IO_L5P_T0U_N8_AD14P_A22_65 NET 'FLASH_A23' U25-H8 U1-AR18 # IO_L5N_T0U_N9_AD14N_A23_65 NET 'FLASH_A24' U25-B6 U1-AM21 # IO_L4P_T0U_N6_DBC_AD7P_A24_65 NET 'FLASH_A25' U25-B8 U1-AN21 # IO_L4N_T0U_N7_DBC_AD7N_A25_65 # # Control Signals between Configuration Flash Memory and BANKS 0 & 65 # # These signals include pull-up resistors as described in # the Xilinx Configuration User's Guide. # NET 'FLASH_RESET_B' U25-D4 U1-P14 R1802-1 # INIT_B_0 NET 'FLASH_CHIP_ENB_B' U25-B4 U1-AF14 R1804-1 # RDWR_FCS_B_0 NET 'FLASH_WRITE_ENB_B' U25-G8 U1-AP20 R1805-1 # IO_L2N_T0L_N3_FWE_FCS2_B_65 NET 'FLASH_OUTPUT_ENB_B' U25-F8 U1-AN20 R1806-1 # IO_L2P_T0L_N2_FOE_B_65 NET 'BULK_1V8' R1802-2 R1804-2 R1805-2 R1806-2 # Pull-Up Resistors to 1V8 # # Other Control Signals to the Configuration Flash Memory # NET 'FLASH_WRITE_PROTECT_B' U25-C6 R1807-1 # Flash Mem Write Protect Pin NET 'GROUND' U25-F6 # Flash Address Valid Bar NET 'GROUND' U25-E6 # Flash Clock for Sync Operation NET 'BULK_1V8' R1807-2 # Pull-Up Resistor to 1V8 # # ALL Other Bank 0 Configuration Signals Except for JTAG # ----------- # NET 'PROGRAM_B' U1-AE14 R1801-1 # PROGRAM_B_0 NET 'BULK_1V8' R1801-2 # Pull-Up Resistor to 1V8 NET 'FPGA_Config_DONE' U1-AC14 R1803-1 # DONE_0 NET 'BULK_1V8' R1803-2 # Pull-Up Resistor to 1V8 NET 'CONFIG_M0' R1811-1 R1812-1 U1-Y14 # M0_0 Configuration Mode NET 'CONFIG_M1' R1813-1 R1814-1 U1-V14 # M1_0 NET 'CONFIG_M2' R1815-1 R1816-1 U1-T14 # M2_0 NET 'BULK_1V8' R1811-2 R1813-2 R1815-2 # Pull-Up on Config Mode NET 'GROUND' R1812-2 R1814-2 R1816-2 # Pull-Down on Config Mode # We want 100 Ohm: 0,1,0 NET 'POR_OVERRIDE' U1-AB14 R1821-1 R1822-1 # POR_OVERRIDE Power On Reset Delay NET 'FPGA_CORE' R1821-2 # Shorter POR Delay Note: Zero Ohm NET 'GROUND' R1822-2 # Standard POR Delay to FPGA_CORE # We want Standard or to GND NET 'CFGBVS' U1-M14 R1823-1 R1824-1 # CFGBVS_0 Configuration Bank Voltage NET 'BULK_1V8' R1823-2 # Hi for 2V5 or 3V3 Note: Zero Ohm NET 'GROUND' R1824-2 # GND for VCCO_0 1V8 to VCCO_0 # We need GND. or to GND NET 'PUDC_B' U1-K14 R1825-1 R1826-1 # PUDC_B_0 Pull-Ups During Configuration NET 'BULK_1V8' R1825-2 # Hi --> Pull-Ups OFF Note: 100 Ohm NET 'GROUND' R1826-2 # GND -> Pull_Ups ON to VCCO_0 # We want weak pull-up or to GND # turned ON --> Gnd NET 'VBATT' U1-AN13 R1827-1 # VBATT Jumper to GND if not used NET 'GROUND' R1827-2 # GND We want VBATT Zero Ohm to GND NET 'NO_CONN_FPGA_BANK_0_CCLK' U1-AB16 # CCLK_0 We want No Connection # # No Connection pins on the Configuration Flash Memory # NET 'NO_CONN_FLASH_MEM_U25_F7' U25-F7 # WAIT NET 'NO_CONN_FLASH_MEM_U25_E8' U25-E8 # RFU NET 'NO_CONN_FLASH_MEM_U25_F1' U25-F1 # RFU NET 'NO_CONN_FLASH_MEM_U25_G2' U25-G2 # RFU NET 'NO_CONN_FLASH_MEM_U25_H1' U25-H1 # RFU # # No Connection pins on Bank 65 of the UltraScale FPGA # NET 'NO_CONN_FPGA_BANK_65_BE20' U1-BE20 # IO_L24P_T3U_N10_EMCCLK_65 NET 'NO_CONN_FPGA_BANK_65_BF20' U1-BF20 # IO_L24N_T3U_N11_DOUT_CSO_B_65 NET 'NO_CONN_FPGA_BANK_65_BD20' U1-BD20 # IO_T3U_N12_PERSTN0_65 NET 'NO_CONN_FPGA_BANK_65_BC21' U1-BC21 # IO_T2U_N12_CSI_ADV_B_65 NET 'NO_CONN_FPGA_BANK_65_AV19' U1-AV19 # IO_T1U_N12_PERSTN1_65 NET 'NO_CONN_FPGA_BANK_65_AM19' U1-AM19 # IO_L3P_T0L_N4_AD15P_A26_65 NET 'NO_CONN_FPGA_BANK_65_AN19' U1-AN19 # IO_L3N_T0L_N5_AD15N_A27_65 NET 'NO_CONN_FPGA_BANK_65_AN18' U1-AN18 # IO_L1P_T0L_N0_DBC_RS0_65 NET 'NO_CONN_FPGA_BANK_65_AP18' U1-AP18 # IO_L1N_T0L_N1_DBC_RS1_65 # # Note: There are 4 additional pins in Bank 65 but # they are not defined as No_Conn pins above. # # - 2 of these are pins: U1-AP21 # IO_T0U_N12_VRP_A28_65 # U1-AM18 # VREF_65 # # These pins are used for DCI calibration resistor and # the VREF pin is pulled down if it is not used as a # source of external reference to the differential # input buffer for single-ended signals. # # These two pins are defined in the nets file: # # ultra_dci_vref_mgt_calib_resistors_nets # # # # - 2 of these are pins: U1-BE16 # IO_L23P_T3U_N8_I2C_SCLK_65 # U1-BF16 # IO_L23N_T3U_N9_I2C_SDA_65 # # These pins are the I2C Bus port to the FPGA's SysMon. # These two pins are defined in the nets file: # # i2C_sensor_bus_nets # # # # This completes the definition of all pins # in Select I/O Bank 65.