#
#            Clock Generation  Nets File
#          -------------------------------
#
#
#                                      Original Rev.  22-May-2015
#                                       Current Rev.  17-Jan-2017
#
#
#
#   This file holds the nets involved in the Generation
#   of the various Clock signals on the Hub Module.
#
#   The Clock signals include:
#
#     -  25.00 MHz  crystal clock for the Ethernet Phys chips,
#                   for the Ethernet Switch chips, and send to
#                   the FPGA as a Logic Clock.
#
#     -  40.08 MHz  LHC locked clock that is sent to the
#                   12 FEX cards, to the Other Hub, to
#                   the ROD mezzanine, to This Hub's FPGA
#                   as a Logic Clock, and sent as a reference
#                   to the high frequency clock generators
#                   for the two MTG reference clocks.
#
#     - 320.64 MHz  LHC locked clock that is sent to the
#                   FPGA as both a Transceiver Reference
#                   Clock and as a Logic Clock.
#
#
#   This file also includes the distribution networks
#   for most of these clock signals.   Typically the
#   section of the distribution network that is included
#   in this file includes just the fanout chip, and any
#   AC Coupling Capacitors or Termination Resistors.
#   The actual net list connection to the pin on the
#   load  (e.g. a Reference Clock Input on the FPGA)
#   is called out in a separate file.
#
#


#
#   The  25.000 MHz Crystal Clock and its Distribution Network
#  ------------------------------------------------------------
#
#
#   The components included in the 25 MHz crystal clock and
#   its distribution network are the following:
#
#      U38  25 MHz Crystal Oscillator  ConWin 813 25 MHz
#
#      U39  6 way Single Ended CMOS Fanout  TI  CDCLVC1106
#
#      L391 and C391 are power filters to make the ECLK_3V3 rail.
# 
#      C392:C395  ByPass Capacitors on the ECLK_3V3 rail
#
#      R2019, R2119, R2219  the series terminators to the Switch Chips
#
#      R1916, R1966     are the series terminators to the Phys Chips
#
#      R501              is the series terminator to the Hub FPGA
#                        25 MHz Global Clock Input
#
#   This file defines the Global Clock input pin on the Hub's
#   FPGA  for the 25 MHz Ethernet Clock signal.   Note that
#   this is a 3V3 pin in a 3V3 Select I/O Bank.
#


#
#   Start with the 3V3  Ethernet Clock  power noise/isolation filters.
#

NET  'BULK_3V3'   L391-1   C391-1
NET  'ECLK_3V3'   L391-2
NET  'GROUND'              C391-2


#
#    The 25.000 MHz Crystal Oscillator
#

NET  'ECLK_3V3'             U38-4    U38-1   C392-1   C393-1
NET  'GROUND'               U38-2            C392-2   C393-2


#
#    The 25.000 Mhz Fanout
#

NET  'ECLK_3V3'             U39-5   U39-8   U39-12   C394-1   C395-1
NET  'GROUND'               U39-4   U39-7   U39-10   C394-2   C395-2

NET  'ECLK_3V3'             U39-2


NET  'CLOCK_25_MHz_to_Fanout'          U38-3    U39-1


NET  'CLOCK_for_Phys_U21'              U39-14   R1916-1
NET  'CLOCK_for_Phys_U22'              U39-13   R1966-1

NET  'Phys_U22_X1'                              R1916-2
NET  'Phys_U21_X1'                              R1966-2


NET  'CLOCK_25_MHz_Series_Term_FPGA'   U39-3    R501-1
NET  'CLOCK_25_MHz_FPGA'               R501-2   U1-AT15    # IO_L14P_T2L_N2_GC_84


NET  'CLOCK_for_SW_C'                  U39-6    R2219-2
NET  'CLOCK_for_SW_B'                  U39-11   R2119-2
NET  'CLOCK_for_SW_A'                  U39-9    R2019-2

NET  'SW_C_CLOCK'                               R2219-1
NET  'SW_B_CLOCK'                               R2119-1
NET  'SW_A_CLOCK'                               R2019-1







#
#   The  40.08 MHz Clock Generation and Distribution Feed:
#  --------------------------------------------------------
#
#
#   The components in the 40.08 MHz LHC Locked Clock include:
#
#      U501  an LVDS Receiver that receives the 40.08 MHz reference
#            from the Hub FPGA and delivers a back terminated singled
#            ended 3.3 Volt CMOS level copy of this reference to
#            the 40.08 MHz PLL.
#
#
#      U502  a 40.0787 MHz PLL with a Quartz Crystal VCXO.
#            The Reference for this PLL comes from either:
#
#             - the recovered clock from the optical TTC signal that
#               is received by the Hub and processed by its FPGA   or
#
#             - it comes from the Other Hub and is received on
#               backplane connector J23 pins C4, D4.
#
#            Note that the MUX to select which reference clock is
#            sent to the 40.08 MHz PLL is in the Hub's FPGA itself.
#
#
#      U503  a 4 way LVDS Clock Fanout chip that runs on 2V5
#            power.  The output nets from this Fanout Chip are
#            in a separate nets file named, "clock_40.08_MHz_distribution_nets".
#            This chips feeds the 40.08 MHz LHC Locked clock
#            to the following consumers located on this Hub Module:
#
#             - to the ROD on This Hub
#             - to the 320.64 MHz  PLL
#             - to a Global Logic Clock input on This Hub's FPGA
#             - to the U504  16 way fanout chip for the 40.08 MHz Clk
#
#
#      U504  a 16 way LVDS Clock Fanout chip that runs on 2V5
#            power.  The output nets from this Fanout Chip are
#            in a separate nets file named, "clock_40.08_MHz_distribution_nets".
#            This chips feeds the 40.08 MHz LHC Locked clock
#            over the backplane to the following consumers:
#
#             - to the 12 FEX cards
#             - to the Other Hub
#
#            Note that the U504 outputs can be put into a still
#            driven but quiescent state under the control of this
#            Hub Module's FPGA.
#


#
#   Start with the 2V5 and 3V3  Clock  power noise/isolation filters.
#
#     The BULK_2V5 feed to L352 will arrive via discrete wire
#     to the wire terminal component  WTERM52  and  uses
#     Power Via Arrays  to get down to the CLK_2V5 Area Fill.
#

NET  'BULK_3V3'  L351-1   C351-1   PVA11_CLK-1   PVA12_CLK-1   PVA13_CLK-1
NET  'CLK_3V3'   L351-2            PVA14_CLK-1   PVA15_CLK-1   PVA16_CLK-1
NET  'GROUND'             C351-2


NET  'BULK_2V5_Wire'  L352-1   C352-1       WTERM52-1    PVA4_CLK-1
NET  'CLK_2V5'        L352-2   PVA1_CLK-1   PVA2_CLK-1   PVA3_CLK-1
NET  'GROUND'                  C352-2



#
#   Nets that receiver the 40.08 MHz Reference Clock
#   from the Other Hub.   Note that these runs from
#   the Backplane to the FPGA involve a Diff Pair Via.
#

NET  'Ref_40.08_MHz_from_Other_Hub_Dir'   J23-C4   U1-H23   # IO_L14P_T2L_N2_GC_71
NET  'Ref_40.08_MHz_from_Other_Hub_Cmp'   J23-D4   U1-G23   # IO_L14N_T2L_N3_GC_71

NET  'Ref_40.08_MHz_from_Other_Hub_Dir'   DPV701-2          # Differential Pair
NET  'Ref_40.08_MHz_from_Other_Hub_Cmp'   DPV701-3          # Via in run from the
NET  'GROUND'                         DPV701-1   DPV701-4   # Backplane to the FPGA



#
#   Nets that connect the 40.08 MHz LVDS Reference from the
#   Hub FPGA,  through a LVDS Receiver,  and then to the
#   40.08 MHz PLL's reference input.
#

NET  'Ref_40.08_MHz_from_FPGA_to_Rec_Dir'   U501-3   U1-AV31   # IO_L7P_T1L_N0_QBC_AD13P_68
NET  'Ref_40.08_MHz_from_FPGA_to_Rec_Cmp'   U501-4   U1-AW31   # IO_L7N_T1L_N1_QBC_AD13N_68

NET  'Ref_40.08_MHz_from_Rec_to_Term'       U501-5   R1607-1

NET  'Ref_40.08_MHz_from_Term_to_PLL'      R1607-2   U502-1




#
#   Nets that connect the  U502  40.08 MHz  PLL  Output
#   to  Input 0  of the  U503  4x LVDS fanout chip,
#   i.e. the  FIRST  40.08 MHz Fanout.
#
#   Note that I'm using Back Termination in the form of
#   R1613 and R1614  to make the conversion from an LVPECL
#   swing to the LVDS swing that is required at the input
#   to this Fanout chip, the  FIRST  40.08 MHz Fanout.
#
#   INPUT #0  is being used on this Fanout.
#

NET  'PLL_40.08_MHz_Output_Dir'      U502-6    R1613-1
NET  'PLL_40.08_MHz_Output_Cmp'      U502-7    R1614-1

NET  'PLL_40.08_MHz_R_to_C_Dir'     R1613-2    C1651-1
NET  'PLL_40.08_MHz_R_to_C_Cmp'     R1614-2    C1652-1

NET  'Fanout_40.08_MHz_Input_Dir'   C1651-2    U503-6     R1615-1
NET  'Fanout_40.08_MHz_Input_Cmp'   C1652-2    U503-7     R1616-1

NET  'First_Fanout_CMM_Ref'       U503-8    R1615-2    R1616-2   C374-1

NET  'GROUND'                                                    C374-2



#
#   Nets that tell the  FIRST  40.08 MHz  Fanout chip
#   to use its Input 0.  Grounding the  U503  In_Sel
#   pin #2  selects its Input 0.
#

NET  'Select_Input_First_40_Fanout'    U503-2   R1611-1
NET  'GROUND'                                   R1611-2



#
#   Nets to Tie Off the IN #1 input on the  FIRST  40.08 MHz Fanout.
#

NET  'First_Fanout_CMM_Ref'       U503-4

NET  'Tie_Off_1st_40_FO_IN1_P'    U503-3   R1620-1

NET  'GROUND'                              R1620-2







#
#   Input to the  SECOND  40.08 MHz  Fanout Chip
#   comes from the  FIRST  40.08 MHz  Fanout Chip.
#
#   Show here the termination / DC operating point resistors
#   and the AC Coupling Capacitors.
#
#   This is  Input 0  on the Second 40.08 MHz Fanout  U504
#
#   The input signal source for this Second Fanout is given
#   in the nets file:   clock_40.08_MHz_distribution_nets
#
#   Note that I'm using the #1 Common Mode Voltage Reference
#   even though I'm using Input #0.  This is for routing.
#
#   Note that the Input #1 is not left floating.  One side
#   is tied to the Common Mode Reference Voltage Source and
#   the other side is tied to Ground through a 1k Ohm resistor.
#

NET  'Drive_to_Second_40.08_MHz_Fanout_Dir'   C1655-1
NET  'Drive_to_Second_40.08_MHz_Fanout_Cmp'   C1656-1

NET  'Second_Fanout_40.08_MHz_Input_Dir'      C1655-2   U504-10    R1601-1
NET  'Second_Fanout_40.08_MHz_Input_Cmp'      C1656-2   U504-9     R1602-1

NET  'Second_Fanout_CMM_Ref'         U504-5   C372-1    R1601-2    R1602-2

NET  'GROUND'                                 C372-2


#   Tie off  Input #1  of the SECOND 40.08 MHz Fanout

NET  'Second_Fanout_CMM_Ref'         U504-4

NET  'Tie_Off_2nd_40_FO_IN1_P'       U504-3   R1619-1

NET  'GROUND'                                 R1619-2





#
#   Nets that tell the  SECOND  40.08 MHz  Fanout chip
#   to follow the instructions and select either its
#   Input 0   or   not to select either input.
#
#   When the U504  In_Sel pin #2 is  Low  then this
#   fanout chip  selects its Input 0.
#
#   When the U504  In_Sel pin #2 is in the Middle of
#   its 2V5 Vcc range  then it selects  neither  of
#   its inputs and thus its output is static.
#
#   The control information to the U504 fanout chip
#   In_Sel pin comes from this Hub Module's FPGA
#   (and Open Drain pin in a 1V8 I/O Bank)  and
#   a pair of 5k Ohm resistors between BULK_2V5
#   and Ground/
#

NET  'Select_Input_Second_40_Fanout'    U504-2   R1617-1   R1618-1
NET  'CLK_2V5'                                   R1617-2
NET  'GROUND'                                              R1618-2

NET  'Select_Input_Second_40_Fanout'    U1-A26   # IO_L24N_T3U_N11_70





#
#   Nets to connect the 40.08 MHz PLL Lock Detect
#   signal  from the PLL  to the Hub's FPGA.
#

NET  'PLL_40.08_MHz_Lock_Detect_Output'    U502-10   R1609-1

NET  'PLL_40.08_MHz_Lock_Detect_to_FPGA'   R1609-2   U1-B27   # IO_L22P_T3U_N6_DBC_AD0P_70





#
#   Power and Ground:  to the  U501  65LVDT2  Receiver for the FPGA Ref Signal
#   in the             to the  U502  40.08 MHz PLL
#   40.08 MHz          to The  U503   4x Fanout of the 40.08 MHz clock
#   section            to The  U504  16x Fanout of the 40.08 MHz clock
#


NET  'CLK_3V3'   U501-1   C370-1
NET  'GROUND'    U501-2   C370-2


NET  'CLK_3V3'   U502-9
NET  'GROUND'    U502-2   U502-8

NET  'CLK_3V3'   C353-1   C354-1   C355-1
NET  'GROUND'    C353-2   C354-2   C355-2


NET  'CLK_2V5'   U503-5
NET  'GROUND'    U503-1   U503-17   U503-18   U503-19   U503-20

NET  'CLK_2V5'   C375-1   C376-1   C377-1
NET  'GROUND'    C375-2   C376-2   C377-2


NET  'CLK_2V5'   U504-6    U504-7    U504-13   U504-24   U504-37   U504-48
NET  'GROUND'    U504-1    U504-12
NET  'GROUND'    U504-49   U504-50   U504-51   U504-52
NET  'GROUND'    U504-53   U504-54   U504-55   U504-56
NET  'GROUND'    U504-57   U504-58   U504-59   U504-60
NET  'GROUND'    U504-61   U504-62   U504-63   U504-64

NET  'CLK_2V5'   C359-1   C360-1   C361-1   C362-1   C363-1   C364-1
NET  'GROUND'    C359-2   C360-2   C361-2   C362-2   C363-2   C364-2



#
#   No_Connect pins on the 40.08 MHz PLL and its Fanout Chips:
#

NET  'No_Conn_40_PLL_pin_3'        U502-3
NET  'No_Conn_40_PLL_pin_4'        U502-4
NET  'No_Conn_40_PLL_pin_5'        U502-5

NET  'No_Conn_2nd_40_FO_Ref_8'     U504-8
NET  'No_Conn_2nd_40_FO_11'        U504-11









#
#   The  320.64 MHz Clock Generation:
#  -----------------------------------
#
#
#   The components in the 320.64 MHz LHC Locked Clock include:
#
#      U505  an LVDS Receiver that receives the 40.08 MHz reference
#            from the 40.08 MHz PLL distribution and delivers a back
#            terminated singled ended 2.5 Volt CMOS level copy of
#            this reference to the 320.64 MHz PLL.
#
#      U506  a 320.6296 MHz PLL with a Quartz Crystal VCXO.
#            The Reference for this PLL comes from the distribution
#            fanout for the 40.08 MHz PLL.
#
#      U507  a 10 way LVPECL Clock Fanout chip that runs on 2V5
#            power.  The output nets from this Fanout Chip are
#            at the end of this file.
#            This chips feeds the 320.64 MHz LHC Locked clock to:
#
#             - up to 8 Reference Clock inputs to the
#               MGT Transceivers on the Hub FPGA
#
#             - to a Global Logic Clock input on the Hub's FPGA
#


#
#   Nets that connect the 40.08 MHz LVDS Reference from the
#   Fanout of the 40.08 MHz PLL,  through a LVDS Receiver,
#   and then to the 320.64 MHz PLL's reference input.
#

NET  'Clk_40.08_MHz_Ref_to_HF_PLL_Dir'   U505-3
NET  'Clk_40.08_MHz_Ref_to_HF_PLL_Cmp'   U505-4

NET  'HF_PLL_Ref_from_Rec_to_Term'       U505-5    R1608-1

NET  'HF_PLL_Ref_from_Term_to_PLL'       R1608-2   U506-1



#
#   Nets that connect the  U506  320.64 MHz PLL  Output
#   to Input 0  of the  U507  10x LVPECL Fanout chip:
#

NET  'PLL_320.64_MHz_Output_Dir'      U506-6    C1654-1    # Polarity Flip
NET  'PLL_320.64_MHz_Output_Cmp'      U506-7    C1653-1    # for Routing

NET  'Fanout_320.64_MHz_Input_Dir'    C1653-2   U507-3    R1603-1
NET  'Fanout_320.64_MHz_Input_Cmp'    C1654-2   U507-4    R1604-1

NET  'Fanout_320.64_MHz_CMM_Ref'                R1603-2   R1604-2   C373-1

NET  'GROUND'                      R1606-1                       C373-2
NET  'CLK_2V5'                               R1605-1
NET  'Fanout_320.64_MHz_CMM_Ref'      R1606-2   R1605-2


#
#   Nets to connect the 320.64 MHz PLL Lock Detect
#   signal  from the PLL  to the Hub's FPGA.
#

NET  'PLL_320.64_MHz_Lock_Detect_Output'    U506-10   R1610-1

NET  'PLL_320.64_MHz_Lock_Detect_to_FPGA'   R1610-2   U1-B26   # IO_L24P_T3U_N10_70



#
#   Nets that tell the 320.64 MHz Fanout chip to use its Input 0.
#   Grounding  U507  In_Sel  pin #2   selects its Input 0.
#

NET  'Select_Input_320_Fanout'    U507-2   R1612-1
NET  'GROUND'                              R1612-2



#
#   Power and Ground:  to the  U505  65LVDT2  Receiver for the 40.08 Fanout Ref Signal
#                      to the  U506  320.64 MHz PLL
#                      to The  U507  10x Fanout of the 320.64 MHz clock
#

NET  'CLK_3V3'   U505-1   C371-1
NET  'GROUND'    U505-2   C371-2


NET  'CLK_3V3'   U506-9
NET  'GROUND'    U506-2   U506-8

NET  'CLK_3V3'   C356-1   C357-1   C358-1
NET  'GROUND'    C356-2   C357-2   C358-2


NET  'CLK_2V5'   U507-1    U507-9    U507-16   U507-25   U507-32
NET  'GROUND'    U507-8    U507-33   U507-34   U507-35   U507-36
NET  'GROUND'    U507-37   U507-38   U507-39   U507-40   U507-41

NET  'CLK_2V5'   C365-1   C366-1   C367-1   C368-1   C369-1
NET  'GROUND'    C365-2   C366-2   C367-2   C368-2   C369-2




#
#   No_Connect pins on the 320.64 MHz PLL and its Fanout Chip:
#

NET  'No_Conn_320_PLL_pin_3'        U506-3
NET  'No_Conn_320_PLL_pin_4'        U506-4
NET  'No_Conn_320_PLL_pin_5'        U506-5

NET  'No_Conn_320_Fanout_Ref_5'     U507-5
NET  'No_Conn_320_Fanout_Clk_1'     U507-6
NET  'No_Conn_320_Fanout_Clk_1_b'   U507-7
NET  'No_Conn_320_Fanout_Q0_B'      U507-30
NET  'No_Conn_320_Fanout_Q0'        U507-31






#
#   The  320.64 MHz Clock Distribution:
#  -------------------------------------
#
#
#   This section of the netlist contains the outputs
#   from the  U507  LVPECL Fanout chip for the
#   320.64 MHz clock signal.
#
#   8 of these AC Coupled LVPECL 320.64 MHz Fanout signals
#   are Reference Clocks to the MGT Transceivers.
#
#   1 of these AC Coupled LVPECL 320.64 MHz Fanout signals
#   is a Logic Clock to a Global Clock Input in HP IO Bank 71.
#   Note that in this case the LVPECL clock signal is back
#   terminated with R1651/R1652 so that it can correctly drive
#   the LVDS input in HP IO Bank 71.
#

NET  'MHz_320.64_Fan_Ouput_1_Dir'   U507-29   C1631-2   R1631-2
NET  'MHz_320.64_Fan_Ouput_1_Cmp'   U507-28   C1632-2   R1632-2

NET  'MHz_320.64_COPY_0_DIR'                  C1631-1   U1-AE36   # MGTREFCLK0P_125
NET  'MHz_320.64_COPY_0_CMP'                  C1632-1   U1-AE37   # MGTREFCLK0N_125

NET  'GROUND'                    R1631-1   R1632-1


NET  'MHz_320.64_Fan_Ouput_2_Dir'   U507-27   C1633-2   R1633-2
NET  'MHz_320.64_Fan_Ouput_2_Cmp'   U507-26   C1634-2   R1634-2

NET  'MHz_320.64_COPY_1_DIR'                  C1633-1   U1-R36    # MGTREFCLK0P_130
NET  'MHz_320.64_COPY_1_CMP'                  C1634-1   U1-R37    # MGTREFCLK0N_130

NET  'GROUND'                    R1633-1   R1634-1


NET  'MHz_320.64_Fan_Ouput_3_Dir'   U507-24   C1635-2   R1635-2
NET  'MHz_320.64_Fan_Ouput_3_Cmp'   U507-23   C1636-2   R1636-2

NET  'MHz_320.64_COPY_2_DIR'                  C1635-1   U1-K34    # MGTREFCLK1P_132
NET  'MHz_320.64_COPY_2_CMP'                  C1636-1   U1-K35    # MGTREFCLK1N_132

NET  'GROUND'                    R1635-1   R1636-1


NET  'MHz_320.64_Fan_Ouput_4_Dir'   U507-22   C1637-2   R1637-2
NET  'MHz_320.64_Fan_Ouput_4_Cmp'   U507-21   C1638-2   R1638-2

NET  'MHz_320.64_COPY_3_DIR'                  C1637-1   U1-Y34    # MGTREFCLK1P_127
NET  'MHz_320.64_COPY_3_CMP'                  C1638-1   U1-Y35    # MGTREFCLK1N_127

NET  'GROUND'                    R1637-1   R1638-1





NET  'MHz_320.64_Fan_Ouput_5_Dir'   U507-20   C1639-2   R1639-2
NET  'MHz_320.64_Fan_Ouput_5_Cmp'   U507-19   C1640-2   R1640-2

NET  'Logic_Clk_320.64_MHz_Back_Term_Dir'     C1639-1   R1651-1
NET  'Logic_Clk_320.64_MHz_Back_Term_Cmp'     C1640-1   R1652-1

NET  'Logic_Clk_320.64_MHz_to_FPGA_Dir'       R1651-2   U1-K22   # IO_L11P_T1U_N8_GC_71
NET  'Logic_Clk_320.64_MHz_to_FPGA_Cmp'       R1652-2   U1-J22   # IO_L11N_T1U_N9_GC_71

NET  'GROUND'                    R1639-1   R1640-1





NET  'MHz_320.64_Fan_Ouput_6_Dir'   U507-18   C1641-2   R1641-2
NET  'MHz_320.64_Fan_Ouput_6_Cmp'   U507-17   C1642-2   R1642-2

NET  'MHz_320.64_COPY_6_DIR'                  C1641-1   U1-Y13    # MGTREFCLK1P_227
NET  'MHz_320.64_COPY_6_CMP'                  C1642-1   U1-Y12    # MGTREFCLK1N_227

NET  'GROUND'                    R1641-1   R1642-1


NET  'MHz_320.64_Fan_Ouput_7_Dir'   U507-15   C1643-2   R1643-2
NET  'MHz_320.64_Fan_Ouput_7_Cmp'   U507-14   C1644-2   R1644-2

NET  'MHz_320.64_COPY_7_DIR'                  C1643-1   U1-K13    # MGTREFCLK1P_232
NET  'MHz_320.64_COPY_7_CMP'                  C1644-1   U1-K12    # MGTREFCLK1N_232

NET  'GROUND'                    R1643-1   R1644-1


NET  'MHz_320.64_Fan_Ouput_8_Dir'   U507-13   C1645-2   R1645-2
NET  'MHz_320.64_Fan_Ouput_8_Cmp'   U507-12   C1646-2   R1646-2

NET  'MHz_320.64_COPY_8_DIR'                  C1645-1   U1-R11    # MGTREFCLK0P_230
NET  'MHz_320.64_COPY_8_CMP'                  C1646-1   U1-R10    # MGTREFCLK0N_230

NET  'GROUND'                    R1645-1   R1646-1


NET  'MHz_320.64_Fan_Ouput_9_Dir'   U507-11   C1647-2   R1647-2
NET  'MHz_320.64_Fan_Ouput_9_Cmp'   U507-10   C1648-2   R1648-2

NET  'MHz_320.64_COPY_9_DIR'                  C1647-1   U1-AE11   # MGTREFCLK0P_225
NET  'MHz_320.64_COPY_9_CMP'                  C1648-1   U1-AE10   # MGTREFCLK0N_225

NET  'GROUND'                    R1647-1   R1648-1