# # # Overall Hardware Address to Hub FPGA and to ROD Nets # # Key In Net List file for the Hub Module # --------------------------------------------------------- # # # # Original Rev. 29-Sep-2015 # Most Recent Rev. 13-Oct-2016 # # # This file holds the nets that make up the Overall # Hardware Address and route it to both the Hub's FPGA # and via the S2 MegArray Connector up to the ROD. # # The Overall Hardware Address is put together from two # parts: the Slot Backplane Hardware Address that also goes # to the IPMC and the Shelf Address that the IPMC obtains # from the Shelf Manager. # # # The Slot Backplane Hardware Address is provided by a set # of open or grounded pins in the Zone 1 connector. These # lines are pulled up to 3V3 by R1551 : R1558 and filtered # by C1551 : C1558. The resulting 8 signals run into the # IPMC as described in the nets file, # # ipmc_hw_adrs_handle_switch_ipmb_nets # # In this file these 8 signals will also provide the Slot # Backplane Hardware Address to a 3V3 HR Bank 94 in the # Hub FPGA through a 470 Ohm resistor array, R1571. # # NET 'HW_ADRS_0' R1571-16 NET 'HW_ADRS_1' R1571-15 NET 'HW_ADRS_2' R1571-14 NET 'HW_ADRS_3' R1571-13 NET 'HW_ADRS_4' R1571-12 NET 'HW_ADRS_5' R1571-11 NET 'HW_ADRS_6' R1571-10 NET 'HW_ADRS_7' R1571-9 NET 'ISO_SLOT_HW_ADRS_0' R1571-1 U1-AT12 # IO_L15N_T2L_N5_AD11N_84 NET 'ISO_SLOT_HW_ADRS_1' R1571-2 U1-AT11 # IO_T2U_N12_84 NET 'ISO_SLOT_HW_ADRS_2' R1571-3 U1-AU12 # IO_L17P_T2U_N8_AD10P_84 NET 'ISO_SLOT_HW_ADRS_3' R1571-4 U1-AU11 # IO_L17N_T2U_N9_AD10N_84 NET 'ISO_SLOT_HW_ADRS_4' R1571-5 U1-AV11 # IO_L7P_T1L_N0_QBC_AD13P_94 NET 'ISO_SLOT_HW_ADRS_5' R1571-6 U1-AW12 # IO_L12N_T1U_N11_GC_94 NET 'ISO_SLOT_HW_ADRS_6' R1571-7 U1-AW11 # IO_L7N_T1L_N1_QBC_AD13N_94 NET 'ISO_SLOT_HW_ADRS_7' R1571-8 U1-AY12 # IO_L9P_T1L_N4_AD12P_94 # # The next step in making the Overall Hardware Address # is to learn what Shelf this Hub is in. The IPMC learns # what Shelf it is in from the Shelf Manager. The IPMC # then sets this Shelf Address in 8 of its GPIO pins. # From these IPMC GPIO pins the Shelf Address is carried # to a 3V3 HR Bank 94 pins on the Hub's FPGA. # # Notes: One of these 8 signals from the IPMC to the # Hub's FPGA should indicate that it has been # successful in getting the Shelf Address from # the Shelf Manager, i.e. it indicates that the # state of the other 7 pins is valid. # # At this time I do not know which 8 pins on the # IPMC will be used for this function. So for # now I'm just going to pick the 8 GPIO pins that # are easy to route for this function. # NET 'SHELF_ADRS_0_TO_RES_NET' IPMC-197 R1572-1 # USR_2 INOUT IOIF User IO pin 2 NET 'SHELF_ADRS_1_TO_RES_NET' IPMC-198 R1572-2 # USR_3 INOUT IOIF User IO pin 3 NET 'SHELF_ADRS_2_TO_RES_NET' IPMC-200 R1572-3 # USR_6 INOUT IOIF User IO pin 6 NET 'SHELF_ADRS_3_TO_RES_NET' IPMC-201 R1572-4 # USR_7 INOUT IOIF User IO pin 7 NET 'SHELF_ADRS_4_TO_RES_NET' IPMC-203 R1572-5 # USR_10 INOUT IOIF User IO pin 10 NET 'SHELF_ADRS_5_TO_RES_NET' IPMC-204 R1572-6 # USR_11 INOUT IOIF User IO pin 11 NET 'SHELF_ADRS_6_TO_RES_NET' IPMC-206 R1572-7 # USR_14 INOUT IOIF User IO pin 14 NET 'SHELF_ADRS_7_TO_RES_NET' IPMC-207 R1572-8 # USR_15 INOUT IOIF User IO pin 15 NET 'SHELF_ADRS_0_TO_FPGA' R1572-16 U1-BB15 # IO_L3N_T0L_N5_AD15N_94 NET 'SHELF_ADRS_1_TO_FPGA' R1572-15 U1-BB14 # IO_L5N_T0U_N9_AD14N_94 NET 'SHELF_ADRS_2_TO_FPGA' R1572-14 U1-BA14 # IO_L5P_T0U_N8_AD14P_94 NET 'SHELF_ADRS_3_TO_FPGA' R1572-13 U1-BB13 # IO_L8P_T1L_N2_AD5P_94 NET 'SHELF_ADRS_4_TO_FPGA' R1572-12 U1-BB12 # IO_L8N_T1L_N3_AD5N_94 NET 'SHELF_ADRS_5_TO_FPGA' R1572-11 U1-BB11 # IO_L10N_T1U_N7_QBC_AD4N_94 NET 'SHELF_ADRS_6_TO_FPGA' R1572-10 U1-BA12 # IO_L9N_T1L_N5_AD12N_94 NET 'SHELF_ADRS_7_TO_FPGA' R1572-9 U1-BA11 # IO_L10P_T1U_N6_QBC_AD4P_94 # # Inside the Hub FPGA the Slot Backplane Hardware Address # Is combined with the Shelf Address to make up the # Overall Hardware Address. # # Then the Overall Hardware Address must be conveyed to # the ROD over 8 pins in the S2 Meg Array Connector. # # The Overall Hardware Address comes out of the Hub FPGA # on pins in the 1V8 HP Banks 67 and 68. # NET 'OVERALL_ADRS_0_TO_RES_NET' R1573-1 U1-BF25 # IO_L23N_T3U_N9_67 NET 'OVERALL_ADRS_1_TO_RES_NET' R1573-2 U1-BE25 # IO_L23P_T3U_N8_67 NET 'OVERALL_ADRS_2_TO_RES_NET' R1573-3 U1-BF26 # IO_L20P_T3L_N2_AD1P_67 NET 'OVERALL_ADRS_3_TO_RES_NET' R1573-4 U1-BE27 # IO_L22P_T3U_N6_DBC_AD0P_67 NET 'OVERALL_ADRS_4_TO_RES_NET' R1573-5 U1-BF27 # IO_L20N_T3L_N3_AD1N_67 NET 'OVERALL_ADRS_5_TO_RES_NET' R1573-6 U1-BE28 # IO_L22N_T3U_N7_DBC_AD0N_67 NET 'OVERALL_ADRS_6_TO_RES_NET' R1573-7 U1-BE29 # IO_L22P_T3U_N6_DBC_AD0P_68 NET 'OVERALL_ADRS_7_TO_RES_NET' R1573-8 U1-BE30 # IO_L20N_T3L_N3_AD1N_68 NET 'LOCATION_ADRS_1_TO_ROD' R1573-16 Meg_S2-H1 NET 'LOCATION_ADRS_2_TO_ROD' R1573-15 Meg_S2-J1 NET 'LOCATION_ADRS_3_TO_ROD' R1573-14 Meg_S2-H2 NET 'LOCATION_ADRS_4_TO_ROD' R1573-13 Meg_S2-J2 NET 'LOCATION_ADRS_5_TO_ROD' R1573-12 Meg_S2-H3 NET 'LOCATION_ADRS_6_TO_ROD' R1573-11 Meg_S2-J3 NET 'LOCATION_ADRS_7_TO_ROD' R1573-10 Meg_S2-H4 NET 'LOCATION_ADRS_8_TO_ROD' R1573-9 Meg_S2-J4