# # This is a Hub-Module Key In Net List file # # All Other MGT Nets # ----------------------------------------------- # # # Original Rev. 3-May-2015 # Most Recent Rev. 3-Jan-2017 # # # This file holds all of the sundry MGT nets. # The MGT nets presented here are: # # 1 GTY input for the Other Hub's TCC + Readout Control # Combined Data # # 1 GTH input for This Hub's ROD Readout Control Data # # # 4 GTH>Y inputs from the Receiver MiniPOD (its first 4 channels) # # 8 GTH outputs to the Transmitter MiniPOD # # # 2 GTH outputs to send This Hub's readout data # to the ROD on This Hub # # 2 GTY outputs to send This Hub's readout data # to the Other Hub # # 34 Differential Via Pair connections to the DVP # components around the FPGA that handle the # FEX MGT Receiver Input Data # # # Note that all 80 of the MGT input are connected and most # are used during the normal operation of the Hub Module. # A total of 6 MGT inputs are defined in this nets file. # 74 MGT inputs are defined in other nets files. # # # 12 MGT outputs are defined in this nets file. # # 14 MGT outputs for Combined Data signals are # defined in another nets file. # # Note that there are 54 MGT outputs that are not # connected on the Hub Module. # # # Note the other nets files that describe the MGT # connections to the Hub's FPGA are: # # mgt_fanout_to_hub_fpga_nets in the /Net_Lists/Build_MGT_Readout_Nets/ # # combined_data_distribution_nets # # # # GTY Input of the Other Hub's TTC + Readout Control # Combined Data # # This data from the Other Hub arrives on # Fabric Interface Rx1 Channel 1 # J23 Row 4 G & H # # and goes into GTY Input Rx1 Bank 124 # NET 'Combined_Data_from_OTHER_Hub_Dir' J23-G4 U1-AP44 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Rx1 Bank 124 NET 'Combined_Data_from_OTHER_Hub_Cmp' J23-H4 U1-AP43 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- # # MGT Input of This Hub's ROD Readout Control Data # # This data from This Hub's ROD arrives on # MegArray Connector 2, RRC pins, H39 & J39 # # and goes into GTH Input Rx3 Bank 224 # # The ROD does provide the DC Blocking Caps for this link. # NET 'This_RODs_Readout_Ctrl_to_GTH_Input_Dir' Meg_S2-H39 U1-AM3 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx3 Bank 224 NET 'This_RODs_Readout_Ctrl_to_GTH_Input_Cmp' Meg_S2-J39 U1-AM4 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- # # MGT Inputs from the Receiver MiniPOD for 4 fibers # # This optical data arrives to Receiver MiniPOD 2 # on Fibers: 2, 4, 6, 8 # # and goes into GTH Input Rx0 Rx1 Rx2 of Bank 224 # and GTY Input Rx0 of Bank 124 # # DC Blocking Caps are required: C2301 through C2308 # # Note that 3 of these 4 circuits include Differential Pair # Via components at the breakout from the FPGA. # These are DPV101, DPV135, and DPV136. # # Note that all 4 circuit include a Differential Pair Via # component at the connection to the MiniPOD adjacent # to the DC Blocking Capacitors. These are DPVs 137:140. # NET 'Rec_MP_Fiber_8_Data_Dir' Rec_MP2-A8 C2401-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 8 NET 'Rec_MP_Fiber_8_Data_Cmp' Rec_MP2-B8 C2402-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_8_to_FPGA_Dir' C2401-2 U1-AR45 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Rx0 Bank 124 NET 'Rec_MP_Fiber_8_to_FPGA_Cmp' C2402-2 U1-AR46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_8_to_FPGA_Dir' DPV101-3 DPV140-2 NET 'Rec_MP_Fiber_8_to_FPGA_Cmp' DPV101-2 DPV140-3 NET 'GROUND' DPV101-1 DPV140-1 NET 'GROUND' DPV141-1 NET 'Rec_MP_Fiber_6_Data_Dir' Rec_MP2-A6 C2404-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 6 NET 'Rec_MP_Fiber_6_Data_Cmp' Rec_MP2-B6 C2403-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_6_to_FPGA_Dir' C2404-2 U1-AR2 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx0 Bank 224 NET 'Rec_MP_Fiber_6_to_FPGA_Cmp' C2403-2 U1-AR1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_6_to_FPGA_Dir' DPV135-3 DPV139-3 NET 'Rec_MP_Fiber_6_to_FPGA_Cmp' DPV135-2 DPV139-2 NET 'GROUND' DPV135-1 DPV139-1 NET 'Rec_MP_Fiber_4_Data_Dir' Rec_MP2-A4 C2405-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 4 NET 'Rec_MP_Fiber_4_Data_Cmp' Rec_MP2-B4 C2406-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_4_to_FPGA_Dir' C2405-2 U1-AP4 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx1 Bank 224 NET 'Rec_MP_Fiber_4_to_FPGA_Cmp' C2406-2 U1-AP3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_4_to_FPGA_Dir' DPV138-3 NET 'Rec_MP_Fiber_4_to_FPGA_Cmp' DPV138-2 NET 'GROUND' DPV138-1 NET 'Rec_MP_Fiber_2_Data_Dir' Rec_MP2-A2 C2407-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 2 NET 'Rec_MP_Fiber_2_Data_Cmp' Rec_MP2-B2 C2408-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_2_to_FPGA_Dir' C2407-2 U1-AN2 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx2 Bank 224 NET 'Rec_MP_Fiber_2_to_FPGA_Cmp' C2408-2 U1-AN1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_2_to_FPGA_Dir' DPV136-3 DPV137-3 NET 'Rec_MP_Fiber_2_to_FPGA_Cmp' DPV136-2 DPV137-2 NET 'GROUND' DPV136-1 DPV137-1 # # Mgt Outputs to the MiniPOD Transmitter 8 of 12 fibers # # This data is send out from MiniPOD Transmitter on # # Fibers: 0, 1, 2, 4, 6, 8, 10, 11 are currently driven # # Fibers: 3, 5, 7, 9 are not currently driven # # This data comes from MGT Outputs Tx0 & Tx2 # from Banks: 224 225 226 227 # NET 'MiniPOD_Trans_Fiber_0_Data_Dir' Trn_MP1-D1 U1-AA6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 227 NET 'MiniPOD_Trans_Fiber_0_Data_Cmp' Trn_MP1-D2 U1-AA7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_1_Data_Dir' Trn_MP1-F1 U1-AC6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 227 NET 'MiniPOD_Trans_Fiber_1_Data_Cmp' Trn_MP1-F2 U1-AC7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_2_Data_Dir' Trn_MP1-B2 U1-AE6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 226 NET 'MiniPOD_Trans_Fiber_2_Data_Cmp' Trn_MP1-A2 U1-AE7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_4_Data_Dir' Trn_MP1-B4 U1-AG6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 226 NET 'MiniPOD_Trans_Fiber_4_Data_Cmp' Trn_MP1-A4 U1-AG7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_6_Data_Dir' Trn_MP1-B6 U1-AJ6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 225 NET 'MiniPOD_Trans_Fiber_6_Data_Cmp' Trn_MP1-A6 U1-AJ7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_8_Data_Dir' Trn_MP1-B8 U1-AL6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 225 NET 'MiniPOD_Trans_Fiber_8_Data_Cmp' Trn_MP1-A8 U1-AL7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_10_Data_Dir' Trn_MP1-D8 U1-AN6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 224 NET 'MiniPOD_Trans_Fiber_10_Data_Cmp' Trn_MP1-D9 U1-AN7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_11_Data_Dir' Trn_MP1-F8 U1-AR6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 224 NET 'MiniPOD_Trans_Fiber_11_Data_Cmp' Trn_MP1-F9 U1-AR7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'NO_CONN_MiniPOD_Trans_Fiber_3_Data_Dir' Trn_MP1-H2 NET 'NO_CONN_MiniPOD_Trans_Fiber_3_Data_Cmp' Trn_MP1-J2 NET 'NO_CONN_MiniPOD_Trans_Fiber_5_Data_Dir' Trn_MP1-H4 NET 'NO_CONN_MiniPOD_Trans_Fiber_5_Data_Cmp' Trn_MP1-J4 NET 'NO_CONN_MiniPOD_Trans_Fiber_7_Data_Dir' Trn_MP1-H6 NET 'NO_CONN_MiniPOD_Trans_Fiber_7_Data_Cmp' Trn_MP1-J6 NET 'NO_CONN_MiniPOD_Trans_Fiber_9_Data_Dir' Trn_MP1-H8 NET 'NO_CONN_MiniPOD_Trans_Fiber_9_Data_Cmp' Trn_MP1-J8 # # MGT Outputs of the Readout Data from This Hub's FPGA # # There are 2 paths for This Hub's FPGA Readout Data: # # - to the ROD on This Hub # # - to the Other Hub where it goes through # the 2x fanout and then to the Other Hub's ROD # and to the Other Hub's FPGA # # # This Hub's Readout Data comes out of its FPGA from: # # - GTH Transmitter Tx0 of Bank 229 and Tx2 of Bank 228 # from which it goes to the ROD on This Hub # # - GTY Transmitters Tx2 and Tx0 of Bank 127 # from wich it goes to the Other Hub # # # This Hub's Readout Data: # # - Tx0 of Bank 229 is Aurora Lane 0 to MegArray 2 B2,C2 to ROD # - Tx2 of Bank 228 is Aurora Lane 1 to MegArray 2 H6,J6 to ROD # # - Tx2 of Bank 127 is Aurora Lane 0 to Backplane J23 A3,B3 to Other Hub # - Tx0 of Bank 127 is Aurora Lane 1 to Backplane J23 E3,F3 to Other Hub # # # All 4 of these links need DC Blocking Caps. The standard # is to have DC Blocking Caps on the source end of all GTH links. # # # This Hub's Readout to the ROD on This Hub # NET 'This_Hubs_RO_0_to_Cap_Its_ROD_Dir' U1-R7 C2503-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Tx0 Bank 229 NET 'This_Hubs_RO_0_to_Cap_Its_ROD_Cmp' U1-R6 C2504-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Its_ROD_Dir' C2503-2 Meg_S2-B2 (NET_TYPE, 'DIFF_PAIR_HS') # and into This ROD NET 'This_Hubs_RO_0_Cap_to_Its_ROD_Cmp' C2504-2 Meg_S2-C2 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_1_to_Cap_Its_ROD_Dir' U1-U7 C2505-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Tx2 Bank 228 NET 'This_Hubs_RO_1_to_Cap_Its_ROD_Cmp' U1-U6 C2506-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 NET 'This_Hubs_RO_1_Cap_to_Its_ROD_Dir' C2505-2 Meg_S2-H6 (NET_TYPE, 'DIFF_PAIR_HS') # and into This ROD NET 'This_Hubs_RO_1_Cap_to_Its_ROD_Cmp' C2506-2 Meg_S2-J6 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 # # This Hub's Readout to the ROD on the Other Hub # # Note that these two connections involve both AC Coupling # Capacitors and Differential Pair Vias on their runs # from the FPGA to the Backplane Connectors. # NET 'This_Hubs_RO_0_to_Cap_Other_ROD_Dir' U1-AA40 C2507-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Tx2 Bank 127 NET 'This_Hubs_RO_0_to_Cap_Other_ROD_Cmp' U1-AA41 C2508-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Dir' C2507-2 J23-A3 (NET_TYPE, 'DIFF_PAIR_HS') # RO to Other Hub NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Cmp' C2508-2 J23-B3 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Dir' DPV702-3 # Diff Pair Via NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Cmp' DPV702-2 # in run from caps NET 'GROUND' DPV702-1 # to Backplane NET 'This_Hubs_RO_1_to_Cap_Other_ROD_Dir' U1-AC41 C2509-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Tx0 Bank 127 NET 'This_Hubs_RO_1_to_Cap_Other_ROD_Cmp' U1-AC40 C2510-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 # -- FLIPPED -- NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Dir' C2509-2 J23-E3 (NET_TYPE, 'DIFF_PAIR_HS') # RO to Other Hub NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Cmp' C2510-2 J23-F3 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Dir' DPV703-2 # Diff Pair Via NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Cmp' DPV703-3 # in run from caps NET 'GROUND' DPV703-1 # to Backplane # # Finally the Differential Via Pairs that are # around the Hub's FPGA. # # These are for FEX Data MGT Receiver Inputs # NET 'MGT_FO_CH_8_OUT_HUB_CMP' DPV102-2 NET 'MGT_FO_CH_8_OUT_HUB_DIR' DPV102-3 NET 'GROUND' DPV102-1 NET 'MGT_FO_CH_6_OUT_HUB_CMP' DPV103-2 NET 'MGT_FO_CH_6_OUT_HUB_DIR' DPV103-3 NET 'GROUND' DPV103-1 NET 'MGT_FO_CH_4_OUT_HUB_CMP' DPV104-2 NET 'MGT_FO_CH_4_OUT_HUB_DIR' DPV104-3 NET 'GROUND' DPV104-1 NET 'MGT_FO_CH_2_OUT_HUB_CMP' DPV105-2 NET 'MGT_FO_CH_2_OUT_HUB_DIR' DPV105-3 NET 'GROUND' DPV105-1 NET 'MGT_FO_CH_16_OUT_HUB_CMP' DPV106-2 NET 'MGT_FO_CH_16_OUT_HUB_DIR' DPV106-3 NET 'GROUND' DPV106-1 NET 'MGT_FO_CH_14_OUT_HUB_CMP' DPV107-2 NET 'MGT_FO_CH_14_OUT_HUB_DIR' DPV107-3 NET 'GROUND' DPV107-1 NET 'MGT_FO_CH_12_OUT_HUB_CMP' DPV108-2 NET 'MGT_FO_CH_12_OUT_HUB_DIR' DPV108-3 NET 'GROUND' DPV108-1 NET 'MGT_FO_CH_10_OUT_HUB_CMP' DPV109-2 NET 'MGT_FO_CH_10_OUT_HUB_DIR' DPV109-3 NET 'GROUND' DPV109-1 NET 'MGT_FO_CH_24_OUT_HUB_CMP' DPV110-2 NET 'MGT_FO_CH_24_OUT_HUB_DIR' DPV110-3 NET 'GROUND' DPV110-1 NET 'MGT_FO_CH_22_OUT_HUB_CMP' DPV111-2 NET 'MGT_FO_CH_22_OUT_HUB_DIR' DPV111-3 NET 'GROUND' DPV111-1 NET 'MGT_FO_CH_20_OUT_HUB_CMP' DPV112-2 NET 'MGT_FO_CH_20_OUT_HUB_DIR' DPV112-3 NET 'GROUND' DPV112-1 NET 'MGT_FO_CH_18_OUT_HUB_CMP' DPV113-2 NET 'MGT_FO_CH_18_OUT_HUB_DIR' DPV113-3 NET 'GROUND' DPV113-1 NET 'MGT_FO_CH_32_OUT_HUB_CMP' DPV114-2 NET 'MGT_FO_CH_32_OUT_HUB_DIR' DPV114-3 NET 'GROUND' DPV114-1 NET 'MGT_FO_CH_30_OUT_HUB_CMP' DPV115-2 NET 'MGT_FO_CH_30_OUT_HUB_DIR' DPV115-3 NET 'GROUND' DPV115-1 NET 'MGT_FO_CH_28_OUT_HUB_CMP' DPV116-2 NET 'MGT_FO_CH_28_OUT_HUB_DIR' DPV116-3 NET 'GROUND' DPV116-1 NET 'MGT_FO_CH_26_OUT_HUB_CMP' DPV117-2 NET 'MGT_FO_CH_26_OUT_HUB_DIR' DPV117-3 NET 'GROUND' DPV117-1 NET 'MGT_FO_CH_65_OUT_HUB_CMP' DPV118-2 NET 'MGT_FO_CH_65_OUT_HUB_DIR' DPV118-3 NET 'GROUND' DPV118-1 NET 'MGT_FO_CH_67_OUT_HUB_CMP' DPV119-2 NET 'MGT_FO_CH_67_OUT_HUB_DIR' DPV119-3 NET 'GROUND' DPV119-1 NET 'MGT_FO_CH_69_OUT_HUB_CMP' DPV120-2 NET 'MGT_FO_CH_69_OUT_HUB_DIR' DPV120-3 NET 'GROUND' DPV120-1 NET 'MGT_FO_CH_71_OUT_HUB_CMP' DPV121-2 NET 'MGT_FO_CH_71_OUT_HUB_DIR' DPV121-3 NET 'GROUND' DPV121-1 NET 'MGT_FO_CH_73_OUT_HUB_CMP' DPV122-2 NET 'MGT_FO_CH_73_OUT_HUB_DIR' DPV122-3 NET 'GROUND' DPV122-1 NET 'MGT_FO_CH_57_OUT_HUB_CMP' DPV123-2 NET 'MGT_FO_CH_57_OUT_HUB_DIR' DPV123-3 NET 'GROUND' DPV123-1 NET 'MGT_FO_CH_59_OUT_HUB_CMP' DPV124-2 NET 'MGT_FO_CH_59_OUT_HUB_DIR' DPV124-3 NET 'GROUND' DPV124-1 NET 'MGT_FO_CH_61_OUT_HUB_CMP' DPV125-2 NET 'MGT_FO_CH_61_OUT_HUB_DIR' DPV125-3 NET 'GROUND' DPV125-1 NET 'MGT_FO_CH_63_OUT_HUB_CMP' DPV126-2 NET 'MGT_FO_CH_63_OUT_HUB_DIR' DPV126-3 NET 'GROUND' DPV126-1 NET 'MGT_FO_CH_49_OUT_HUB_CMP' DPV127-2 NET 'MGT_FO_CH_49_OUT_HUB_DIR' DPV127-3 NET 'GROUND' DPV127-1 NET 'MGT_FO_CH_51_OUT_HUB_CMP' DPV128-2 NET 'MGT_FO_CH_51_OUT_HUB_DIR' DPV128-3 NET 'GROUND' DPV128-1 NET 'MGT_FO_CH_53_OUT_HUB_CMP' DPV129-2 NET 'MGT_FO_CH_53_OUT_HUB_DIR' DPV129-3 NET 'GROUND' DPV129-1 NET 'MGT_FO_CH_55_OUT_HUB_CMP' DPV130-2 NET 'MGT_FO_CH_55_OUT_HUB_DIR' DPV130-3 NET 'GROUND' DPV130-1 NET 'MGT_FO_CH_41_OUT_HUB_CMP' DPV131-2 NET 'MGT_FO_CH_41_OUT_HUB_DIR' DPV131-3 NET 'GROUND' DPV131-1 NET 'MGT_FO_CH_43_OUT_HUB_CMP' DPV132-2 NET 'MGT_FO_CH_43_OUT_HUB_DIR' DPV132-3 NET 'GROUND' DPV132-1 NET 'MGT_FO_CH_48_OUT_HUB_CMP' DPV133-2 NET 'MGT_FO_CH_48_OUT_HUB_DIR' DPV133-3 NET 'GROUND' DPV133-1 NET 'MGT_FO_CH_37_OUT_HUB_CMP' DPV134-2 NET 'MGT_FO_CH_37_OUT_HUB_DIR' DPV134-3 NET 'GROUND' DPV134-1