# # Hub Module - Key-In Nets File # # JTAG String # -------------- # # # Original Rev. 20-Nov-2015 # Most Recent Rev. 9-Nov-2016 # # # This file holds all of the nets associated with the # Hub Module JTAG string. This includes the front # pannel J2 connections, level translator/buffers, # Hub FPGA and ROD JTAG circuits. # # Rcall the pinout of the JTAG section of the front # panel J2 connector: # # Pin Function # --- --------------- # # 2 3V3 JTAG Reference Power # 4 TMS # 6 TCK # 8 TDO # 10 TDI # # The 5 odd pins 1, 3, 5, 7, 9 are Ground # # # Connect the 3V3 JTAG Reference power and ground # to the front panel J2 connector. # NET 'BULK_3V3' F7-2 NET 'FUSED_JTAG_POWER' F7-1 J2-2 NET 'GROUND' J2-1 J2-3 J2-5 J2-7 J2-9 # # Connections from J2 to the Level Translator chips. # # Note that we are using the "B" side to "A" side direction. # # "B" data input to "A" data output. # # Thus both the Direction pin and the OE_B pin are tied Low. # # The input "B" side has 3V3 power. # The output "A" side has 1V8 power. # NET 'TMS_FROM_J2' J2-4 R581-1 U554-14 U554-16 NET 'TCK_FROM_J2' J2-6 R582-1 U554-15 U554-17 NET 'TDI_FROM_J2' J2-10 R583-1 U554-18 NET 'TDO_TO_J2' J2-8 R590-1 NET 'TDO_FROM_U555' R590-2 U555-3 NET 'BULK_3V3' R581-2 R582-2 R583-2 # # Connect the Power and Ground and DIR and OE_B # to the U554 Translator # # The input "B" side has 3V3 power. # The output "A" side has 1V8 power. # # U554 POWER AND GROUND NET 'BULK_1V8' U554-1 NET 'BULK_3V3' U554-23 U554-24 NET 'GROUND' U554-11 U554-12 U554-13 # U554 DIR and OE_B pins: NET 'GROUND' U554-2 U554-22 # # Connect the Power and Ground and DIR # to the U555 Translator # # The input "B" side has 1V8 power. # The output "A" side has 3V3 power. # NET 'BULK_1V8' U555-8 NET 'BULK_3V3' U555-1 NET 'GROUND' U555-4 # U555 DIR pin: NET 'GROUND' U555-5 # # ByPass Capacitors for U554 and U555 Translators # NET 'BULK_1V8' C2941-1 C2943-1 NET 'GROUND' C2941-2 C2943-2 NET 'BULK_3V3' C2942-1 C2944-1 NET 'GROUND' C2942-2 C2944-2 # # Define the Un-Used Inputs and Outputs # on the Translators U554. # # NOTE that the other section of the U555 # Translator is used to make a 3V3 version # of the FPGA Configuration DONE signal. # NET 'No_Conn_U554_Pin_3' U554-3 NET 'No_Conn_U554_Pin_4' U554-4 NET 'No_Conn_U554_Pin_5' U554-5 NET 'No_Conn_U554_Pin_19' U554-19 NET 'No_Conn_U554_Pin_20' U554-20 NET 'No_Conn_U554_Pin_21' U554-21 # # Now the TMS and TCK connections to the Hub's FPGA # NET 'TMS_HUB_PRE_SERIES' U554-10 R584-2 NET 'TMS_TO_HUB_FPGA' R584-1 U1-AB15 NET 'TCK_HUB_PRE_SERIES' U554-9 R585-2 NET 'TCK_TO_HUB_FPGA' R585-1 U1-AD16 # # Now the TMS and TCK connections to the ROD # NET 'TMS_ROD_PRE_SERIES' U554-8 R586-2 NET 'TMS_TO_ROD_FPGA' R586-1 Meg_S2-J24 NET 'TCK_ROD_PRE_SERIES' U554-7 R587-2 NET 'TCK_TO_ROD_FPGA' R587-1 Meg_S2-H24 # # Now the TDI to TDO circuit # # see also the AND Buffer for the TDI to the ROD # NET 'TDI_TO_SERIES_RES' U554-6 R588-2 NET 'TDI_SERIES_TO_HUB_FPGA' R588-1 U1-AF15 JMP2-2 NET 'TD_HUB_FPGA_TO_JMP1' U1-AD15 JMP1-2 NET 'TD_TO_MUX_AND_ROD_BUF' JMP2-1 JMP1-1 NET 'TD_TO_MUX_AND_ROD_BUF' U556-3 U557-1 U557-2 NET 'TD_FROM_ROD_TO_MUX' Meg_S2-J25 U556-1 NET 'TD_FROM_MUX_TO_SERIES' U556-4 R589-2 NET 'TDO_FROM_SERIES_TO_TRANS' U555-6 R589-1 # # Now the control line to the JTAG Multiplexer U556 # # When Power Control #2 aka ROD Power Good # signal is Hi then the JTAG multiplexer switches # to include the ROD in the JTAG string. # NET 'ROD_Power_Control_2_ROD' U556-6 # # Now the Multiplexer Power and Ground connections # NET 'BULK_1V8' U556-5 C2945-1 C2946-1 NET 'GROUND' U556-2 C2945-2 C2946-2 # # Now the AND Gate Buffer for the TDI to the ROD # and its Power and Ground connections # # The input to pins 1 and 2 of this buffer is given above. # NET 'TD_TO_ROD_BUFF_RES' U557-4 R593-1 NET 'TD_BUFF_RES_TO_ROD' R593-2 Meg_S2-H25 NET 'BULK_1V8' U557-5 C2947-1 NET 'GROUND' U557-3 C2947-2 # # Finally the ROD_Present_B circuit # # with its connection to the to the Hub's FPGA. # NET 'ROD_PRESENT_B' Meg_S1-C37 R591-1 R592-1 NET 'ROD_PRESENT_B_TO_FPGA' R592-2 NET 'BULK_1V8' R591-2 NET 'ROD_PRESENT_B_TO_FPGA' U1-AW27 # IO_L14P_T2L_N2_GC_67