# # Hub Module - Key-In Nets File # # Power Supply - All Other NETs # # # # Original Rev. 2-Nov-2015 # Most Recent Rev. 28-Dec-2016 # # # This file holds All Other NETs for the # Hub Module Power Supply crcuits. These Include: # # - Header for Power Supply Monitoring # - Power Supply Statup Supervisor # - Power Supply "All Good" signal generator # - The "Always On" supply # - The Reference Supplies for the FPGA System Monitor # # # Because of the different types of components in this # file, it is divided into sections. # # # # System Monitor for the UltraScale Virtex FPGA # ----------------------------------------------- # # This includes the Reference supply and power filtering # for the System Monitor as well as the analog scaling # components for the monitored signals. # # The SysMon NETs use Reference Designators: 1851 through 1899. # # # SysMon Power/Ground Filtering and Reference Supply # NET 'BULK_1V8' L1851-1 C1851-2 NET 'GROUND' C1851-1 NET 'GROUND' L1852-1 NET 'SYSMON_GND' L1852-2 NET 'SYSMON_1V8' L1851-2 C1852-1 C1853-1 C1854-1 C1855-1 C1859-1 NET 'SYSMON_GND' C1852-2 C1853-2 C1854-2 C1855-2 C1859-2 NET 'SYSMON_1V8' U1851-1 NET 'SYSMON_GND' U1851-3 C1856-2 C1857-2 C1858-2 NET 'SYSMON_VREFP' U1851-2 C1856-1 C1857-1 C1858-1 # # Connections to the FPGA's SysMon Pins: # # - SysMon Power # - SysMon Reference Supply # - SysMon Main Input Voltage # - SysMon Temperature Diode # NET 'SYSMON_1V8' U1-AB20 NET 'SYSMON_GND' U1-AB19 U1-AC19 NET 'SYSMON_VREFP' U1-AD20 NET 'SysMon_Main_Input_VP' U1-AC20 NET 'SysMon_Main_Input_VN' U1-AD19 NET 'Temp_Diode_DXN' U1-AE19 NET 'Temp_Diode_DXP' U1-AE20 # # ================================================================= # # # Power Supply Controller # -------------------------- # # Controls the Startup and Shutdown # of the DCDC Converters on the Hub Module # # # Detect GOOD Iso_12V and then Delay for 500 msec. # NET 'ISO_12V' R2951-1 NET 'SENSE_12V' R2951-2 R2952-1 C2951-1 U2951-5 NET 'GROUND' R2952-2 C2951-2 NET 'CNST_5V0' U2951-6 C2955-1 C2959-1 NET 'GROUND' U2951-2 C2955-2 C2959-2 NET 'No_Conn_U2951_Pin_3' U2951-3 NET 'DEL_CAP_12V_DET' U2951-4 C2952-1 NET 'GROUND' C2952-2 NET 'GOOD_ISO_12V' U2951-1 R2953-1 NET 'CNST_5V0' R2953-2 # # Sequence the 3 Flags # NET 'GOOD_ISO_12V' U2952-3 NET 'CNST_5V0' U2952-1 C2956-1 NET 'GROUND' U2952-2 C2956-2 NET 'SEQUENCE_FLAG_1' U2952-6 R2954-1 NET 'SEQUENCE_FLAG_2' U2952-5 R2955-1 NET 'SEQUENCE_FLAG_3' U2952-4 R2956-1 NET 'CNST_5V0' R2954-2 R2955-2 R2956-2 # # Power and Ground to the NANDs and Inverters # NET 'CNST_5V0' U2953-14 C2957-1 U2954-14 C2958-1 NET 'GROUND' U2953-7 C2957-2 U2954-7 C2958-2 # # First Enable NAND # NET 'SEQUENCE_FLAG_1' U2953-1 NET 'GOOD_ISO_12V' U2953-2 NET 'HI_U2953_13' U2953-13 R2960-1 NET 'CNST_5V0' R2960-2 NET 'FIRST_ENABLE_NAND_OUT' U2953-12 # # First Enable Fanout Inverters # NET 'FIRST_ENABLE_NAND_OUT' U2954-1 NET 'BUFD_FIRST_ENABLE' U2954-2 U2954-3 U2954-5 U2954-9 NET 'FIRST_ENABLE_COPY_1' U2954-4 R2961-1 R2962-1 NET 'FIRST_ENABLE_COPY_2' U2954-6 R2963-1 R2965-1 NET 'FIRST_ENABLE_COPY_3' U2954-8 R2964-1 R2966-1 NET 'DCDC_1_OFF_ON' R2961-2 NET 'DCDC_2_OFF_ON' R2962-2 NET 'DCDC_3_OFF_ON' R2963-2 NET 'DCDC_6_OFF_ON' R2964-2 NET 'DCDC_7_OFF_ON' R2965-2 NET 'DCDC_8_OFF_ON' R2966-2 # # Second Enable NAND # NET 'SEQUENCE_FLAG_3' U2953-9 NET 'ENABLE_12V_2ND_BUF' U2953-10 NET 'GOOD_ISO_12V' U2953-11 NET 'SECOND_ENABLE_NAND_OUT' U2953-8 R2967-1 NET 'DCDC_5_OFF_ON' R2967-2 # # Sequence Ramp NAND # NET 'SEQUENCE_FLAG_2' U2953-3 NET 'GOOD_ISO_12V' U2953-4 NET 'ENABLE_12V_2ND_BUF' U2953-5 NET 'RAMP_ENABLE_NAND_OUT' U2953-6 R2957-1 # # Sequence Ramp Generator # NET 'RAMP_SWITCH_BASE' Q2951-2 R2957-2 NET 'GROUND' Q2951-1 NET 'RAMP_SWITCH_COLLECTOR' Q2951-3 R2959-1 NET 'ISO_12V' R2958-1 NET 'CONVERTER_RAMP' R2958-2 R2959-2 NET 'CONVERTER_RAMP' C2985-1 C2986-1 C2987-1 C2988-1 C2989-1 NET 'GROUND' C2985-2 C2986-2 C2987-2 C2988-2 C2989-2 # # Buffer the Hub_Power_Enable signal. # # - Note that this 3.3 Volt CMOS Logic signal normally comes # from the IPMC's Payload Power Enable pin and that it # drives an opto-coupler LED through R956 and drives this # U2954 input to the Hub's power supply control logic. # # - But that this signal can also come from an "always ON" # signal as a way to ignore the IPMC and have immediate # power up of the Hub Module. # # - Use JMP5 and JMP6 to select the desired mode of power up. # NET 'Hub_Power_Enable' U2954-13 NET 'ENABLE_12V_1ST_BUF' U2954-12 U2954-11 NET 'ENABLE_12V_2ND_BUF' U2954-10 # # ================================================================= # # # ALL Hub Power Good and Board Startup Reset # ---------------------------------------------- # # # This section of the net list really contains # two different: # # - Generate the Hub_Power_Good signal # # - from that generate the Board_Startup_Reset_B signal # # # To generate the Hub_Power_Good signal: # # - examine the Power Good signals from the # 7x DC/DC Converters and # # - examine the output of the MGT_AVAUX # and BULK_2V5 linear supplies and # # - include the Enable Iso_12V signal. # # # Connect Power, Ground, and ByPass Capacitors to the # 5 ICs in this functional section. # NET 'CNST_5V0' U2955-14 U2956-14 NET 'CNST_5V0' U2957-6 U2958-6 U2959-6 NET 'GROUND' U2955-7 U2956-7 NET 'GROUND' U2957-2 U2958-2 U2959-2 NET 'CNST_5V0' C2962-1 C2963-1 C2964-1 C2965-1 C2966-1 NET 'GROUND' C2962-2 C2963-2 C2964-2 C2965-2 C2966-2 # # Connect the DCDC Converter "Power_Good" signals to # the AND gates and connect the associated Pull-Up resistors # These Pull-Up resistors pull to CNST_5V0. # NET 'DCDC_1_POWER_GOOD' U2955-1 R2981-1 NET 'DCDC_2_POWER_GOOD' U2955-2 R2982-1 NET 'DCDC_3_POWER_GOOD' U2955-4 R2983-1 NET 'DCDC_5_POWER_GOOD' U2955-5 R2984-1 NET 'DCDC_6_POWER_GOOD' U2955-9 R2985-1 NET 'DCDC_7_POWER_GOOD' U2955-10 R2986-1 NET 'DCDC_8_POWER_GOOD' U2955-12 R2987-1 NET 'CNST_5V0' R2981-2 R2982-2 R2983-2 R2984-2 NET 'CNST_5V0' R2985-2 R2986-2 R2987-2 # # Include the Enable Iso_12V power supply signal # in the overall Hub Power Good generation. # # Note This 5 volt version of the Enable Isolated +12V # comes from U2954 in the Hub Power Supply Control circuit. # This forces the Board_Startup_Reset_B signal to be # asserted as soon the the Isolated +12V supply is # turned OFF. # NET 'ENABLE_12V_2ND_BUF' U2955-13 # # Connect the MGT_AVAUX power good threshold detector # and its associated components # NET 'MGT_AVAUX' R2971-1 NET 'PG_SENSE_MGT_AVAUX' R2971-2 R2972-2 U2957-5 NET 'GROUND' R2972-1 NET 'No_Conn_U2957_3_MR_B' U2957-3 NET 'No_Conn_U2957_4_TCap' U2957-4 NET 'MGT_AVAUX_GT_OK' U2957-1 R2975-1 U2956-10 NET 'CNST_5V0' R2975-2 # # Connect the BULK_2V5 power good threshold detector # and its associated components # NET 'BULK_2V5' R2973-1 NET 'PG_SENSE_BULK_2V5' R2973-2 R2974-2 U2958-5 NET 'GROUND' R2974-1 NET 'No_Conn_U2958_3_MR_B' U2958-3 NET 'No_Conn_U2958_4_TCap' U2958-4 NET 'BULK_2V5_GT_OK' U2958-1 R2976-1 U2956-9 NET 'CNST_5V0' R2976-2 # # Connect the various AND gates into the overall Hub Power Good # NET 'QUAD_ONE_PG_OK' U2955-6 U2956-13 NET 'QUAD_TWO_PG_OK' U2955-8 U2956-12 NET 'HUB_POWER_GOOD' U2956-8 # # Connect the HUB_POWER_GOOD signal to an FPGA Input. # # Note the 2.7k Ohm series resistor R2979 between the # 5.0V CMOS signal source and the 3.3V CMOS FPGA Input. # # The other connection to HUB_POWER_GOOD is shown below. # NET 'HUB_POWER_GOOD' R2979-1 NET 'ALL_HUB_POWER_GOOD_TO_FPGA' R2979-2 U1-AM16 # IO_T3U_N12_84 # # Ground the inputs on the unused section of U2956 # and assign a No_Conn net to the output of its # unused section. # # Assign No_Conn nets to the "no internal connection" # pins on both U2955 and U2956. # NET 'GROUND' U2956-1 U2956-2 U2956-4 U2956-5 NET 'No_Conn_U2956_Pin_6' U2956-6 NET 'No_Conn_U2955_Pin_3' U2955-3 NET 'No_Conn_U2955_Pin_11' U2955-11 NET 'No_Conn_U2956_Pin_3' U2956-3 NET 'No_Conn_U2956_Pin_11' U2956-11 # # Finally generate the Board_Startup_Reset_B signal # # Note that the MR_B pin on the TPS3808 that generates # the Board_Startup_Reset_B signal is not used. It # could be used as another input if needed. As on the # other TPS3808s the MR_B pins can be left open. # # Note that the Board_Startup_Reset_B signal is # pulled up to the Bulk_3V3 level. # NET 'HUB_POWER_GOOD' R2978-1 U2959-5 NET 'GROUND' R2978-2 NET 'BRD_STR_RESET_CAP' U2959-4 C2961-1 NET 'GROUND' C2961-2 NET 'No_Conn_U2959_Pin_3' U2959-3 NET 'BOARD_STARTUP_RESET_B' U2959-1 R2977-1 NET 'BULK_3V3' R2977-2 # # ================================================================= # # # Board Reset Distribution and part of ROD Power Control # ---------------------------------------------------------- # # # This section of the net list Distributes the # BOARD_STARTUP_RESET_B signal. # # The BOARD_STARTUP_RESET_B signal goes to: # # - The FPGA INIT pin and the Configuration # Flash Memory Reset pin. This prevents corruption # of the Flash Memory when the power supplies are # not all running and stable. # # - The 3 Switch chip Reset pins. As required, hold # the 3 Switch chips in reset until the power supplies # are all up and stable. # # - The reset pin on the 2 Phys chips.. As required, hold # the 2 Phys chips in reset until the power supplies are # all up and stable. # # - The BOARD_STARTUP_RESET_B signal goes into the AND # gate that makes up the Enable_ROD_Power signal. # The BOARD_STARTUP_RESET_B must NOT be asserted to # turn power ON on the ROD. # # # Connect Power, Ground, and ByPass Capacitors to the # 8x ICs in this functional section. Define the No_Conn # pin on the 5x NC7SV05 inverter chips. # NET 'BULK_3V3' U2960-5 U2961-5 U2962-5 NET 'BULK_3V3' U2963-5 U2964-5 U2965-5 NET 'BULK_3V3' U2966-5 U2967-5 NET 'GROUND' U2960-3 U2961-3 U2962-3 NET 'GROUND' U2963-3 U2964-3 U2965-3 NET 'GROUND' U2966-3 U2967-3 NET 'BULK_1V8' U2968-5 NET 'GROUND' U2968-3 NET 'No_Conn_U2960_pin_1' U2960-1 NET 'No_Conn_U2961_pin_1' U2961-1 NET 'No_Conn_U2962_pin_1' U2962-1 NET 'No_Conn_U2963_pin_1' U2963-1 NET 'No_Conn_U2964_pin_1' U2964-1 NET 'No_Conn_U2965_pin_1' U2965-1 NET 'BULK_3V3' C2971-1 C2972-1 C2973-1 NET 'BULK_3V3' C2974-1 C2975-1 C2976-1 C2980-1 NET 'GROUND' C2971-2 C2972-2 C2973-2 NET 'GROUND' C2974-2 C2975-2 C2976-2 C2980-2 NET 'BULK_1V8' C2977-1 C2978-1 C2979-1 NET 'GROUND' C2977-2 C2978-2 C2979-2 # # Connect the Board_Startup_Reset_B signal and # make the inverted version and distribute both. # NET 'BOARD_STARTUP_RESET_B' U2960-2 U2961-2 NET 'BOARD_STARTUP_RESET' U2960-4 NET 'BOARD_STARTUP_RESET' R2991-1 U2962-2 U2963-2 U2964-2 NET 'BULK_3V3' R2991-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # FPGA Init and Flash Memory Reset circuit. # # NOTE This is a 1V8 version of this signal. # # NOTE That the Pull-Up Resistor for this circuit # and the other connections to this circuit are in # the net file: bank_0_and_bank_65_config_mem_nets # NET 'FLASH_RESET_B' U2962-4 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # Reset pins on the 3x Switch Chips. # # Note This is a 3V3 version of this signal. # # Note The connection to the Switch Chips themselves # is made in the file: switch_chips_all_other_nets # NET 'SWITCH_CHIPS_RESET_B' U2963-4 R2992-1 NET 'BULK_3V3' R2992-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # Reset pins on the 2x Phys Chips. # # Note This is a 1V8 version of this signal. # # Note The connection to the Phys Chips themselves # is made in the files: rgmii_phys_chip_u21_nets # rgmii_phys_chip_u22_nets # NET 'Phys_Chips_RESET_B' U2964-4 R2993-1 NET 'BULK_1V8' R2993-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset signal to the # LED_54 Cathode. This is the LED that Illuminates # when all of the Hub power supplies are up and stable # and the Board_Startup_Reset is over. # # This LED is usually called "All Hub Power Good". # # Note that this is an inverted copy of the normal # Board_Startup_Reset_B signal. # # Note that the connection to LED_54 is made # in the file: led_connection_nets # NET 'LED_54_Cathode' U2961-4 # # ================================================================= # # # ROD Power Control # --------------------- # # # This section of the net list file involves the generation # of the Enable ROD Power signal aka ROD Power Control #1. # # It also includes the other 3 ROD Powr Control sginals # numbers: 2,3,4. For now these 3 ROD Power Control # signals will just be connected to the Hub's Virtex FPGA. # # The Enable ROD Power signal is generated by ICs # U2965 through U2968. The power and ground and bypass # capacitor connections to these 4 chips were made in the # above section of this nets list file. # # All 4 of the ROD Power Control signals are defined as # 1V8 level CMOS signals. # # # Include the All Hub Power Good signal # NET 'BOARD_STARTUP_RESET_B' U2966-2 # # Include the ROD_Power_Enable and ROD_Power_Enable_B # logic signals from the Hub's FPGA. # # These two ROD_Power_Enable signals are 3V3 logic level # and must be connected to one of the 3V3 Select I/O Banks. # NET 'ROD_Power_Enable' U1-AR17 # IO_L24N_T3U_N11_84 NET 'ROD_Power_Enable_B' U1-AP17 # IO_L24P_T3U_N10_84 NET 'ROD_Power_Enable' U2966-1 NET 'ROD_Power_Enable_B' U2965-2 NET 'Flipped_ROD_Power_Enable_B' U2965-4 U2967-2 R2994-1 NET 'Bulk_3V3' R2994-2 # # Optionally include the 3V3 version of the # FPGA_Configuration_DONE signal. Including or # not including this signal is controlled by jumpers # JMP3 and JMP4. # # Start by converting the FPGA_Configuration_DONE # signal from 1V8 to 3V3. This logic level conversion # is done by U555. The other half of the U555 Translator # is used in the JTAG string as shown in Drawing 33 # and described in the file: jtag_and_associated_nets # # The FPGA_Configuration_DONE signal and its pull-up # are defined in the file: bank_0_and_bank_65_config_mem_nets # NET 'FPGA_Config_DONE' U555-7 NET 'FPGA_Config_DONE_3V3' U555-2 JMP3-1 NET 'Optional_DONE_RPC' JMP4-2 JMP3-2 U2967-1 NET 'BULK_3V3' JMP4-1 # # Now AND things together to make the overall # Enable ROD Power signal. # # Note that the Logic output from U2966 and from U2967 # is 3.3 Volt CMOS level. It is OK to connect these # directly to the 1V8 powered U2968 because this family # of Fairchild logic has 3.6 Volt I/O tolerance when # powered with Vcc from 0V9 to 3V6. # NET 'First_Part_ROD_Pow' U2966-4 U2968-2 NET 'Second_Part_ROD_Pow' U2967-4 U2968-1 NET 'Enable_ROD_Power' U2968-4 # # Define the Hub FPGA end of 3 of # the 4 Power_Control signals that # run to the ROD: PC2, PC3, PC4 # # These Power_Control signals to/from # the ROD are 1V8 logic level and must # run to a 1V8 bank. # NET 'ROD_Power_Control_2_FPGA' U1-AW28 # IO_L14N_T2L_N3_GC_67 NET 'ROD_Power_Control_3_FPGA' U1-AV30 # IO_L12N_T1U_N11_GC_67 NET 'ROD_Power_Control_4_FPGA' U1-AV29 # IO_L12P_T1U_N10_GC_67 # # Define the MegArray Connector - ROD end # of the 4 Power_Control signals that # run to the ROD: PC1, PC2, PC3, PC4 # NET 'Enable_ROD_Power' Meg_S2-H26 NET 'ROD_Power_Control_2_ROD' Meg_S2-J26 NET 'ROD_Power_Control_3_ROD' Meg_S2-H27 NET 'ROD_Power_Control_4_ROD' Meg_S2-J27 # # Connect the 3 ROD Power Control sginals: # PC2, PC3, PC4 Hub-FPGA to MegArray-ROD # with isolating resistors. # # At this time only PC2 is defined. Power Control #2 # is "ROD Power Good". When PC2 is Hi it indicates # that the ROD Power is Good. # # The Hub has a 10k Ohm pull-down R2998 on PC2 so # that when the ROD is not installed on the Hub, the # Hub will not have a floating input signal. # # Note that the PC2, ROD Power Good, is both an input # to the Hub's FPGA and it controls the JTAG Multiplexer # U556 that jumps the JTAG chain over the ROD when it is # not both installed and powered up. # NET 'ROD_Power_Control_2_FPGA' R2995-1 NET 'ROD_Power_Control_2_ROD' R2995-2 R2998-1 NET 'GROUND' R2998-2 NET 'ROD_Power_Control_3_FPGA' R2996-1 NET 'ROD_Power_Control_3_ROD' R2996-2 NET 'ROD_Power_Control_4_FPGA' R2997-1 NET 'ROD_Power_Control_4_ROD' R2997-2 # # Connect the ROD's SMBALERT_B signal through an # isolating resistor and then to a 1V8 Select I/O # pin in the Hub's FPGA. # # - This connection lets the Hub see the ROD's # SMBALERT_B status as requested by Ed. # # - Note that on the ROD, it pulls its SMBALERT_B # signal up to its 1V8 rail with a 1k Ohm resistor, # ROD reference designator R117. # # - Note that in the official ROD/Hub MegArray pinout, # Rev 1.4 6-May-2015, that the SMBALERT signal is # on pin S1-B27. I will make the Hub's connection # for this signal to this pin. I do not see this # connection in the Rev 1-July-2016 ROD schmatics # and I must ask Ed about this. # NET 'RODs_SMBALERT_B' Meg_S1-B27 NET 'RODs_SMBALERT_B' R2999-1 NET 'FPGA_RODs_SMBALERT_B' R2999-2 NET 'FPGA_RODs_SMBALERT_B' U1-BB28 # IO_T2U_N12_67 # # RC Filter and Safety Components Associated # with the J3 Power Supply Monitor Connector # ---------------------------------------------- # # These 11 RC filters are for the Power Supply Voltage # Monitor Test Points in the J3 Connector in the North # East corner of the Hub Module. The 100 Ohm Rs are # also a current limiter for safety. Reference # Designators in the range x2351 : x2369 may be used # for the J3 associated components. # # When using these Voltage Monitor Test Points note # that they have a series resistor connecting them # to the actual power supply rail. In all case but one # these are 100 Ohm series resistors. In the case of # the low current low noise SysMon Ref Supply this is # a 1k Ohm series resistor. # # The mapping of the Voltage Monitor pins on the J3 # connector is in the same basic order as the naming # of the DCDC_? Converters in the rest of the Hub # documentation. # # # J3 Voltage # Monitor Pin Hub Supply Monitored with this Pin # ----------- ------------------------------------ # # 1 DCDC_1 FPGA_Core 0.950 Volts # 3 DCDC_2 MGT_AVCC 1.000 # 5 DCDC_3 MGT_AVTT 1.200 # 7 DCDC_4 MGT_AVAUX 1.800 Linear # 9 DCDC_5 SWCH_1V2 1.200 # 11 DCDC_6 BULK_1V8 1.800 # 13 DCDC_7 FAN_1V8 1.800 # 15 DCDC_8 BULK_3V3 3.300 # 17 DCDC_9 BULK_2V5 2.500 Linear # 21 SysMon Reference 1.250 Linear # 25 Isolated +12V 12.000 ATCA Module # # Even Numbered Pins 2 through 26 are all Grounds. # # Note that I'm skipping monitor pins #19 and #23 # as I want to keep some isolation around the # SysMon Reference monitor pin (especially to # keep Iso_12V noise out of the SysMon Reference). # # # # Start by Grounding the low side of the 1 uFd 25V # ceramic filter capacitors. # NET 'GROUND' C2351-2 C2352-2 C2353-2 C2354-2 C2355-2 NET 'GROUND' C2356-2 C2357-2 C2358-2 C2359-2 C2360-2 NET 'GROUND' C2361-2 # # Now Ground the Even J3 Voltage Monitor Pins. # NET 'GROUND' J3-2 J3-4 J3-6 J3-8 J3-10 NET 'GROUND' J3-12 J3-14 J3-16 J3-18 J3-20 NET 'GROUND' J3-22 J3-24 J3-26 # # Now connect up each of the 10 RC filter circuits # and connect them to the power supply rail that # they monitor. # # DCDC_1 FPGA_Core 0.950 Volts NET 'DCDC_1_Monitor_Point' J3-1 R2351-2 C2351-1 NET 'FPGA_CORE' R2351-1 # DCDC_2 MGT_AVCC 1.000 Volts NET 'DCDC_2_Monitor_Point' J3-3 R2352-2 C2352-1 NET 'MGT_AVCC' R2352-1 # DCDC_3 MGT_AVTT 1.200 Volts NET 'DCDC_3_Monitor_Point' J3-5 R2353-2 C2353-1 NET 'MGT_AVTT' R2353-1 # DCDC_4 MGT_AVAUX 1.800 Volts Linear NET 'DCDC_4_Monitor_Point' J3-7 R2354-2 C2354-1 NET 'MGT_AVAUX' R2354-1 # DCDC_5 SWCH_1V2 1.200 Volts NET 'DCDC_5_Monitor_Point' J3-9 R2355-2 C2355-1 NET 'SWCH_1V2' R2355-1 # DCDC_6 BULK_1V8 1.800 Volts NET 'DCDC_6_Monitor_Point' J3-11 R2356-2 C2356-1 NET 'BULK_1V8' R2356-1 # DCDC_7 FAN_1V8 1.800 Volts NET 'DCDC_7_Monitor_Point' J3-13 R2357-2 C2357-1 NET 'FAN_1V8' R2357-1 # DCDC_8 BULK_3V3 3.300 Volts NET 'DCDC_8_Monitor_Point' J3-15 R2358-2 C2358-1 NET 'BULK_3V3' R2358-1 # DCDC_9 BULK_2V5 2.500 Volts Linear NET 'DCDC_9_Monitor_Point' J3-17 R2359-2 C2359-1 NET 'BULK_2V5' R2359-1 # SysMon Reference 1.250 Volts Linear NET 'DCDC_10_Monitor_Point' J3-21 R2360-2 C2360-1 NET 'SYSMON_VREFP' R2360-1 # Isolated +12 Volt 12.0 Volts ATCA Module NET 'ISO_12V_Monitor_Point' J3-25 R2361-2 C2361-1 NET 'ISO_12V' R2361-1 # # SMB_Alert_B Signal from the Hub's # 7 DCDC Converters to the Hub's FPGA # # The connection of the Hubs_SMB_Alert_B signal to # the SMB_Alert_B pin on each DCDC Converter is shown # in that converter's net list file. Shown here in # this file is just the Hubs_SMB_Alert_B connection # to its pull-up resistor and to a 3.3V I/O pin on # the Hub's FPGA. # NET 'Hubs_SMB_Alert_B' R2989-1 NET 'BULK_3V3' R2989-2 NET 'Hubs_SMB_Alert_B' U1-AP16 # IO_L21N_T3L_N5_AD8N_84