#
#
#                ROD  to/from  Hub  Spare Signal  Nets
#
#              Key In  Net List  file for the  Hub Module
#             --------------------------------------------
#
#
#
#                                          Original Rev.  30-Sept-2015
#                                       Most Recent Rev.  10-Nov-2016
#
#
#   This file holds the nets for the  8 Spare Signals  between
#   the ROD and the Hub.
#
#   These  8 Spare Signals  are Select I/O pins on both the ROD
#   FPGA and on the Hub FPGA.  If needed they may be run as:
#
#    -  8 single ended lines
#
#    -  4 LVDS differential pair signals
#
#    -  4 LVDS differential pairs carrying a serial protocol
#
#
#   Note that these  8 Spare Signals  can send data in either
#   direction,  ROD to Hub  or  Hub to ROD,  whichever is needed.
#
#   On the Hub FPGA these  8 Spare Signals  connect to the 1V8
#   HP Select I/O Bank 67.
#
#   These  8 Spare Signals  must not be confused with the 
#   4 spare Rod to Hub  MGT  links which are one way only.
#
#


NET  'TBD_SPARE_LINK_0_DIR'   Meg_S1-C22   U1-AV26    # IO_L7P_T1L_N0_QBC_AD13P_67
NET  'TBD_SPARE_LINK_0_CMP'   Meg_S1-B22   U1-AW26    # IO_L7N_T1L_N1_QBC_AD13N_67

NET  'TBD_SPARE_LINK_1_DIR'   Meg_S1-C20   U1-AT27    # IO_L8P_T1L_N2_AD5P_67
NET  'TBD_SPARE_LINK_1_CMP'   Meg_S1-B20   U1-AU27    # IO_L8N_T1L_N3_AD5N_67

NET  'TBD_SPARE_LINK_2_DIR'   Meg_S1-C18   U1-AY27    # IO_L13P_T2L_N0_GC_QBC_67
NET  'TBD_SPARE_LINK_2_CMP'   Meg_S1-B18   U1-AY28    # IO_L13N_T2L_N1_GC_QBC_67

NET  'TBD_SPARE_LINK_3_DIR'   Meg_S1-C16   U1-AT29    # IO_L9P_T1L_N4_AD12P_67
NET  'TBD_SPARE_LINK_3_CMP'   Meg_S1-B16   U1-AU29    # IO_L9N_T1L_N5_AD12N_67