# # Ultra FPGA Bypass Capacitor Nets # ------------------------------------ # # Initial Rev. 27-Mar-2015 # Current Rev. 5-Nov-2016 # # This file holds all of the Power and Ground connections # to the ByPass Capacitors on the Hub's Virtex-7 FPGA. # # # FPGA_CORE Bus # VCCINT & VCCBRAM 8x 470 uFd 2.5V case V 9 mOhm C10 : C17 # 1.000 V Supply 11x 10 uFd 10V 0805 X7R C19 : C29 # 3760 uFd total Tant 10x 2.2 uFd 10 V 0603 X7R C30 : C39 # 132 uFd total Ceramic # NET 'FPGA_CORE' C10-1 C11-1 C12-1 C13-1 C14-1 NET 'GROUND' C10-2 C11-2 C12-2 C13-2 C14-2 NET 'FPGA_CORE' C15-1 C16-1 C17-1 NET 'GROUND' C15-2 C16-2 C17-2 NET 'FPGA_CORE' C19-1 C20-1 C21-1 C22-1 C23-1 NET 'GROUND' C19-2 C20-2 C21-2 C22-2 C23-2 NET 'FPGA_CORE' C24-1 C25-1 C26-1 C27-1 C28-1 C29-1 NET 'GROUND' C24-2 C25-2 C26-2 C27-2 C28-2 C29-2 NET 'FPGA_CORE' C30-1 C31-1 C32-1 C33-1 C34-1 NET 'GROUND' C30-2 C31-2 C32-2 C33-2 C34-2 NET 'FPGA_CORE' C35-1 C36-1 C37-1 C38-1 C39-1 NET 'GROUND' C35-2 C36-2 C37-2 C38-2 C39-2 # # BULK_1V8 Bus 2x 470 uFd 2.5V case V 9 mOhm C50, C51 # VCCAUX, VCCAUX_IO, 10x 10 uFd 10V 0805 X7R C60 : C69 # VCCO Bank 0 10x 2.2 uFd 10 V 0603 X7R C70 : C79 # VCCO per Bank, 12 Banks # 940 uFd total Tant # 122 uFd total Ceramic # NET 'BULK_1V8' C50-1 C51-1 NET 'GROUND' C50-2 C51-2 NET 'BULK_1V8' C60-1 C61-1 C62-1 C63-1 C64-1 NET 'GROUND' C60-2 C61-2 C62-2 C63-2 C64-2 NET 'BULK_1V8' C65-1 C66-1 C67-1 C68-1 C69-1 NET 'GROUND' C65-2 C66-2 C67-2 C68-2 C69-2 NET 'BULK_1V8' C70-1 C71-1 C72-1 C73-1 C74-1 NET 'GROUND' C70-2 C71-2 C72-2 C73-2 C74-2 NET 'BULK_1V8' C75-1 C76-1 C77-1 C78-1 C79-1 NET 'GROUND' C75-2 C76-2 C77-2 C78-2 C79-2 # # MGT_AVCC Bus 2x 470 uFd 2.5V case V 9 mOhm C90, C91 # 1.000 V 7x 10 uFd 10V 0805 X7R C100 : C106 # 940 uFd total Tant 7x 2.2 uFd 10 V 0603 X7R C110 : C116 # 85 uFd total Ceramic # NET 'MGT_AVCC' C90-1 C91-1 NET 'GROUND' C90-2 C91-2 NET 'MGT_AVCC' C100-1 C101-1 C102-1 C103-1 C104-1 C105-1 C106-1 NET 'GROUND' C100-2 C101-2 C102-2 C103-2 C104-2 C105-2 C106-2 NET 'MGT_AVCC' C110-1 C111-1 C112-1 C113-1 C114-1 C115-1 C116-1 NET 'GROUND' C110-2 C111-2 C112-2 C113-2 C114-2 C115-2 C116-2 # # MGT_AVTT Bus 2x 470 uFd 2.5V case V 9 mOhm C120, C121 # 1.200 V 7x 10 uFd 10V 0805 X7R C130 : C136 # 940 uFd total Tant 7x 2.2 uFd 10 V 0603 X7R C140 : C146 # 85 uFd total Ceramic # NET 'MGT_AVTT' C120-1 C121-1 NET 'GROUND' C120-2 C121-2 NET 'MGT_AVTT' C130-1 C131-1 C132-1 C133-1 C134-1 C135-1 C136-1 NET 'GROUND' C130-2 C131-2 C132-2 C133-2 C134-2 C135-2 C136-2 NET 'MGT_AVTT' C140-1 C141-1 C142-1 C143-1 C144-1 C145-1 C146-1 NET 'GROUND' C140-2 C141-2 C142-2 C143-2 C144-2 C145-2 C146-2 # # MGT_AVAUX Bus 2x 470 uFd 2.5V case V 9 mOhm C150, C151 # 1.200 V 6x 10 uFd 10V 0805 X7R C160 : C165 # 940 uFd total Tant 6x 2.2 uFd 10 V 0603 X7R C170 : C175 # 73 uFd total Ceramic # NET 'MGT_AVAUX' C150-1 C151-1 NET 'GROUND' C150-2 C151-2 NET 'MGT_AVAUX' C160-1 C161-1 C162-1 C163-1 C164-1 C165-1 NET 'GROUND' C160-2 C161-2 C162-2 C163-2 C164-2 C165-2 NET 'MGT_AVAUX' C170-1 C171-1 C172-1 C173-1 C174-1 C175-1 NET 'GROUND' C170-2 C171-2 C172-2 C173-2 C174-2 C175-2 # # BULK_3V3 Bus - DCDC-8 5x 10 uFd 10V 0805 X7R C180 : C184 # VCCO per Bank 2x 2.2 uFd 10 V 0603 X7R C185 : C186 # total of 2 Banks # 54 uFd total Ceramic # NET 'BULK_3V3' C180-1 C181-1 C182-1 C183-1 C184-1 NET 'GROUND' C180-2 C181-2 C182-2 C183-2 C184-2 NET 'BULK_3V3' C185-1 C186-1 NET 'GROUND' C185-2 C186-2 # # -------------------------------------------------------------- # -------------------------------------------------------------- # # # ByPass Capacitors Under the FPGA # # # -------------------------------------------------------------- # -------------------------------------------------------------- # # # FPGA_CORE Bypass Caps Under the FPGA NET 'FPGA_CORE' C191-1 C192-1 C193-1 C194-1 C195-1 NET 'GROUND' C191-2 C192-2 C193-2 C194-2 C195-2 NET 'FPGA_CORE' C196-1 C197-1 C198-1 C199-1 C200-1 NET 'GROUND' C196-2 C197-2 C198-2 C199-2 C200-2 NET 'FPGA_CORE' C201-1 C202-1 NET 'GROUND' C201-2 C202-2 # # BULK_1V8 Bypass Caps Under the FPGA NET 'BULK_1V8' C211-1 C212-1 C213-1 C214-1 C215-1 NET 'GROUND' C211-2 C212-2 C213-2 C214-2 C215-2 NET 'BULK_1V8' C216-1 C217-1 C218-1 C219-1 NET 'GROUND' C216-2 C217-2 C218-2 C219-2 NET 'BULK_1V8' C245-1 C246-1 C247-1 C248-1 C249-1 NET 'GROUND' C245-2 C246-2 C247-2 C248-2 C249-2 # # MGT_AVCC Bypass Caps Under the FPGA NET 'MGT_AVCC' C221-1 C222-1 C223-1 C224-1 C225-1 NET 'GROUND' C221-2 C222-2 C223-2 C224-2 C225-2 NET 'MGT_AVCC' C226-1 C227-1 C228-1 C229-1 C230-1 NET 'GROUND' C226-2 C227-2 C228-2 C229-2 C230-2 NET 'MGT_AVCC' C231-1 C232-1 C233-1 C234-1 C235-1 NET 'GROUND' C231-2 C232-2 C233-2 C234-2 C235-2 NET 'MGT_AVCC' C236-1 C237-1 C238-1 NET 'GROUND' C236-2 C237-2 C238-2 # # MGT_AVTT Bypass Caps Under the FPGA NET 'MGT_AVTT' C311-1 C312-1 C313-1 C314-1 C315-1 NET 'GROUND' C311-2 C312-2 C313-2 C314-2 C315-2 NET 'MGT_AVTT' C316-1 C317-1 C318-1 C319-1 C320-1 NET 'GROUND' C316-2 C317-2 C318-2 C319-2 C320-2 NET 'MGT_AVTT' C321-1 C322-1 C323-1 C324-1 C325-1 NET 'GROUND' C321-2 C322-2 C323-2 C324-2 C325-2 NET 'MGT_AVTT' C326-1 C327-1 C328-1 NET 'GROUND' C326-2 C327-2 C328-2 # # MGT_AVAUX Bypass Caps Under the FPGA NET 'MGT_AVAUX' C331-1 C332-1 C333-1 C334-1 C335-1 NET 'GROUND' C331-2 C332-2 C333-2 C334-2 C335-2 NET 'MGT_AVAUX' C336-1 C337-1 C338-1 C339-1 C340-1 NET 'GROUND' C336-2 C337-2 C338-2 C339-2 C340-2 # # BULK_3V3 Bypass Caps Under the FPGA NET 'BULK_3V3' C241-1 C242-1 NET 'GROUND' C241-2 C242-2