//
// File created by   ListCompPinNets V2.4 on Fri Jan 20 12:00:39 2017 
//

# IO_L10P_T1U_N6_QBC_AD4P_67
set_property PACKAGE_PIN  AT30 [get_ports "ACCESS_SIGNAL_1_FROM_FPGA"] ;

# IO_L10N_T1U_N7_QBC_AD4N_67
set_property PACKAGE_PIN  AT31 [get_ports "ACCESS_SIGNAL_2_FROM_FPGA"] ;

# IO_T3U_N12_84
set_property PACKAGE_PIN  AM16 [get_ports "ALL_HUB_POWER_GOOD_TO_FPGA"] ;

# IO_L14P_T2L_N2_GC_84
set_property PACKAGE_PIN  AT15 [get_ports "CLOCK_25_MHz_FPGA"] ;

# MGTYTXN2_129
set_property PACKAGE_PIN   N41 [get_ports "Comb_Data_to_Cap_to_FEX_03_Cmp"] ;

# MGTYTXP2_129
set_property PACKAGE_PIN   N40 [get_ports "Comb_Data_to_Cap_to_FEX_03_Dir"] ;

# MGTYTXN0_130
set_property PACKAGE_PIN   L41 [get_ports "Comb_Data_to_Cap_to_FEX_04_Cmp"] ;

# MGTYTXP0_130
set_property PACKAGE_PIN   L40 [get_ports "Comb_Data_to_Cap_to_FEX_04_Dir"] ;

# MGTYTXN2_130
set_property PACKAGE_PIN   J41 [get_ports "Comb_Data_to_Cap_to_FEX_05_Cmp"] ;

# MGTYTXP2_130
set_property PACKAGE_PIN   J40 [get_ports "Comb_Data_to_Cap_to_FEX_05_Dir"] ;

# MGTYTXN3_132
set_property PACKAGE_PIN   A41 [get_ports "Comb_Data_to_Cap_to_FEX_06_Cmp"] ;

# MGTYTXP3_132
set_property PACKAGE_PIN   A40 [get_ports "Comb_Data_to_Cap_to_FEX_06_Dir"] ;

# MGTYTXN2_133
set_property PACKAGE_PIN   B39 [get_ports "Comb_Data_to_Cap_to_FEX_07_Cmp"] ;

# MGTYTXP2_133
set_property PACKAGE_PIN   B38 [get_ports "Comb_Data_to_Cap_to_FEX_07_Dir"] ;

# MGTYTXN3_133
set_property PACKAGE_PIN   A37 [get_ports "Comb_Data_to_Cap_to_FEX_08_Cmp"] ;

# MGTYTXP3_133
set_property PACKAGE_PIN   A36 [get_ports "Comb_Data_to_Cap_to_FEX_08_Dir"] ;

# MGTHTXP3_233
set_property PACKAGE_PIN   A11 [get_ports "Comb_Data_to_Cap_to_FEX_09_Cmp"] ;

# MGTHTXN3_233
set_property PACKAGE_PIN   A10 [get_ports "Comb_Data_to_Cap_to_FEX_09_Dir"] ;

# MGTHTXP2_233
set_property PACKAGE_PIN    B9 [get_ports "Comb_Data_to_Cap_to_FEX_10_Cmp"] ;

# MGTHTXN2_233
set_property PACKAGE_PIN    B8 [get_ports "Comb_Data_to_Cap_to_FEX_10_Dir"] ;

# MGTHTXP3_232
set_property PACKAGE_PIN    A7 [get_ports "Comb_Data_to_Cap_to_FEX_11_Cmp"] ;

# MGTHTXN3_232
set_property PACKAGE_PIN    A6 [get_ports "Comb_Data_to_Cap_to_FEX_11_Dir"] ;

# MGTHTXP2_230
set_property PACKAGE_PIN    J7 [get_ports "Comb_Data_to_Cap_to_FEX_12_Cmp"] ;

# MGTHTXN2_230
set_property PACKAGE_PIN    J6 [get_ports "Comb_Data_to_Cap_to_FEX_12_Dir"] ;

# MGTHTXP0_230
set_property PACKAGE_PIN    L7 [get_ports "Comb_Data_to_Cap_to_FEX_13_Cmp"] ;

# MGTHTXN0_230
set_property PACKAGE_PIN    L6 [get_ports "Comb_Data_to_Cap_to_FEX_13_Dir"] ;

# MGTHTXP2_229
set_property PACKAGE_PIN    N7 [get_ports "Comb_Data_to_Cap_to_FEX_14_Cmp"] ;

# MGTHTXN2_229
set_property PACKAGE_PIN    N6 [get_ports "Comb_Data_to_Cap_to_FEX_14_Dir"] ;

# MGTYTXN0_129
set_property PACKAGE_PIN   R41 [get_ports "Comb_Data_to_Cap_to_Other_Hub_Cmp"] ;

# MGTYTXP0_129
set_property PACKAGE_PIN   R40 [get_ports "Comb_Data_to_Cap_to_Other_Hub_Dir"] ;

# MGTHTXN0_228
set_property PACKAGE_PIN    W6 [get_ports "Comb_Data_to_Cap_to_ROD_Cmp"] ;

# MGTHTXP0_228
set_property PACKAGE_PIN    W7 [get_ports "Comb_Data_to_Cap_to_ROD_Dir"] ;

# MGTYRXP1_124
set_property PACKAGE_PIN  AP43 [get_ports "Combined_Data_from_OTHER_Hub_Cmp"] ;

# MGTYRXN1_124
set_property PACKAGE_PIN  AP44 [get_ports "Combined_Data_from_OTHER_Hub_Dir"] ;

# IO_T2U_N12_67
set_property PACKAGE_PIN  BB28 [get_ports "FPGA_RODs_SMBALERT_B"] ;

# IO_L11N_T1U_N9_GC_94
set_property PACKAGE_PIN  AV13 [get_ports "FPGA_SW_A_ATC_LOOP_DET"] ;

# IO_L1P_T0L_N0_DBC_94
set_property PACKAGE_PIN  AY15 [get_ports "FPGA_SW_A_LOOP_DETECTED"] ;

# IO_L12P_T1U_N10_GC_94
set_property PACKAGE_PIN  AW13 [get_ports "FPGA_SW_A_MDC"] ;

# IO_L2P_T0L_N2_94
set_property PACKAGE_PIN  AW15 [get_ports "FPGA_SW_A_MDIO"] ;

# IO_L14N_T2L_N3_GC_84
set_property PACKAGE_PIN  AT14 [get_ports "FPGA_SW_B_ATC_LOOP_DET"] ;

# IO_L13N_T2L_N1_GC_QBC_84
set_property PACKAGE_PIN  AU13 [get_ports "FPGA_SW_B_LOOP_DETECTED"] ;

# IO_L19P_T3L_N0_DBC_AD9P_84
set_property PACKAGE_PIN  AT16 [get_ports "FPGA_SW_B_MDC"] ;

# IO_L19N_T3L_N1_DBC_AD9N_84
set_property PACKAGE_PIN  AU16 [get_ports "FPGA_SW_B_MDIO"] ;

# IO_L22N_T3U_N7_DBC_AD0N_84
set_property PACKAGE_PIN  AV15 [get_ports "FPGA_SW_C_ATC_LOOP_DET"] ;

# IO_L22P_T3U_N6_DBC_AD0P_84
set_property PACKAGE_PIN  AV16 [get_ports "FPGA_SW_C_LOOP_DETECTED"] ;

# IO_T1U_N12_94
set_property PACKAGE_PIN  AY13 [get_ports "FPGA_SW_C_MDC"] ;

# IO_L2N_T0L_N3_94
set_property PACKAGE_PIN  AY14 [get_ports "FPGA_SW_C_MDIO"] ;

# IO_L22N_T3U_N7_DBC_AD0N_68
set_property PACKAGE_PIN  BF29 [get_ports "HUB_FPGA_LED50_DRV"] ;

# IO_L24P_T3U_N10_68
set_property PACKAGE_PIN  BF30 [get_ports "HUB_FPGA_LED51_DRV"] ;

# IO_L24N_T3U_N11_68
set_property PACKAGE_PIN  BF31 [get_ports "HUB_FPGA_LED52_DRV"] ;

# IO_L18P_T2U_N10_AD2P_67
set_property PACKAGE_PIN  BA29 [get_ports "Hub_I2C_to_FPGA_SCL"] ;

# IO_L18N_T2U_N11_AD2N_67
set_property PACKAGE_PIN  BB29 [get_ports "Hub_I2C_to_FPGA_SDA"] ;

# IO_L21N_T3L_N5_AD8N_84
set_property PACKAGE_PIN  AP16 [get_ports "Hubs_SMB_Alert_B"] ;

# IO_L3P_T0L_N4_AD15P_94
set_property PACKAGE_PIN  BA16 [get_ports "I2C_Buf_1501_ENABLE"] ;

# IO_L1N_T0L_N1_DBC_94
set_property PACKAGE_PIN  BA15 [get_ports "I2C_Buf_1502_ENABLE"] ;

# IO_L4N_T0U_N7_DBC_AD7N_94
set_property PACKAGE_PIN  BB16 [get_ports "I2C_Buf_1503_ENABLE"] ;

# IO_L15N_T2L_N5_AD11N_84
set_property PACKAGE_PIN  AT12 [get_ports "ISO_SLOT_HW_ADRS_0"] ;

# IO_T2U_N12_84
set_property PACKAGE_PIN  AT11 [get_ports "ISO_SLOT_HW_ADRS_1"] ;

# IO_L17P_T2U_N8_AD10P_84
set_property PACKAGE_PIN  AU12 [get_ports "ISO_SLOT_HW_ADRS_2"] ;

# IO_L17N_T2U_N9_AD10N_84
set_property PACKAGE_PIN  AU11 [get_ports "ISO_SLOT_HW_ADRS_3"] ;

# IO_L7P_T1L_N0_QBC_AD13P_94
set_property PACKAGE_PIN  AV11 [get_ports "ISO_SLOT_HW_ADRS_4"] ;

# IO_L12N_T1U_N11_GC_94
set_property PACKAGE_PIN  AW12 [get_ports "ISO_SLOT_HW_ADRS_5"] ;

# IO_L7N_T1L_N1_QBC_AD13N_94
set_property PACKAGE_PIN  AW11 [get_ports "ISO_SLOT_HW_ADRS_6"] ;

# IO_L9P_T1L_N4_AD12P_94
set_property PACKAGE_PIN  AY12 [get_ports "ISO_SLOT_HW_ADRS_7"] ;

# IO_L11N_T1U_N9_GC_71
set_property PACKAGE_PIN   J22 [get_ports "Logic_Clk_320.64_MHz_to_FPGA_Cmp"] ;

# IO_L11P_T1U_N8_GC_71
set_property PACKAGE_PIN   K22 [get_ports "Logic_Clk_320.64_MHz_to_FPGA_Dir"] ;

# IO_L12N_T1U_N11_GC_71
set_property PACKAGE_PIN   H24 [get_ports "Logic_Clk_40.08_MHz_to_FPGA_Cmp"] ;

# IO_L12P_T1U_N10_GC_71
set_property PACKAGE_PIN   J24 [get_ports "Logic_Clk_40.08_MHz_to_FPGA_Dir"] ;

# MGTYRXN0_128
set_property PACKAGE_PIN   W46 [get_ports "MGT_FO_CH_10_OUT_Hub_CMP"] ;

# MGTYRXP0_128
set_property PACKAGE_PIN   W45 [get_ports "MGT_FO_CH_10_OUT_Hub_DIR"] ;

# MGTYRXP3_127
set_property PACKAGE_PIN   Y43 [get_ports "MGT_FO_CH_11_OUT_Hub_CMP"] ;

# MGTYRXN3_127
set_property PACKAGE_PIN   Y44 [get_ports "MGT_FO_CH_11_OUT_Hub_DIR"] ;

# MGTYRXN2_127
set_property PACKAGE_PIN  AA46 [get_ports "MGT_FO_CH_12_OUT_Hub_CMP"] ;

# MGTYRXP2_127
set_property PACKAGE_PIN  AA45 [get_ports "MGT_FO_CH_12_OUT_Hub_DIR"] ;

# MGTYRXP1_127
set_property PACKAGE_PIN  AB43 [get_ports "MGT_FO_CH_13_OUT_Hub_CMP"] ;

# MGTYRXN1_127
set_property PACKAGE_PIN  AB44 [get_ports "MGT_FO_CH_13_OUT_Hub_DIR"] ;

# MGTYRXN0_127
set_property PACKAGE_PIN  AC46 [get_ports "MGT_FO_CH_14_OUT_Hub_CMP"] ;

# MGTYRXP0_127
set_property PACKAGE_PIN  AC45 [get_ports "MGT_FO_CH_14_OUT_Hub_DIR"] ;

# MGTYRXP3_126
set_property PACKAGE_PIN  AD43 [get_ports "MGT_FO_CH_15_OUT_Hub_CMP"] ;

# MGTYRXN3_126
set_property PACKAGE_PIN  AD44 [get_ports "MGT_FO_CH_15_OUT_Hub_DIR"] ;

# MGTYRXN2_126
set_property PACKAGE_PIN  AE46 [get_ports "MGT_FO_CH_16_OUT_Hub_CMP"] ;

# MGTYRXP2_126
set_property PACKAGE_PIN  AE45 [get_ports "MGT_FO_CH_16_OUT_Hub_DIR"] ;

# MGTYRXP1_130
set_property PACKAGE_PIN   K43 [get_ports "MGT_FO_CH_17_OUT_Hub_CMP"] ;

# MGTYRXN1_130
set_property PACKAGE_PIN   K44 [get_ports "MGT_FO_CH_17_OUT_Hub_DIR"] ;

# MGTYRXN0_130
set_property PACKAGE_PIN   L46 [get_ports "MGT_FO_CH_18_OUT_Hub_CMP"] ;

# MGTYRXP0_130
set_property PACKAGE_PIN   L45 [get_ports "MGT_FO_CH_18_OUT_Hub_DIR"] ;

# MGTYRXP3_129
set_property PACKAGE_PIN   M43 [get_ports "MGT_FO_CH_19_OUT_Hub_CMP"] ;

# MGTYRXN3_129
set_property PACKAGE_PIN   M44 [get_ports "MGT_FO_CH_19_OUT_Hub_DIR"] ;

# MGTYRXP1_126
set_property PACKAGE_PIN  AF43 [get_ports "MGT_FO_CH_1_OUT_Hub_CMP"] ;

# MGTYRXN1_126
set_property PACKAGE_PIN  AF44 [get_ports "MGT_FO_CH_1_OUT_Hub_DIR"] ;

# MGTYRXN2_129
set_property PACKAGE_PIN   N46 [get_ports "MGT_FO_CH_20_OUT_Hub_CMP"] ;

# MGTYRXP2_129
set_property PACKAGE_PIN   N45 [get_ports "MGT_FO_CH_20_OUT_Hub_DIR"] ;

# MGTYRXP1_129
set_property PACKAGE_PIN   P43 [get_ports "MGT_FO_CH_21_OUT_Hub_CMP"] ;

# MGTYRXN1_129
set_property PACKAGE_PIN   P44 [get_ports "MGT_FO_CH_21_OUT_Hub_DIR"] ;

# MGTYRXN0_129
set_property PACKAGE_PIN   R46 [get_ports "MGT_FO_CH_22_OUT_Hub_CMP"] ;

# MGTYRXP0_129
set_property PACKAGE_PIN   R45 [get_ports "MGT_FO_CH_22_OUT_Hub_DIR"] ;

# MGTYRXP3_128
set_property PACKAGE_PIN   T43 [get_ports "MGT_FO_CH_23_OUT_Hub_CMP"] ;

# MGTYRXN3_128
set_property PACKAGE_PIN   T44 [get_ports "MGT_FO_CH_23_OUT_Hub_DIR"] ;

# MGTYRXN2_128
set_property PACKAGE_PIN   U46 [get_ports "MGT_FO_CH_24_OUT_Hub_CMP"] ;

# MGTYRXP2_128
set_property PACKAGE_PIN   U45 [get_ports "MGT_FO_CH_24_OUT_Hub_DIR"] ;

# MGTYRXP3_132
set_property PACKAGE_PIN   B43 [get_ports "MGT_FO_CH_25_OUT_Hub_CMP"] ;

# MGTYRXN3_132
set_property PACKAGE_PIN   B44 [get_ports "MGT_FO_CH_25_OUT_Hub_DIR"] ;

# MGTYRXN2_132
set_property PACKAGE_PIN   C46 [get_ports "MGT_FO_CH_26_OUT_Hub_CMP"] ;

# MGTYRXP2_132
set_property PACKAGE_PIN   C45 [get_ports "MGT_FO_CH_26_OUT_Hub_DIR"] ;

# MGTYRXP1_132
set_property PACKAGE_PIN   D43 [get_ports "MGT_FO_CH_27_OUT_Hub_CMP"] ;

# MGTYRXN1_132
set_property PACKAGE_PIN   D44 [get_ports "MGT_FO_CH_27_OUT_Hub_DIR"] ;

# MGTYRXN0_132
set_property PACKAGE_PIN   E46 [get_ports "MGT_FO_CH_28_OUT_Hub_CMP"] ;

# MGTYRXP0_132
set_property PACKAGE_PIN   E45 [get_ports "MGT_FO_CH_28_OUT_Hub_DIR"] ;

# MGTYRXP1_131
set_property PACKAGE_PIN   F43 [get_ports "MGT_FO_CH_29_OUT_Hub_CMP"] ;

# MGTYRXN1_131
set_property PACKAGE_PIN   F44 [get_ports "MGT_FO_CH_29_OUT_Hub_DIR"] ;

# MGTYRXN0_126
set_property PACKAGE_PIN  AG46 [get_ports "MGT_FO_CH_2_OUT_Hub_CMP"] ;

# MGTYRXP0_126
set_property PACKAGE_PIN  AG45 [get_ports "MGT_FO_CH_2_OUT_Hub_DIR"] ;

# MGTYRXN0_131
set_property PACKAGE_PIN   G46 [get_ports "MGT_FO_CH_30_OUT_Hub_CMP"] ;

# MGTYRXP0_131
set_property PACKAGE_PIN   G45 [get_ports "MGT_FO_CH_30_OUT_Hub_DIR"] ;

# MGTYRXP3_130
set_property PACKAGE_PIN   H43 [get_ports "MGT_FO_CH_31_OUT_Hub_CMP"] ;

# MGTYRXN3_130
set_property PACKAGE_PIN   H44 [get_ports "MGT_FO_CH_31_OUT_Hub_DIR"] ;

# MGTYRXN2_130
set_property PACKAGE_PIN   J46 [get_ports "MGT_FO_CH_32_OUT_Hub_CMP"] ;

# MGTYRXP2_130
set_property PACKAGE_PIN   J45 [get_ports "MGT_FO_CH_32_OUT_Hub_DIR"] ;

# MGTHRXN2_231
set_property PACKAGE_PIN   G15 [get_ports "MGT_FO_CH_33_OUT_Hub_CMP"] ;

# MGTHRXP2_231
set_property PACKAGE_PIN   G16 [get_ports "MGT_FO_CH_33_OUT_Hub_DIR"] ;

# MGTHRXP3_231
set_property PACKAGE_PIN   E16 [get_ports "MGT_FO_CH_34_OUT_Hub_CMP"] ;

# MGTHRXN3_231
set_property PACKAGE_PIN   E15 [get_ports "MGT_FO_CH_34_OUT_Hub_DIR"] ;

# MGTYRXP3_131
set_property PACKAGE_PIN   E31 [get_ports "MGT_FO_CH_35_OUT_Hub_CMP"] ;

# MGTYRXN3_131
set_property PACKAGE_PIN   E32 [get_ports "MGT_FO_CH_35_OUT_Hub_DIR"] ;

# MGTYRXN2_131
set_property PACKAGE_PIN   G32 [get_ports "MGT_FO_CH_36_OUT_Hub_CMP"] ;

# MGTYRXP2_131
set_property PACKAGE_PIN   G31 [get_ports "MGT_FO_CH_36_OUT_Hub_DIR"] ;

# MGTYRXN3_133
set_property PACKAGE_PIN   A32 [get_ports "MGT_FO_CH_37_OUT_Hub_CMP"] ;

# MGTYRXP3_133
set_property PACKAGE_PIN   A31 [get_ports "MGT_FO_CH_37_OUT_Hub_DIR"] ;

# MGTYRXN2_133
set_property PACKAGE_PIN   B34 [get_ports "MGT_FO_CH_38_OUT_Hub_CMP"] ;

# MGTYRXP2_133
set_property PACKAGE_PIN   B33 [get_ports "MGT_FO_CH_38_OUT_Hub_DIR"] ;

# MGTYRXP1_133
set_property PACKAGE_PIN   C31 [get_ports "MGT_FO_CH_39_OUT_Hub_CMP"] ;

# MGTYRXN1_133
set_property PACKAGE_PIN   C32 [get_ports "MGT_FO_CH_39_OUT_Hub_DIR"] ;

# MGTYRXP3_125
set_property PACKAGE_PIN  AH43 [get_ports "MGT_FO_CH_3_OUT_Hub_CMP"] ;

# MGTYRXN3_125
set_property PACKAGE_PIN  AH44 [get_ports "MGT_FO_CH_3_OUT_Hub_DIR"] ;

# MGTYRXN0_133
set_property PACKAGE_PIN   D34 [get_ports "MGT_FO_CH_40_OUT_Hub_CMP"] ;

# MGTYRXP0_133
set_property PACKAGE_PIN   D33 [get_ports "MGT_FO_CH_40_OUT_Hub_DIR"] ;

# MGTHRXN0_232
set_property PACKAGE_PIN    E1 [get_ports "MGT_FO_CH_41_OUT_Hub_CMP"] ;

# MGTHRXP0_232
set_property PACKAGE_PIN    E2 [get_ports "MGT_FO_CH_41_OUT_Hub_DIR"] ;

# MGTHRXP1_232
set_property PACKAGE_PIN    D4 [get_ports "MGT_FO_CH_42_OUT_Hub_CMP"] ;

# MGTHRXN1_232
set_property PACKAGE_PIN    D3 [get_ports "MGT_FO_CH_42_OUT_Hub_DIR"] ;

# MGTHRXN2_232
set_property PACKAGE_PIN    C1 [get_ports "MGT_FO_CH_43_OUT_Hub_CMP"] ;

# MGTHRXP2_232
set_property PACKAGE_PIN    C2 [get_ports "MGT_FO_CH_43_OUT_Hub_DIR"] ;

# MGTHRXP3_232
set_property PACKAGE_PIN    B4 [get_ports "MGT_FO_CH_44_OUT_Hub_CMP"] ;

# MGTHRXN3_232
set_property PACKAGE_PIN    B3 [get_ports "MGT_FO_CH_44_OUT_Hub_DIR"] ;

# MGTHRXN0_233
set_property PACKAGE_PIN   D13 [get_ports "MGT_FO_CH_45_OUT_Hub_CMP"] ;

# MGTHRXP0_233
set_property PACKAGE_PIN   D14 [get_ports "MGT_FO_CH_45_OUT_Hub_DIR"] ;

# MGTHRXP1_233
set_property PACKAGE_PIN   C16 [get_ports "MGT_FO_CH_46_OUT_Hub_CMP"] ;

# MGTHRXN1_233
set_property PACKAGE_PIN   C15 [get_ports "MGT_FO_CH_46_OUT_Hub_DIR"] ;

# MGTHRXN2_233
set_property PACKAGE_PIN   B13 [get_ports "MGT_FO_CH_47_OUT_Hub_CMP"] ;

# MGTHRXP2_233
set_property PACKAGE_PIN   B14 [get_ports "MGT_FO_CH_47_OUT_Hub_DIR"] ;

# MGTHRXN3_233
set_property PACKAGE_PIN   A15 [get_ports "MGT_FO_CH_48_OUT_Hub_CMP"] ;

# MGTHRXP3_233
set_property PACKAGE_PIN   A16 [get_ports "MGT_FO_CH_48_OUT_Hub_DIR"] ;

# MGTHRXN2_229
set_property PACKAGE_PIN    N1 [get_ports "MGT_FO_CH_49_OUT_Hub_CMP"] ;

# MGTHRXP2_229
set_property PACKAGE_PIN    N2 [get_ports "MGT_FO_CH_49_OUT_Hub_DIR"] ;

# MGTYRXN2_125
set_property PACKAGE_PIN  AJ46 [get_ports "MGT_FO_CH_4_OUT_Hub_CMP"] ;

# MGTYRXP2_125
set_property PACKAGE_PIN  AJ45 [get_ports "MGT_FO_CH_4_OUT_Hub_DIR"] ;

# MGTHRXP3_229
set_property PACKAGE_PIN    M4 [get_ports "MGT_FO_CH_50_OUT_Hub_CMP"] ;

# MGTHRXN3_229
set_property PACKAGE_PIN    M3 [get_ports "MGT_FO_CH_50_OUT_Hub_DIR"] ;

# MGTHRXN0_230
set_property PACKAGE_PIN    L1 [get_ports "MGT_FO_CH_51_OUT_Hub_CMP"] ;

# MGTHRXP0_230
set_property PACKAGE_PIN    L2 [get_ports "MGT_FO_CH_51_OUT_Hub_DIR"] ;

# MGTHRXP1_230
set_property PACKAGE_PIN    K4 [get_ports "MGT_FO_CH_52_OUT_Hub_CMP"] ;

# MGTHRXN1_230
set_property PACKAGE_PIN    K3 [get_ports "MGT_FO_CH_52_OUT_Hub_DIR"] ;

# MGTHRXN2_230
set_property PACKAGE_PIN    J1 [get_ports "MGT_FO_CH_53_OUT_Hub_CMP"] ;

# MGTHRXP2_230
set_property PACKAGE_PIN    J2 [get_ports "MGT_FO_CH_53_OUT_Hub_DIR"] ;

# MGTHRXP3_230
set_property PACKAGE_PIN    H4 [get_ports "MGT_FO_CH_54_OUT_Hub_CMP"] ;

# MGTHRXN3_230
set_property PACKAGE_PIN    H3 [get_ports "MGT_FO_CH_54_OUT_Hub_DIR"] ;

# MGTHRXN0_231
set_property PACKAGE_PIN    G1 [get_ports "MGT_FO_CH_55_OUT_Hub_CMP"] ;

# MGTHRXP0_231
set_property PACKAGE_PIN    G2 [get_ports "MGT_FO_CH_55_OUT_Hub_DIR"] ;

# MGTHRXP1_231
set_property PACKAGE_PIN    F4 [get_ports "MGT_FO_CH_56_OUT_Hub_CMP"] ;

# MGTHRXN1_231
set_property PACKAGE_PIN    F3 [get_ports "MGT_FO_CH_56_OUT_Hub_DIR"] ;

# MGTHRXN2_227
set_property PACKAGE_PIN   AA1 [get_ports "MGT_FO_CH_57_OUT_Hub_CMP"] ;

# MGTHRXP2_227
set_property PACKAGE_PIN   AA2 [get_ports "MGT_FO_CH_57_OUT_Hub_DIR"] ;

# MGTHRXP3_227
set_property PACKAGE_PIN    Y4 [get_ports "MGT_FO_CH_58_OUT_Hub_CMP"] ;

# MGTHRXN3_227
set_property PACKAGE_PIN    Y3 [get_ports "MGT_FO_CH_58_OUT_Hub_DIR"] ;

# MGTHRXN0_228
set_property PACKAGE_PIN    W1 [get_ports "MGT_FO_CH_59_OUT_Hub_CMP"] ;

# MGTHRXP0_228
set_property PACKAGE_PIN    W2 [get_ports "MGT_FO_CH_59_OUT_Hub_DIR"] ;

# MGTYRXP1_125
set_property PACKAGE_PIN  AK43 [get_ports "MGT_FO_CH_5_OUT_Hub_CMP"] ;

# MGTYRXN1_125
set_property PACKAGE_PIN  AK44 [get_ports "MGT_FO_CH_5_OUT_Hub_DIR"] ;

# MGTHRXP1_228
set_property PACKAGE_PIN    V4 [get_ports "MGT_FO_CH_60_OUT_Hub_CMP"] ;

# MGTHRXN1_228
set_property PACKAGE_PIN    V3 [get_ports "MGT_FO_CH_60_OUT_Hub_DIR"] ;

# MGTHRXN2_228
set_property PACKAGE_PIN    U1 [get_ports "MGT_FO_CH_61_OUT_Hub_CMP"] ;

# MGTHRXP2_228
set_property PACKAGE_PIN    U2 [get_ports "MGT_FO_CH_61_OUT_Hub_DIR"] ;

# MGTHRXP3_228
set_property PACKAGE_PIN    T4 [get_ports "MGT_FO_CH_62_OUT_Hub_CMP"] ;

# MGTHRXN3_228
set_property PACKAGE_PIN    T3 [get_ports "MGT_FO_CH_62_OUT_Hub_DIR"] ;

# MGTHRXN0_229
set_property PACKAGE_PIN    R1 [get_ports "MGT_FO_CH_63_OUT_Hub_CMP"] ;

# MGTHRXP0_229
set_property PACKAGE_PIN    R2 [get_ports "MGT_FO_CH_63_OUT_Hub_DIR"] ;

# MGTHRXP1_229
set_property PACKAGE_PIN    P4 [get_ports "MGT_FO_CH_64_OUT_Hub_CMP"] ;

# MGTHRXN1_229
set_property PACKAGE_PIN    P3 [get_ports "MGT_FO_CH_64_OUT_Hub_DIR"] ;

# MGTHRXN0_225
set_property PACKAGE_PIN   AL1 [get_ports "MGT_FO_CH_65_OUT_Hub_CMP"] ;

# MGTHRXP0_225
set_property PACKAGE_PIN   AL2 [get_ports "MGT_FO_CH_65_OUT_Hub_DIR"] ;

# MGTHRXP1_225
set_property PACKAGE_PIN   AK4 [get_ports "MGT_FO_CH_66_OUT_Hub_CMP"] ;

# MGTHRXN1_225
set_property PACKAGE_PIN   AK3 [get_ports "MGT_FO_CH_66_OUT_Hub_DIR"] ;

# MGTHRXN2_225
set_property PACKAGE_PIN   AJ1 [get_ports "MGT_FO_CH_67_OUT_Hub_CMP"] ;

# MGTHRXP2_225
set_property PACKAGE_PIN   AJ2 [get_ports "MGT_FO_CH_67_OUT_Hub_DIR"] ;

# MGTHRXP3_225
set_property PACKAGE_PIN   AH4 [get_ports "MGT_FO_CH_68_OUT_Hub_CMP"] ;

# MGTHRXN3_225
set_property PACKAGE_PIN   AH3 [get_ports "MGT_FO_CH_68_OUT_Hub_DIR"] ;

# MGTHRXN0_226
set_property PACKAGE_PIN   AG1 [get_ports "MGT_FO_CH_69_OUT_Hub_CMP"] ;

# MGTHRXP0_226
set_property PACKAGE_PIN   AG2 [get_ports "MGT_FO_CH_69_OUT_Hub_DIR"] ;

# MGTYRXN0_125
set_property PACKAGE_PIN  AL46 [get_ports "MGT_FO_CH_6_OUT_Hub_CMP"] ;

# MGTYRXP0_125
set_property PACKAGE_PIN  AL45 [get_ports "MGT_FO_CH_6_OUT_Hub_DIR"] ;

# MGTHRXP1_226
set_property PACKAGE_PIN   AF4 [get_ports "MGT_FO_CH_70_OUT_Hub_CMP"] ;

# MGTHRXN1_226
set_property PACKAGE_PIN   AF3 [get_ports "MGT_FO_CH_70_OUT_Hub_DIR"] ;

# MGTHRXN2_226
set_property PACKAGE_PIN   AE1 [get_ports "MGT_FO_CH_71_OUT_Hub_CMP"] ;

# MGTHRXP2_226
set_property PACKAGE_PIN   AE2 [get_ports "MGT_FO_CH_71_OUT_Hub_DIR"] ;

# MGTHRXP3_226
set_property PACKAGE_PIN   AD4 [get_ports "MGT_FO_CH_72_OUT_Hub_CMP"] ;

# MGTHRXN3_226
set_property PACKAGE_PIN   AD3 [get_ports "MGT_FO_CH_72_OUT_Hub_DIR"] ;

# MGTHRXN0_227
set_property PACKAGE_PIN   AC1 [get_ports "MGT_FO_CH_73_OUT_Hub_CMP"] ;

# MGTHRXP0_227
set_property PACKAGE_PIN   AC2 [get_ports "MGT_FO_CH_73_OUT_Hub_DIR"] ;

# MGTHRXP1_227
set_property PACKAGE_PIN   AB4 [get_ports "MGT_FO_CH_74_OUT_Hub_CMP"] ;

# MGTHRXN1_227
set_property PACKAGE_PIN   AB3 [get_ports "MGT_FO_CH_74_OUT_Hub_DIR"] ;

# MGTYRXP3_124
set_property PACKAGE_PIN  AM43 [get_ports "MGT_FO_CH_7_OUT_Hub_CMP"] ;

# MGTYRXN3_124
set_property PACKAGE_PIN  AM44 [get_ports "MGT_FO_CH_7_OUT_Hub_DIR"] ;

# MGTYRXN2_124
set_property PACKAGE_PIN  AN46 [get_ports "MGT_FO_CH_8_OUT_Hub_CMP"] ;

# MGTYRXP2_124
set_property PACKAGE_PIN  AN45 [get_ports "MGT_FO_CH_8_OUT_Hub_DIR"] ;

# MGTYRXP1_128
set_property PACKAGE_PIN   V43 [get_ports "MGT_FO_CH_9_OUT_Hub_CMP"] ;

# MGTYRXN1_128
set_property PACKAGE_PIN   V44 [get_ports "MGT_FO_CH_9_OUT_Hub_DIR"] ;

# IO_L21N_T3L_N5_AD8N_71
set_property PACKAGE_PIN   C25 [get_ports "MGT_FO_EQU_ENB_GRP_1"] ;

# IO_L21N_T3L_N5_AD8N_72
set_property PACKAGE_PIN   A21 [get_ports "MGT_FO_EQU_ENB_GRP_10"] ;

# IO_L23P_T3U_N8_72
set_property PACKAGE_PIN   A20 [get_ports "MGT_FO_EQU_ENB_GRP_11"] ;

# IO_L23N_T3U_N9_72
set_property PACKAGE_PIN   A19 [get_ports "MGT_FO_EQU_ENB_GRP_12"] ;

# IO_L24N_T3U_N11_72
set_property PACKAGE_PIN   A18 [get_ports "MGT_FO_EQU_ENB_GRP_13"] ;

# IO_L23N_T3U_N9_71
set_property PACKAGE_PIN   A25 [get_ports "MGT_FO_EQU_ENB_GRP_2"] ;

# IO_L23P_T3U_N8_71
set_property PACKAGE_PIN   B25 [get_ports "MGT_FO_EQU_ENB_GRP_3"] ;

# IO_L20P_T3L_N2_AD1P_71
set_property PACKAGE_PIN   A24 [get_ports "MGT_FO_EQU_ENB_GRP_4"] ;

# IO_L19N_T3L_N1_DBC_AD9N_71
set_property PACKAGE_PIN   C24 [get_ports "MGT_FO_EQU_ENB_GRP_5"] ;

# IO_L24N_T3U_N11_71
set_property PACKAGE_PIN   B22 [get_ports "MGT_FO_EQU_ENB_GRP_6"] ;

# IO_L20P_T3L_N2_AD1P_72
set_property PACKAGE_PIN   D20 [get_ports "MGT_FO_EQU_ENB_GRP_7"] ;

# IO_L19P_T3L_N0_DBC_AD9P_72
set_property PACKAGE_PIN   C20 [get_ports "MGT_FO_EQU_ENB_GRP_8"] ;

# IO_L20N_T3L_N3_AD1N_71
set_property PACKAGE_PIN   A23 [get_ports "MGT_FO_EQU_ENB_GRP_9"] ;

# MGTREFCLK0N_125
set_property PACKAGE_PIN  AE37 [get_ports "MHz_320.64_COPY_0_CMP"] ;

# MGTREFCLK0P_125
set_property PACKAGE_PIN  AE36 [get_ports "MHz_320.64_COPY_0_DIR"] ;

# MGTREFCLK0N_130
set_property PACKAGE_PIN   R37 [get_ports "MHz_320.64_COPY_1_CMP"] ;

# MGTREFCLK0P_130
set_property PACKAGE_PIN   R36 [get_ports "MHz_320.64_COPY_1_DIR"] ;

# MGTREFCLK1N_132
set_property PACKAGE_PIN   K35 [get_ports "MHz_320.64_COPY_2_CMP"] ;

# MGTREFCLK1P_132
set_property PACKAGE_PIN   K34 [get_ports "MHz_320.64_COPY_2_DIR"] ;

# MGTREFCLK1N_127
set_property PACKAGE_PIN   Y35 [get_ports "MHz_320.64_COPY_3_CMP"] ;

# MGTREFCLK1P_127
set_property PACKAGE_PIN   Y34 [get_ports "MHz_320.64_COPY_3_DIR"] ;

# MGTREFCLK1N_227
set_property PACKAGE_PIN   Y12 [get_ports "MHz_320.64_COPY_6_CMP"] ;

# MGTREFCLK1P_227
set_property PACKAGE_PIN   Y13 [get_ports "MHz_320.64_COPY_6_DIR"] ;

# MGTREFCLK1N_232
set_property PACKAGE_PIN   K12 [get_ports "MHz_320.64_COPY_7_CMP"] ;

# MGTREFCLK1P_232
set_property PACKAGE_PIN   K13 [get_ports "MHz_320.64_COPY_7_DIR"] ;

# MGTREFCLK0N_230
set_property PACKAGE_PIN   R10 [get_ports "MHz_320.64_COPY_8_CMP"] ;

# MGTREFCLK0P_230
set_property PACKAGE_PIN   R11 [get_ports "MHz_320.64_COPY_8_DIR"] ;

# MGTREFCLK0N_225
set_property PACKAGE_PIN  AE10 [get_ports "MHz_320.64_COPY_9_CMP"] ;

# MGTREFCLK0P_225
set_property PACKAGE_PIN  AE11 [get_ports "MHz_320.64_COPY_9_DIR"] ;

# MGTHTXP2_227
set_property PACKAGE_PIN   AA7 [get_ports "MiniPOD_Trans_Fiber_0_Data_Cmp"] ;

# MGTHTXN2_227
set_property PACKAGE_PIN   AA6 [get_ports "MiniPOD_Trans_Fiber_0_Data_Dir"] ;

# MGTHTXP2_224
set_property PACKAGE_PIN   AN7 [get_ports "MiniPOD_Trans_Fiber_10_Data_Cmp"] ;

# MGTHTXN2_224
set_property PACKAGE_PIN   AN6 [get_ports "MiniPOD_Trans_Fiber_10_Data_Dir"] ;

# MGTHTXP0_224
set_property PACKAGE_PIN   AR7 [get_ports "MiniPOD_Trans_Fiber_11_Data_Cmp"] ;

# MGTHTXN0_224
set_property PACKAGE_PIN   AR6 [get_ports "MiniPOD_Trans_Fiber_11_Data_Dir"] ;

# MGTHTXP0_227
set_property PACKAGE_PIN   AC7 [get_ports "MiniPOD_Trans_Fiber_1_Data_Cmp"] ;

# MGTHTXN0_227
set_property PACKAGE_PIN   AC6 [get_ports "MiniPOD_Trans_Fiber_1_Data_Dir"] ;

# MGTHTXP2_226
set_property PACKAGE_PIN   AE7 [get_ports "MiniPOD_Trans_Fiber_2_Data_Cmp"] ;

# MGTHTXN2_226
set_property PACKAGE_PIN   AE6 [get_ports "MiniPOD_Trans_Fiber_2_Data_Dir"] ;

# MGTHTXP0_226
set_property PACKAGE_PIN   AG7 [get_ports "MiniPOD_Trans_Fiber_4_Data_Cmp"] ;

# MGTHTXN0_226
set_property PACKAGE_PIN   AG6 [get_ports "MiniPOD_Trans_Fiber_4_Data_Dir"] ;

# MGTHTXP2_225
set_property PACKAGE_PIN   AJ7 [get_ports "MiniPOD_Trans_Fiber_6_Data_Cmp"] ;

# MGTHTXN2_225
set_property PACKAGE_PIN   AJ6 [get_ports "MiniPOD_Trans_Fiber_6_Data_Dir"] ;

# MGTHTXP0_225
set_property PACKAGE_PIN   AL7 [get_ports "MiniPOD_Trans_Fiber_8_Data_Cmp"] ;

# MGTHTXN0_225
set_property PACKAGE_PIN   AL6 [get_ports "MiniPOD_Trans_Fiber_8_Data_Dir"] ;

# CCLK_0
set_property PACKAGE_PIN  AB16 [get_ports "NO_CONN_FPGA_BANK_0_CCLK"] ;

# IO_L3P_T0L_N4_AD15P_A26_65
set_property PACKAGE_PIN  AM19 [get_ports "NO_CONN_FPGA_BANK_65_AM19"] ;

# IO_L1P_T0L_N0_DBC_RS0_65
set_property PACKAGE_PIN  AN18 [get_ports "NO_CONN_FPGA_BANK_65_AN18"] ;

# IO_L3N_T0L_N5_AD15N_A27_65
set_property PACKAGE_PIN  AN19 [get_ports "NO_CONN_FPGA_BANK_65_AN19"] ;

# IO_L1N_T0L_N1_DBC_RS1_65
set_property PACKAGE_PIN  AP18 [get_ports "NO_CONN_FPGA_BANK_65_AP18"] ;

# IO_T1U_N12_PERSTN1_65
set_property PACKAGE_PIN  AV19 [get_ports "NO_CONN_FPGA_BANK_65_AV19"] ;

# IO_T2U_N12_CSI_ADV_B_65
set_property PACKAGE_PIN  BC21 [get_ports "NO_CONN_FPGA_BANK_65_BC21"] ;

# IO_T3U_N12_PERSTN0_65
set_property PACKAGE_PIN  BD20 [get_ports "NO_CONN_FPGA_BANK_65_BD20"] ;

# IO_L24P_T3U_N10_EMCCLK_65
set_property PACKAGE_PIN  BE20 [get_ports "NO_CONN_FPGA_BANK_65_BE20"] ;

# IO_L24N_T3U_N11_DOUT_CSO_B_65
set_property PACKAGE_PIN  BF20 [get_ports "NO_CONN_FPGA_BANK_65_BF20"] ;

# IO_L20P_T3L_N2_AD1P_70
set_property PACKAGE_PIN   A28 [get_ports "No_Conn_FPGA_A28"] ;

# IO_L20N_T3L_N3_AD1N_70
set_property PACKAGE_PIN   A29 [get_ports "No_Conn_FPGA_A29"] ;

# NC
set_property PACKAGE_PIN   A38 [get_ports "No_Conn_FPGA_A38"] ;

# NC
set_property PACKAGE_PIN   A39 [get_ports "No_Conn_FPGA_A39"] ;

# NC
set_property PACKAGE_PIN    A8 [get_ports "No_Conn_FPGA_A8"] ;

# NC
set_property PACKAGE_PIN    A9 [get_ports "No_Conn_FPGA_A9"] ;

# MGTREFCLK0N_227
set_property PACKAGE_PIN  AA10 [get_ports "No_Conn_FPGA_AA10"] ;

# MGTREFCLK0P_227
set_property PACKAGE_PIN  AA11 [get_ports "No_Conn_FPGA_AA11"] ;

# MGTREFCLK0P_127
set_property PACKAGE_PIN  AA36 [get_ports "No_Conn_FPGA_AA36"] ;

# MGTREFCLK0N_127
set_property PACKAGE_PIN  AA37 [get_ports "No_Conn_FPGA_AA37"] ;

# MGTREFCLK1N_226
set_property PACKAGE_PIN  AB12 [get_ports "No_Conn_FPGA_AB12"] ;

# MGTREFCLK1P_226
set_property PACKAGE_PIN  AB13 [get_ports "No_Conn_FPGA_AB13"] ;

# MGTREFCLK1P_126
set_property PACKAGE_PIN  AB34 [get_ports "No_Conn_FPGA_AB34"] ;

# MGTREFCLK1N_126
set_property PACKAGE_PIN  AB35 [get_ports "No_Conn_FPGA_AB35"] ;

# MGTYTXP1_127
set_property PACKAGE_PIN  AB38 [get_ports "No_Conn_FPGA_AB38"] ;

# MGTYTXN1_127
set_property PACKAGE_PIN  AB39 [get_ports "No_Conn_FPGA_AB39"] ;

# MGTHTXN1_227
set_property PACKAGE_PIN   AB8 [get_ports "No_Conn_FPGA_AB8"] ;

# MGTHTXP1_227
set_property PACKAGE_PIN   AB9 [get_ports "No_Conn_FPGA_AB9"] ;

# MGTREFCLK0N_226
set_property PACKAGE_PIN  AC10 [get_ports "No_Conn_FPGA_AC10"] ;

# MGTREFCLK0P_226
set_property PACKAGE_PIN  AC11 [get_ports "No_Conn_FPGA_AC11"] ;

# MGTREFCLK0P_126
set_property PACKAGE_PIN  AC36 [get_ports "No_Conn_FPGA_AC36"] ;

# MGTREFCLK0N_126
set_property PACKAGE_PIN  AC37 [get_ports "No_Conn_FPGA_AC37"] ;

# MGTREFCLK1N_225
set_property PACKAGE_PIN  AD12 [get_ports "No_Conn_FPGA_AD12"] ;

# MGTREFCLK1P_225
set_property PACKAGE_PIN  AD13 [get_ports "No_Conn_FPGA_AD13"] ;

# MGTREFCLK1P_125
set_property PACKAGE_PIN  AD34 [get_ports "No_Conn_FPGA_AD34"] ;

# MGTREFCLK1N_125
set_property PACKAGE_PIN  AD35 [get_ports "No_Conn_FPGA_AD35"] ;

# MGTYTXP3_126
set_property PACKAGE_PIN  AD38 [get_ports "No_Conn_FPGA_AD38"] ;

# MGTYTXN3_126
set_property PACKAGE_PIN  AD39 [get_ports "No_Conn_FPGA_AD39"] ;

# MGTHTXN3_226
set_property PACKAGE_PIN   AD8 [get_ports "No_Conn_FPGA_AD8"] ;

# MGTHTXP3_226
set_property PACKAGE_PIN   AD9 [get_ports "No_Conn_FPGA_AD9"] ;

# MGTYTXP2_126
set_property PACKAGE_PIN  AE40 [get_ports "No_Conn_FPGA_AE40"] ;

# MGTYTXN2_126
set_property PACKAGE_PIN  AE41 [get_ports "No_Conn_FPGA_AE41"] ;

# MGTREFCLK1N_224
set_property PACKAGE_PIN  AF12 [get_ports "No_Conn_FPGA_AF12"] ;

# MGTREFCLK1P_224
set_property PACKAGE_PIN  AF13 [get_ports "No_Conn_FPGA_AF13"] ;

# MGTREFCLK1P_124
set_property PACKAGE_PIN  AF34 [get_ports "No_Conn_FPGA_AF34"] ;

# MGTREFCLK1N_124
set_property PACKAGE_PIN  AF35 [get_ports "No_Conn_FPGA_AF35"] ;

# MGTYTXP1_126
set_property PACKAGE_PIN  AF38 [get_ports "No_Conn_FPGA_AF38"] ;

# MGTYTXN1_126
set_property PACKAGE_PIN  AF39 [get_ports "No_Conn_FPGA_AF39"] ;

# MGTHTXN1_226
set_property PACKAGE_PIN   AF8 [get_ports "No_Conn_FPGA_AF8"] ;

# MGTHTXP1_226
set_property PACKAGE_PIN   AF9 [get_ports "No_Conn_FPGA_AF9"] ;

# MGTREFCLK0N_224
set_property PACKAGE_PIN  AG10 [get_ports "No_Conn_FPGA_AG10"] ;

# MGTREFCLK0P_224
set_property PACKAGE_PIN  AG11 [get_ports "No_Conn_FPGA_AG11"] ;

# MGTREFCLK0P_124
set_property PACKAGE_PIN  AG36 [get_ports "No_Conn_FPGA_AG36"] ;

# MGTREFCLK0N_124
set_property PACKAGE_PIN  AG37 [get_ports "No_Conn_FPGA_AG37"] ;

# MGTYTXP0_126
set_property PACKAGE_PIN  AG40 [get_ports "No_Conn_FPGA_AG40"] ;

# MGTYTXN0_126
set_property PACKAGE_PIN  AG41 [get_ports "No_Conn_FPGA_AG41"] ;

# NC
set_property PACKAGE_PIN  AH12 [get_ports "No_Conn_FPGA_AH12"] ;

# NC
set_property PACKAGE_PIN  AH13 [get_ports "No_Conn_FPGA_AH13"] ;

# NC
set_property PACKAGE_PIN  AH34 [get_ports "No_Conn_FPGA_AH34"] ;

# NC
set_property PACKAGE_PIN  AH35 [get_ports "No_Conn_FPGA_AH35"] ;

# MGTYTXP3_125
set_property PACKAGE_PIN  AH38 [get_ports "No_Conn_FPGA_AH38"] ;

# MGTYTXN3_125
set_property PACKAGE_PIN  AH39 [get_ports "No_Conn_FPGA_AH39"] ;

# MGTHTXN3_225
set_property PACKAGE_PIN   AH8 [get_ports "No_Conn_FPGA_AH8"] ;

# MGTHTXP3_225
set_property PACKAGE_PIN   AH9 [get_ports "No_Conn_FPGA_AH9"] ;

# NC
set_property PACKAGE_PIN  AJ10 [get_ports "No_Conn_FPGA_AJ10"] ;

# NC
set_property PACKAGE_PIN  AJ11 [get_ports "No_Conn_FPGA_AJ11"] ;

# NC
set_property PACKAGE_PIN  AJ36 [get_ports "No_Conn_FPGA_AJ36"] ;

# NC
set_property PACKAGE_PIN  AJ37 [get_ports "No_Conn_FPGA_AJ37"] ;

# MGTYTXP2_125
set_property PACKAGE_PIN  AJ40 [get_ports "No_Conn_FPGA_AJ40"] ;

# MGTYTXN2_125
set_property PACKAGE_PIN  AJ41 [get_ports "No_Conn_FPGA_AJ41"] ;

# NC
set_property PACKAGE_PIN  AK12 [get_ports "No_Conn_FPGA_AK12"] ;

# NC
set_property PACKAGE_PIN  AK13 [get_ports "No_Conn_FPGA_AK13"] ;

# NC
set_property PACKAGE_PIN  AK34 [get_ports "No_Conn_FPGA_AK34"] ;

# NC
set_property PACKAGE_PIN  AK35 [get_ports "No_Conn_FPGA_AK35"] ;

# MGTYTXP1_125
set_property PACKAGE_PIN  AK38 [get_ports "No_Conn_FPGA_AK38"] ;

# MGTYTXN1_125
set_property PACKAGE_PIN  AK39 [get_ports "No_Conn_FPGA_AK39"] ;

# MGTHTXN1_225
set_property PACKAGE_PIN   AK8 [get_ports "No_Conn_FPGA_AK8"] ;

# MGTHTXP1_225
set_property PACKAGE_PIN   AK9 [get_ports "No_Conn_FPGA_AK9"] ;

# NC
set_property PACKAGE_PIN  AL10 [get_ports "No_Conn_FPGA_AL10"] ;

# NC
set_property PACKAGE_PIN  AL11 [get_ports "No_Conn_FPGA_AL11"] ;

# NC
set_property PACKAGE_PIN  AL36 [get_ports "No_Conn_FPGA_AL36"] ;

# NC
set_property PACKAGE_PIN  AL37 [get_ports "No_Conn_FPGA_AL37"] ;

# MGTYTXP0_125
set_property PACKAGE_PIN  AL40 [get_ports "No_Conn_FPGA_AL40"] ;

# MGTYTXN0_125
set_property PACKAGE_PIN  AL41 [get_ports "No_Conn_FPGA_AL41"] ;

# NC
set_property PACKAGE_PIN  AM12 [get_ports "No_Conn_FPGA_AM12"] ;

# NC
set_property PACKAGE_PIN  AM13 [get_ports "No_Conn_FPGA_AM13"] ;

# IO_L1P_T0L_N0_DBC_66
set_property PACKAGE_PIN  AM23 [get_ports "No_Conn_FPGA_AM23"] ;

# IO_L5P_T0U_N8_AD14P_66
set_property PACKAGE_PIN  AM24 [get_ports "No_Conn_FPGA_AM24"] ;

# IO_L2P_T0L_N2_66
set_property PACKAGE_PIN  AM26 [get_ports "No_Conn_FPGA_AM26"] ;

# IO_L3P_T0L_N4_AD15P_67
set_property PACKAGE_PIN  AM29 [get_ports "No_Conn_FPGA_AM29"] ;

# IO_L2P_T0L_N2_67
set_property PACKAGE_PIN  AM31 [get_ports "No_Conn_FPGA_AM31"] ;

# NC
set_property PACKAGE_PIN  AM34 [get_ports "No_Conn_FPGA_AM34"] ;

# NC
set_property PACKAGE_PIN  AM35 [get_ports "No_Conn_FPGA_AM35"] ;

# MGTYTXP3_124
set_property PACKAGE_PIN  AM38 [get_ports "No_Conn_FPGA_AM38"] ;

# MGTYTXN3_124
set_property PACKAGE_PIN  AM39 [get_ports "No_Conn_FPGA_AM39"] ;

# MGTHTXN3_224
set_property PACKAGE_PIN   AM8 [get_ports "No_Conn_FPGA_AM8"] ;

# MGTHTXP3_224
set_property PACKAGE_PIN   AM9 [get_ports "No_Conn_FPGA_AM9"] ;

# NC
set_property PACKAGE_PIN  AN10 [get_ports "No_Conn_FPGA_AN10"] ;

# NC
set_property PACKAGE_PIN  AN11 [get_ports "No_Conn_FPGA_AN11"] ;

# IO_L1N_T0L_N1_DBC_66
set_property PACKAGE_PIN  AN23 [get_ports "No_Conn_FPGA_AN23"] ;

# IO_L5N_T0U_N9_AD14N_66
set_property PACKAGE_PIN  AN24 [get_ports "No_Conn_FPGA_AN24"] ;

# IO_L4P_T0U_N6_DBC_AD7P_66
set_property PACKAGE_PIN  AN25 [get_ports "No_Conn_FPGA_AN25"] ;

# IO_L2N_T0L_N3_66
set_property PACKAGE_PIN  AN26 [get_ports "No_Conn_FPGA_AN26"] ;

# IO_L1P_T0L_N0_DBC_67
set_property PACKAGE_PIN  AN28 [get_ports "No_Conn_FPGA_AN28"] ;

# IO_L3N_T0L_N5_AD15N_67
set_property PACKAGE_PIN  AN29 [get_ports "No_Conn_FPGA_AN29"] ;

# IO_L6P_T0U_N10_AD6P_67
set_property PACKAGE_PIN  AN30 [get_ports "No_Conn_FPGA_AN30"] ;

# IO_L2N_T0L_N3_67
set_property PACKAGE_PIN  AN31 [get_ports "No_Conn_FPGA_AN31"] ;

# IO_L1P_T0L_N0_DBC_68
set_property PACKAGE_PIN  AN32 [get_ports "No_Conn_FPGA_AN32"] ;

# NC
set_property PACKAGE_PIN  AN36 [get_ports "No_Conn_FPGA_AN36"] ;

# NC
set_property PACKAGE_PIN  AN37 [get_ports "No_Conn_FPGA_AN37"] ;

# MGTYTXP2_124
set_property PACKAGE_PIN  AN40 [get_ports "No_Conn_FPGA_AN40"] ;

# MGTYTXN2_124
set_property PACKAGE_PIN  AN41 [get_ports "No_Conn_FPGA_AN41"] ;

# IO_L3P_T0L_N4_AD15P_66
set_property PACKAGE_PIN  AP22 [get_ports "No_Conn_FPGA_AP22"] ;

# IO_L3N_T0L_N5_AD15N_66
set_property PACKAGE_PIN  AP23 [get_ports "No_Conn_FPGA_AP23"] ;

# IO_L4N_T0U_N7_DBC_AD7N_66
set_property PACKAGE_PIN  AP25 [get_ports "No_Conn_FPGA_AP25"] ;

# IO_L6P_T0U_N10_AD6P_66
set_property PACKAGE_PIN  AP26 [get_ports "No_Conn_FPGA_AP26"] ;

# IO_L6N_T0U_N11_AD6N_66
set_property PACKAGE_PIN  AP27 [get_ports "No_Conn_FPGA_AP27"] ;

# IO_L1N_T0L_N1_DBC_67
set_property PACKAGE_PIN  AP28 [get_ports "No_Conn_FPGA_AP28"] ;

# IO_L6N_T0U_N11_AD6N_67
set_property PACKAGE_PIN  AP30 [get_ports "No_Conn_FPGA_AP30"] ;

# IO_L1N_T0L_N1_DBC_68
set_property PACKAGE_PIN  AP32 [get_ports "No_Conn_FPGA_AP32"] ;

# IO_L5P_T0U_N8_AD14P_68
set_property PACKAGE_PIN  AP33 [get_ports "No_Conn_FPGA_AP33"] ;

# MGTYTXP1_124
set_property PACKAGE_PIN  AP38 [get_ports "No_Conn_FPGA_AP38"] ;

# MGTYTXN1_124
set_property PACKAGE_PIN  AP39 [get_ports "No_Conn_FPGA_AP39"] ;

# MGTHTXN1_224
set_property PACKAGE_PIN   AP8 [get_ports "No_Conn_FPGA_AP8"] ;

# MGTHTXP1_224
set_property PACKAGE_PIN   AP9 [get_ports "No_Conn_FPGA_AP9"] ;

# IO_L7P_T1L_N0_QBC_AD13P_66
set_property PACKAGE_PIN  AR22 [get_ports "No_Conn_FPGA_AR22"] ;

# IO_L7N_T1L_N1_QBC_AD13N_66
set_property PACKAGE_PIN  AR23 [get_ports "No_Conn_FPGA_AR23"] ;

# IO_L8P_T1L_N2_AD5P_66
set_property PACKAGE_PIN  AR24 [get_ports "No_Conn_FPGA_AR24"] ;

# IO_L8N_T1L_N3_AD5N_66
set_property PACKAGE_PIN  AR25 [get_ports "No_Conn_FPGA_AR25"] ;

# IO_L5P_T0U_N8_AD14P_67
set_property PACKAGE_PIN  AR27 [get_ports "No_Conn_FPGA_AR27"] ;

# IO_L5N_T0U_N9_AD14N_67
set_property PACKAGE_PIN  AR28 [get_ports "No_Conn_FPGA_AR28"] ;

# IO_L4P_T0U_N6_DBC_AD7P_67
set_property PACKAGE_PIN  AR29 [get_ports "No_Conn_FPGA_AR29"] ;

# IO_L4N_T0U_N7_DBC_AD7N_67
set_property PACKAGE_PIN  AR30 [get_ports "No_Conn_FPGA_AR30"] ;

# IO_L3P_T0L_N4_AD15P_68
set_property PACKAGE_PIN  AR32 [get_ports "No_Conn_FPGA_AR32"] ;

# IO_L5N_T0U_N9_AD14N_68
set_property PACKAGE_PIN  AR33 [get_ports "No_Conn_FPGA_AR33"] ;

# IO_L2P_T0L_N2_68
set_property PACKAGE_PIN  AR34 [get_ports "No_Conn_FPGA_AR34"] ;

# MGTYTXP0_124
set_property PACKAGE_PIN  AR40 [get_ports "No_Conn_FPGA_AR40"] ;

# MGTYTXN0_124
set_property PACKAGE_PIN  AR41 [get_ports "No_Conn_FPGA_AR41"] ;

# IO_L20P_T3L_N2_AD1P_84
set_property PACKAGE_PIN  AT17 [get_ports "No_Conn_FPGA_AT17"] ;

# IO_L9P_T1L_N4_AD12P_66
set_property PACKAGE_PIN  AT22 [get_ports "No_Conn_FPGA_AT22"] ;

# IO_L12P_T1U_N10_GC_66
set_property PACKAGE_PIN  AT24 [get_ports "No_Conn_FPGA_AT24"] ;

# IO_L12N_T1U_N11_GC_66
set_property PACKAGE_PIN  AT25 [get_ports "No_Conn_FPGA_AT25"] ;

# IO_L10P_T1U_N6_QBC_AD4P_66
set_property PACKAGE_PIN  AT26 [get_ports "No_Conn_FPGA_AT26"] ;

# NC
set_property PACKAGE_PIN   AT3 [get_ports "No_Conn_FPGA_AT3"] ;

# IO_L3N_T0L_N5_AD15N_68
set_property PACKAGE_PIN  AT32 [get_ports "No_Conn_FPGA_AT32"] ;

# NC
set_property PACKAGE_PIN  AT38 [get_ports "No_Conn_FPGA_AT38"] ;

# NC
set_property PACKAGE_PIN  AT39 [get_ports "No_Conn_FPGA_AT39"] ;

# NC
set_property PACKAGE_PIN   AT4 [get_ports "No_Conn_FPGA_AT4"] ;

# NC
set_property PACKAGE_PIN  AT43 [get_ports "No_Conn_FPGA_AT43"] ;

# NC
set_property PACKAGE_PIN  AT44 [get_ports "No_Conn_FPGA_AT44"] ;

# NC
set_property PACKAGE_PIN   AT8 [get_ports "No_Conn_FPGA_AT8"] ;

# NC
set_property PACKAGE_PIN   AT9 [get_ports "No_Conn_FPGA_AT9"] ;

# NC
set_property PACKAGE_PIN   AU1 [get_ports "No_Conn_FPGA_AU1"] ;

# IO_L13P_T2L_N0_GC_QBC_84
set_property PACKAGE_PIN  AU14 [get_ports "No_Conn_FPGA_AU14"] ;

# IO_L20N_T3L_N3_AD1N_84
set_property PACKAGE_PIN  AU17 [get_ports "No_Conn_FPGA_AU17"] ;

# NC
set_property PACKAGE_PIN   AU2 [get_ports "No_Conn_FPGA_AU2"] ;

# IO_L9N_T1L_N5_AD12N_66
set_property PACKAGE_PIN  AU22 [get_ports "No_Conn_FPGA_AU22"] ;

# IO_L11P_T1U_N8_GC_66
set_property PACKAGE_PIN  AU23 [get_ports "No_Conn_FPGA_AU23"] ;

# IO_L11N_T1U_N9_GC_66
set_property PACKAGE_PIN  AU24 [get_ports "No_Conn_FPGA_AU24"] ;

# IO_L10N_T1U_N7_QBC_AD4N_66
set_property PACKAGE_PIN  AU26 [get_ports "No_Conn_FPGA_AU26"] ;

# IO_L8P_T1L_N2_AD5P_68
set_property PACKAGE_PIN  AU31 [get_ports "No_Conn_FPGA_AU31"] ;

# NC
set_property PACKAGE_PIN  AU40 [get_ports "No_Conn_FPGA_AU40"] ;

# NC
set_property PACKAGE_PIN  AU41 [get_ports "No_Conn_FPGA_AU41"] ;

# NC
set_property PACKAGE_PIN  AU45 [get_ports "No_Conn_FPGA_AU45"] ;

# NC
set_property PACKAGE_PIN  AU46 [get_ports "No_Conn_FPGA_AU46"] ;

# NC
set_property PACKAGE_PIN   AU6 [get_ports "No_Conn_FPGA_AU6"] ;

# NC
set_property PACKAGE_PIN   AU7 [get_ports "No_Conn_FPGA_AU7"] ;

# IO_L11P_T1U_N8_GC_94
set_property PACKAGE_PIN  AV14 [get_ports "No_Conn_FPGA_AV14"] ;

# IO_L13P_T2L_N0_GC_QBC_66
set_property PACKAGE_PIN  AV23 [get_ports "No_Conn_FPGA_AV23"] ;

# IO_L13N_T2L_N1_GC_QBC_66
set_property PACKAGE_PIN  AV24 [get_ports "No_Conn_FPGA_AV24"] ;

# IO_T1U_N12_66
set_property PACKAGE_PIN  AV25 [get_ports "No_Conn_FPGA_AV25"] ;

# NC
set_property PACKAGE_PIN   AV3 [get_ports "No_Conn_FPGA_AV3"] ;

# NC
set_property PACKAGE_PIN  AV38 [get_ports "No_Conn_FPGA_AV38"] ;

# NC
set_property PACKAGE_PIN  AV39 [get_ports "No_Conn_FPGA_AV39"] ;

# NC
set_property PACKAGE_PIN   AV4 [get_ports "No_Conn_FPGA_AV4"] ;

# NC
set_property PACKAGE_PIN  AV43 [get_ports "No_Conn_FPGA_AV43"] ;

# NC
set_property PACKAGE_PIN  AV44 [get_ports "No_Conn_FPGA_AV44"] ;

# NC
set_property PACKAGE_PIN   AV8 [get_ports "No_Conn_FPGA_AV8"] ;

# NC
set_property PACKAGE_PIN   AV9 [get_ports "No_Conn_FPGA_AV9"] ;

# NC
set_property PACKAGE_PIN   AW1 [get_ports "No_Conn_FPGA_AW1"] ;

# NC
set_property PACKAGE_PIN   AW2 [get_ports "No_Conn_FPGA_AW2"] ;

# IO_L14P_T2L_N2_GC_66
set_property PACKAGE_PIN  AW22 [get_ports "No_Conn_FPGA_AW22"] ;

# IO_L14N_T2L_N3_GC_66
set_property PACKAGE_PIN  AW23 [get_ports "No_Conn_FPGA_AW23"] ;

# IO_T2U_N12_66
set_property PACKAGE_PIN  AW25 [get_ports "No_Conn_FPGA_AW25"] ;

# IO_T1U_N12_67
set_property PACKAGE_PIN  AW30 [get_ports "No_Conn_FPGA_AW30"] ;

# NC
set_property PACKAGE_PIN  AW40 [get_ports "No_Conn_FPGA_AW40"] ;

# NC
set_property PACKAGE_PIN  AW41 [get_ports "No_Conn_FPGA_AW41"] ;

# NC
set_property PACKAGE_PIN  AW45 [get_ports "No_Conn_FPGA_AW45"] ;

# NC
set_property PACKAGE_PIN  AW46 [get_ports "No_Conn_FPGA_AW46"] ;

# NC
set_property PACKAGE_PIN   AW6 [get_ports "No_Conn_FPGA_AW6"] ;

# NC
set_property PACKAGE_PIN   AW7 [get_ports "No_Conn_FPGA_AW7"] ;

# IO_L6P_T0U_N10_AD6P_94
set_property PACKAGE_PIN  AY17 [get_ports "No_Conn_FPGA_AY17"] ;

# IO_L15P_T2L_N4_AD11P_66
set_property PACKAGE_PIN  AY22 [get_ports "No_Conn_FPGA_AY22"] ;

# IO_L15N_T2L_N5_AD11N_66
set_property PACKAGE_PIN  AY23 [get_ports "No_Conn_FPGA_AY23"] ;

# IO_L16P_T2U_N6_QBC_AD3P_66
set_property PACKAGE_PIN  AY24 [get_ports "No_Conn_FPGA_AY24"] ;

# IO_L18P_T2U_N10_AD2P_66
set_property PACKAGE_PIN  AY25 [get_ports "No_Conn_FPGA_AY25"] ;

# IO_L15P_T2L_N4_AD11P_67
set_property PACKAGE_PIN  AY29 [get_ports "No_Conn_FPGA_AY29"] ;

# NC
set_property PACKAGE_PIN   AY3 [get_ports "No_Conn_FPGA_AY3"] ;

# IO_L15N_T2L_N5_AD11N_67
set_property PACKAGE_PIN  AY30 [get_ports "No_Conn_FPGA_AY30"] ;

# NC
set_property PACKAGE_PIN  AY38 [get_ports "No_Conn_FPGA_AY38"] ;

# NC
set_property PACKAGE_PIN  AY39 [get_ports "No_Conn_FPGA_AY39"] ;

# NC
set_property PACKAGE_PIN   AY4 [get_ports "No_Conn_FPGA_AY4"] ;

# NC
set_property PACKAGE_PIN  AY43 [get_ports "No_Conn_FPGA_AY43"] ;

# NC
set_property PACKAGE_PIN  AY44 [get_ports "No_Conn_FPGA_AY44"] ;

# NC
set_property PACKAGE_PIN   AY8 [get_ports "No_Conn_FPGA_AY8"] ;

# NC
set_property PACKAGE_PIN   AY9 [get_ports "No_Conn_FPGA_AY9"] ;

# IO_L24P_T3U_N10_72
set_property PACKAGE_PIN   B18 [get_ports "No_Conn_FPGA_B18"] ;

# IO_L19N_T3L_N1_DBC_AD9N_72
set_property PACKAGE_PIN   B20 [get_ports "No_Conn_FPGA_B20"] ;

# IO_L21P_T3L_N4_AD8P_72
set_property PACKAGE_PIN   B21 [get_ports "No_Conn_FPGA_B21"] ;

# IO_L22N_T3U_N7_DBC_AD0N_71
set_property PACKAGE_PIN   B23 [get_ports "No_Conn_FPGA_B23"] ;

# IO_L22N_T3U_N7_DBC_AD0N_70
set_property PACKAGE_PIN   B28 [get_ports "No_Conn_FPGA_B28"] ;

# NC
set_property PACKAGE_PIN   BA1 [get_ports "No_Conn_FPGA_BA1"] ;

# IO_L6N_T0U_N11_AD6N_94
set_property PACKAGE_PIN  BA17 [get_ports "No_Conn_FPGA_BA17"] ;

# NC
set_property PACKAGE_PIN   BA2 [get_ports "No_Conn_FPGA_BA2"] ;

# IO_L17P_T2U_N8_AD10P_66
set_property PACKAGE_PIN  BA22 [get_ports "No_Conn_FPGA_BA22"] ;

# IO_L16N_T2U_N7_QBC_AD3N_66
set_property PACKAGE_PIN  BA24 [get_ports "No_Conn_FPGA_BA24"] ;

# IO_L18N_T2U_N11_AD2N_66
set_property PACKAGE_PIN  BA25 [get_ports "No_Conn_FPGA_BA25"] ;

# IO_L17P_T2U_N8_AD10P_67
set_property PACKAGE_PIN  BA26 [get_ports "No_Conn_FPGA_BA26"] ;

# IO_L16P_T2U_N6_QBC_AD3P_67
set_property PACKAGE_PIN  BA27 [get_ports "No_Conn_FPGA_BA27"] ;

# IO_L15N_T2L_N5_AD11N_68
set_property PACKAGE_PIN  BA32 [get_ports "No_Conn_FPGA_BA32"] ;

# NC
set_property PACKAGE_PIN  BA40 [get_ports "No_Conn_FPGA_BA40"] ;

# NC
set_property PACKAGE_PIN  BA41 [get_ports "No_Conn_FPGA_BA41"] ;

# NC
set_property PACKAGE_PIN  BA45 [get_ports "No_Conn_FPGA_BA45"] ;

# NC
set_property PACKAGE_PIN  BA46 [get_ports "No_Conn_FPGA_BA46"] ;

# NC
set_property PACKAGE_PIN   BA6 [get_ports "No_Conn_FPGA_BA6"] ;

# NC
set_property PACKAGE_PIN   BA7 [get_ports "No_Conn_FPGA_BA7"] ;

# IO_L4P_T0U_N6_DBC_AD7P_94
set_property PACKAGE_PIN  BB17 [get_ports "No_Conn_FPGA_BB17"] ;

# IO_L17N_T2U_N9_AD10N_66
set_property PACKAGE_PIN  BB22 [get_ports "No_Conn_FPGA_BB22"] ;

# IO_L19P_T3L_N0_DBC_AD9P_66
set_property PACKAGE_PIN  BB23 [get_ports "No_Conn_FPGA_BB23"] ;

# IO_L21P_T3L_N4_AD8P_66
set_property PACKAGE_PIN  BB24 [get_ports "No_Conn_FPGA_BB24"] ;

# IO_L17N_T2U_N9_AD10N_67
set_property PACKAGE_PIN  BB26 [get_ports "No_Conn_FPGA_BB26"] ;

# IO_L16N_T2U_N7_QBC_AD3N_67
set_property PACKAGE_PIN  BB27 [get_ports "No_Conn_FPGA_BB27"] ;

# NC
set_property PACKAGE_PIN   BB3 [get_ports "No_Conn_FPGA_BB3"] ;

# NC
set_property PACKAGE_PIN  BB38 [get_ports "No_Conn_FPGA_BB38"] ;

# NC
set_property PACKAGE_PIN  BB39 [get_ports "No_Conn_FPGA_BB39"] ;

# NC
set_property PACKAGE_PIN   BB4 [get_ports "No_Conn_FPGA_BB4"] ;

# NC
set_property PACKAGE_PIN  BB43 [get_ports "No_Conn_FPGA_BB43"] ;

# NC
set_property PACKAGE_PIN  BB44 [get_ports "No_Conn_FPGA_BB44"] ;

# NC
set_property PACKAGE_PIN   BB8 [get_ports "No_Conn_FPGA_BB8"] ;

# NC
set_property PACKAGE_PIN   BB9 [get_ports "No_Conn_FPGA_BB9"] ;

# NC
set_property PACKAGE_PIN   BC1 [get_ports "No_Conn_FPGA_BC1"] ;

# IO_T0U_N12_94
set_property PACKAGE_PIN  BC16 [get_ports "No_Conn_FPGA_BC16"] ;

# NC
set_property PACKAGE_PIN   BC2 [get_ports "No_Conn_FPGA_BC2"] ;

# IO_L19N_T3L_N1_DBC_AD9N_66
set_property PACKAGE_PIN  BC23 [get_ports "No_Conn_FPGA_BC23"] ;

# IO_L21N_T3L_N5_AD8N_66
set_property PACKAGE_PIN  BC24 [get_ports "No_Conn_FPGA_BC24"] ;

# IO_L19P_T3L_N0_DBC_AD9P_67
set_property PACKAGE_PIN  BC25 [get_ports "No_Conn_FPGA_BC25"] ;

# IO_L21P_T3L_N4_AD8P_67
set_property PACKAGE_PIN  BC26 [get_ports "No_Conn_FPGA_BC26"] ;

# IO_L24P_T3U_N10_67
set_property PACKAGE_PIN  BC28 [get_ports "No_Conn_FPGA_BC28"] ;

# IO_L19P_T3L_N0_DBC_AD9P_68
set_property PACKAGE_PIN  BC29 [get_ports "No_Conn_FPGA_BC29"] ;

# NC
set_property PACKAGE_PIN  BC40 [get_ports "No_Conn_FPGA_BC40"] ;

# NC
set_property PACKAGE_PIN  BC41 [get_ports "No_Conn_FPGA_BC41"] ;

# NC
set_property PACKAGE_PIN  BC45 [get_ports "No_Conn_FPGA_BC45"] ;

# NC
set_property PACKAGE_PIN  BC46 [get_ports "No_Conn_FPGA_BC46"] ;

# NC
set_property PACKAGE_PIN   BC6 [get_ports "No_Conn_FPGA_BC6"] ;

# NC
set_property PACKAGE_PIN   BC7 [get_ports "No_Conn_FPGA_BC7"] ;

# NC
set_property PACKAGE_PIN  BD10 [get_ports "No_Conn_FPGA_BD10"] ;

# NC
set_property PACKAGE_PIN  BD11 [get_ports "No_Conn_FPGA_BD11"] ;

# NC
set_property PACKAGE_PIN  BD13 [get_ports "No_Conn_FPGA_BD13"] ;

# NC
set_property PACKAGE_PIN  BD14 [get_ports "No_Conn_FPGA_BD14"] ;

# IO_T3U_N12_66
set_property PACKAGE_PIN  BD21 [get_ports "No_Conn_FPGA_BD21"] ;

# IO_L20P_T3L_N2_AD1P_66
set_property PACKAGE_PIN  BD22 [get_ports "No_Conn_FPGA_BD22"] ;

# IO_L23P_T3U_N8_66
set_property PACKAGE_PIN  BD23 [get_ports "No_Conn_FPGA_BD23"] ;

# IO_L19N_T3L_N1_DBC_AD9N_67
set_property PACKAGE_PIN  BD25 [get_ports "No_Conn_FPGA_BD25"] ;

# IO_L21N_T3L_N5_AD8N_67
set_property PACKAGE_PIN  BD26 [get_ports "No_Conn_FPGA_BD26"] ;

# IO_T3U_N12_67
set_property PACKAGE_PIN  BD27 [get_ports "No_Conn_FPGA_BD27"] ;

# IO_L24N_T3U_N11_67
set_property PACKAGE_PIN  BD28 [get_ports "No_Conn_FPGA_BD28"] ;

# NC
set_property PACKAGE_PIN   BD3 [get_ports "No_Conn_FPGA_BD3"] ;

# IO_L20P_T3L_N2_AD1P_68
set_property PACKAGE_PIN  BD30 [get_ports "No_Conn_FPGA_BD30"] ;

# IO_L23N_T3U_N9_68
set_property PACKAGE_PIN  BD31 [get_ports "No_Conn_FPGA_BD31"] ;

# NC
set_property PACKAGE_PIN  BD33 [get_ports "No_Conn_FPGA_BD33"] ;

# NC
set_property PACKAGE_PIN  BD34 [get_ports "No_Conn_FPGA_BD34"] ;

# NC
set_property PACKAGE_PIN  BD36 [get_ports "No_Conn_FPGA_BD36"] ;

# NC
set_property PACKAGE_PIN  BD37 [get_ports "No_Conn_FPGA_BD37"] ;

# NC
set_property PACKAGE_PIN  BD38 [get_ports "No_Conn_FPGA_BD38"] ;

# NC
set_property PACKAGE_PIN  BD39 [get_ports "No_Conn_FPGA_BD39"] ;

# NC
set_property PACKAGE_PIN   BD4 [get_ports "No_Conn_FPGA_BD4"] ;

# NC
set_property PACKAGE_PIN  BD43 [get_ports "No_Conn_FPGA_BD43"] ;

# NC
set_property PACKAGE_PIN  BD44 [get_ports "No_Conn_FPGA_BD44"] ;

# NC
set_property PACKAGE_PIN   BD8 [get_ports "No_Conn_FPGA_BD8"] ;

# NC
set_property PACKAGE_PIN   BD9 [get_ports "No_Conn_FPGA_BD9"] ;

# NC
set_property PACKAGE_PIN  BE10 [get_ports "No_Conn_FPGA_BE10"] ;

# NC
set_property PACKAGE_PIN  BE11 [get_ports "No_Conn_FPGA_BE11"] ;

# IO_L20N_T3L_N3_AD1N_66
set_property PACKAGE_PIN  BE22 [get_ports "No_Conn_FPGA_BE22"] ;

# IO_L23N_T3U_N9_66
set_property PACKAGE_PIN  BE23 [get_ports "No_Conn_FPGA_BE23"] ;

# IO_L24P_T3U_N10_66
set_property PACKAGE_PIN  BE24 [get_ports "No_Conn_FPGA_BE24"] ;

# NC
set_property PACKAGE_PIN  BE36 [get_ports "No_Conn_FPGA_BE36"] ;

# NC
set_property PACKAGE_PIN  BE37 [get_ports "No_Conn_FPGA_BE37"] ;

# NC
set_property PACKAGE_PIN  BE40 [get_ports "No_Conn_FPGA_BE40"] ;

# NC
set_property PACKAGE_PIN  BE41 [get_ports "No_Conn_FPGA_BE41"] ;

# NC
set_property PACKAGE_PIN   BE6 [get_ports "No_Conn_FPGA_BE6"] ;

# NC
set_property PACKAGE_PIN   BE7 [get_ports "No_Conn_FPGA_BE7"] ;

# NC
set_property PACKAGE_PIN  BF13 [get_ports "No_Conn_FPGA_BF13"] ;

# NC
set_property PACKAGE_PIN  BF14 [get_ports "No_Conn_FPGA_BF14"] ;

# IO_L22P_T3U_N6_DBC_AD0P_66
set_property PACKAGE_PIN  BF21 [get_ports "No_Conn_FPGA_BF21"] ;

# IO_L22N_T3U_N7_DBC_AD0N_66
set_property PACKAGE_PIN  BF22 [get_ports "No_Conn_FPGA_BF22"] ;

# IO_L24N_T3U_N11_66
set_property PACKAGE_PIN  BF24 [get_ports "No_Conn_FPGA_BF24"] ;

# NC
set_property PACKAGE_PIN   BF3 [get_ports "No_Conn_FPGA_BF3"] ;

# NC
set_property PACKAGE_PIN  BF33 [get_ports "No_Conn_FPGA_BF33"] ;

# NC
set_property PACKAGE_PIN  BF34 [get_ports "No_Conn_FPGA_BF34"] ;

# NC
set_property PACKAGE_PIN  BF38 [get_ports "No_Conn_FPGA_BF38"] ;

# NC
set_property PACKAGE_PIN  BF39 [get_ports "No_Conn_FPGA_BF39"] ;

# NC
set_property PACKAGE_PIN   BF4 [get_ports "No_Conn_FPGA_BF4"] ;

# NC
set_property PACKAGE_PIN  BF43 [get_ports "No_Conn_FPGA_BF43"] ;

# NC
set_property PACKAGE_PIN  BF44 [get_ports "No_Conn_FPGA_BF44"] ;

# NC
set_property PACKAGE_PIN   BF8 [get_ports "No_Conn_FPGA_BF8"] ;

# NC
set_property PACKAGE_PIN   BF9 [get_ports "No_Conn_FPGA_BF9"] ;

# MGTHTXN1_233
set_property PACKAGE_PIN   C10 [get_ports "No_Conn_FPGA_C10"] ;

# MGTHTXP1_233
set_property PACKAGE_PIN   C11 [get_ports "No_Conn_FPGA_C11"] ;

# IO_L22N_T3U_N7_DBC_AD0N_72
set_property PACKAGE_PIN   C18 [get_ports "No_Conn_FPGA_C18"] ;

# IO_L22P_T3U_N6_DBC_AD0P_72
set_property PACKAGE_PIN   C19 [get_ports "No_Conn_FPGA_C19"] ;

# IO_L24P_T3U_N10_71
set_property PACKAGE_PIN   C22 [get_ports "No_Conn_FPGA_C22"] ;

# IO_L22P_T3U_N6_DBC_AD0P_71
set_property PACKAGE_PIN   C23 [get_ports "No_Conn_FPGA_C23"] ;

# IO_L21P_T3L_N4_AD8P_70
set_property PACKAGE_PIN   C27 [get_ports "No_Conn_FPGA_C27"] ;

# IO_L21N_T3L_N5_AD8N_70
set_property PACKAGE_PIN   C28 [get_ports "No_Conn_FPGA_C28"] ;

# IO_L23N_T3U_N9_70
set_property PACKAGE_PIN   C29 [get_ports "No_Conn_FPGA_C29"] ;

# MGTYTXP1_133
set_property PACKAGE_PIN   C36 [get_ports "No_Conn_FPGA_C36"] ;

# MGTYTXN1_133
set_property PACKAGE_PIN   C37 [get_ports "No_Conn_FPGA_C37"] ;

# MGTYTXP2_132
set_property PACKAGE_PIN   C40 [get_ports "No_Conn_FPGA_C40"] ;

# MGTYTXN2_132
set_property PACKAGE_PIN   C41 [get_ports "No_Conn_FPGA_C41"] ;

# MGTHTXN2_232
set_property PACKAGE_PIN    C6 [get_ports "No_Conn_FPGA_C6"] ;

# MGTHTXP2_232
set_property PACKAGE_PIN    C7 [get_ports "No_Conn_FPGA_C7"] ;

# IO_L20N_T3L_N3_AD1N_72
set_property PACKAGE_PIN   D19 [get_ports "No_Conn_FPGA_D19"] ;

# IO_T3U_N12_72
set_property PACKAGE_PIN   D21 [get_ports "No_Conn_FPGA_D21"] ;

# IO_T3U_N12_71
set_property PACKAGE_PIN   D22 [get_ports "No_Conn_FPGA_D22"] ;

# IO_L19P_T3L_N0_DBC_AD9P_71
set_property PACKAGE_PIN   D24 [get_ports "No_Conn_FPGA_D24"] ;

# IO_L21P_T3L_N4_AD8P_71
set_property PACKAGE_PIN   D25 [get_ports "No_Conn_FPGA_D25"] ;

# IO_L19P_T3L_N0_DBC_AD9P_70
set_property PACKAGE_PIN   D26 [get_ports "No_Conn_FPGA_D26"] ;

# IO_L19N_T3L_N1_DBC_AD9N_70
set_property PACKAGE_PIN   D27 [get_ports "No_Conn_FPGA_D27"] ;

# IO_L23P_T3U_N8_70
set_property PACKAGE_PIN   D29 [get_ports "No_Conn_FPGA_D29"] ;

# MGTYTXP0_133
set_property PACKAGE_PIN   D38 [get_ports "No_Conn_FPGA_D38"] ;

# MGTYTXN0_133
set_property PACKAGE_PIN   D39 [get_ports "No_Conn_FPGA_D39"] ;

# MGTHTXN0_233
set_property PACKAGE_PIN    D8 [get_ports "No_Conn_FPGA_D8"] ;

# MGTHTXP0_233
set_property PACKAGE_PIN    D9 [get_ports "No_Conn_FPGA_D9"] ;

# MGTHTXN1_232
set_property PACKAGE_PIN   E10 [get_ports "No_Conn_FPGA_E10"] ;

# MGTHTXP1_232
set_property PACKAGE_PIN   E11 [get_ports "No_Conn_FPGA_E11"] ;

# IO_L18N_T2U_N11_AD2N_72
set_property PACKAGE_PIN   E18 [get_ports "No_Conn_FPGA_E18"] ;

# IO_L18P_T2U_N10_AD2P_72
set_property PACKAGE_PIN   E19 [get_ports "No_Conn_FPGA_E19"] ;

# IO_T2U_N12_72
set_property PACKAGE_PIN   E21 [get_ports "No_Conn_FPGA_E21"] ;

# IO_T2U_N12_71
set_property PACKAGE_PIN   E22 [get_ports "No_Conn_FPGA_E22"] ;

# IO_L16N_T2U_N7_QBC_AD3N_71
set_property PACKAGE_PIN   E23 [get_ports "No_Conn_FPGA_E23"] ;

# IO_L17N_T2U_N9_AD10N_71
set_property PACKAGE_PIN   E24 [get_ports "No_Conn_FPGA_E24"] ;

# IO_T3U_N12_70
set_property PACKAGE_PIN   E26 [get_ports "No_Conn_FPGA_E26"] ;

# IO_L18P_T2U_N10_AD2P_70
set_property PACKAGE_PIN   E27 [get_ports "No_Conn_FPGA_E27"] ;

# IO_L18N_T2U_N11_AD2N_70
set_property PACKAGE_PIN   E28 [get_ports "No_Conn_FPGA_E28"] ;

# IO_L17N_T2U_N9_AD10N_70
set_property PACKAGE_PIN   E29 [get_ports "No_Conn_FPGA_E29"] ;

# MGTYTXP1_132
set_property PACKAGE_PIN   E36 [get_ports "No_Conn_FPGA_E36"] ;

# MGTYTXN1_132
set_property PACKAGE_PIN   E37 [get_ports "No_Conn_FPGA_E37"] ;

# MGTYTXP0_132
set_property PACKAGE_PIN   E40 [get_ports "No_Conn_FPGA_E40"] ;

# MGTYTXN0_132
set_property PACKAGE_PIN   E41 [get_ports "No_Conn_FPGA_E41"] ;

# MGTHTXN0_232
set_property PACKAGE_PIN    E6 [get_ports "No_Conn_FPGA_E6"] ;

# MGTHTXP0_232
set_property PACKAGE_PIN    E7 [get_ports "No_Conn_FPGA_E7"] ;

# MGTHTXN3_231
set_property PACKAGE_PIN   F12 [get_ports "No_Conn_FPGA_F12"] ;

# MGTHTXP3_231
set_property PACKAGE_PIN   F13 [get_ports "No_Conn_FPGA_F13"] ;

# IO_L15N_T2L_N5_AD11N_72
set_property PACKAGE_PIN   F18 [get_ports "No_Conn_FPGA_F18"] ;

# IO_L15P_T2L_N4_AD11P_72
set_property PACKAGE_PIN   F19 [get_ports "No_Conn_FPGA_F19"] ;

# IO_L17N_T2U_N9_AD10N_72
set_property PACKAGE_PIN   F20 [get_ports "No_Conn_FPGA_F20"] ;

# IO_L18N_T2U_N11_AD2N_71
set_property PACKAGE_PIN   F21 [get_ports "No_Conn_FPGA_F21"] ;

# IO_L16P_T2U_N6_QBC_AD3P_71
set_property PACKAGE_PIN   F23 [get_ports "No_Conn_FPGA_F23"] ;

# IO_L17P_T2U_N8_AD10P_71
set_property PACKAGE_PIN   F24 [get_ports "No_Conn_FPGA_F24"] ;

# IO_L15N_T2L_N5_AD11N_71
set_property PACKAGE_PIN   F25 [get_ports "No_Conn_FPGA_F25"] ;

# IO_L16N_T2U_N7_QBC_AD3N_70
set_property PACKAGE_PIN   F26 [get_ports "No_Conn_FPGA_F26"] ;

# IO_L15N_T2L_N5_AD11N_70
set_property PACKAGE_PIN   F28 [get_ports "No_Conn_FPGA_F28"] ;

# IO_L17P_T2U_N8_AD10P_70
set_property PACKAGE_PIN   F29 [get_ports "No_Conn_FPGA_F29"] ;

# MGTYTXP3_131
set_property PACKAGE_PIN   F34 [get_ports "No_Conn_FPGA_F34"] ;

# MGTYTXN3_131
set_property PACKAGE_PIN   F35 [get_ports "No_Conn_FPGA_F35"] ;

# MGTYTXP1_131
set_property PACKAGE_PIN   F38 [get_ports "No_Conn_FPGA_F38"] ;

# MGTYTXN1_131
set_property PACKAGE_PIN   F39 [get_ports "No_Conn_FPGA_F39"] ;

# MGTHTXN1_231
set_property PACKAGE_PIN    F8 [get_ports "No_Conn_FPGA_F8"] ;

# MGTHTXP1_231
set_property PACKAGE_PIN    F9 [get_ports "No_Conn_FPGA_F9"] ;

# MGTHTXN2_231
set_property PACKAGE_PIN   G10 [get_ports "No_Conn_FPGA_G10"] ;

# MGTHTXP2_231
set_property PACKAGE_PIN   G11 [get_ports "No_Conn_FPGA_G11"] ;

# IO_L16N_T2U_N7_QBC_AD3N_72
set_property PACKAGE_PIN   G18 [get_ports "No_Conn_FPGA_G18"] ;

# IO_L17P_T2U_N8_AD10P_72
set_property PACKAGE_PIN   G20 [get_ports "No_Conn_FPGA_G20"] ;

# IO_L18P_T2U_N10_AD2P_71
set_property PACKAGE_PIN   G21 [get_ports "No_Conn_FPGA_G21"] ;

# IO_L13N_T2L_N1_GC_QBC_71
set_property PACKAGE_PIN   G22 [get_ports "No_Conn_FPGA_G22"] ;

# IO_L15P_T2L_N4_AD11P_71
set_property PACKAGE_PIN   G25 [get_ports "No_Conn_FPGA_G25"] ;

# IO_L16P_T2U_N6_QBC_AD3P_70
set_property PACKAGE_PIN   G26 [get_ports "No_Conn_FPGA_G26"] ;

# IO_T2U_N12_70
set_property PACKAGE_PIN   G27 [get_ports "No_Conn_FPGA_G27"] ;

# IO_L15P_T2L_N4_AD11P_70
set_property PACKAGE_PIN   G28 [get_ports "No_Conn_FPGA_G28"] ;

# MGTYTXP2_131
set_property PACKAGE_PIN   G36 [get_ports "No_Conn_FPGA_G36"] ;

# MGTYTXN2_131
set_property PACKAGE_PIN   G37 [get_ports "No_Conn_FPGA_G37"] ;

# MGTYTXP0_131
set_property PACKAGE_PIN   G40 [get_ports "No_Conn_FPGA_G40"] ;

# MGTYTXN0_131
set_property PACKAGE_PIN   G41 [get_ports "No_Conn_FPGA_G41"] ;

# MGTHTXN0_231
set_property PACKAGE_PIN    G6 [get_ports "No_Conn_FPGA_G6"] ;

# MGTHTXP0_231
set_property PACKAGE_PIN    G7 [get_ports "No_Conn_FPGA_G7"] ;

# MGTREFCLK1N_233
set_property PACKAGE_PIN   H12 [get_ports "No_Conn_FPGA_H12"] ;

# MGTREFCLK1P_233
set_property PACKAGE_PIN   H13 [get_ports "No_Conn_FPGA_H13"] ;

# IO_L16P_T2U_N6_QBC_AD3P_72
set_property PACKAGE_PIN   H18 [get_ports "No_Conn_FPGA_H18"] ;

# IO_L14N_T2L_N3_GC_72
set_property PACKAGE_PIN   H19 [get_ports "No_Conn_FPGA_H19"] ;

# IO_L14P_T2L_N2_GC_72
set_property PACKAGE_PIN   H20 [get_ports "No_Conn_FPGA_H20"] ;

# IO_L13P_T2L_N0_GC_QBC_71
set_property PACKAGE_PIN   H22 [get_ports "No_Conn_FPGA_H22"] ;

# IO_L9N_T1L_N5_AD12N_71
set_property PACKAGE_PIN   H25 [get_ports "No_Conn_FPGA_H25"] ;

# IO_L14N_T2L_N3_GC_70
set_property PACKAGE_PIN   H27 [get_ports "No_Conn_FPGA_H27"] ;

# IO_L13P_T2L_N0_GC_QBC_70
set_property PACKAGE_PIN   H28 [get_ports "No_Conn_FPGA_H28"] ;

# IO_L13N_T2L_N1_GC_QBC_70
set_property PACKAGE_PIN   H29 [get_ports "No_Conn_FPGA_H29"] ;

# MGTREFCLK1P_133
set_property PACKAGE_PIN   H34 [get_ports "No_Conn_FPGA_H34"] ;

# MGTREFCLK1N_133
set_property PACKAGE_PIN   H35 [get_ports "No_Conn_FPGA_H35"] ;

# MGTYTXP3_130
set_property PACKAGE_PIN   H38 [get_ports "No_Conn_FPGA_H38"] ;

# MGTYTXN3_130
set_property PACKAGE_PIN   H39 [get_ports "No_Conn_FPGA_H39"] ;

# MGTHTXN3_230
set_property PACKAGE_PIN    H8 [get_ports "No_Conn_FPGA_H8"] ;

# MGTHTXP3_230
set_property PACKAGE_PIN    H9 [get_ports "No_Conn_FPGA_H9"] ;

# MGTREFCLK0N_233
set_property PACKAGE_PIN   J10 [get_ports "No_Conn_FPGA_J10"] ;

# MGTREFCLK0P_233
set_property PACKAGE_PIN   J11 [get_ports "No_Conn_FPGA_J11"] ;

# IO_T1U_N12_72
set_property PACKAGE_PIN   J15 [get_ports "No_Conn_FPGA_J15"] ;

# IO_L10N_T1U_N7_QBC_AD4N_72
set_property PACKAGE_PIN   J16 [get_ports "No_Conn_FPGA_J16"] ;

# IO_L7N_T1L_N1_QBC_AD13N_72
set_property PACKAGE_PIN   J17 [get_ports "No_Conn_FPGA_J17"] ;

# IO_L13N_T2L_N1_GC_QBC_72
set_property PACKAGE_PIN   J19 [get_ports "No_Conn_FPGA_J19"] ;

# IO_L13P_T2L_N0_GC_QBC_72
set_property PACKAGE_PIN   J20 [get_ports "No_Conn_FPGA_J20"] ;

# IO_L10N_T1U_N7_QBC_AD4N_71
set_property PACKAGE_PIN   J21 [get_ports "No_Conn_FPGA_J21"] ;

# IO_L9P_T1L_N4_AD12P_71
set_property PACKAGE_PIN   J25 [get_ports "No_Conn_FPGA_J25"] ;

# IO_L10N_T1U_N7_QBC_AD4N_70
set_property PACKAGE_PIN   J26 [get_ports "No_Conn_FPGA_J26"] ;

# IO_L14P_T2L_N2_GC_70
set_property PACKAGE_PIN   J27 [get_ports "No_Conn_FPGA_J27"] ;

# IO_L12N_T1U_N11_GC_70
set_property PACKAGE_PIN   J29 [get_ports "No_Conn_FPGA_J29"] ;

# IO_T0U_N12_VRP_70
set_property PACKAGE_PIN   J30 [get_ports "No_Conn_FPGA_J30"] ;

# IO_L5N_T0U_N9_AD14N_70
set_property PACKAGE_PIN   J31 [get_ports "No_Conn_FPGA_J31"] ;

# IO_L3N_T0L_N5_AD15N_70
set_property PACKAGE_PIN   J32 [get_ports "No_Conn_FPGA_J32"] ;

# MGTREFCLK0P_133
set_property PACKAGE_PIN   J36 [get_ports "No_Conn_FPGA_J36"] ;

# MGTREFCLK0N_133
set_property PACKAGE_PIN   J37 [get_ports "No_Conn_FPGA_J37"] ;

# IO_L10P_T1U_N6_QBC_AD4P_72
set_property PACKAGE_PIN   K16 [get_ports "No_Conn_FPGA_K16"] ;

# IO_L7P_T1L_N0_QBC_AD13P_72
set_property PACKAGE_PIN   K17 [get_ports "No_Conn_FPGA_K17"] ;

# IO_L12N_T1U_N11_GC_72
set_property PACKAGE_PIN   K18 [get_ports "No_Conn_FPGA_K18"] ;

# IO_L12P_T1U_N10_GC_72
set_property PACKAGE_PIN   K19 [get_ports "No_Conn_FPGA_K19"] ;

# IO_L10P_T1U_N6_QBC_AD4P_71
set_property PACKAGE_PIN   K21 [get_ports "No_Conn_FPGA_K21"] ;

# IO_L8N_T1L_N3_AD5N_71
set_property PACKAGE_PIN   K23 [get_ports "No_Conn_FPGA_K23"] ;

# IO_L7N_T1L_N1_QBC_AD13N_71
set_property PACKAGE_PIN   K24 [get_ports "No_Conn_FPGA_K24"] ;

# IO_L10P_T1U_N6_QBC_AD4P_70
set_property PACKAGE_PIN   K26 [get_ports "No_Conn_FPGA_K26"] ;

# IO_L11P_T1U_N8_GC_70
set_property PACKAGE_PIN   K27 [get_ports "No_Conn_FPGA_K27"] ;

# IO_L11N_T1U_N9_GC_70
set_property PACKAGE_PIN   K28 [get_ports "No_Conn_FPGA_K28"] ;

# IO_L12P_T1U_N10_GC_70
set_property PACKAGE_PIN   K29 [get_ports "No_Conn_FPGA_K29"] ;

# IO_L5P_T0U_N8_AD14P_70
set_property PACKAGE_PIN   K31 [get_ports "No_Conn_FPGA_K31"] ;

# IO_L3P_T0L_N4_AD15P_70
set_property PACKAGE_PIN   K32 [get_ports "No_Conn_FPGA_K32"] ;

# MGTYTXP1_130
set_property PACKAGE_PIN   K38 [get_ports "No_Conn_FPGA_K38"] ;

# MGTYTXN1_130
set_property PACKAGE_PIN   K39 [get_ports "No_Conn_FPGA_K39"] ;

# MGTHTXN1_230
set_property PACKAGE_PIN    K8 [get_ports "No_Conn_FPGA_K8"] ;

# MGTHTXP1_230
set_property PACKAGE_PIN    K9 [get_ports "No_Conn_FPGA_K9"] ;

# MGTREFCLK0N_232
set_property PACKAGE_PIN   L10 [get_ports "No_Conn_FPGA_L10"] ;

# MGTREFCLK0P_232
set_property PACKAGE_PIN   L11 [get_ports "No_Conn_FPGA_L11"] ;

# IO_L8N_T1L_N3_AD5N_72
set_property PACKAGE_PIN   L15 [get_ports "No_Conn_FPGA_L15"] ;

# IO_L8P_T1L_N2_AD5P_72
set_property PACKAGE_PIN   L16 [get_ports "No_Conn_FPGA_L16"] ;

# IO_L11N_T1U_N9_GC_72
set_property PACKAGE_PIN   L18 [get_ports "No_Conn_FPGA_L18"] ;

# IO_L11P_T1U_N8_GC_72
set_property PACKAGE_PIN   L19 [get_ports "No_Conn_FPGA_L19"] ;

# IO_L9N_T1L_N5_AD12N_72
set_property PACKAGE_PIN   L20 [get_ports "No_Conn_FPGA_L20"] ;

# IO_L6N_T0U_N11_AD6N_71
set_property PACKAGE_PIN   L21 [get_ports "No_Conn_FPGA_L21"] ;

# IO_L8P_T1L_N2_AD5P_71
set_property PACKAGE_PIN   L23 [get_ports "No_Conn_FPGA_L23"] ;

# IO_L7P_T1L_N0_QBC_AD13P_71
set_property PACKAGE_PIN   L24 [get_ports "No_Conn_FPGA_L24"] ;

# IO_T1U_N12_71
set_property PACKAGE_PIN   L25 [get_ports "No_Conn_FPGA_L25"] ;

# IO_T1U_N12_70
set_property PACKAGE_PIN   L26 [get_ports "No_Conn_FPGA_L26"] ;

# IO_L9P_T1L_N4_AD12P_70
set_property PACKAGE_PIN   L28 [get_ports "No_Conn_FPGA_L28"] ;

# IO_L9N_T1L_N5_AD12N_70
set_property PACKAGE_PIN   L29 [get_ports "No_Conn_FPGA_L29"] ;

# IO_L6N_T0U_N11_AD6N_70
set_property PACKAGE_PIN   L30 [get_ports "No_Conn_FPGA_L30"] ;

# IO_L1N_T0L_N1_DBC_70
set_property PACKAGE_PIN   L31 [get_ports "No_Conn_FPGA_L31"] ;

# MGTREFCLK0P_132
set_property PACKAGE_PIN   L36 [get_ports "No_Conn_FPGA_L36"] ;

# MGTREFCLK0N_132
set_property PACKAGE_PIN   L37 [get_ports "No_Conn_FPGA_L37"] ;

# MGTREFCLK1N_231
set_property PACKAGE_PIN   M12 [get_ports "No_Conn_FPGA_M12"] ;

# MGTREFCLK1P_231
set_property PACKAGE_PIN   M13 [get_ports "No_Conn_FPGA_M13"] ;

# IO_L4N_T0U_N7_DBC_AD7N_72
set_property PACKAGE_PIN   M15 [get_ports "No_Conn_FPGA_M15"] ;

# IO_L4P_T0U_N6_DBC_AD7P_72
set_property PACKAGE_PIN   M16 [get_ports "No_Conn_FPGA_M16"] ;

# IO_L2N_T0L_N3_72
set_property PACKAGE_PIN   M17 [get_ports "No_Conn_FPGA_M17"] ;

# IO_L1N_T0L_N1_DBC_72
set_property PACKAGE_PIN   M18 [get_ports "No_Conn_FPGA_M18"] ;

# IO_L9P_T1L_N4_AD12P_72
set_property PACKAGE_PIN   M20 [get_ports "No_Conn_FPGA_M20"] ;

# IO_L6P_T0U_N10_AD6P_71
set_property PACKAGE_PIN   M21 [get_ports "No_Conn_FPGA_M21"] ;

# IO_L4N_T0U_N7_DBC_AD7N_71
set_property PACKAGE_PIN   M22 [get_ports "No_Conn_FPGA_M22"] ;

# IO_L1N_T0L_N1_DBC_71
set_property PACKAGE_PIN   M23 [get_ports "No_Conn_FPGA_M23"] ;

# IO_L3N_T0L_N5_AD15N_71
set_property PACKAGE_PIN   M25 [get_ports "No_Conn_FPGA_M25"] ;

# IO_L3P_T0L_N4_AD15P_71
set_property PACKAGE_PIN   M26 [get_ports "No_Conn_FPGA_M26"] ;

# IO_L8N_T1L_N3_AD5N_70
set_property PACKAGE_PIN   M27 [get_ports "No_Conn_FPGA_M27"] ;

# IO_L7N_T1L_N1_QBC_AD13N_70
set_property PACKAGE_PIN   M28 [get_ports "No_Conn_FPGA_M28"] ;

# IO_L6P_T0U_N10_AD6P_70
set_property PACKAGE_PIN   M30 [get_ports "No_Conn_FPGA_M30"] ;

# IO_L1P_T0L_N0_DBC_70
set_property PACKAGE_PIN   M31 [get_ports "No_Conn_FPGA_M31"] ;

# IO_L2N_T0L_N3_70
set_property PACKAGE_PIN   M32 [get_ports "No_Conn_FPGA_M32"] ;

# MGTREFCLK1P_131
set_property PACKAGE_PIN   M34 [get_ports "No_Conn_FPGA_M34"] ;

# MGTREFCLK1N_131
set_property PACKAGE_PIN   M35 [get_ports "No_Conn_FPGA_M35"] ;

# MGTYTXP3_129
set_property PACKAGE_PIN   M38 [get_ports "No_Conn_FPGA_M38"] ;

# MGTYTXN3_129
set_property PACKAGE_PIN   M39 [get_ports "No_Conn_FPGA_M39"] ;

# MGTHTXN3_229
set_property PACKAGE_PIN    M8 [get_ports "No_Conn_FPGA_M8"] ;

# MGTHTXP3_229
set_property PACKAGE_PIN    M9 [get_ports "No_Conn_FPGA_M9"] ;

# MGTREFCLK0N_231
set_property PACKAGE_PIN   N10 [get_ports "No_Conn_FPGA_N10"] ;

# MGTREFCLK0P_231
set_property PACKAGE_PIN   N11 [get_ports "No_Conn_FPGA_N11"] ;

# IO_T0U_N12_VRP_72
set_property PACKAGE_PIN   N15 [get_ports "No_Conn_FPGA_N15"] ;

# IO_L2P_T0L_N2_72
set_property PACKAGE_PIN   N17 [get_ports "No_Conn_FPGA_N17"] ;

# IO_L1P_T0L_N0_DBC_72
set_property PACKAGE_PIN   N18 [get_ports "No_Conn_FPGA_N18"] ;

# IO_L3N_T0L_N5_AD15N_72
set_property PACKAGE_PIN   N19 [get_ports "No_Conn_FPGA_N19"] ;

# IO_L5N_T0U_N9_AD14N_72
set_property PACKAGE_PIN   N20 [get_ports "No_Conn_FPGA_N20"] ;

# IO_L4P_T0U_N6_DBC_AD7P_71
set_property PACKAGE_PIN   N22 [get_ports "No_Conn_FPGA_N22"] ;

# IO_L1P_T0L_N0_DBC_71
set_property PACKAGE_PIN   N23 [get_ports "No_Conn_FPGA_N23"] ;

# IO_L2N_T0L_N3_71
set_property PACKAGE_PIN   N24 [get_ports "No_Conn_FPGA_N24"] ;

# IO_L5N_T0U_N9_AD14N_71
set_property PACKAGE_PIN   N25 [get_ports "No_Conn_FPGA_N25"] ;

# IO_L8P_T1L_N2_AD5P_70
set_property PACKAGE_PIN   N27 [get_ports "No_Conn_FPGA_N27"] ;

# IO_L7P_T1L_N0_QBC_AD13P_70
set_property PACKAGE_PIN   N28 [get_ports "No_Conn_FPGA_N28"] ;

# IO_L4P_T0U_N6_DBC_AD7P_70
set_property PACKAGE_PIN   N29 [get_ports "No_Conn_FPGA_N29"] ;

# IO_L4N_T0U_N7_DBC_AD7N_70
set_property PACKAGE_PIN   N30 [get_ports "No_Conn_FPGA_N30"] ;

# IO_L2P_T0L_N2_70
set_property PACKAGE_PIN   N32 [get_ports "No_Conn_FPGA_N32"] ;

# MGTREFCLK0P_131
set_property PACKAGE_PIN   N36 [get_ports "No_Conn_FPGA_N36"] ;

# MGTREFCLK0N_131
set_property PACKAGE_PIN   N37 [get_ports "No_Conn_FPGA_N37"] ;

# MGTREFCLK1N_230
set_property PACKAGE_PIN   P12 [get_ports "No_Conn_FPGA_P12"] ;

# MGTREFCLK1P_230
set_property PACKAGE_PIN   P13 [get_ports "No_Conn_FPGA_P13"] ;

# VREF_72
set_property PACKAGE_PIN   P15 [get_ports "No_Conn_FPGA_P15"] ;

# IO_L6N_T0U_N11_AD6N_72
set_property PACKAGE_PIN   P16 [get_ports "No_Conn_FPGA_P16"] ;

# IO_L6P_T0U_N10_AD6P_72
set_property PACKAGE_PIN   P17 [get_ports "No_Conn_FPGA_P17"] ;

# IO_L3P_T0L_N4_AD15P_72
set_property PACKAGE_PIN   P19 [get_ports "No_Conn_FPGA_P19"] ;

# IO_L5P_T0U_N8_AD14P_72
set_property PACKAGE_PIN   P20 [get_ports "No_Conn_FPGA_P20"] ;

# IO_L2P_T0L_N2_71
set_property PACKAGE_PIN   P24 [get_ports "No_Conn_FPGA_P24"] ;

# IO_L5P_T0U_N8_AD14P_71
set_property PACKAGE_PIN   P25 [get_ports "No_Conn_FPGA_P25"] ;

# VREF_70
set_property PACKAGE_PIN   P27 [get_ports "No_Conn_FPGA_P27"] ;

# MGTREFCLK1P_130
set_property PACKAGE_PIN   P34 [get_ports "No_Conn_FPGA_P34"] ;

# MGTREFCLK1N_130
set_property PACKAGE_PIN   P35 [get_ports "No_Conn_FPGA_P35"] ;

# MGTYTXP1_129
set_property PACKAGE_PIN   P38 [get_ports "No_Conn_FPGA_P38"] ;

# MGTYTXN1_129
set_property PACKAGE_PIN   P39 [get_ports "No_Conn_FPGA_P39"] ;

# MGTHTXN1_229
set_property PACKAGE_PIN    P8 [get_ports "No_Conn_FPGA_P8"] ;

# MGTHTXP1_229
set_property PACKAGE_PIN    P9 [get_ports "No_Conn_FPGA_P9"] ;

# MGTREFCLK1N_229
set_property PACKAGE_PIN   T12 [get_ports "No_Conn_FPGA_T12"] ;

# MGTREFCLK1P_229
set_property PACKAGE_PIN   T13 [get_ports "No_Conn_FPGA_T13"] ;

# MGTREFCLK1P_129
set_property PACKAGE_PIN   T34 [get_ports "No_Conn_FPGA_T34"] ;

# MGTREFCLK1N_129
set_property PACKAGE_PIN   T35 [get_ports "No_Conn_FPGA_T35"] ;

# MGTYTXP3_128
set_property PACKAGE_PIN   T38 [get_ports "No_Conn_FPGA_T38"] ;

# MGTYTXN3_128
set_property PACKAGE_PIN   T39 [get_ports "No_Conn_FPGA_T39"] ;

# MGTHTXN3_228
set_property PACKAGE_PIN    T8 [get_ports "No_Conn_FPGA_T8"] ;

# MGTHTXP3_228
set_property PACKAGE_PIN    T9 [get_ports "No_Conn_FPGA_T9"] ;

# MGTREFCLK0N_229
set_property PACKAGE_PIN   U10 [get_ports "No_Conn_FPGA_U10"] ;

# MGTREFCLK0P_229
set_property PACKAGE_PIN   U11 [get_ports "No_Conn_FPGA_U11"] ;

# MGTREFCLK0P_129
set_property PACKAGE_PIN   U36 [get_ports "No_Conn_FPGA_U36"] ;

# MGTREFCLK0N_129
set_property PACKAGE_PIN   U37 [get_ports "No_Conn_FPGA_U37"] ;

# MGTYTXP2_128
set_property PACKAGE_PIN   U40 [get_ports "No_Conn_FPGA_U40"] ;

# MGTYTXN2_128
set_property PACKAGE_PIN   U41 [get_ports "No_Conn_FPGA_U41"] ;

# MGTREFCLK1N_228
set_property PACKAGE_PIN   V12 [get_ports "No_Conn_FPGA_V12"] ;

# MGTREFCLK1P_228
set_property PACKAGE_PIN   V13 [get_ports "No_Conn_FPGA_V13"] ;

# MGTREFCLK1P_128
set_property PACKAGE_PIN   V34 [get_ports "No_Conn_FPGA_V34"] ;

# MGTREFCLK1N_128
set_property PACKAGE_PIN   V35 [get_ports "No_Conn_FPGA_V35"] ;

# MGTYTXP1_128
set_property PACKAGE_PIN   V38 [get_ports "No_Conn_FPGA_V38"] ;

# MGTYTXN1_128
set_property PACKAGE_PIN   V39 [get_ports "No_Conn_FPGA_V39"] ;

# MGTHTXN1_228
set_property PACKAGE_PIN    V8 [get_ports "No_Conn_FPGA_V8"] ;

# MGTHTXP1_228
set_property PACKAGE_PIN    V9 [get_ports "No_Conn_FPGA_V9"] ;

# MGTREFCLK0N_228
set_property PACKAGE_PIN   W10 [get_ports "No_Conn_FPGA_W10"] ;

# MGTREFCLK0P_228
set_property PACKAGE_PIN   W11 [get_ports "No_Conn_FPGA_W11"] ;

# MGTREFCLK0P_128
set_property PACKAGE_PIN   W36 [get_ports "No_Conn_FPGA_W36"] ;

# MGTREFCLK0N_128
set_property PACKAGE_PIN   W37 [get_ports "No_Conn_FPGA_W37"] ;

# MGTYTXP0_128
set_property PACKAGE_PIN   W40 [get_ports "No_Conn_FPGA_W40"] ;

# MGTYTXN0_128
set_property PACKAGE_PIN   W41 [get_ports "No_Conn_FPGA_W41"] ;

# MGTYTXP3_127
set_property PACKAGE_PIN   Y38 [get_ports "No_Conn_FPGA_Y38"] ;

# MGTYTXN3_127
set_property PACKAGE_PIN   Y39 [get_ports "No_Conn_FPGA_Y39"] ;

# MGTHTXN3_227
set_property PACKAGE_PIN    Y8 [get_ports "No_Conn_FPGA_Y8"] ;

# MGTHTXP3_227
set_property PACKAGE_PIN    Y9 [get_ports "No_Conn_FPGA_Y9"] ;

# IO_L23N_T3U_N9_67
set_property PACKAGE_PIN  BF25 [get_ports "OVERALL_ADRS_0_TO_RES_NET"] ;

# IO_L23P_T3U_N8_67
set_property PACKAGE_PIN  BE25 [get_ports "OVERALL_ADRS_1_TO_RES_NET"] ;

# IO_L20P_T3L_N2_AD1P_67
set_property PACKAGE_PIN  BF26 [get_ports "OVERALL_ADRS_2_TO_RES_NET"] ;

# IO_L22P_T3U_N6_DBC_AD0P_67
set_property PACKAGE_PIN  BE27 [get_ports "OVERALL_ADRS_3_TO_RES_NET"] ;

# IO_L20N_T3L_N3_AD1N_67
set_property PACKAGE_PIN  BF27 [get_ports "OVERALL_ADRS_4_TO_RES_NET"] ;

# IO_L22N_T3U_N7_DBC_AD0N_67
set_property PACKAGE_PIN  BE28 [get_ports "OVERALL_ADRS_5_TO_RES_NET"] ;

# IO_L22P_T3U_N6_DBC_AD0P_68
set_property PACKAGE_PIN  BE29 [get_ports "OVERALL_ADRS_6_TO_RES_NET"] ;

# IO_L20N_T3L_N3_AD1N_68
set_property PACKAGE_PIN  BE30 [get_ports "OVERALL_ADRS_7_TO_RES_NET"] ;

# IO_L24P_T3U_N10_70
set_property PACKAGE_PIN   B26 [get_ports "PLL_320.64_MHz_Lock_Detect_to_FPGA"] ;

# IO_L22P_T3U_N6_DBC_AD0P_70
set_property PACKAGE_PIN   B27 [get_ports "PLL_40.08_MHz_Lock_Detect_to_FPGA"] ;

# IO_L12P_T1U_N10_GC_68
set_property PACKAGE_PIN  AU33 [get_ports "Phys_U21_CLK125__LED_MODE"] ;

# IO_L16P_T2U_N6_QBC_AD3P_68
set_property PACKAGE_PIN  BA34 [get_ports "Phys_U21_GTX_CLK"] ;

# IO_L19N_T3L_N1_DBC_AD9N_68
set_property PACKAGE_PIN  BC30 [get_ports "Phys_U21_INT_B"] ;

# IO_L17P_T2U_N8_AD10P_68
set_property PACKAGE_PIN  BB32 [get_ports "Phys_U21_MDC"] ;

# IO_T3U_N12_68
set_property PACKAGE_PIN  BA30 [get_ports "Phys_U21_MDIO"] ;

# IO_L23P_T3U_N8_68
set_property PACKAGE_PIN  BC31 [get_ports "Phys_U21_RXD0__MODE0"] ;

# IO_L15P_T2L_N4_AD11P_68
set_property PACKAGE_PIN  AY32 [get_ports "Phys_U21_RXD1__MODE1"] ;

# IO_L17N_T2U_N9_AD10N_68
set_property PACKAGE_PIN  BB33 [get_ports "Phys_U21_RXD2__MODE2"] ;

# IO_L14N_T2L_N3_GC_68
set_property PACKAGE_PIN  AY33 [get_ports "Phys_U21_RXD3__MODE3"] ;

# IO_L11P_T1U_N8_GC_68
set_property PACKAGE_PIN  AV33 [get_ports "Phys_U21_RX_CLK__PHYAD2"] ;

# IO_L21N_T3L_N5_AD8N_68
set_property PACKAGE_PIN  BB31 [get_ports "Phys_U21_RX_DV__CLK125_EN"] ;

# IO_L18P_T2U_N10_AD2P_68
set_property PACKAGE_PIN  BA36 [get_ports "Phys_U21_TXD0"] ;

# IO_L13N_T2L_N1_GC_QBC_68
set_property PACKAGE_PIN  AY35 [get_ports "Phys_U21_TXD1"] ;

# IO_L18N_T2U_N11_AD2N_68
set_property PACKAGE_PIN  BB36 [get_ports "Phys_U21_TXD2"] ;

# IO_T2U_N12_68
set_property PACKAGE_PIN  BA35 [get_ports "Phys_U21_TXD3"] ;

# IO_L16N_T2U_N7_QBC_AD3N_68
set_property PACKAGE_PIN  BB34 [get_ports "Phys_U21_TX_EN"] ;

# IO_L13P_T2L_N0_GC_QBC_68
set_property PACKAGE_PIN  AY34 [get_ports "Phys_U22_CLK125__LED_MODE"] ;

# IO_L2N_T0L_N3_68
set_property PACKAGE_PIN  AT34 [get_ports "Phys_U22_GTX_CLK"] ;

# IO_L21P_T3L_N4_AD8P_68
set_property PACKAGE_PIN  BA31 [get_ports "Phys_U22_INT_B"] ;

# IO_L10N_T1U_N7_QBC_AD4N_68
set_property PACKAGE_PIN  AW36 [get_ports "Phys_U22_MDC"] ;

# IO_L9N_T1L_N5_AD12N_68
set_property PACKAGE_PIN  AW35 [get_ports "Phys_U22_MDIO"] ;

# IO_L9P_T1L_N4_AD12P_68
set_property PACKAGE_PIN  AV35 [get_ports "Phys_U22_RXD0__MODE0"] ;

# IO_L10P_T1U_N6_QBC_AD4P_68
set_property PACKAGE_PIN  AV36 [get_ports "Phys_U22_RXD1__MODE1"] ;

# IO_L11N_T1U_N9_GC_68
set_property PACKAGE_PIN  AV34 [get_ports "Phys_U22_RXD2__MODE2"] ;

# IO_L8N_T1L_N3_AD5N_68
set_property PACKAGE_PIN  AU32 [get_ports "Phys_U22_RXD3__MODE3"] ;

# IO_L14P_T2L_N2_GC_68
set_property PACKAGE_PIN  AW33 [get_ports "Phys_U22_RX_CLK__PHYAD2"] ;

# IO_T1U_N12_68
set_property PACKAGE_PIN  AW32 [get_ports "Phys_U22_RX_DV__CLK125_EN"] ;

# IO_L6P_T0U_N10_AD6P_68
set_property PACKAGE_PIN  AR36 [get_ports "Phys_U22_TXD0"] ;

# IO_L6N_T0U_N11_AD6N_68
set_property PACKAGE_PIN  AT36 [get_ports "Phys_U22_TXD1"] ;

# IO_L4P_T0U_N6_DBC_AD7P_68
set_property PACKAGE_PIN  AR35 [get_ports "Phys_U22_TXD2"] ;

# IO_L4N_T0U_N7_DBC_AD7N_68
set_property PACKAGE_PIN  AT35 [get_ports "Phys_U22_TXD3"] ;

# IO_L12N_T1U_N11_GC_68
set_property PACKAGE_PIN  AU34 [get_ports "Phys_U22_TX_EN"] ;

# IO_L14P_T2L_N2_GC_67
set_property PACKAGE_PIN  AW27 [get_ports "ROD_PRESENT_B_TO_FPGA"] ;

# IO_L14N_T2L_N3_GC_67
set_property PACKAGE_PIN  AW28 [get_ports "ROD_Power_Control_2_FPGA"] ;

# IO_L12N_T1U_N11_GC_67
set_property PACKAGE_PIN  AV30 [get_ports "ROD_Power_Control_3_FPGA"] ;

# IO_L12P_T1U_N10_GC_67
set_property PACKAGE_PIN  AV29 [get_ports "ROD_Power_Control_4_FPGA"] ;

# IO_L24N_T3U_N11_84
set_property PACKAGE_PIN  AR17 [get_ports "ROD_Power_Enable"] ;

# IO_L24P_T3U_N10_84
set_property PACKAGE_PIN  AP17 [get_ports "ROD_Power_Enable_B"] ;

# MGTHRXN2_224
set_property PACKAGE_PIN   AN1 [get_ports "Rec_MP_Fiber_2_to_FPGA_Cmp"] ;

# MGTHRXP2_224
set_property PACKAGE_PIN   AN2 [get_ports "Rec_MP_Fiber_2_to_FPGA_Dir"] ;

# MGTHRXN1_224
set_property PACKAGE_PIN   AP3 [get_ports "Rec_MP_Fiber_4_to_FPGA_Cmp"] ;

# MGTHRXP1_224
set_property PACKAGE_PIN   AP4 [get_ports "Rec_MP_Fiber_4_to_FPGA_Dir"] ;

# MGTHRXN0_224
set_property PACKAGE_PIN   AR1 [get_ports "Rec_MP_Fiber_6_to_FPGA_Cmp"] ;

# MGTHRXP0_224
set_property PACKAGE_PIN   AR2 [get_ports "Rec_MP_Fiber_6_to_FPGA_Dir"] ;

# MGTYRXN0_124
set_property PACKAGE_PIN  AR46 [get_ports "Rec_MP_Fiber_8_to_FPGA_Cmp"] ;

# MGTYRXP0_124
set_property PACKAGE_PIN  AR45 [get_ports "Rec_MP_Fiber_8_to_FPGA_Dir"] ;

# IO_L16P_T2U_N6_QBC_AD3P_84
set_property PACKAGE_PIN  AR15 [get_ports "Recvr_MiniPOD_INTR_B"] ;

# IO_L16N_T2U_N7_QBC_AD3N_84
set_property PACKAGE_PIN  AR14 [get_ports "Recvr_MiniPOD_RESET_B"] ;

# IO_L15P_T2L_N4_AD11P_84
set_property PACKAGE_PIN  AR12 [get_ports "Recvr_MiniPOD_SCL"] ;

# IO_L18N_T2U_N11_AD2N_84
set_property PACKAGE_PIN  AR13 [get_ports "Recvr_MiniPOD_SDA"] ;

# IO_L7N_T1L_N1_QBC_AD13N_68
set_property PACKAGE_PIN  AW31 [get_ports "Ref_40.08_MHz_from_FPGA_to_Rec_Cmp"] ;

# IO_L7P_T1L_N0_QBC_AD13P_68
set_property PACKAGE_PIN  AV31 [get_ports "Ref_40.08_MHz_from_FPGA_to_Rec_Dir"] ;

# IO_L14N_T2L_N3_GC_71
set_property PACKAGE_PIN   G23 [get_ports "Ref_40.08_MHz_from_Other_Hub_Cmp"] ;

# IO_L14P_T2L_N2_GC_71
set_property PACKAGE_PIN   H23 [get_ports "Ref_40.08_MHz_from_Other_Hub_Dir"] ;

# IO_L3N_T0L_N5_AD15N_94
set_property PACKAGE_PIN  BB15 [get_ports "SHELF_ADRS_0_TO_FPGA"] ;

# IO_L5N_T0U_N9_AD14N_94
set_property PACKAGE_PIN  BB14 [get_ports "SHELF_ADRS_1_TO_FPGA"] ;

# IO_L5P_T0U_N8_AD14P_94
set_property PACKAGE_PIN  BA14 [get_ports "SHELF_ADRS_2_TO_FPGA"] ;

# IO_L8P_T1L_N2_AD5P_94
set_property PACKAGE_PIN  BB13 [get_ports "SHELF_ADRS_3_TO_FPGA"] ;

# IO_L8N_T1L_N3_AD5N_94
set_property PACKAGE_PIN  BB12 [get_ports "SHELF_ADRS_4_TO_FPGA"] ;

# IO_L10N_T1U_N7_QBC_AD4N_94
set_property PACKAGE_PIN  BB11 [get_ports "SHELF_ADRS_5_TO_FPGA"] ;

# IO_L9N_T1L_N5_AD12N_94
set_property PACKAGE_PIN  BA12 [get_ports "SHELF_ADRS_6_TO_FPGA"] ;

# IO_L10P_T1U_N6_QBC_AD4P_94
set_property PACKAGE_PIN  BA11 [get_ports "SHELF_ADRS_7_TO_FPGA"] ;

# IO_L11N_T1U_N9_GC_67
set_property PACKAGE_PIN  AV28 [get_ports "SPARE_OSC_TO_FPGA_CMP"] ;

# IO_L11P_T1U_N8_GC_67
set_property PACKAGE_PIN  AU28 [get_ports "SPARE_OSC_TO_FPGA_DIR"] ;

# IO_L24N_T3U_N11_70
set_property PACKAGE_PIN   A26 [get_ports "Select_Input_Second_40_Fanout"] ;

# IO_L7N_T1L_N1_QBC_AD13N_67
set_property PACKAGE_PIN  AW26 [get_ports "TBD_SPARE_LINK_0_CMP"] ;

# IO_L7P_T1L_N0_QBC_AD13P_67
set_property PACKAGE_PIN  AV26 [get_ports "TBD_SPARE_LINK_0_DIR"] ;

# IO_L8N_T1L_N3_AD5N_67
set_property PACKAGE_PIN  AU27 [get_ports "TBD_SPARE_LINK_1_CMP"] ;

# IO_L8P_T1L_N2_AD5P_67
set_property PACKAGE_PIN  AT27 [get_ports "TBD_SPARE_LINK_1_DIR"] ;

# IO_L13N_T2L_N1_GC_QBC_67
set_property PACKAGE_PIN  AY28 [get_ports "TBD_SPARE_LINK_2_CMP"] ;

# IO_L13P_T2L_N0_GC_QBC_67
set_property PACKAGE_PIN  AY27 [get_ports "TBD_SPARE_LINK_2_DIR"] ;

# IO_L9N_T1L_N5_AD12N_67
set_property PACKAGE_PIN  AU29 [get_ports "TBD_SPARE_LINK_3_CMP"] ;

# IO_L9P_T1L_N4_AD12P_67
set_property PACKAGE_PIN  AT29 [get_ports "TBD_SPARE_LINK_3_DIR"] ;

# MGTHTXN0_229
set_property PACKAGE_PIN    R6 [get_ports "This_Hubs_RO_0_to_Cap_Its_ROD_Cmp"] ;

# MGTHTXP0_229
set_property PACKAGE_PIN    R7 [get_ports "This_Hubs_RO_0_to_Cap_Its_ROD_Dir"] ;

# MGTYTXN2_127
set_property PACKAGE_PIN  AA41 [get_ports "This_Hubs_RO_0_to_Cap_Other_ROD_Cmp"] ;

# MGTYTXP2_127
set_property PACKAGE_PIN  AA40 [get_ports "This_Hubs_RO_0_to_Cap_Other_ROD_Dir"] ;

# MGTHTXN2_228
set_property PACKAGE_PIN    U6 [get_ports "This_Hubs_RO_1_to_Cap_Its_ROD_Cmp"] ;

# MGTHTXP2_228
set_property PACKAGE_PIN    U7 [get_ports "This_Hubs_RO_1_to_Cap_Its_ROD_Dir"] ;

# MGTYTXP0_127
set_property PACKAGE_PIN  AC40 [get_ports "This_Hubs_RO_1_to_Cap_Other_ROD_Cmp"] ;

# MGTYTXN0_127
set_property PACKAGE_PIN  AC41 [get_ports "This_Hubs_RO_1_to_Cap_Other_ROD_Dir"] ;

# MGTHRXP3_224
set_property PACKAGE_PIN   AM4 [get_ports "This_RODs_Readout_Ctrl_to_GTH_Input_Cmp"] ;

# MGTHRXN3_224
set_property PACKAGE_PIN   AM3 [get_ports "This_RODs_Readout_Ctrl_to_GTH_Input_Dir"] ;

# IO_L21P_T3L_N4_AD8P_84
set_property PACKAGE_PIN  AN16 [get_ports "Trans_MiniPOD_INTR_B"] ;

# IO_L18P_T2U_N10_AD2P_84
set_property PACKAGE_PIN  AP13 [get_ports "Trans_MiniPOD_RESET_B"] ;

# IO_L23P_T3U_N8_84
set_property PACKAGE_PIN  AN15 [get_ports "Trans_MiniPOD_SCL"] ;

# IO_L23N_T3U_N9_84
set_property PACKAGE_PIN  AP15 [get_ports "Trans_MiniPOD_SDA"] ;