####################################################### # Configuration file for the Hub project # for use with ListCompPinNets.py Version > =2.3 # Rev 14-Dec-2016 took copy/snapshot of Components and NetList for Internal Release # Rev 09-Jan-2017 update Components and NetList # date stamp now automatic generated by mother script, just use it # Rev 20-Jan-2017 Fix Meg array dictionary and remove the +1 increment on ROD numbering # Fix ethernet transformer dictionary # Expand dictionary description for Switch's and IPMC's EEPROM pins # Cosmetic fix for 2 pin names of Zone 2 connector # Add datasheet dictionary for RJ45, # No longer skip creating ouput for components starting with "RJ" # Fix request for skipping components starting with "ESD" # Skip components starting with "X" ####################################################### ####################################################### # The list of netlist file names, as strings, to be read and parsed # The default is to read no netlist file, i.e. not very useful :-) # netfile_list = ( ) netfile_list = ( #aa_hub_0_mixed_case_net_list.txt #aa_hub_0_net_list.txt #aa_hub_0_net_list.txt.nls #aa_list_of_files_with_fpga_connection.txt #aaa_hub_0_build_all_nets.sh #aaa_hub_0_data_path_nets.sh "in_From_Mentor/Net_List/atca_esd_strip_nets", "in_From_Mentor/Net_List/atca_isolated_12v_nets", "in_From_Mentor/Net_List/atca_power_entry_nets", "in_From_Mentor/Net_List/backplane_no_conn_pin_nets", "in_From_Mentor/Net_List/bank_0_and_bank_65_config_mem_nets", "in_From_Mentor/Net_List/clock_40.08_MHz_distribution_nets", "in_From_Mentor/Net_List/clock_generation_nets", "in_From_Mentor/Net_List/combined_data_distribution_nets", "in_From_Mentor/Net_List/dcdc_1_converter_nets", "in_From_Mentor/Net_List/dcdc_2_converter_nets", "in_From_Mentor/Net_List/dcdc_3_converter_nets", "in_From_Mentor/Net_List/dcdc_4_converter_nets", "in_From_Mentor/Net_List/dcdc_5_converter_nets", "in_From_Mentor/Net_List/dcdc_6_converter_nets", "in_From_Mentor/Net_List/dcdc_7_converter_nets", "in_From_Mentor/Net_List/dcdc_8_converter_nets", "in_From_Mentor/Net_List/dcdc_9_converter_nets", "in_From_Mentor/Net_List/dcdc_bulk_input_filter_nets", "in_From_Mentor/Net_List/distributed_bypass_cap_nets", "in_From_Mentor/Net_List/hardware_address_to_rod_nets", "in_From_Mentor/Net_List/hub_0_all_other_nets", "in_From_Mentor/Net_List/hub_all_other_mgt_nets", "in_From_Mentor/Net_List/i2c_sensor_bus_nets", "in_From_Mentor/Net_List/ipmc_hw_adrs_handle_switch_ipmb_nets", #ipmc_net_names_raw "in_From_Mentor/Net_List/ipmc_power_ground_and_nc_nets", "in_From_Mentor/Net_List/jtag_and_associated_nets", "in_From_Mentor/Net_List/led_connection_nets", "in_From_Mentor/Net_List/led_lemo_translator_driver_nets", "in_From_Mentor/Net_List/meg_array_1_power_ground_nets", "in_From_Mentor/Net_List/meg_array_2_ground_nets", "in_From_Mentor/Net_List/meg_array_reserved_and_spare_pins", "in_From_Mentor/Net_List/mgt_fanout_channel_nets", "in_From_Mentor/Net_List/minipod_pow_gnd_ctrl_no_conn_nets", "in_From_Mentor/Net_List/power_supply_all_other_nets", "in_From_Mentor/Net_List/rgmii_phys_chip_power_gnd_nets", "in_From_Mentor/Net_List/rgmii_phys_chip_u21_nets", "in_From_Mentor/Net_List/rgmii_phys_chip_u22_nets", "in_From_Mentor/Net_List/rj1_trns1_nets", "in_From_Mentor/Net_List/rod_to_from_hub_spare_nets", "in_From_Mentor/Net_List/sundry_hub_nets", #switch_chip_net_names_raw #switch_chip_nets_all_other_raw "in_From_Mentor/Net_List/switch_chip_to_cap_coupled_nets", "in_From_Mentor/Net_List/switch_chips_all_other_nets", "in_From_Mentor/Net_List/switch_chips_no_conn_nets", "in_From_Mentor/Net_List/switch_chips_power_and_ground_nets", "in_From_Mentor/Net_List/switch_chips_to_adf_conn_nets", "in_From_Mentor/Net_List/switch_chips_to_rj2_conn_nets", "in_From_Mentor/Net_List/switch_chips_to_rj3_conn_nets", "in_From_Mentor/Net_List/ultra_dci_vref_mgt_calib_resistors_nets", "in_From_Mentor/Net_List/ultra_fpga_bypass_cap_nets", "in_From_Mentor/Net_List/ultra_fpga_power_ground_nets", "in_From_Mentor/Net_List/ultra_fpga_to_phys_chips_nets", "in_From_Mentor/Net_List/ultra_no_connect_pins_nets", #xcvu125_flvc2104_pkgpinout_formatted.txt, #xcvu125_flvc2104_pkgpinout_gth_gty.txt, #xcvu125_flvc2104_pkgpinout_raw_unix.txt "in_From_Mentor/Net_List/zone_2_connector_ground_nets", ) # Or we could instead have grabbed the whole netlist (either mixed case or uppercase) # but the index of pin name versus source file name and line number would be less useful # #netfile_list = ( #"Net_Lists\aa_hub_0_net_list.txt", # for windows #"../../Net_Lists/aa_hub_0_net_list.txt", # on moto #"../../aa_hub_0_mixed_case_net_list.txt", #) ####################################################### # This sets a path for all output files (the path must end with a /) # This path may be obsolute or relative, but must already exist. # This path does not apply to the logfile which is always opened # in the local working directory before this configuration file is executed. # This is optional and the default is the local working directory # output_dir_name = "./" output_dir_name = "out_Comp_Pin_Nets_%s/" % current_time_stamp ####################################################### # specify a list of component prefixes # for which the output file will be skipped # This is optional and the default is to skip nothing # The filter is case-NONsensitive -> the list must use uppercase while any case combination is filtered out # skip_comp_prefix = () skip_comp_prefix = ( "R", # Resistor "C", # Capacitance "L", # Inductance "F", # Fuse "DZ", # Zerner Diode "Q", # Transistor "X", # Not a part, used for grounding "SW", # Switch "K", # Guide Pin "DPV", # Differential Pair vias "DPVSG", # Differential Pair vias - Single Ground "WTERM", # Wire Terminal "LE", # LED "JMP", # Jumper "AKA", # Remote Sense Connections "VR", # Ground Rivet "ESD_STRIP_FO", # ESD strip grounding "ESD_STRIP_MB", # ESD strip grounding "ROD_MEZZANINE", # ROD mountinc screws and silkscreen "HS", # Heat Sink # skip some connectors "J1", # Lemo "J2", # Front Panel "J3", # Voltage Monitor # Power Via Arrays "PVA1_DC", "PVA2_DC", "PVA3_DC", "PVA4_DC", "PVA5_DC", "PVA6_DC", "PVA7_DC", "PVA8_DC", "PVA9_DC", "PVA10_DC", "PVA11_DC", "PVA12_DC", "PVA13_DC", "PVA14_DC", "PVA15_DC", "PVA16_DC", "PVA17_DC", "PVA18_DC", "PVA19_DC", "PVA20_DC", "PVA21_DC", "PVA1_CLK", "PVA2_CLK", "PVA3_CLK", "PVA4_CLK", "PVA11_CLK", "PVA12_CLK", "PVA13_CLK", "PVA14_CLK", "PVA15_CLK", "PVA16_CLK", ) ####################################################### # If a Mentor component file is given here, # the name of the output files will include the component name. # e.g. U31_has_328_pins_is_IC_BCM53128.txt # This is optional and the default is to not read a component file # component_file_name = "" component_file_name = "in_From_Mentor/Components/aa_hub_0_comp_file.txt" ####################################################### # list of files defining component type pin name dictionaries called "comp_type_pin_name_dict_list" comp_type_pin_name_dict_list = ( "in_Datasheet_Pin_Names/Fpga_VCU125.dct", "in_Datasheet_Pin_Names/Fpga_Flash.dct", "in_Datasheet_Pin_Names/PowerSupplies.dct", "in_Datasheet_Pin_Names/Clock_40MHz.dct", "in_Datasheet_Pin_Names/Clock_320MHz.dct", "in_Datasheet_Pin_Names/Clock_25MHz.dct", "in_Datasheet_Pin_Names/Eth_Switch.dct", "in_Datasheet_Pin_Names/Eth_Prom.dct", "in_Datasheet_Pin_Names/Eth_PhysChip.dct", "in_Datasheet_Pin_Names/Eth_Transf.dct", "in_Datasheet_Pin_Names/Eth_RJ45.dct", "in_Datasheet_Pin_Names/MiniPOD.dct", "in_Datasheet_Pin_Names/IPMC.dct", "in_Datasheet_Pin_Names/MGT_Fanout.dct", "in_Datasheet_Pin_Names/LevelTranslators.dct", "in_Datasheet_Pin_Names/LogicGates.dct", "in_Datasheet_Pin_Names/I2C_Misc.dct", "in_Datasheet_Pin_Names/MegArrays.dct", "in_Datasheet_Pin_Names/ATCA.dct", ) ####################################################### # If this variable is set to True each output line that lists a pin name # will also show the pin name/description/usage for that component type, if it was made available # e.g.: # A6 = COMB_DATA_TO_CAP_TO_FEX_11_DIR MGTHTXN3_232 # This is optional and the default is to skip including pin names # include_pin_name = False include_pin_name = True ####################################################### # If this variable is set to True each output line that lists a pin name # will also show which line of which net file it was read from. # e.g.: # 1 = LED_30_Cath_Res from line 184 of led_connection_nets # This is optional and the default is skip generating an index #include_index = False include_index = True ####################################################### # If this variable is set to False the section listing the pins sorted by pin number will be omitted # e.g.: # 1 = LED_30_Cath_Res # 2 = No_Conn_SW_A_LEDP30_IMP_TXC_DELAY # 3 = BULK_3V3 # ... # This is optional and the default is to include this list. # include_sort_by_pin = True ####################################################### # If this variable is set to False the section listing the pins sorted by net tname will be omitted # e.g.: # ... # 202 = Chip_A_TRD0_0_CMP # 201 = Chip_A_TRD0_0_DIR # 222 = Chip_A_TRD0_1_CMP # ... # This is optional and the default is to include this list. # include_sort_by_name = True ####################################################### # Provide entries in a dictionary for component reference names for which a UCF Xilinx Constraint file should be created. # For each entry, specify the desired UCF file name. # # this output file will receive lines like # NET "P12_21" LOC = "B4"; # # The default is to generate no UCF file # Note: The Hub has only one Xilinx FPGA, one could create more than one constraint file for other projects # No longer useful # ucf_file_dict [ "U1" ] = "Hub_FPGA_ucf_%s.txt" % current_time_stamp # Provide entries in a dictionary for component reference names for which a XDC Xilinx Constraint file should be created. # For each entry, specify the desired XDC file name. # # this output file will receive lines like # set_property PACKAGE_PIN AU33 [get_ports "Phys_U21_CLK125_LED_MODE"] ; # # The default is to generate no XDC file xdc_file_dict [ "U1" ] = "Hub_FPGA_xdc_%s.txt" % current_time_stamp # Provide a list of Net Names to be skipped when creating the UCF and XDC file(s) # e.g. ucfxdc_skip_net_name_lst = ( "GROUND", ) # The default is to skip nothing. ucfxdc_skip_net_name_lst = \ ( "GROUND", "BULK_1V8", "BULK_3V3", "FPGA_CORE", "VBATT", "MGT_AVAUX","MGT_AVCC", "MGT_AVTT", "SysMon_Main_Input_VN", "SysMon_Main_Input_VP", "FPGA_Config_DONE", "POR_OVERRIDE", "PROGRAM_B", "SYSMON_1V8", "SYSMON_GND","SYSMON_VREFP", "Temp_Diode_DXN", "Temp_Diode_DXP", "CONFIG_M0", "CONFIG_M1", "CONFIG_M2", "PUDC_B", "CFGBVS", "FLASH_OUTPUT_ENB_B", "FLASH_RESET_B", "FLASH_WRITE_ENB_B", "FLASH_CHIP_ENB_B", "FLASH_A00", "FLASH_A01", "FLASH_A02", "FLASH_A03", "FLASH_A04", "FLASH_A05", "FLASH_A06", "FLASH_A07", "FLASH_A08", "FLASH_A09", "FLASH_A10", "FLASH_A11", "FLASH_A12", "FLASH_A13", "FLASH_A14", "FLASH_A15", "FLASH_A16", "FLASH_A17", "FLASH_A18", "FLASH_A19", "FLASH_A20", "FLASH_A21", "FLASH_A22", "FLASH_A23", "FLASH_A24", "FLASH_A25", "FLASH_D00", "FLASH_D01", "FLASH_D02", "FLASH_D03", "FLASH_D04", "FLASH_D05", "FLASH_D06", "FLASH_D07", "FLASH_D08", "FLASH_D09", "FLASH_D10", "FLASH_D11", "FLASH_D12", "FLASH_D13", "FLASH_D14", "FLASH_D15", "Bank_65_VREF", "Bank_65_VRP_DCI", "Bank_66_VREF", "Bank_66_VRP_DCI", "Bank_67_VREF", "Bank_67_VRP_DCI", "Bank_68_VREF", "Bank_68_VRP_DCI", "Bank_71_VREF", "Bank_71_VRP_DCI", "Bank_84_VREF", "Bank_94_VREF", "QUAD_125_MGTRREF", "QUAD_130_MGTRREF", "QUAD_226_MGTRREF", "QUAD_231_MGTRREF", "TCK_TO_HUB_FPGA", "TMS_TO_HUB_FPGA", "TDI_SERIES_TO_HUB_FPGA", "TD_HUB_FPGA_TO_JMP1", ) # Provide a list of Component Reference Designator with Pin Name to be skipped when creating the UCF and XDC file(s) # e.g. ucfxdc_skip_comp_pin_ref_lst = ( "U1-BE16", ) # The default is to skip nothing. ucfxdc_skip_comp_pin_ref_lst = \ ( "U1-BE16", # IO_L23P_T3U_N8_I2C_SCLK_65 repeats 'Hub_I2C_to_FPGA_SCL' "U1-BF16", # IO_L23N_T3U_N9_I2C_SDA_65 repeats 'Hub_I2C_to_FPGA_SDA' )