progress checklist for Philippe as of 20-Jan-2017 corrections in second pass http://www.pa.msu.edu/hep/atlas/l1calo/hub/hardware/tools/list_nets_by_components/out_Comp_Pin_Nets_2017-01-20_12-00/ as of 18-Jan-2017 first pass http://www.pa.msu.edu/hep/atlas/l1calo/hub/hardware/tools/list_nets_by_components/out_Comp_Pin_Nets_2017-01-09_17-09/ *** RJ45 components were exlcuded --> create dictionary and include --> done in out_Comp_Pin_Nets_2017-01-20_12-00 DCDC1_has_19_pins_is_POL_MDT040A.txt is power supply module 40A of 0.95 V for VCCINT FPGA_CORE with ramp drawing 26A DCDC2_has_16_pins_is_POL_UDT020A.txt is power supply module 20A of 1.0 V for MGT AVCC with ramp drawing 26B DCDC3_has_16_pins_is_POL_UDT020A.txt is power supply module 20A for of 1.2V for MGT AVTT with ramp drawing 26B DCDC4_has_6_pins_is_IC_Linear_LT1764A.txt is power supply module 3A of 1.8 V for MGT VAUX without ramp drawing 27 DCDC5_has_17_pins_is_POL_PDT012A.txt is power supply module 12A of 1.2 V for switches without ramp drawing 26C DCDC6_has_17_pins_is_POL_PDT012A.txt is power supply module 12A of 1.8 V Bulk with ramp drawing 26C DCDC7_has_16_pins_is_POL_UDT020A.txt is power supply module 20A of 1.8 V for Fanout with ramp drawing 26B DCDC8_has_17_pins_is_POL_PDT012A.txt is power supply module 12A of 3.3 V Bulk with ramp drawing 26C DCDC9_has_40_pins_is_IC_Linear_LT1764A.txt is power supply module 3A of 2.5 V Bulk without ramp drawing 27 ESD_Strip_FO_has_1_pins.txt ESD_Strip_MB_has_2_pins.txt *** should skip ESD_Strip components --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 IPMC_has_248_pins_is_Molex_877823003.txt is IPMC for sending hardware address for receiving shelf address for receivinb LED signals for Fast or Gb ethernet port for receiving Enable 12V power for sending Power Entry Alarm For PMbus A & B For Sensor I2C bus *** part of same typo 12C -> I2C --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 220 = IPMC_MGT_12C_SCK Mgt_I2C_SCL OUTpu from line 172 of ipmc_hw_adrs_handle_switch_ipmb_nets 221 = IPMC_MGT_12C_SDA Mgt_I2C_SDA INOUTpu from line 170 of ipmc_hw_adrs_handle_switch_ipmb_nets *** same on both pins? 226 = IPMC_Power_Entry_ALARM Alarm_A IN from line 187 of atca_power_entry_nets 227 = IPMC_Power_Entry_ALARM Alarm_B IN from line 187 of atca_power_entry_nets *** improve dict ? e.g. add parenthesis "IPMB-A_SCL INOUT(pu)" --> leave as is 120 = IPMBus_A_SCL IPMB-A_SCL INOUTpu from line 123 of ipmc_hw_adrs_handle_switch_ipmb_nets J20_has_128_pins_is_TE_2065657-1_J20.txt is Zone 2 connector for Fabric interface Clk & CombData to FEX 14 MGT Fanout 69 to 74 i.e. FEX 14 for Update Interface Gbe to other Hub Gbe from other Hub J21_has_160_pins_is_TE_2065657-1_J21.txt is Zone 2 connector for Fabric interface Clk & CombData to FEX 9 to 13 MGT Fanout 39 to 68 i.e. FEX 9 to 13 J22_has_160_pins_is_TE_2065657-1_J22.txt is Zone 2 connector for Fabric interface Clk & CombData to FEX 4 to 8 MGT Fanout 7 to 36 i.e. FEX 4 to 8 J23_has_160_pins_is_TE_2065657-1_J23.txt is Zone 2 connector for Fabric interface Clk & CombData to other Hub Readout 0 and 1 to other Hub Clk & CombData from other Hub MGT Fanout 37 and 38 Readout from other Hub Clk & CombData to FEX3 MGT Fanout 1 to 6 i.e. FEX 3 for Base interface GbE to FEX 3 to 6 *** check dict for missing space on "RO Str2 from othHUB" --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 C3 = MGT_FO_CH_37_IN_CMP Rx2[01]+ RO Str 1 from othHUB from line 9891 of mgt_fanout_channel_nets D3 = MGT_FO_CH_37_IN_DIR Rx2[01]- RO Str 1 from othHUB from line 9892 of mgt_fanout_channel_nets H3 = MGT_FO_CH_38_IN_CMP Rx3[01]- RO Str2 from othHUB from line 9898 of mgt_fanout_channel_nets G3 = MGT_FO_CH_38_IN_DIR Rx3[01]+ RO Str2 from othHUB from line 9897 of mgt_fanout_channel_nets D1 = MGT_FO_CH_3_IN_CMP Rx2[02]- RO Str 3 from FEX 03 from line 9651 of mgt_fanout_channel_nets J24_has_128_pins_is_TE_2065657-1_J24.txt is Zone 2 connector for Base interface GbE to FEX 7 to 14 Meg_S1_has_400_pins_is_FCI_Conn_74221_S1.txt is ROD Meg Array S1 with Fanout 1 to 36 on Hub called FexRO 1 to 36 on ROD (after +1 offset in dictionary) Meg_S2_has_400_pins_is_FCI_Conn_74221_S2.txt is ROD Meg Array S2 with Fanout 39 to 74 on Hub called FexRO 72 to 37 on ROD (after +1 offset in dictionary) with Fanout 37 & 38 on Hub (Other Hub Readout) called HRD 0 & 2 on ROD with ThisHubRO 0 & 1 on Hub called HRD 1 & 3 on ROD OPT1_has_4_pins_is_ACPL-217-56CE.txt is opto coupler for islated 12V power enable shown in drawing 7 P10_has_22_pins_is_TE_1766500-1.txt is Zone 1 connector Power pin numbers shown on left side of drawing 6 IPMC pin numbers shown on left side of drawing 13 Power_12V_has_8_pins_is_SynQor_PQ60120.txt is isolated 12V power 25A 300W shown in drawing 7 Power_Entry_has_18_pins_is_SynQor_IQ65033.txt is ATCA power entry moduled shown in drawing 6 *** part of same typo 12C -> I2C --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 11 = IPMC_MGT_12C_SDA I2C_DAT from line 192 of atca_power_entry_nets 12 = IPMC_MGT_12C_SCK I2C_CLK from line 190 of atca_power_entry_nets Rec_MP2_has_83_pins_is_Conn_FCI_55714.txt is MiniPod Receiver with address 000 Non-Inv 2,4,6,8 Unused 0,1,3,5,7,9,10,11 Power 3.3V and 2.5V called Trans_MP1 ind drawing 21 TRNS1_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for IPMC to RJ1 lower right: for ROD to RJ1 upper generic shown in drawing 43 port assignments shown in drawing 4 *** add R/L to datasheet dictionary names --> to be improved --> done in out_Comp_Pin_Nets_2017-01-20_12-00 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 L16 = RJ1_L_C_2_CMP MX2+ from line 112 of rj1_trns1_nets L18 = RJ1_L_C_2_DIR MX2- from line 111 of rj1_trns1_nets L13 = RJ1_L_D_3_CMP MX3+ from line 115 of rj1_trns1_nets L15 = RJ1_L_D_3_DIR MX3- from line 114 of rj1_trns1_nets R16 = RJ1_U_C_2_CMP MX2+ from line 73 of rj1_trns1_nets R18 = RJ1_U_C_2_DIR MX2- from line 72 of rj1_trns1_nets R13 = RJ1_U_D_3_CMP MX3+ from line 76 of rj1_trns1_nets R15 = RJ1_U_D_3_DIR MX3- from line 75 of rj1_trns1_nets TRNS2_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip A port 6 to RJ2 lower right: for Chip C port 6 to RJ2 upper generic shown in drawing 43 port assignments shown in drawing 4 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS3_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip B 6 to RJ3 Lower right: for Chip B 7 to RJ3 Upper generic shown in drawing 43 port assignments shown in drawing 4 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS4_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Hub FPGA Phys U21 from other Hub via Update Channel Rx right: for Chip B port 5 to other Hub via Update Channel Tx generic shown in drawing 43 port assignments shown in drawing 4 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS5_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip C port 5 to Base Interface 3 right: for Chip C port 4 to Base Interface 4 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS6_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip C port 3 to Base Interface 5 right: for Chip C port 2 to Base Interface 6 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS7_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip C port 1 to Base Interface 7 right: for Chip C port 0 to Base Interface 8 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS8_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip A port 5 to Base Interface 9 right: for Chip A port 4 to Base Interface 10 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS9_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip A port 3 to Base Interface 11 right: for Chip A port 2 to Base Interface 12 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 TRNS10_has_48_pins_is_Pulse_HX5201NL.txt is ethernet transformer left: for Chip A port 1 to Base Interface 13 right: for Chip A port 0 to Base Interface 14 generic shown in drawing 43 port assignments shown in drawing 4 ok, inversion in both primary and secondary for lane 1 and 3 *** error in dectionary : inversion + / - for MX2 and MX3, for left and right --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 Trn_MP1_has_83_pins_is_Conn_FCI_55714.txt is MiniPod Transmitter with address 000 Non-Inv 0,1 Inv 2,4,6,8,10,11 Unused 3,5,7,9 Power 3.3V and 2.5V called Trans_MP1 ind drawing 21 U1_has_2104_pins_is_IC_XCVU125.txt 1.8V Bank 0 Congig 1.8V bank 65 Flash Interface I2C_In: Scl, Sda AM18 = Bank_65_VREF VREF_65 from line 75 of ultra_dci_vref_mgt_calib_resistors_nets AP21 = Bank_65_VRP_DCI IO_T0U_N12_VRP_A28_65 from line 38 of ultra_dci_vref_mgt_calib_resistors_nets 1.8V bank 66 AM22 = Bank_66_VREF VREF_66 from line 78 of ultra_dci_vref_mgt_calib_resistors_nets AM27 = Bank_66_VRP_DCI IO_T0U_N12_VRP_66 from line 41 of ultra_dci_vref_mgt_calib_resistors_nets 1.8V bank 67 Access Signal x2 Rod Power Control 2,3,4, Rod Present I2C_Out: Scl, Sda RodSmbAlert SlotAddrOut 0,1,2,3,4,5 AV26 = TBD_SPARE_LINK_0_DIR IO_L7P_T1L_N0_QBC_AD13P_67 from line 40 of rod_to_from_hub_spare_nets AW26 = TBD_SPARE_LINK_0_CMP IO_L7N_T1L_N1_QBC_AD13N_67 from line 41 of rod_to_from_hub_spare_nets AT27 = TBD_SPARE_LINK_1_DIR IO_L8P_T1L_N2_AD5P_67 from line 43 of rod_to_from_hub_spare_nets AU27 = TBD_SPARE_LINK_1_CMP IO_L8N_T1L_N3_AD5N_67 from line 44 of rod_to_from_hub_spare_nets AY27 = TBD_SPARE_LINK_2_DIR IO_L13P_T2L_N0_GC_QBC_67 from line 46 of rod_to_from_hub_spare_nets AY28 = TBD_SPARE_LINK_2_CMP IO_L13N_T2L_N1_GC_QBC_67 from line 47 of rod_to_from_hub_spare_nets AT29 = TBD_SPARE_LINK_3_DIR IO_L9P_T1L_N4_AD12P_67 from line 49 of rod_to_from_hub_spare_nets AU29 = TBD_SPARE_LINK_3_CMP IO_L9N_T1L_N5_AD12N_67 from line 50 of rod_to_from_hub_spare_nets AU28 = SPARE_OSC_TO_FPGA_DIR IO_L11P_T1U_N8_GC_67 from line 127 of sundry_hub_nets AV28 = SPARE_OSC_TO_FPGA_CMP IO_L11N_T1U_N9_GC_67 from line 128 of sundry_hub_nets AM28 = Bank_67_VREF VREF_67 from line 81 of ultra_dci_vref_mgt_calib_resistors_nets AP31 = Bank_67_VRP_DCI IO_T0U_N12_VRP_67 from line 44 of ultra_dci_vref_mgt_calib_resistors_nets 1.8V bank 68 Phys U21: Tx0,1,2,3 TxClk, TxEn, Rx0 1,2,3, RxClk, RxDV, Clk125, Mdio, Mdc, Int Phys U22: Tx0,1,2,3 TxClk, TxEn, Rx0,1,2,3, RxClk, RxDV, Clk125, Mdio, Mdc, Int OutAddr 6,7 HubLed 50,51,52 AV31 = Ref_40.08_MHz_from_FPGA_to_Rec_Dir IO_L7P_T1L_N0_QBC_AD13P_68 from line 222 of clock_generation_nets AW31 = Ref_40.08_MHz_from_FPGA_to_Rec_Cmp IO_L7N_T1L_N1_QBC_AD13N_68 from line 223 of clock_generation_nets AM32 = Bank_68_VREF VREF_68 from line 84 of ultra_dci_vref_mgt_calib_resistors_nets AU36 = Bank_68_VRP_DCI IO_T0U_N12_VRP_68 from line 47 of ultra_dci_vref_mgt_calib_resistors_nets 1.8V bank 70 PllLockIn (3.3 V) 40MHzFanoutSelect (=low to enable, off via open drain to 1/2 of 2.5V) 1.8V bank 71 FanoutEqEnab 1,2,3,4,5,6,9 G23 = Ref_40.08_MHz_from_Other_Hub_Cmp IO_L14N_T2L_N3_GC_71 from line 208 of clock_generation_nets H23 = Ref_40.08_MHz_from_Other_Hub_Dir IO_L14P_T2L_N2_GC_71 from line 207 of clock_generation_nets H24 = Logic_Clk_40.08_MHz_to_FPGA_Cmp IO_L12N_T1U_N11_GC_71 from line 60 of clock_40.08_MHz_distribution_nets J24 = Logic_Clk_40.08_MHz_to_FPGA_Dir IO_L12P_T1U_N10_GC_71 from line 59 of clock_40.08_MHz_distribution_nets J22 = Logic_Clk_320.64_MHz_to_FPGA_Cmp IO_L11N_T1U_N9_GC_71 from line 622 of clock_generation_nets K22 = Logic_Clk_320.64_MHz_to_FPGA_Dir IO_L11P_T1U_N8_GC_71 from line 621 of clock_generation_nets P21 = Bank_71_VREF VREF_71 from line 88 of ultra_dci_vref_mgt_calib_resistors_nets P22 = Bank_71_VRP_DCI IO_T0U_N12_VRP_71 from line 50 of ultra_dci_vref_mgt_calib_resistors_nets 1.8V bank 72 FanoutEqEnab 7,8,10,11,12,13 3.3V bank 84 PowerGood MiniPod Tx: SCL, Intr, Reset, SDA MiniPod Rx: SCL, Intr, Reset, SDA SmbAlert RodPowerEnable & Enable_B SlotAddrIn 0,1,2,3 Switch B: LoopDetect, LoopDetected, MDC, MDIO Switch C: LoopDetect, LoopDetected AT15 = CLOCK_25_MHz_FPGA IO_L14P_T2L_N2_GC_84 from line 112 of clock_generation_nets AM17 = Bank_84_VREF VREF_84 from line 92 of ultra_dci_vref_mgt_calib_resistors_nets 3.3V bank 94 SlotAddrIn 4,5,6,7 ShelfAddrIn 0,1,2,3,4,5,6,7 I2cBufEn 1501,1502,1503 Switch A: LoopDetect, LoopDetected, MDC, MDIO Switch C: MDC, MDIO AW16 = Bank_94_VREF VREF_94 from line 95 of ultra_dci_vref_mgt_calib_resistors_nets P14 = FLASH_RESET_B INIT_B_0 from line 126 of bank_0_and_bank_65_config_mem_nets AE36 = MHz_320.64_COPY_0_DIR MGTREFCLK0P_125 from line 579 of clock_generation_nets AE37 = MHz_320.64_COPY_0_CMP MGTREFCLK0N_125 from line 580 of clock_generation_nets R36 = MHz_320.64_COPY_1_DIR MGTREFCLK0P_130 from line 588 of clock_generation_nets R37 = MHz_320.64_COPY_1_CMP MGTREFCLK0N_130 from line 589 of clock_generation_nets K34 = MHz_320.64_COPY_2_DIR MGTREFCLK1P_132 from line 597 of clock_generation_nets K35 = MHz_320.64_COPY_2_CMP MGTREFCLK1N_132 from line 598 of clock_generation_nets Y34 = MHz_320.64_COPY_3_DIR MGTREFCLK1P_127 from line 606 of clock_generation_nets Y35 = MHz_320.64_COPY_3_CMP MGTREFCLK1N_127 from line 607 of clock_generation_nets Y12 = MHz_320.64_COPY_6_CMP MGTREFCLK1N_227 from line 634 of clock_generation_nets Y13 = MHz_320.64_COPY_6_DIR MGTREFCLK1P_227 from line 633 of clock_generation_nets K12 = MHz_320.64_COPY_7_CMP MGTREFCLK1N_232 from line 643 of clock_generation_nets K13 = MHz_320.64_COPY_7_DIR MGTREFCLK1P_232 from line 642 of clock_generation_nets R10 = MHz_320.64_COPY_8_CMP MGTREFCLK0N_230 from line 652 of clock_generation_nets R11 = MHz_320.64_COPY_8_DIR MGTREFCLK0P_230 from line 651 of clock_generation_nets AE10 = MHz_320.64_COPY_9_CMP MGTREFCLK0N_225 from line 661 of clock_generation_nets AE11 = MHz_320.64_COPY_9_DIR MGTREFCLK0P_225 from line 660 of clock_generation_nets AH41 = QUAD_125_MGTRREF MGTRREF_LC from line 119 of ultra_dci_vref_mgt_calib_resistors_nets D41 = QUAD_130_MGTRREF MGTRREF_LN from line 122 of ultra_dci_vref_mgt_calib_resistors_nets AH6 = QUAD_226_MGTRREF MGTRREF_RC from line 125 of ultra_dci_vref_mgt_calib_resistors_nets D6 = QUAD_231_MGTRREF MGTRREF_RN from line 128 of ultra_dci_vref_mgt_calib_resistors_nets P26 = FPGA_CORE VCCINT from line 827 of ultra_fpga_power_ground_nets V16 = FPGA_CORE VCCBRAM from line 963 of ultra_fpga_power_ground_nets V30 = FPGA_CORE VCCINT_IO from line 945 of ultra_fpga_power_ground_nets W15 = FPGA_CORE VCCBRAM from line 964 of ultra_fpga_power_ground_nets A43 = MGT_AVTT MGTAVTT_LN from line 1252 of ultra_fpga_power_ground_nets Y41 = MGT_AVTT MGTAVTT_LC from line 1232 of ultra_fpga_power_ground_nets AU39 = MGT_AVTT MGTAVTT_LS from line 1274 of ultra_fpga_power_ground_nets A4 = MGT_AVTT MGTAVTT_RN from line 1312 of ultra_fpga_power_ground_nets U8 = MGT_AVTT MGTAVTT_RC from line 1290 of ultra_fpga_power_ground_nets AU8 = MGT_AVTT MGTAVTT_RS from line 1334 of ultra_fpga_power_ground_nets AH40 = MGT_AVTT MGTAVTTRCAL_LC from line 118 of ultra_dci_vref_mgt_calib_resistors_nets D7 = MGT_AVTT MGTAVTTRCAL_RN from line 127 of ultra_dci_vref_mgt_calib_resistors_nets AH7 = MGT_AVTT MGTAVTTRCAL_RC from line 124 of ultra_dci_vref_mgt_calib_resistors_nets D40 = MGT_AVTT MGTAVTTRCAL_LN from line 121 of ultra_dci_vref_mgt_calib_resistors_nets V32 = BULK_1V8 VCCAUX from line 984 of ultra_fpga_power_ground_nets W31 = BULK_1V8 VCCAUX_IO from line 1006 of ultra_fpga_power_ground_nets J35 = MGT_AVAUX MGTVCCAUX_LN from line 1365 of ultra_fpga_power_ground_nets Y37 = MGT_AVAUX MGTVCCAUX_LC from line 1358 of ultra_fpga_power_ground_nets AK36 = MGT_AVAUX MGTVCCAUX_LS from line 1372 of ultra_fpga_power_ground_nets J12 = MGT_AVAUX MGTVCCAUX_RN from line 1386 of ultra_fpga_power_ground_nets Y10 = MGT_AVAUX MGTVCCAUX_RC from line 1379 of ultra_fpga_power_ground_nets AK11 = MGT_AVAUX MGTVCCAUX_RS from line 1393 of ultra_fpga_power_ground_nets F36 = MGT_AVCC MGTAVCC_LN from line 1160 of ultra_fpga_power_ground_nets U35 = MGT_AVCC MGTAVCC_LC from line 1146 of ultra_fpga_power_ground_nets AJ35 = MGT_AVCC MGTAVCC_LS from line 1176 of ultra_fpga_power_ground_nets G13 = MGT_AVCC MGTAVCC_RN from line 1199 of ultra_fpga_power_ground_nets AA12 = MGT_AVCC MGTAVCC_RC from line 1188 of ultra_fpga_power_ground_nets AG13 = MGT_AVCC MGTAVCC_RS from line 1212 of ultra_fpga_power_ground_nets AN13 = VBATT VBATT from line 205 of bank_0_and_bank_65_config_mem_nets AB20 = SYSMON_1V8 VCCADC from line 75 of power_supply_all_other_nets AB19 = SYSMON_GND GNDADC from line 77 of power_supply_all_other_nets AD20 = SYSMON_VREFP VREFP from line 79 of power_supply_all_other_nets AC19 = SYSMON_GND VREFN from line 77 of power_supply_all_other_nets AC20 = SysMon_Main_Input_VP VP from line 82 of power_supply_all_other_nets AD19 = SysMon_Main_Input_VN VN from line 83 of power_supply_all_other_nets AN1 = Rec_MP_Fiber_2_to_FPGA_Cmp MGTHRXN2_224 from line 167 of hub_all_other_mgt_nets AN2 = Rec_MP_Fiber_2_to_FPGA_Dir MGTHRXP2_224 from line 166 of hub_all_other_mgt_nets AP3 = Rec_MP_Fiber_4_to_FPGA_Cmp MGTHRXN1_224 from line 154 of hub_all_other_mgt_nets AP4 = Rec_MP_Fiber_4_to_FPGA_Dir MGTHRXP1_224 from line 153 of hub_all_other_mgt_nets AR1 = Rec_MP_Fiber_6_to_FPGA_Cmp MGTHRXN0_224 from line 141 of hub_all_other_mgt_nets AR2 = Rec_MP_Fiber_6_to_FPGA_Dir MGTHRXP0_224 from line 140 of hub_all_other_mgt_nets AR46 = Rec_MP_Fiber_8_to_FPGA_Cmp MGTYRXN0_124 from line 127 of hub_all_other_mgt_nets AR45 = Rec_MP_Fiber_8_to_FPGA_Dir MGTYRXP0_124 from line 126 of hub_all_other_mgt_nets AA7 = MiniPOD_Trans_Fiber_0_Data_Cmp MGTHTXP2_227 from line 193 of hub_all_other_mgt_nets AA6 = MiniPOD_Trans_Fiber_0_Data_Dir MGTHTXN2_227 from line 192 of hub_all_other_mgt_nets AN7 = MiniPOD_Trans_Fiber_10_Data_Cmp MGTHTXP2_224 from line 217 of hub_all_other_mgt_nets AN6 = MiniPOD_Trans_Fiber_10_Data_Dir MGTHTXN2_224 from line 216 of hub_all_other_mgt_nets AR7 = MiniPOD_Trans_Fiber_11_Data_Cmp MGTHTXP0_224 from line 221 of hub_all_other_mgt_nets AR6 = MiniPOD_Trans_Fiber_11_Data_Dir MGTHTXN0_224 from line 220 of hub_all_other_mgt_nets AC7 = MiniPOD_Trans_Fiber_1_Data_Cmp MGTHTXP0_227 from line 197 of hub_all_other_mgt_nets AC6 = MiniPOD_Trans_Fiber_1_Data_Dir MGTHTXN0_227 from line 196 of hub_all_other_mgt_nets AE7 = MiniPOD_Trans_Fiber_2_Data_Cmp MGTHTXP2_226 from line 201 of hub_all_other_mgt_nets AE6 = MiniPOD_Trans_Fiber_2_Data_Dir MGTHTXN2_226 from line 200 of hub_all_other_mgt_nets AG7 = MiniPOD_Trans_Fiber_4_Data_Cmp MGTHTXP0_226 from line 205 of hub_all_other_mgt_nets AG6 = MiniPOD_Trans_Fiber_4_Data_Dir MGTHTXN0_226 from line 204 of hub_all_other_mgt_nets AJ7 = MiniPOD_Trans_Fiber_6_Data_Cmp MGTHTXP2_225 from line 209 of hub_all_other_mgt_nets AJ6 = MiniPOD_Trans_Fiber_6_Data_Dir MGTHTXN2_225 from line 208 of hub_all_other_mgt_nets AL7 = MiniPOD_Trans_Fiber_8_Data_Cmp MGTHTXP0_225 from line 213 of hub_all_other_mgt_nets AL6 = MiniPOD_Trans_Fiber_8_Data_Dir MGTHTXN0_225 from line 212 of hub_all_other_mgt_nets R6 = This_Hubs_RO_0_to_Cap_Its_ROD_Cmp MGTHTXN0_229 from line 281 of hub_all_other_mgt_nets R7 = This_Hubs_RO_0_to_Cap_Its_ROD_Dir MGTHTXP0_229 from line 280 of hub_all_other_mgt_nets AA41 = This_Hubs_RO_0_to_Cap_Other_ROD_Cmp MGTYTXN2_127 from line 304 of hub_all_other_mgt_nets AA40 = This_Hubs_RO_0_to_Cap_Other_ROD_Dir MGTYTXP2_127 from line 303 of hub_all_other_mgt_nets U6 = This_Hubs_RO_1_to_Cap_Its_ROD_Cmp MGTHTXN2_228 from line 288 of hub_all_other_mgt_nets U7 = This_Hubs_RO_1_to_Cap_Its_ROD_Dir MGTHTXP2_228 from line 287 of hub_all_other_mgt_nets AC40 = This_Hubs_RO_1_to_Cap_Other_ROD_Cmp MGTYTXP0_127 from line 316 of hub_all_other_mgt_nets AC41 = This_Hubs_RO_1_to_Cap_Other_ROD_Dir MGTYTXN0_127 from line 315 of hub_all_other_mgt_nets AM4 = This_RODs_Readout_Ctrl_to_GTH_Input_Cmp MGTHRXP3_224 from line 94 of hub_all_other_mgt_nets AM3 = This_RODs_Readout_Ctrl_to_GTH_Input_Dir MGTHRXN3_224 from line 93 of hub_all_other_mgt_nets W46 = MGT_FO_CH_10_OUT_Hub_CMP MGTYRXN0_128 from line 10801 of mgt_fanout_channel_nets W45 = MGT_FO_CH_10_OUT_Hub_DIR MGTYRXP0_128 from line 10800 of mgt_fanout_channel_nets Y43 = MGT_FO_CH_11_OUT_Hub_CMP MGTYRXP3_127 from line 10794 of mgt_fanout_channel_nets Y44 = MGT_FO_CH_11_OUT_Hub_DIR MGTYRXN3_127 from line 10795 of mgt_fanout_channel_nets AA46 = MGT_FO_CH_12_OUT_Hub_CMP MGTYRXN2_127 from line 10791 of mgt_fanout_channel_nets AA45 = MGT_FO_CH_12_OUT_Hub_DIR MGTYRXP2_127 from line 10790 of mgt_fanout_channel_nets AB43 = MGT_FO_CH_13_OUT_Hub_CMP MGTYRXP1_127 from line 10786 of mgt_fanout_channel_nets AB44 = MGT_FO_CH_13_OUT_Hub_DIR MGTYRXN1_127 from line 10787 of mgt_fanout_channel_nets AC46 = MGT_FO_CH_14_OUT_Hub_CMP MGTYRXN0_127 from line 10783 of mgt_fanout_channel_nets AC45 = MGT_FO_CH_14_OUT_Hub_DIR MGTYRXP0_127 from line 10782 of mgt_fanout_channel_nets AD43 = MGT_FO_CH_15_OUT_Hub_CMP MGTYRXP3_126 from line 10776 of mgt_fanout_channel_nets AD44 = MGT_FO_CH_15_OUT_Hub_DIR MGTYRXN3_126 from line 10777 of mgt_fanout_channel_nets AE46 = MGT_FO_CH_16_OUT_Hub_CMP MGTYRXN2_126 from line 10773 of mgt_fanout_channel_nets AE45 = MGT_FO_CH_16_OUT_Hub_DIR MGTYRXP2_126 from line 10772 of mgt_fanout_channel_nets K43 = MGT_FO_CH_17_OUT_Hub_CMP MGTYRXP1_130 from line 10842 of mgt_fanout_channel_nets K44 = MGT_FO_CH_17_OUT_Hub_DIR MGTYRXN1_130 from line 10843 of mgt_fanout_channel_nets L46 = MGT_FO_CH_18_OUT_Hub_CMP MGTYRXN0_130 from line 10839 of mgt_fanout_channel_nets L45 = MGT_FO_CH_18_OUT_Hub_DIR MGTYRXP0_130 from line 10838 of mgt_fanout_channel_nets M43 = MGT_FO_CH_19_OUT_Hub_CMP MGTYRXP3_129 from line 10831 of mgt_fanout_channel_nets M44 = MGT_FO_CH_19_OUT_Hub_DIR MGTYRXN3_129 from line 10832 of mgt_fanout_channel_nets AF43 = MGT_FO_CH_1_OUT_Hub_CMP MGTYRXP1_126 from line 10768 of mgt_fanout_channel_nets AF44 = MGT_FO_CH_1_OUT_Hub_DIR MGTYRXN1_126 from line 10769 of mgt_fanout_channel_nets N46 = MGT_FO_CH_20_OUT_Hub_CMP MGTYRXN2_129 from line 10828 of mgt_fanout_channel_nets N45 = MGT_FO_CH_20_OUT_Hub_DIR MGTYRXP2_129 from line 10827 of mgt_fanout_channel_nets P43 = MGT_FO_CH_21_OUT_Hub_CMP MGTYRXP1_129 from line 10823 of mgt_fanout_channel_nets P44 = MGT_FO_CH_21_OUT_Hub_DIR MGTYRXN1_129 from line 10824 of mgt_fanout_channel_nets R46 = MGT_FO_CH_22_OUT_Hub_CMP MGTYRXN0_129 from line 10820 of mgt_fanout_channel_nets R45 = MGT_FO_CH_22_OUT_Hub_DIR MGTYRXP0_129 from line 10819 of mgt_fanout_channel_nets T43 = MGT_FO_CH_23_OUT_Hub_CMP MGTYRXP3_128 from line 10812 of mgt_fanout_channel_nets T44 = MGT_FO_CH_23_OUT_Hub_DIR MGTYRXN3_128 from line 10813 of mgt_fanout_channel_nets U46 = MGT_FO_CH_24_OUT_Hub_CMP MGTYRXN2_128 from line 10809 of mgt_fanout_channel_nets U45 = MGT_FO_CH_24_OUT_Hub_DIR MGTYRXP2_128 from line 10808 of mgt_fanout_channel_nets B43 = MGT_FO_CH_25_OUT_Hub_CMP MGTYRXP3_132 from line 10880 of mgt_fanout_channel_nets B44 = MGT_FO_CH_25_OUT_Hub_DIR MGTYRXN3_132 from line 10881 of mgt_fanout_channel_nets C46 = MGT_FO_CH_26_OUT_Hub_CMP MGTYRXN2_132 from line 10877 of mgt_fanout_channel_nets C45 = MGT_FO_CH_26_OUT_Hub_DIR MGTYRXP2_132 from line 10876 of mgt_fanout_channel_nets D43 = MGT_FO_CH_27_OUT_Hub_CMP MGTYRXP1_132 from line 10872 of mgt_fanout_channel_nets D44 = MGT_FO_CH_27_OUT_Hub_DIR MGTYRXN1_132 from line 10873 of mgt_fanout_channel_nets E46 = MGT_FO_CH_28_OUT_Hub_CMP MGTYRXN0_132 from line 10869 of mgt_fanout_channel_nets E45 = MGT_FO_CH_28_OUT_Hub_DIR MGTYRXP0_132 from line 10868 of mgt_fanout_channel_nets F43 = MGT_FO_CH_29_OUT_Hub_CMP MGTYRXP1_131 from line 10861 of mgt_fanout_channel_nets F44 = MGT_FO_CH_29_OUT_Hub_DIR MGTYRXN1_131 from line 10862 of mgt_fanout_channel_nets AG46 = MGT_FO_CH_2_OUT_Hub_CMP MGTYRXN0_126 from line 10765 of mgt_fanout_channel_nets AG45 = MGT_FO_CH_2_OUT_Hub_DIR MGTYRXP0_126 from line 10764 of mgt_fanout_channel_nets G46 = MGT_FO_CH_30_OUT_Hub_CMP MGTYRXN0_131 from line 10858 of mgt_fanout_channel_nets G45 = MGT_FO_CH_30_OUT_Hub_DIR MGTYRXP0_131 from line 10857 of mgt_fanout_channel_nets H43 = MGT_FO_CH_31_OUT_Hub_CMP MGTYRXP3_130 from line 10850 of mgt_fanout_channel_nets H44 = MGT_FO_CH_31_OUT_Hub_DIR MGTYRXN3_130 from line 10851 of mgt_fanout_channel_nets J46 = MGT_FO_CH_32_OUT_Hub_CMP MGTYRXN2_130 from line 10847 of mgt_fanout_channel_nets J45 = MGT_FO_CH_32_OUT_Hub_DIR MGTYRXP2_130 from line 10846 of mgt_fanout_channel_nets G15 = MGT_FO_CH_33_OUT_Hub_CMP MGTHRXN2_231 from line 10930 of mgt_fanout_channel_nets G16 = MGT_FO_CH_33_OUT_Hub_DIR MGTHRXP2_231 from line 10929 of mgt_fanout_channel_nets E16 = MGT_FO_CH_34_OUT_Hub_CMP MGTHRXP3_231 from line 10925 of mgt_fanout_channel_nets E15 = MGT_FO_CH_34_OUT_Hub_DIR MGTHRXN3_231 from line 10926 of mgt_fanout_channel_nets E31 = MGT_FO_CH_35_OUT_Hub_CMP MGTYRXP3_131 from line 10910 of mgt_fanout_channel_nets E32 = MGT_FO_CH_35_OUT_Hub_DIR MGTYRXN3_131 from line 10911 of mgt_fanout_channel_nets G32 = MGT_FO_CH_36_OUT_Hub_CMP MGTYRXN2_131 from line 10907 of mgt_fanout_channel_nets G31 = MGT_FO_CH_36_OUT_Hub_DIR MGTYRXP2_131 from line 10906 of mgt_fanout_channel_nets A32 = MGT_FO_CH_37_OUT_Hub_CMP MGTYRXN3_133 from line 10900 of mgt_fanout_channel_nets A31 = MGT_FO_CH_37_OUT_Hub_DIR MGTYRXP3_133 from line 10899 of mgt_fanout_channel_nets B34 = MGT_FO_CH_38_OUT_Hub_CMP MGTYRXN2_133 from line 10896 of mgt_fanout_channel_nets B33 = MGT_FO_CH_38_OUT_Hub_DIR MGTYRXP2_133 from line 10895 of mgt_fanout_channel_nets C31 = MGT_FO_CH_39_OUT_Hub_CMP MGTYRXP1_133 from line 10891 of mgt_fanout_channel_nets C32 = MGT_FO_CH_39_OUT_Hub_DIR MGTYRXN1_133 from line 10892 of mgt_fanout_channel_nets AH43 = MGT_FO_CH_3_OUT_Hub_CMP MGTYRXP3_125 from line 10758 of mgt_fanout_channel_nets AH44 = MGT_FO_CH_3_OUT_Hub_DIR MGTYRXN3_125 from line 10759 of mgt_fanout_channel_nets D34 = MGT_FO_CH_40_OUT_Hub_CMP MGTYRXN0_133 from line 10888 of mgt_fanout_channel_nets D33 = MGT_FO_CH_40_OUT_Hub_DIR MGTYRXP0_133 from line 10887 of mgt_fanout_channel_nets E1 = MGT_FO_CH_41_OUT_Hub_CMP MGTHRXN0_232 from line 10968 of mgt_fanout_channel_nets E2 = MGT_FO_CH_41_OUT_Hub_DIR MGTHRXP0_232 from line 10967 of mgt_fanout_channel_nets D4 = MGT_FO_CH_42_OUT_Hub_CMP MGTHRXP1_232 from line 10963 of mgt_fanout_channel_nets D3 = MGT_FO_CH_42_OUT_Hub_DIR MGTHRXN1_232 from line 10964 of mgt_fanout_channel_nets C1 = MGT_FO_CH_43_OUT_Hub_CMP MGTHRXN2_232 from line 10960 of mgt_fanout_channel_nets C2 = MGT_FO_CH_43_OUT_Hub_DIR MGTHRXP2_232 from line 10959 of mgt_fanout_channel_nets B4 = MGT_FO_CH_44_OUT_Hub_CMP MGTHRXP3_232 from line 10955 of mgt_fanout_channel_nets B3 = MGT_FO_CH_44_OUT_Hub_DIR MGTHRXN3_232 from line 10956 of mgt_fanout_channel_nets D13 = MGT_FO_CH_45_OUT_Hub_CMP MGTHRXN0_233 from line 10949 of mgt_fanout_channel_nets D14 = MGT_FO_CH_45_OUT_Hub_DIR MGTHRXP0_233 from line 10948 of mgt_fanout_channel_nets C16 = MGT_FO_CH_46_OUT_Hub_CMP MGTHRXP1_233 from line 10944 of mgt_fanout_channel_nets C15 = MGT_FO_CH_46_OUT_Hub_DIR MGTHRXN1_233 from line 10945 of mgt_fanout_channel_nets B13 = MGT_FO_CH_47_OUT_Hub_CMP MGTHRXN2_233 from line 10941 of mgt_fanout_channel_nets B14 = MGT_FO_CH_47_OUT_Hub_DIR MGTHRXP2_233 from line 10940 of mgt_fanout_channel_nets A15 = MGT_FO_CH_48_OUT_Hub_CMP MGTHRXN3_233 from line 10937 of mgt_fanout_channel_nets A16 = MGT_FO_CH_48_OUT_Hub_DIR MGTHRXP3_233 from line 10936 of mgt_fanout_channel_nets N1 = MGT_FO_CH_49_OUT_Hub_CMP MGTHRXN2_229 from line 11009 of mgt_fanout_channel_nets N2 = MGT_FO_CH_49_OUT_Hub_DIR MGTHRXP2_229 from line 11008 of mgt_fanout_channel_nets AJ46 = MGT_FO_CH_4_OUT_Hub_CMP MGTYRXN2_125 from line 10755 of mgt_fanout_channel_nets AJ45 = MGT_FO_CH_4_OUT_Hub_DIR MGTYRXP2_125 from line 10754 of mgt_fanout_channel_nets M4 = MGT_FO_CH_50_OUT_Hub_CMP MGTHRXP3_229 from line 11004 of mgt_fanout_channel_nets M3 = MGT_FO_CH_50_OUT_Hub_DIR MGTHRXN3_229 from line 11005 of mgt_fanout_channel_nets L1 = MGT_FO_CH_51_OUT_Hub_CMP MGTHRXN0_230 from line 10998 of mgt_fanout_channel_nets L2 = MGT_FO_CH_51_OUT_Hub_DIR MGTHRXP0_230 from line 10997 of mgt_fanout_channel_nets K4 = MGT_FO_CH_52_OUT_Hub_CMP MGTHRXP1_230 from line 10993 of mgt_fanout_channel_nets K3 = MGT_FO_CH_52_OUT_Hub_DIR MGTHRXN1_230 from line 10994 of mgt_fanout_channel_nets J1 = MGT_FO_CH_53_OUT_Hub_CMP MGTHRXN2_230 from line 10990 of mgt_fanout_channel_nets J2 = MGT_FO_CH_53_OUT_Hub_DIR MGTHRXP2_230 from line 10989 of mgt_fanout_channel_nets H4 = MGT_FO_CH_54_OUT_Hub_CMP MGTHRXP3_230 from line 10985 of mgt_fanout_channel_nets H3 = MGT_FO_CH_54_OUT_Hub_DIR MGTHRXN3_230 from line 10986 of mgt_fanout_channel_nets G1 = MGT_FO_CH_55_OUT_Hub_CMP MGTHRXN0_231 from line 10979 of mgt_fanout_channel_nets G2 = MGT_FO_CH_55_OUT_Hub_DIR MGTHRXP0_231 from line 10978 of mgt_fanout_channel_nets F4 = MGT_FO_CH_56_OUT_Hub_CMP MGTHRXP1_231 from line 10974 of mgt_fanout_channel_nets F3 = MGT_FO_CH_56_OUT_Hub_DIR MGTHRXN1_231 from line 10975 of mgt_fanout_channel_nets AA1 = MGT_FO_CH_57_OUT_Hub_CMP MGTHRXN2_227 from line 11047 of mgt_fanout_channel_nets AA2 = MGT_FO_CH_57_OUT_Hub_DIR MGTHRXP2_227 from line 11046 of mgt_fanout_channel_nets Y4 = MGT_FO_CH_58_OUT_Hub_CMP MGTHRXP3_227 from line 11042 of mgt_fanout_channel_nets Y3 = MGT_FO_CH_58_OUT_Hub_DIR MGTHRXN3_227 from line 11043 of mgt_fanout_channel_nets W1 = MGT_FO_CH_59_OUT_Hub_CMP MGTHRXN0_228 from line 11036 of mgt_fanout_channel_nets W2 = MGT_FO_CH_59_OUT_Hub_DIR MGTHRXP0_228 from line 11035 of mgt_fanout_channel_nets AK43 = MGT_FO_CH_5_OUT_Hub_CMP MGTYRXP1_125 from line 10750 of mgt_fanout_channel_nets AK44 = MGT_FO_CH_5_OUT_Hub_DIR MGTYRXN1_125 from line 10751 of mgt_fanout_channel_nets V4 = MGT_FO_CH_60_OUT_Hub_CMP MGTHRXP1_228 from line 11031 of mgt_fanout_channel_nets V3 = MGT_FO_CH_60_OUT_Hub_DIR MGTHRXN1_228 from line 11032 of mgt_fanout_channel_nets U1 = MGT_FO_CH_61_OUT_Hub_CMP MGTHRXN2_228 from line 11028 of mgt_fanout_channel_nets U2 = MGT_FO_CH_61_OUT_Hub_DIR MGTHRXP2_228 from line 11027 of mgt_fanout_channel_nets T4 = MGT_FO_CH_62_OUT_Hub_CMP MGTHRXP3_228 from line 11023 of mgt_fanout_channel_nets T3 = MGT_FO_CH_62_OUT_Hub_DIR MGTHRXN3_228 from line 11024 of mgt_fanout_channel_nets R1 = MGT_FO_CH_63_OUT_Hub_CMP MGTHRXN0_229 from line 11017 of mgt_fanout_channel_nets R2 = MGT_FO_CH_63_OUT_Hub_DIR MGTHRXP0_229 from line 11016 of mgt_fanout_channel_nets P4 = MGT_FO_CH_64_OUT_Hub_CMP MGTHRXP1_229 from line 11012 of mgt_fanout_channel_nets P3 = MGT_FO_CH_64_OUT_Hub_DIR MGTHRXN1_229 from line 11013 of mgt_fanout_channel_nets AL1 = MGT_FO_CH_65_OUT_Hub_CMP MGTHRXN0_225 from line 11093 of mgt_fanout_channel_nets AL2 = MGT_FO_CH_65_OUT_Hub_DIR MGTHRXP0_225 from line 11092 of mgt_fanout_channel_nets AK4 = MGT_FO_CH_66_OUT_Hub_CMP MGTHRXP1_225 from line 11088 of mgt_fanout_channel_nets AK3 = MGT_FO_CH_66_OUT_Hub_DIR MGTHRXN1_225 from line 11089 of mgt_fanout_channel_nets AJ1 = MGT_FO_CH_67_OUT_Hub_CMP MGTHRXN2_225 from line 11085 of mgt_fanout_channel_nets AJ2 = MGT_FO_CH_67_OUT_Hub_DIR MGTHRXP2_225 from line 11084 of mgt_fanout_channel_nets AH4 = MGT_FO_CH_68_OUT_Hub_CMP MGTHRXP3_225 from line 11080 of mgt_fanout_channel_nets AH3 = MGT_FO_CH_68_OUT_Hub_DIR MGTHRXN3_225 from line 11081 of mgt_fanout_channel_nets AG1 = MGT_FO_CH_69_OUT_Hub_CMP MGTHRXN0_226 from line 11074 of mgt_fanout_channel_nets AG2 = MGT_FO_CH_69_OUT_Hub_DIR MGTHRXP0_226 from line 11073 of mgt_fanout_channel_nets AL46 = MGT_FO_CH_6_OUT_Hub_CMP MGTYRXN0_125 from line 10747 of mgt_fanout_channel_nets AL45 = MGT_FO_CH_6_OUT_Hub_DIR MGTYRXP0_125 from line 10746 of mgt_fanout_channel_nets AF4 = MGT_FO_CH_70_OUT_Hub_CMP MGTHRXP1_226 from line 11069 of mgt_fanout_channel_nets AF3 = MGT_FO_CH_70_OUT_Hub_DIR MGTHRXN1_226 from line 11070 of mgt_fanout_channel_nets AE1 = MGT_FO_CH_71_OUT_Hub_CMP MGTHRXN2_226 from line 11066 of mgt_fanout_channel_nets AE2 = MGT_FO_CH_71_OUT_Hub_DIR MGTHRXP2_226 from line 11065 of mgt_fanout_channel_nets AD4 = MGT_FO_CH_72_OUT_Hub_CMP MGTHRXP3_226 from line 11061 of mgt_fanout_channel_nets AD3 = MGT_FO_CH_72_OUT_Hub_DIR MGTHRXN3_226 from line 11062 of mgt_fanout_channel_nets AC1 = MGT_FO_CH_73_OUT_Hub_CMP MGTHRXN0_227 from line 11055 of mgt_fanout_channel_nets AC2 = MGT_FO_CH_73_OUT_Hub_DIR MGTHRXP0_227 from line 11054 of mgt_fanout_channel_nets AB4 = MGT_FO_CH_74_OUT_Hub_CMP MGTHRXP1_227 from line 11050 of mgt_fanout_channel_nets AB3 = MGT_FO_CH_74_OUT_Hub_DIR MGTHRXN1_227 from line 11051 of mgt_fanout_channel_nets AM43 = MGT_FO_CH_7_OUT_Hub_CMP MGTYRXP3_124 from line 10740 of mgt_fanout_channel_nets AM44 = MGT_FO_CH_7_OUT_Hub_DIR MGTYRXN3_124 from line 10741 of mgt_fanout_channel_nets AN46 = MGT_FO_CH_8_OUT_Hub_CMP MGTYRXN2_124 from line 10737 of mgt_fanout_channel_nets AN45 = MGT_FO_CH_8_OUT_Hub_DIR MGTYRXP2_124 from line 10736 of mgt_fanout_channel_nets V43 = MGT_FO_CH_9_OUT_Hub_CMP MGTYRXP1_128 from line 10804 of mgt_fanout_channel_nets V44 = MGT_FO_CH_9_OUT_Hub_DIR MGTYRXN1_128 from line 10805 of mgt_fanout_channel_nets AA10 = No_Conn_FPGA_AA10 MGTREFCLK0N_227 from line 820 of ultra_no_connect_pins_nets AA11 = No_Conn_FPGA_AA11 MGTREFCLK0P_227 from line 819 of ultra_no_connect_pins_nets AA36 = No_Conn_FPGA_AA36 MGTREFCLK0P_127 from line 761 of ultra_no_connect_pins_nets AA37 = No_Conn_FPGA_AA37 MGTREFCLK0N_127 from line 762 of ultra_no_connect_pins_nets AB12 = No_Conn_FPGA_AB12 MGTREFCLK1N_226 from line 813 of ultra_no_connect_pins_nets AB13 = No_Conn_FPGA_AB13 MGTREFCLK1P_226 from line 812 of ultra_no_connect_pins_nets AB34 = No_Conn_FPGA_AB34 MGTREFCLK1P_126 from line 754 of ultra_no_connect_pins_nets AB35 = No_Conn_FPGA_AB35 MGTREFCLK1N_126 from line 755 of ultra_no_connect_pins_nets AB38 = No_Conn_FPGA_AB38 MGTYTXP1_127 from line 477 of ultra_no_connect_pins_nets AB39 = No_Conn_FPGA_AB39 MGTYTXN1_127 from line 478 of ultra_no_connect_pins_nets AB8 = No_Conn_FPGA_AB8 MGTHTXN1_227 from line 637 of ultra_no_connect_pins_nets AB9 = No_Conn_FPGA_AB9 MGTHTXP1_227 from line 636 of ultra_no_connect_pins_nets AC10 = No_Conn_FPGA_AC10 MGTREFCLK0N_226 from line 816 of ultra_no_connect_pins_nets AC11 = No_Conn_FPGA_AC11 MGTREFCLK0P_226 from line 815 of ultra_no_connect_pins_nets AC36 = No_Conn_FPGA_AC36 MGTREFCLK0P_126 from line 757 of ultra_no_connect_pins_nets AC37 = No_Conn_FPGA_AC37 MGTREFCLK0N_126 from line 758 of ultra_no_connect_pins_nets AD12 = No_Conn_FPGA_AD12 MGTREFCLK1N_225 from line 809 of ultra_no_connect_pins_nets AD13 = No_Conn_FPGA_AD13 MGTREFCLK1P_225 from line 808 of ultra_no_connect_pins_nets AD34 = No_Conn_FPGA_AD34 MGTREFCLK1P_125 from line 750 of ultra_no_connect_pins_nets AD35 = No_Conn_FPGA_AD35 MGTREFCLK1N_125 from line 751 of ultra_no_connect_pins_nets AD38 = No_Conn_FPGA_AD38 MGTYTXP3_126 from line 454 of ultra_no_connect_pins_nets AD39 = No_Conn_FPGA_AD39 MGTYTXN3_126 from line 455 of ultra_no_connect_pins_nets AD8 = No_Conn_FPGA_AD8 MGTHTXN3_226 from line 620 of ultra_no_connect_pins_nets AD9 = No_Conn_FPGA_AD9 MGTHTXP3_226 from line 619 of ultra_no_connect_pins_nets AE40 = No_Conn_FPGA_AE40 MGTYTXP2_126 from line 457 of ultra_no_connect_pins_nets AE41 = No_Conn_FPGA_AE41 MGTYTXN2_126 from line 458 of ultra_no_connect_pins_nets AF12 = No_Conn_FPGA_AF12 MGTREFCLK1N_224 from line 802 of ultra_no_connect_pins_nets AF13 = No_Conn_FPGA_AF13 MGTREFCLK1P_224 from line 801 of ultra_no_connect_pins_nets AF34 = No_Conn_FPGA_AF34 MGTREFCLK1P_124 from line 743 of ultra_no_connect_pins_nets AF35 = No_Conn_FPGA_AF35 MGTREFCLK1N_124 from line 744 of ultra_no_connect_pins_nets AF38 = No_Conn_FPGA_AF38 MGTYTXP1_126 from line 460 of ultra_no_connect_pins_nets AF39 = No_Conn_FPGA_AF39 MGTYTXN1_126 from line 461 of ultra_no_connect_pins_nets AF8 = No_Conn_FPGA_AF8 MGTHTXN1_226 from line 623 of ultra_no_connect_pins_nets AF9 = No_Conn_FPGA_AF9 MGTHTXP1_226 from line 622 of ultra_no_connect_pins_nets AG10 = No_Conn_FPGA_AG10 MGTREFCLK0N_224 from line 805 of ultra_no_connect_pins_nets AG11 = No_Conn_FPGA_AG11 MGTREFCLK0P_224 from line 804 of ultra_no_connect_pins_nets AG36 = No_Conn_FPGA_AG36 MGTREFCLK0P_124 from line 746 of ultra_no_connect_pins_nets AG37 = No_Conn_FPGA_AG37 MGTREFCLK0N_124 from line 747 of ultra_no_connect_pins_nets AG40 = No_Conn_FPGA_AG40 MGTYTXP0_126 from line 463 of ultra_no_connect_pins_nets AG41 = No_Conn_FPGA_AG41 MGTYTXN0_126 from line 464 of ultra_no_connect_pins_nets AH38 = No_Conn_FPGA_AH38 MGTYTXP3_125 from line 434 of ultra_no_connect_pins_nets AH39 = No_Conn_FPGA_AH39 MGTYTXN3_125 from line 435 of ultra_no_connect_pins_nets AH8 = No_Conn_FPGA_AH8 MGTHTXN3_225 from line 606 of ultra_no_connect_pins_nets AH9 = No_Conn_FPGA_AH9 MGTHTXP3_225 from line 605 of ultra_no_connect_pins_nets AJ40 = No_Conn_FPGA_AJ40 MGTYTXP2_125 from line 437 of ultra_no_connect_pins_nets AJ41 = No_Conn_FPGA_AJ41 MGTYTXN2_125 from line 438 of ultra_no_connect_pins_nets AK38 = No_Conn_FPGA_AK38 MGTYTXP1_125 from line 440 of ultra_no_connect_pins_nets AK39 = No_Conn_FPGA_AK39 MGTYTXN1_125 from line 441 of ultra_no_connect_pins_nets AK8 = No_Conn_FPGA_AK8 MGTHTXN1_225 from line 609 of ultra_no_connect_pins_nets AK9 = No_Conn_FPGA_AK9 MGTHTXP1_225 from line 608 of ultra_no_connect_pins_nets AL40 = No_Conn_FPGA_AL40 MGTYTXP0_125 from line 443 of ultra_no_connect_pins_nets AL41 = No_Conn_FPGA_AL41 MGTYTXN0_125 from line 444 of ultra_no_connect_pins_nets AM38 = No_Conn_FPGA_AM38 MGTYTXP3_124 from line 414 of ultra_no_connect_pins_nets AM39 = No_Conn_FPGA_AM39 MGTYTXN3_124 from line 415 of ultra_no_connect_pins_nets AM8 = No_Conn_FPGA_AM8 MGTHTXN3_224 from line 592 of ultra_no_connect_pins_nets AM9 = No_Conn_FPGA_AM9 MGTHTXP3_224 from line 591 of ultra_no_connect_pins_nets AN40 = No_Conn_FPGA_AN40 MGTYTXP2_124 from line 417 of ultra_no_connect_pins_nets AN41 = No_Conn_FPGA_AN41 MGTYTXN2_124 from line 418 of ultra_no_connect_pins_nets AP38 = No_Conn_FPGA_AP38 MGTYTXP1_124 from line 420 of ultra_no_connect_pins_nets AP39 = No_Conn_FPGA_AP39 MGTYTXN1_124 from line 421 of ultra_no_connect_pins_nets AP8 = No_Conn_FPGA_AP8 MGTHTXN1_224 from line 595 of ultra_no_connect_pins_nets AP9 = No_Conn_FPGA_AP9 MGTHTXP1_224 from line 594 of ultra_no_connect_pins_nets AR40 = No_Conn_FPGA_AR40 MGTYTXP0_124 from line 423 of ultra_no_connect_pins_nets AR41 = No_Conn_FPGA_AR41 MGTYTXN0_124 from line 424 of ultra_no_connect_pins_nets C10 = No_Conn_FPGA_C10 MGTHTXN1_233 from line 727 of ultra_no_connect_pins_nets C11 = No_Conn_FPGA_C11 MGTHTXP1_233 from line 726 of ultra_no_connect_pins_nets C36 = No_Conn_FPGA_C36 MGTYTXP1_133 from line 573 of ultra_no_connect_pins_nets C37 = No_Conn_FPGA_C37 MGTYTXN1_133 from line 574 of ultra_no_connect_pins_nets C40 = No_Conn_FPGA_C40 MGTYTXP2_132 from line 556 of ultra_no_connect_pins_nets C41 = No_Conn_FPGA_C41 MGTYTXN2_132 from line 557 of ultra_no_connect_pins_nets C6 = No_Conn_FPGA_C6 MGTHTXN2_232 from line 710 of ultra_no_connect_pins_nets C7 = No_Conn_FPGA_C7 MGTHTXP2_232 from line 709 of ultra_no_connect_pins_nets D38 = No_Conn_FPGA_D38 MGTYTXP0_133 from line 576 of ultra_no_connect_pins_nets D39 = No_Conn_FPGA_D39 MGTYTXN0_133 from line 577 of ultra_no_connect_pins_nets D8 = No_Conn_FPGA_D8 MGTHTXN0_233 from line 730 of ultra_no_connect_pins_nets D9 = No_Conn_FPGA_D9 MGTHTXP0_233 from line 729 of ultra_no_connect_pins_nets E10 = No_Conn_FPGA_E10 MGTHTXN1_232 from line 713 of ultra_no_connect_pins_nets E11 = No_Conn_FPGA_E11 MGTHTXP1_232 from line 712 of ultra_no_connect_pins_nets E36 = No_Conn_FPGA_E36 MGTYTXP1_132 from line 559 of ultra_no_connect_pins_nets E37 = No_Conn_FPGA_E37 MGTYTXN1_132 from line 560 of ultra_no_connect_pins_nets E40 = No_Conn_FPGA_E40 MGTYTXP0_132 from line 562 of ultra_no_connect_pins_nets E41 = No_Conn_FPGA_E41 MGTYTXN0_132 from line 563 of ultra_no_connect_pins_nets E6 = No_Conn_FPGA_E6 MGTHTXN0_232 from line 716 of ultra_no_connect_pins_nets E7 = No_Conn_FPGA_E7 MGTHTXP0_232 from line 715 of ultra_no_connect_pins_nets F12 = No_Conn_FPGA_F12 MGTHTXN3_231 from line 690 of ultra_no_connect_pins_nets F13 = No_Conn_FPGA_F13 MGTHTXP3_231 from line 689 of ultra_no_connect_pins_nets F34 = No_Conn_FPGA_F34 MGTYTXP3_131 from line 536 of ultra_no_connect_pins_nets F35 = No_Conn_FPGA_F35 MGTYTXN3_131 from line 537 of ultra_no_connect_pins_nets F38 = No_Conn_FPGA_F38 MGTYTXP1_131 from line 542 of ultra_no_connect_pins_nets F39 = No_Conn_FPGA_F39 MGTYTXN1_131 from line 543 of ultra_no_connect_pins_nets F8 = No_Conn_FPGA_F8 MGTHTXN1_231 from line 696 of ultra_no_connect_pins_nets F9 = No_Conn_FPGA_F9 MGTHTXP1_231 from line 695 of ultra_no_connect_pins_nets G10 = No_Conn_FPGA_G10 MGTHTXN2_231 from line 693 of ultra_no_connect_pins_nets G11 = No_Conn_FPGA_G11 MGTHTXP2_231 from line 692 of ultra_no_connect_pins_nets G36 = No_Conn_FPGA_G36 MGTYTXP2_131 from line 539 of ultra_no_connect_pins_nets G37 = No_Conn_FPGA_G37 MGTYTXN2_131 from line 540 of ultra_no_connect_pins_nets G40 = No_Conn_FPGA_G40 MGTYTXP0_131 from line 545 of ultra_no_connect_pins_nets G41 = No_Conn_FPGA_G41 MGTYTXN0_131 from line 546 of ultra_no_connect_pins_nets G6 = No_Conn_FPGA_G6 MGTHTXN0_231 from line 699 of ultra_no_connect_pins_nets G7 = No_Conn_FPGA_G7 MGTHTXP0_231 from line 698 of ultra_no_connect_pins_nets H12 = No_Conn_FPGA_H12 MGTREFCLK1N_233 from line 853 of ultra_no_connect_pins_nets H13 = No_Conn_FPGA_H13 MGTREFCLK1P_233 from line 852 of ultra_no_connect_pins_nets H34 = No_Conn_FPGA_H34 MGTREFCLK1P_133 from line 794 of ultra_no_connect_pins_nets H35 = No_Conn_FPGA_H35 MGTREFCLK1N_133 from line 795 of ultra_no_connect_pins_nets H38 = No_Conn_FPGA_H38 MGTYTXP3_130 from line 522 of ultra_no_connect_pins_nets H39 = No_Conn_FPGA_H39 MGTYTXN3_130 from line 523 of ultra_no_connect_pins_nets H8 = No_Conn_FPGA_H8 MGTHTXN3_230 from line 676 of ultra_no_connect_pins_nets H9 = No_Conn_FPGA_H9 MGTHTXP3_230 from line 675 of ultra_no_connect_pins_nets J10 = No_Conn_FPGA_J10 MGTREFCLK0N_233 from line 856 of ultra_no_connect_pins_nets J11 = No_Conn_FPGA_J11 MGTREFCLK0P_233 from line 855 of ultra_no_connect_pins_nets J36 = No_Conn_FPGA_J36 MGTREFCLK0P_133 from line 797 of ultra_no_connect_pins_nets J37 = No_Conn_FPGA_J37 MGTREFCLK0N_133 from line 798 of ultra_no_connect_pins_nets K38 = No_Conn_FPGA_K38 MGTYTXP1_130 from line 525 of ultra_no_connect_pins_nets K39 = No_Conn_FPGA_K39 MGTYTXN1_130 from line 526 of ultra_no_connect_pins_nets K8 = No_Conn_FPGA_K8 MGTHTXN1_230 from line 679 of ultra_no_connect_pins_nets K9 = No_Conn_FPGA_K9 MGTHTXP1_230 from line 678 of ultra_no_connect_pins_nets L10 = No_Conn_FPGA_L10 MGTREFCLK0N_232 from line 849 of ultra_no_connect_pins_nets L11 = No_Conn_FPGA_L11 MGTREFCLK0P_232 from line 848 of ultra_no_connect_pins_nets L36 = No_Conn_FPGA_L36 MGTREFCLK0P_132 from line 790 of ultra_no_connect_pins_nets L37 = No_Conn_FPGA_L37 MGTREFCLK0N_132 from line 791 of ultra_no_connect_pins_nets M12 = No_Conn_FPGA_M12 MGTREFCLK1N_231 from line 842 of ultra_no_connect_pins_nets M13 = No_Conn_FPGA_M13 MGTREFCLK1P_231 from line 841 of ultra_no_connect_pins_nets M34 = No_Conn_FPGA_M34 MGTREFCLK1P_131 from line 783 of ultra_no_connect_pins_nets M35 = No_Conn_FPGA_M35 MGTREFCLK1N_131 from line 784 of ultra_no_connect_pins_nets M38 = No_Conn_FPGA_M38 MGTYTXP3_129 from line 508 of ultra_no_connect_pins_nets M39 = No_Conn_FPGA_M39 MGTYTXN3_129 from line 509 of ultra_no_connect_pins_nets M8 = No_Conn_FPGA_M8 MGTHTXN3_229 from line 662 of ultra_no_connect_pins_nets M9 = No_Conn_FPGA_M9 MGTHTXP3_229 from line 661 of ultra_no_connect_pins_nets N10 = No_Conn_FPGA_N10 MGTREFCLK0N_231 from line 845 of ultra_no_connect_pins_nets N11 = No_Conn_FPGA_N11 MGTREFCLK0P_231 from line 844 of ultra_no_connect_pins_nets N36 = No_Conn_FPGA_N36 MGTREFCLK0P_131 from line 786 of ultra_no_connect_pins_nets N37 = No_Conn_FPGA_N37 MGTREFCLK0N_131 from line 787 of ultra_no_connect_pins_nets P12 = No_Conn_FPGA_P12 MGTREFCLK1N_230 from line 838 of ultra_no_connect_pins_nets P13 = No_Conn_FPGA_P13 MGTREFCLK1P_230 from line 837 of ultra_no_connect_pins_nets P34 = No_Conn_FPGA_P34 MGTREFCLK1P_130 from line 779 of ultra_no_connect_pins_nets P35 = No_Conn_FPGA_P35 MGTREFCLK1N_130 from line 780 of ultra_no_connect_pins_nets P38 = No_Conn_FPGA_P38 MGTYTXP1_129 from line 511 of ultra_no_connect_pins_nets P39 = No_Conn_FPGA_P39 MGTYTXN1_129 from line 512 of ultra_no_connect_pins_nets P8 = No_Conn_FPGA_P8 MGTHTXN1_229 from line 665 of ultra_no_connect_pins_nets P9 = No_Conn_FPGA_P9 MGTHTXP1_229 from line 664 of ultra_no_connect_pins_nets T12 = No_Conn_FPGA_T12 MGTREFCLK1N_229 from line 831 of ultra_no_connect_pins_nets T13 = No_Conn_FPGA_T13 MGTREFCLK1P_229 from line 830 of ultra_no_connect_pins_nets T34 = No_Conn_FPGA_T34 MGTREFCLK1P_129 from line 772 of ultra_no_connect_pins_nets T35 = No_Conn_FPGA_T35 MGTREFCLK1N_129 from line 773 of ultra_no_connect_pins_nets T38 = No_Conn_FPGA_T38 MGTYTXP3_128 from line 488 of ultra_no_connect_pins_nets T39 = No_Conn_FPGA_T39 MGTYTXN3_128 from line 489 of ultra_no_connect_pins_nets T8 = No_Conn_FPGA_T8 MGTHTXN3_228 from line 648 of ultra_no_connect_pins_nets T9 = No_Conn_FPGA_T9 MGTHTXP3_228 from line 647 of ultra_no_connect_pins_nets U10 = No_Conn_FPGA_U10 MGTREFCLK0N_229 from line 834 of ultra_no_connect_pins_nets U11 = No_Conn_FPGA_U11 MGTREFCLK0P_229 from line 833 of ultra_no_connect_pins_nets U36 = No_Conn_FPGA_U36 MGTREFCLK0P_129 from line 775 of ultra_no_connect_pins_nets U37 = No_Conn_FPGA_U37 MGTREFCLK0N_129 from line 776 of ultra_no_connect_pins_nets U40 = No_Conn_FPGA_U40 MGTYTXP2_128 from line 491 of ultra_no_connect_pins_nets U41 = No_Conn_FPGA_U41 MGTYTXN2_128 from line 492 of ultra_no_connect_pins_nets V12 = No_Conn_FPGA_V12 MGTREFCLK1N_228 from line 824 of ultra_no_connect_pins_nets V13 = No_Conn_FPGA_V13 MGTREFCLK1P_228 from line 823 of ultra_no_connect_pins_nets V34 = No_Conn_FPGA_V34 MGTREFCLK1P_128 from line 765 of ultra_no_connect_pins_nets V35 = No_Conn_FPGA_V35 MGTREFCLK1N_128 from line 766 of ultra_no_connect_pins_nets V38 = No_Conn_FPGA_V38 MGTYTXP1_128 from line 494 of ultra_no_connect_pins_nets V39 = No_Conn_FPGA_V39 MGTYTXN1_128 from line 495 of ultra_no_connect_pins_nets V8 = No_Conn_FPGA_V8 MGTHTXN1_228 from line 651 of ultra_no_connect_pins_nets V9 = No_Conn_FPGA_V9 MGTHTXP1_228 from line 650 of ultra_no_connect_pins_nets W10 = No_Conn_FPGA_W10 MGTREFCLK0N_228 from line 827 of ultra_no_connect_pins_nets W11 = No_Conn_FPGA_W11 MGTREFCLK0P_228 from line 826 of ultra_no_connect_pins_nets W36 = No_Conn_FPGA_W36 MGTREFCLK0P_128 from line 768 of ultra_no_connect_pins_nets W37 = No_Conn_FPGA_W37 MGTREFCLK0N_128 from line 769 of ultra_no_connect_pins_nets W40 = No_Conn_FPGA_W40 MGTYTXP0_128 from line 497 of ultra_no_connect_pins_nets W41 = No_Conn_FPGA_W41 MGTYTXN0_128 from line 498 of ultra_no_connect_pins_nets Y38 = No_Conn_FPGA_Y38 MGTYTXP3_127 from line 474 of ultra_no_connect_pins_nets Y39 = No_Conn_FPGA_Y39 MGTYTXN3_127 from line 475 of ultra_no_connect_pins_nets Y8 = No_Conn_FPGA_Y8 MGTHTXN3_227 from line 634 of ultra_no_connect_pins_nets Y9 = No_Conn_FPGA_Y9 MGTHTXP3_227 from line 633 of ultra_no_connect_pins_nets U21_has_52_pins_is_IC_KSZ9031RNX.txt is Gb Ethernet transceiver for the other Hub's switch called U21 in drawing 34 called U21 in drawing 4 U22_has_52_pins_is_IC_KSZ9031RNX.txt is Gb Ethernet transceiver for this Hub's switch called U21 in drawing 34 called U22 in drawing 4 U25_has_64_pins_is_IC_Micron_MT28GU01G.txt is 1GB parallel flash with asynchronous read (CLK=Low, ADV#= Low) for Hub FPGA configuration power 1.8V called U25 in Drawing 36 U31_has_328_pins_is_IC_BCM53128.txt U32_has_328_pins_is_IC_BCM53128.txt U33_has_328_pins_is_IC_BCM53128.txt *** checked before but to redo *** U35_has_8_pins_is_IC_AT93C66B_EEPROM.txt is 4kBit serial PROM set for 256 x 16 oraganization (cf. Data Sheet p 110) for switch A power 3.3V called U35 in Drawing 17 U36_has_8_pins_is_IC_AT93C66B_EEPROM.txt is 4kBit serial PROM set for 256 x 16 oraganization (cf. Data Sheet p 110) for switch B power 3.3V called U35 in Drawing 17 U37_has_8_pins_is_IC_AT93C66B_EEPROM.txt is 4kBit serial PROM set for 256 x 16 oraganization (cf. Data Sheet p 110) for switch C power 3.3V called U35 in Drawing 17 U38_has_4_pins_is_IC_CWX_813_25_MHz.txt is 26 MHz clock for fanout to ethernet chips power 3.3V called U38 in Drawing 39 U39_has_14_pins_is_IC_TI_CDCLVC1106.txt is clock buffer 1-to-6 for 25MHz to 3x switch chips to 2x phys chips to Hub FPGA power 3.3V called U39 in Drawing 39 U41_has_8_pins_is_IC_M24256.txt is 256 kb 32kx8 400kHz EEPROM with address set for 1010000 with write control floating to enable writing for IPMC power 3.3V from IPMC power called U41 in Drawing 14 *** typo? 12C instead of I2C --> yes, to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 5 = IPMC_MGT_12C_SDA SDA from line 170 of ipmc_hw_adrs_handle_switch_ipmb_nets 6 = IPMC_MGT_12C_SCK SCL from line 172 of ipmc_hw_adrs_handle_switch_ipmb_nets U401_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 01 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U402_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 02 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U403_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 03 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U404_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 04 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U405_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 05 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U406_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 06 / Group 01 = FEX 03 power 1.8V called U401 in Drawing 52 U407_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 07 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U408_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 08 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U409_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 09 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U410_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 10 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U411_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 11 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U412_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 12 / Group 02 = FEX 04 power 1.8V called U401 in Drawing 52 U413_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 13 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U414_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 14 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U415_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 15 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U416_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 16 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U417_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 17 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U418_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 18 / Group 03 = FEX 05 power 1.8V called U401 in Drawing 52 U419_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 19 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U420_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 20 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U421_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 21 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U422_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 22 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U423_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 23 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U424_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 24 / Group 04 = FEX 06 power 1.8V called U401 in Drawing 52 U425_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 25 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U426_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 26 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U427_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 27 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U428_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 28 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U429_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 29 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U430_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 30 / Group 05 = FEX 07 power 1.8V called U401 in Drawing 52 U431_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 31 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U432_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 32 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U433_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 33 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U434_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 34 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U435_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 35 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U436_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 36 / Group 06 = FEX 08 power 1.8V called U401 in Drawing 52 U437_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 36 / Group 07 = Other Hub power 1.8V called U401 in Drawing 52 U438_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 38 / Group 07 = Other Hub power 1.8V called U401 in Drawing 52 U439_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 39 / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U440_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 40 / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U441_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 4` / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U442_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 42 / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U443_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 43 / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U444_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 44 / Group 08 = FEX 09 power 1.8V called U401 in Drawing 52 U445_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 45 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U446_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 46 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U447_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 47 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U448_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 48 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U449_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 49 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U450_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 50 / Group 09 = FEX 10 power 1.8V called U401 in Drawing 52 U451_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 51 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U452_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 52 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U453_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 53 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U454_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 54 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U455_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 55 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U456_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 56 / Group 10 = FEX 11 power 1.8V called U401 in Drawing 52 U457_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 57 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U458_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 58 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U459_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 59 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U460_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 60 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U461_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 61 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U462_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 61 / Group 11 = FEX 12 power 1.8V called U401 in Drawing 52 U463_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 63 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U464_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 64 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U465_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 65 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U466_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 66 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U467_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 67 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U468_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 68 / Group 12 = FEX 13 power 1.8V called U401 in Drawing 52 U469_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 69 / Group 13 = FEX 14 power 1.8V called U401 in Drawing 52 U470_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 70 / Group 13 = FEX 14 power 1.8V called U401 in Drawing 52 U471_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 71 / Group 13 = FEX 14 power 1.8V called U401 in Drawing 52 U472_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 72 / Group 13 = FEX 14 power 1.8V called U401 in Drawing 52 U473_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 73 / Group 13 = FEX 14 power 1.8V called U401 in Drawing 52 U474_has_20_pins_is_IC_NB7VQ14M.txt is 14Gbps 1-to-4 fanout for MGT Fanout channel 74 / Group = FEX 14 power 1.8V called U401 in Drawing 52 *** very minor typo "Hub" not uppercase *** in fact every Even channel number is like that, *** probably from the MIGT template. --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 9 = MGT_FO_CH_74_OCP_Hub_CMP Q2 Inverted Out from line 8877 of mgt_fanout_channel_nets 10 = MGT_FO_CH_74_OCP_Hub_DIR Q2 Non-inv Out from line 8876 of mgt_fanout_channel_nets U501_has_5_pins_is_IC_65LVDT2.txt is high speed differential line receiver to single ended for 40 MHz from FPGA to PLL power 3.3V is U501 in drawing 40A U502_has_10_pins_is_IC_PLL_40M0787.txt is 40 MHz PLL for 40 MHz clock power 3.3V called U502 in drawing 40A *** ok to NOT drive reset pin? --> ok, and as in CMX U503_has_20_pins_is_IC_CDCLVD1204.txt is 2-input clock selector to 4-way fanout with clock select for input 0 for 40 MHz clock to 320 MHz, second fanout, ROD, Hub FPGA power 2.5V called U503 in drawing 40B U504_has_64_pins_is_IC_CDCLVD1216.txt is a 2-input clock selector to 16-way fanout with clock select to either input 0 or no output for 40 MHz to FEXs and other Hub power 2.5V called U504 in drawing 40B U505_has_5_pins_is_IC_65LVDT2.txt is high speed differential line receiver to single ended for 40 MHz to 320MHz PLL power 3.3V is U505 in drawing 41 U506_has_10_pins_is_IC_PLL_320M6296.txt is PLL for 320 MHz for 320 MHz gneration power 3.3V is U506 in drawing 41 *** ok to NOT drive reset pin? --> ok, and as in CMX U507_has_41_pins_is_IC_MC100LVEP111.txt is a 2-input clock selector to 10-way fanout with fixed select input 0 for 320 MHz clock fanout power 2.5V is U507 in drawing 41 *** minor typo "Q5 "vs "Q0" (and backwards "_B") for unused channel --> to be fixed --> fixed in out_Comp_Pin_Nets_2017-01-20_12-00 30 = No_Conn_320_Fanout_Q5 Q0_B from line 549 of clock_generation_nets 31 = No_Conn_320_Fanout_Q5_B Q0 from line 550 of clock_generation_nets U551_has_24_pins_is_IC_74AVCH8T245.txt is 8-channel bus transceiver/level translator with direction A to B for all ROD LEDs and LEMO power 1.8V -> 3.3V called U551 in drawing 50 U552_has_14_pins_is_IC_74LVC07A.txt is hex buffer with open drain for ROD blue LEDs and LEMO power 3.3V called U552 in drawing 50 U553_has_24_pins_is_IC_74AVCH8T245.txt is 8-channel bus transceiver/level translator with direction A to B for 2x Hub FPGA Phys Chip to this hub switch for 2x Hub FPGA Phys Chip to other hub switch for 3x Hub FPGA personal LEDs and 1x channels unused power 1.8V -> 3.3V called U553 in drawing 34 (didn't spot FPGA LEDs) U554_has_24_pins_is_IC_74AVCH8T245.txt is 8-channel bus transceiver/level translator with direction B to A for 2x TMS inputs for 2x TCK inputs for 1x TDI inputs and 3x channels unused power 3.3V -> 1.8V called U554 in drawing 53 U555_has_8_pins_is_IC_74AVCH2T45.txt is 2-channel bus transceiver/level translator with direction B to A for config_done to ROD power control for JTAG TDO power 1.8V -> 3.3V called U555 in drawing 36+32 and drawing 53 U556_has_6_pins_is_IC_NC7SV157.txt is 2-input multiplexer for including/excluding ROD in JTAG chain power 1.8V called U556 in drawing 33 U557_has_5_pins_is_IC_NC7SV08.txt is 2-input AND for sending JTAG TDI to ROD power 1.8V called U557 in drawing 33 U561_has_8_pins_is_IC_74AVCH2T45.txt is 2-channel bus transceiver/level translator with direction B to A for sending 2 signals to front-panel access power 1.8V -> 3.3V called U561 in drawing 53 U562_has_6_pins_is_NOT_A_PART.txt is LVDS oscillator for spare power 3.3V called U562 in drawing 53 U1501_has_12_pins_is_IC_ltc4315.txt is I2C bus buffer for I2C bus to PM bus *with* output rise time acceleration (ACC_B high and VCC2 high) power 3.3V called U1503 in drawing 37 U1502_has_12_pins_is_IC_ltc4315.txt is I2C bus buffer for I2C bus to FPGA disable output rise time acceleration (ACC_B high and VCC2 gnd) power 3.3V called U1502 in drawing 37 U1503_has_12_pins_is_IC_ltc4315.txt is I2C bus buffer for I2C bus to ROD disable output rise time acceleration (ACC_B high and VCC2 gnd) power 3.3V called U1503 in drawing 37 U1851_has_3_pins_is_IC_REF3112.txt is 1.25 voltage reference for Sysmon called U1 in drawing 25 power filtered 1.8V U2951_has_6_pins_is_IC_TPS3808.txt is Programmable-Delay Supervisory Circuit for 12V power startup using 100nF for about .5s power 5V constant called U1 in drawing 30 U2952_has_6_pins_is_IC_LM3880.txt is power sequencer for power enable after 12V good power 5V constant called U2 in drawing 30 U2953_has_14_pins_is_IC_74HC10.txt is triple 3-input NAND gate for power enable logic power 5V constant called U3 in drawing 30 U2954_has_14_pins_is_IC_74HCT04.txt is hex inverter for power enable logic power 5V constant called U4 in drawing 30 U2955_has_14_pins_is_IC_74HC21.txt is Dual 4-input AND gate for 2x partial all power good power 5V constant called U5 in drawing 31 U2956_has_14_pins_is_IC_74HC21.txt is Dual 4-input AND gate for final all power good power 5V constant called U6 in drawing 31 U2957_has_6_pins_is_IC_TPS3808.txt is Programmable-Delay Supervisory Circuit for MGT AVAUX 1.8V ok power 5V constant called U7 in drawing 31 U2958_has_6_pins_is_IC_TPS3808.txt is Programmable-Delay Supervisory Circuit for bulk 2.5V ok power 5V constant called U8 in drawing 31 U2959_has_6_pins_is_IC_TPS3808.txt is Programmable-Delay Supervisory Circuit for final board startup signal 3.3 V output using 100nF for about .5s called U9 in drawing 31 power 5V constant U2960_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U10 in drawing 32 U2961_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U11 in drawing 32 U2962_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U12 in drawing 32 U2963_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U13 in drawing 32 U2964_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U14 in drawing 32 U2965_has_5_pins_is_IC_NC7SV05.txt is Open-Drain inverter power 3.3V called U15 in drawing 32 U2966_has_5_pins_is_IC_NC7SV08.txt is 2-input AND gate for partial enable rod power power 3.3V called U16 in drawing 32 U2967_has_5_pins_is_IC_NC7SV08.txt is 2-input AND gate for partial enable rod power power 3.3V called U17 in drawing 32 U2968_has_5_pins_is_IC_NC7SV08.txt is 2-input AND gate for final enable rod power power 1.8V 2016_07_07_ROD_Hub_interface.pdf called U18 in drawing 32 Table for Fanout check |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | Ref | 1 = Non-Inv Input | 2 = Center-Tap | 3 = VRef Out | 4 = Inverted Input | 5 = Equalizer Enable | 9 = Q2 Inverted Out | 10 = Q2 Non-Inv Out | 11 = Q1 Inverted Out | 12 = Q1 Non-Inv Out | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U401 | MGT_FO_CH_1_IN_DIR | MGT_FO_CMR_CH_1 | MGT_FO_CMR_CH_1 | MGT_FO_CH_1_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_1_OCP_ROD_CMP | MGT_FO_CH_1_OCP_ROD_DIR | MGT_FO_CH_1_OCP_HUB_CMP | MGT_FO_CH_1_OCP_HUB_DIR | | U402 | MGT_FO_CH_2_IN_DIR | MGT_FO_CMR_CH_2 | MGT_FO_CMR_CH_2 | MGT_FO_CH_2_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_2_OCP_Hub_CMP | MGT_FO_CH_2_OCP_Hub_DIR | MGT_FO_CH_2_OCP_ROD_CMP | MGT_FO_CH_2_OCP_ROD_DIR | | U403 | MGT_FO_CH_3_IN_DIR | MGT_FO_CMR_CH_3 | MGT_FO_CMR_CH_3 | MGT_FO_CH_3_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_3_OCP_ROD_CMP | MGT_FO_CH_3_OCP_ROD_DIR | MGT_FO_CH_3_OCP_HUB_CMP | MGT_FO_CH_3_OCP_HUB_DIR | | U404 | MGT_FO_CH_4_IN_DIR | MGT_FO_CMR_CH_4 | MGT_FO_CMR_CH_4 | MGT_FO_CH_4_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_4_OCP_Hub_CMP | MGT_FO_CH_4_OCP_Hub_DIR | MGT_FO_CH_4_OCP_ROD_CMP | MGT_FO_CH_4_OCP_ROD_DIR | | U405 | MGT_FO_CH_5_IN_DIR | MGT_FO_CMR_CH_5 | MGT_FO_CMR_CH_5 | MGT_FO_CH_5_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_5_OCP_ROD_CMP | MGT_FO_CH_5_OCP_ROD_DIR | MGT_FO_CH_5_OCP_HUB_CMP | MGT_FO_CH_5_OCP_HUB_DIR | | U406 | MGT_FO_CH_6_IN_DIR | MGT_FO_CMR_CH_6 | MGT_FO_CMR_CH_6 | MGT_FO_CH_6_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | MGT_FO_CH_6_OCP_Hub_CMP | MGT_FO_CH_6_OCP_Hub_DIR | MGT_FO_CH_6_OCP_ROD_CMP | MGT_FO_CH_6_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U407 | MGT_FO_CH_7_IN_DIR | MGT_FO_CMR_CH_7 | MGT_FO_CMR_CH_7 | MGT_FO_CH_7_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_7_OCP_ROD_CMP | MGT_FO_CH_7_OCP_ROD_DIR | MGT_FO_CH_7_OCP_HUB_CMP | MGT_FO_CH_7_OCP_HUB_DIR | | U408 | MGT_FO_CH_8_IN_DIR | MGT_FO_CMR_CH_8 | MGT_FO_CMR_CH_8 | MGT_FO_CH_8_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_8_OCP_Hub_CMP | MGT_FO_CH_8_OCP_Hub_DIR | MGT_FO_CH_8_OCP_ROD_CMP | MGT_FO_CH_8_OCP_ROD_DIR | | U409 | MGT_FO_CH_9_IN_DIR | MGT_FO_CMR_CH_9 | MGT_FO_CMR_CH_9 | MGT_FO_CH_9_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_9_OCP_ROD_CMP | MGT_FO_CH_9_OCP_ROD_DIR | MGT_FO_CH_9_OCP_HUB_CMP | MGT_FO_CH_9_OCP_HUB_DIR | | U410 | MGT_FO_CH_10_IN_DIR | MGT_FO_CMR_CH_10 | MGT_FO_CMR_CH_10 | MGT_FO_CH_10_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_10_OCP_Hub_CMP | MGT_FO_CH_10_OCP_Hub_DIR | MGT_FO_CH_10_OCP_ROD_CMP | MGT_FO_CH_10_OCP_ROD_DIR | | U411 | MGT_FO_CH_11_IN_DIR | MGT_FO_CMR_CH_11 | MGT_FO_CMR_CH_11 | MGT_FO_CH_11_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_11_OCP_ROD_CMP | MGT_FO_CH_11_OCP_ROD_DIR | MGT_FO_CH_11_OCP_HUB_CMP | MGT_FO_CH_11_OCP_HUB_DIR | | U412 | MGT_FO_CH_12_IN_DIR | MGT_FO_CMR_CH_12 | MGT_FO_CMR_CH_12 | MGT_FO_CH_12_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | MGT_FO_CH_12_OCP_Hub_CMP | MGT_FO_CH_12_OCP_Hub_DIR | MGT_FO_CH_12_OCP_ROD_CMP | MGT_FO_CH_12_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U413 | MGT_FO_CH_13_IN_DIR | MGT_FO_CMR_CH_13 | MGT_FO_CMR_CH_13 | MGT_FO_CH_13_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_13_OCP_ROD_CMP | MGT_FO_CH_13_OCP_ROD_DIR | MGT_FO_CH_13_OCP_HUB_CMP | MGT_FO_CH_13_OCP_HUB_DIR | | U414 | MGT_FO_CH_14_IN_DIR | MGT_FO_CMR_CH_14 | MGT_FO_CMR_CH_14 | MGT_FO_CH_14_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_14_OCP_Hub_CMP | MGT_FO_CH_14_OCP_Hub_DIR | MGT_FO_CH_14_OCP_ROD_CMP | MGT_FO_CH_14_OCP_ROD_DIR | | U415 | MGT_FO_CH_15_IN_DIR | MGT_FO_CMR_CH_15 | MGT_FO_CMR_CH_15 | MGT_FO_CH_15_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_15_OCP_ROD_CMP | MGT_FO_CH_15_OCP_ROD_DIR | MGT_FO_CH_15_OCP_HUB_CMP | MGT_FO_CH_15_OCP_HUB_DIR | | U416 | MGT_FO_CH_16_IN_DIR | MGT_FO_CMR_CH_16 | MGT_FO_CMR_CH_16 | MGT_FO_CH_16_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_16_OCP_Hub_CMP | MGT_FO_CH_16_OCP_Hub_DIR | MGT_FO_CH_16_OCP_ROD_CMP | MGT_FO_CH_16_OCP_ROD_DIR | | U417 | MGT_FO_CH_17_IN_DIR | MGT_FO_CMR_CH_17 | MGT_FO_CMR_CH_17 | MGT_FO_CH_17_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_17_OCP_ROD_CMP | MGT_FO_CH_17_OCP_ROD_DIR | MGT_FO_CH_17_OCP_HUB_CMP | MGT_FO_CH_17_OCP_HUB_DIR | | U418 | MGT_FO_CH_18_IN_DIR | MGT_FO_CMR_CH_18 | MGT_FO_CMR_CH_18 | MGT_FO_CH_18_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | MGT_FO_CH_18_OCP_Hub_CMP | MGT_FO_CH_18_OCP_Hub_DIR | MGT_FO_CH_18_OCP_ROD_CMP | MGT_FO_CH_18_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U419 | MGT_FO_CH_19_IN_DIR | MGT_FO_CMR_CH_19 | MGT_FO_CMR_CH_19 | MGT_FO_CH_19_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_19_OCP_ROD_CMP | MGT_FO_CH_19_OCP_ROD_DIR | MGT_FO_CH_19_OCP_HUB_CMP | MGT_FO_CH_19_OCP_HUB_DIR | | U420 | MGT_FO_CH_20_IN_DIR | MGT_FO_CMR_CH_20 | MGT_FO_CMR_CH_20 | MGT_FO_CH_20_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_20_OCP_Hub_CMP | MGT_FO_CH_20_OCP_Hub_DIR | MGT_FO_CH_20_OCP_ROD_CMP | MGT_FO_CH_20_OCP_ROD_DIR | | U421 | MGT_FO_CH_21_IN_DIR | MGT_FO_CMR_CH_21 | MGT_FO_CMR_CH_21 | MGT_FO_CH_21_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_21_OCP_ROD_CMP | MGT_FO_CH_21_OCP_ROD_DIR | MGT_FO_CH_21_OCP_HUB_CMP | MGT_FO_CH_21_OCP_HUB_DIR | | U422 | MGT_FO_CH_22_IN_DIR | MGT_FO_CMR_CH_22 | MGT_FO_CMR_CH_22 | MGT_FO_CH_22_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_22_OCP_Hub_CMP | MGT_FO_CH_22_OCP_Hub_DIR | MGT_FO_CH_22_OCP_ROD_CMP | MGT_FO_CH_22_OCP_ROD_DIR | | U423 | MGT_FO_CH_23_IN_DIR | MGT_FO_CMR_CH_23 | MGT_FO_CMR_CH_23 | MGT_FO_CH_23_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_23_OCP_ROD_CMP | MGT_FO_CH_23_OCP_ROD_DIR | MGT_FO_CH_23_OCP_HUB_CMP | MGT_FO_CH_23_OCP_HUB_DIR | | U424 | MGT_FO_CH_24_IN_DIR | MGT_FO_CMR_CH_24 | MGT_FO_CMR_CH_24 | MGT_FO_CH_24_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | MGT_FO_CH_24_OCP_Hub_CMP | MGT_FO_CH_24_OCP_Hub_DIR | MGT_FO_CH_24_OCP_ROD_CMP | MGT_FO_CH_24_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U425 | MGT_FO_CH_25_IN_DIR | MGT_FO_CMR_CH_25 | MGT_FO_CMR_CH_25 | MGT_FO_CH_25_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_25_OCP_ROD_CMP | MGT_FO_CH_25_OCP_ROD_DIR | MGT_FO_CH_25_OCP_HUB_CMP | MGT_FO_CH_25_OCP_HUB_DIR | | U426 | MGT_FO_CH_26_IN_DIR | MGT_FO_CMR_CH_26 | MGT_FO_CMR_CH_26 | MGT_FO_CH_26_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_26_OCP_Hub_CMP | MGT_FO_CH_26_OCP_Hub_DIR | MGT_FO_CH_26_OCP_ROD_CMP | MGT_FO_CH_26_OCP_ROD_DIR | | U427 | MGT_FO_CH_27_IN_DIR | MGT_FO_CMR_CH_27 | MGT_FO_CMR_CH_27 | MGT_FO_CH_27_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_27_OCP_ROD_CMP | MGT_FO_CH_27_OCP_ROD_DIR | MGT_FO_CH_27_OCP_HUB_CMP | MGT_FO_CH_27_OCP_HUB_DIR | | U428 | MGT_FO_CH_28_IN_DIR | MGT_FO_CMR_CH_28 | MGT_FO_CMR_CH_28 | MGT_FO_CH_28_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_28_OCP_Hub_CMP | MGT_FO_CH_28_OCP_Hub_DIR | MGT_FO_CH_28_OCP_ROD_CMP | MGT_FO_CH_28_OCP_ROD_DIR | | U429 | MGT_FO_CH_29_IN_DIR | MGT_FO_CMR_CH_29 | MGT_FO_CMR_CH_29 | MGT_FO_CH_29_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_29_OCP_ROD_CMP | MGT_FO_CH_29_OCP_ROD_DIR | MGT_FO_CH_29_OCP_HUB_CMP | MGT_FO_CH_29_OCP_HUB_DIR | | U430 | MGT_FO_CH_30_IN_DIR | MGT_FO_CMR_CH_30 | MGT_FO_CMR_CH_30 | MGT_FO_CH_30_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | MGT_FO_CH_30_OCP_Hub_CMP | MGT_FO_CH_30_OCP_Hub_DIR | MGT_FO_CH_30_OCP_ROD_CMP | MGT_FO_CH_30_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U431 | MGT_FO_CH_31_IN_DIR | MGT_FO_CMR_CH_31 | MGT_FO_CMR_CH_31 | MGT_FO_CH_31_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_31_OCP_ROD_CMP | MGT_FO_CH_31_OCP_ROD_DIR | MGT_FO_CH_31_OCP_HUB_CMP | MGT_FO_CH_31_OCP_HUB_DIR | | U432 | MGT_FO_CH_32_IN_DIR | MGT_FO_CMR_CH_32 | MGT_FO_CMR_CH_32 | MGT_FO_CH_32_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_32_OCP_Hub_CMP | MGT_FO_CH_32_OCP_Hub_DIR | MGT_FO_CH_32_OCP_ROD_CMP | MGT_FO_CH_32_OCP_ROD_DIR | | U433 | MGT_FO_CH_33_IN_DIR | MGT_FO_CMR_CH_33 | MGT_FO_CMR_CH_33 | MGT_FO_CH_33_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_33_OCP_ROD_CMP | MGT_FO_CH_33_OCP_ROD_DIR | MGT_FO_CH_33_OCP_HUB_CMP | MGT_FO_CH_33_OCP_HUB_DIR | | U434 | MGT_FO_CH_34_IN_DIR | MGT_FO_CMR_CH_34 | MGT_FO_CMR_CH_34 | MGT_FO_CH_34_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_34_OCP_Hub_CMP | MGT_FO_CH_34_OCP_Hub_DIR | MGT_FO_CH_34_OCP_ROD_CMP | MGT_FO_CH_34_OCP_ROD_DIR | | U435 | MGT_FO_CH_35_IN_DIR | MGT_FO_CMR_CH_35 | MGT_FO_CMR_CH_35 | MGT_FO_CH_35_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_35_OCP_ROD_CMP | MGT_FO_CH_35_OCP_ROD_DIR | MGT_FO_CH_35_OCP_HUB_CMP | MGT_FO_CH_35_OCP_HUB_DIR | | U436 | MGT_FO_CH_36_IN_DIR | MGT_FO_CMR_CH_36 | MGT_FO_CMR_CH_36 | MGT_FO_CH_36_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | MGT_FO_CH_36_OCP_Hub_CMP | MGT_FO_CH_36_OCP_Hub_DIR | MGT_FO_CH_36_OCP_ROD_CMP | MGT_FO_CH_36_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U437 | MGT_FO_CH_37_IN_DIR | MGT_FO_CMR_CH_37 | MGT_FO_CMR_CH_37 | MGT_FO_CH_37_IN_CMP | MGT_FO_EQU_ENB_GRP_7 | MGT_FO_CH_37_OCP_ROD_CMP | MGT_FO_CH_37_OCP_ROD_DIR | MGT_FO_CH_37_OCP_HUB_CMP | MGT_FO_CH_37_OCP_HUB_DIR | | U438 | MGT_FO_CH_38_IN_DIR | MGT_FO_CMR_CH_38 | MGT_FO_CMR_CH_38 | MGT_FO_CH_38_IN_CMP | MGT_FO_EQU_ENB_GRP_7 | MGT_FO_CH_38_OCP_Hub_CMP | MGT_FO_CH_38_OCP_Hub_DIR | MGT_FO_CH_38_OCP_ROD_CMP | MGT_FO_CH_38_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U439 | MGT_FO_CH_39_IN_DIR | MGT_FO_CMR_CH_39 | MGT_FO_CMR_CH_39 | MGT_FO_CH_39_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_39_OCP_ROD_CMP | MGT_FO_CH_39_OCP_ROD_DIR | MGT_FO_CH_39_OCP_HUB_CMP | MGT_FO_CH_39_OCP_HUB_DIR | | U440 | MGT_FO_CH_40_IN_DIR | MGT_FO_CMR_CH_40 | MGT_FO_CMR_CH_40 | MGT_FO_CH_40_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_40_OCP_Hub_CMP | MGT_FO_CH_40_OCP_Hub_DIR | MGT_FO_CH_40_OCP_ROD_CMP | MGT_FO_CH_40_OCP_ROD_DIR | | U441 | MGT_FO_CH_41_IN_DIR | MGT_FO_CMR_CH_41 | MGT_FO_CMR_CH_41 | MGT_FO_CH_41_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_41_OCP_ROD_CMP | MGT_FO_CH_41_OCP_ROD_DIR | MGT_FO_CH_41_OCP_HUB_CMP | MGT_FO_CH_41_OCP_HUB_DIR | | U442 | MGT_FO_CH_42_IN_DIR | MGT_FO_CMR_CH_42 | MGT_FO_CMR_CH_42 | MGT_FO_CH_42_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_42_OCP_Hub_CMP | MGT_FO_CH_42_OCP_Hub_DIR | MGT_FO_CH_42_OCP_ROD_CMP | MGT_FO_CH_42_OCP_ROD_DIR | | U443 | MGT_FO_CH_43_IN_DIR | MGT_FO_CMR_CH_43 | MGT_FO_CMR_CH_43 | MGT_FO_CH_43_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_43_OCP_ROD_CMP | MGT_FO_CH_43_OCP_ROD_DIR | MGT_FO_CH_43_OCP_HUB_CMP | MGT_FO_CH_43_OCP_HUB_DIR | | U444 | MGT_FO_CH_44_IN_DIR | MGT_FO_CMR_CH_44 | MGT_FO_CMR_CH_44 | MGT_FO_CH_44_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | MGT_FO_CH_44_OCP_Hub_CMP | MGT_FO_CH_44_OCP_Hub_DIR | MGT_FO_CH_44_OCP_ROD_CMP | MGT_FO_CH_44_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U445 | MGT_FO_CH_45_IN_DIR | MGT_FO_CMR_CH_45 | MGT_FO_CMR_CH_45 | MGT_FO_CH_45_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_45_OCP_ROD_CMP | MGT_FO_CH_45_OCP_ROD_DIR | MGT_FO_CH_45_OCP_HUB_CMP | MGT_FO_CH_45_OCP_HUB_DIR | | U446 | MGT_FO_CH_46_IN_DIR | MGT_FO_CMR_CH_46 | MGT_FO_CMR_CH_46 | MGT_FO_CH_46_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_46_OCP_Hub_CMP | MGT_FO_CH_46_OCP_Hub_DIR | MGT_FO_CH_46_OCP_ROD_CMP | MGT_FO_CH_46_OCP_ROD_DIR | | U447 | MGT_FO_CH_47_IN_DIR | MGT_FO_CMR_CH_47 | MGT_FO_CMR_CH_47 | MGT_FO_CH_47_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_47_OCP_ROD_CMP | MGT_FO_CH_47_OCP_ROD_DIR | MGT_FO_CH_47_OCP_HUB_CMP | MGT_FO_CH_47_OCP_HUB_DIR | | U448 | MGT_FO_CH_48_IN_DIR | MGT_FO_CMR_CH_48 | MGT_FO_CMR_CH_48 | MGT_FO_CH_48_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_48_OCP_Hub_CMP | MGT_FO_CH_48_OCP_Hub_DIR | MGT_FO_CH_48_OCP_ROD_CMP | MGT_FO_CH_48_OCP_ROD_DIR | | U449 | MGT_FO_CH_49_IN_DIR | MGT_FO_CMR_CH_49 | MGT_FO_CMR_CH_49 | MGT_FO_CH_49_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_49_OCP_ROD_CMP | MGT_FO_CH_49_OCP_ROD_DIR | MGT_FO_CH_49_OCP_HUB_CMP | MGT_FO_CH_49_OCP_HUB_DIR | | U450 | MGT_FO_CH_50_IN_DIR | MGT_FO_CMR_CH_50 | MGT_FO_CMR_CH_50 | MGT_FO_CH_50_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | MGT_FO_CH_50_OCP_Hub_CMP | MGT_FO_CH_50_OCP_Hub_DIR | MGT_FO_CH_50_OCP_ROD_CMP | MGT_FO_CH_50_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U451 | MGT_FO_CH_51_IN_DIR | MGT_FO_CMR_CH_51 | MGT_FO_CMR_CH_51 | MGT_FO_CH_51_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_51_OCP_ROD_CMP | MGT_FO_CH_51_OCP_ROD_DIR | MGT_FO_CH_51_OCP_HUB_CMP | MGT_FO_CH_51_OCP_HUB_DIR | | U452 | MGT_FO_CH_52_IN_DIR | MGT_FO_CMR_CH_52 | MGT_FO_CMR_CH_52 | MGT_FO_CH_52_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_52_OCP_Hub_CMP | MGT_FO_CH_52_OCP_Hub_DIR | MGT_FO_CH_52_OCP_ROD_CMP | MGT_FO_CH_52_OCP_ROD_DIR | | U453 | MGT_FO_CH_53_IN_DIR | MGT_FO_CMR_CH_53 | MGT_FO_CMR_CH_53 | MGT_FO_CH_53_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_53_OCP_ROD_CMP | MGT_FO_CH_53_OCP_ROD_DIR | MGT_FO_CH_53_OCP_HUB_CMP | MGT_FO_CH_53_OCP_HUB_DIR | | U454 | MGT_FO_CH_54_IN_DIR | MGT_FO_CMR_CH_54 | MGT_FO_CMR_CH_54 | MGT_FO_CH_54_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_54_OCP_Hub_CMP | MGT_FO_CH_54_OCP_Hub_DIR | MGT_FO_CH_54_OCP_ROD_CMP | MGT_FO_CH_54_OCP_ROD_DIR | | U455 | MGT_FO_CH_55_IN_DIR | MGT_FO_CMR_CH_55 | MGT_FO_CMR_CH_55 | MGT_FO_CH_55_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_55_OCP_ROD_CMP | MGT_FO_CH_55_OCP_ROD_DIR | MGT_FO_CH_55_OCP_HUB_CMP | MGT_FO_CH_55_OCP_HUB_DIR | | U456 | MGT_FO_CH_56_IN_DIR | MGT_FO_CMR_CH_56 | MGT_FO_CMR_CH_56 | MGT_FO_CH_56_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | MGT_FO_CH_56_OCP_Hub_CMP | MGT_FO_CH_56_OCP_Hub_DIR | MGT_FO_CH_56_OCP_ROD_CMP | MGT_FO_CH_56_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U457 | MGT_FO_CH_57_IN_DIR | MGT_FO_CMR_CH_57 | MGT_FO_CMR_CH_57 | MGT_FO_CH_57_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_57_OCP_ROD_CMP | MGT_FO_CH_57_OCP_ROD_DIR | MGT_FO_CH_57_OCP_HUB_CMP | MGT_FO_CH_57_OCP_HUB_DIR | | U458 | MGT_FO_CH_58_IN_DIR | MGT_FO_CMR_CH_58 | MGT_FO_CMR_CH_58 | MGT_FO_CH_58_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_58_OCP_Hub_CMP | MGT_FO_CH_58_OCP_Hub_DIR | MGT_FO_CH_58_OCP_ROD_CMP | MGT_FO_CH_58_OCP_ROD_DIR | | U459 | MGT_FO_CH_59_IN_DIR | MGT_FO_CMR_CH_59 | MGT_FO_CMR_CH_59 | MGT_FO_CH_59_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_59_OCP_ROD_CMP | MGT_FO_CH_59_OCP_ROD_DIR | MGT_FO_CH_59_OCP_HUB_CMP | MGT_FO_CH_59_OCP_HUB_DIR | | U460 | MGT_FO_CH_60_IN_DIR | MGT_FO_CMR_CH_60 | MGT_FO_CMR_CH_60 | MGT_FO_CH_60_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_60_OCP_Hub_CMP | MGT_FO_CH_60_OCP_Hub_DIR | MGT_FO_CH_60_OCP_ROD_CMP | MGT_FO_CH_60_OCP_ROD_DIR | | U461 | MGT_FO_CH_61_IN_DIR | MGT_FO_CMR_CH_61 | MGT_FO_CMR_CH_61 | MGT_FO_CH_61_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_61_OCP_ROD_CMP | MGT_FO_CH_61_OCP_ROD_DIR | MGT_FO_CH_61_OCP_HUB_CMP | MGT_FO_CH_61_OCP_HUB_DIR | | U462 | MGT_FO_CH_62_IN_DIR | MGT_FO_CMR_CH_62 | MGT_FO_CMR_CH_62 | MGT_FO_CH_62_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | MGT_FO_CH_62_OCP_Hub_CMP | MGT_FO_CH_62_OCP_Hub_DIR | MGT_FO_CH_62_OCP_ROD_CMP | MGT_FO_CH_62_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U463 | MGT_FO_CH_63_IN_DIR | MGT_FO_CMR_CH_63 | MGT_FO_CMR_CH_63 | MGT_FO_CH_63_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_63_OCP_ROD_CMP | MGT_FO_CH_63_OCP_ROD_DIR | MGT_FO_CH_63_OCP_HUB_CMP | MGT_FO_CH_63_OCP_HUB_DIR | | U464 | MGT_FO_CH_64_IN_DIR | MGT_FO_CMR_CH_64 | MGT_FO_CMR_CH_64 | MGT_FO_CH_64_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_64_OCP_Hub_CMP | MGT_FO_CH_64_OCP_Hub_DIR | MGT_FO_CH_64_OCP_ROD_CMP | MGT_FO_CH_64_OCP_ROD_DIR | | U465 | MGT_FO_CH_65_IN_DIR | MGT_FO_CMR_CH_65 | MGT_FO_CMR_CH_65 | MGT_FO_CH_65_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_65_OCP_ROD_CMP | MGT_FO_CH_65_OCP_ROD_DIR | MGT_FO_CH_65_OCP_HUB_CMP | MGT_FO_CH_65_OCP_HUB_DIR | | U466 | MGT_FO_CH_66_IN_DIR | MGT_FO_CMR_CH_66 | MGT_FO_CMR_CH_66 | MGT_FO_CH_66_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_66_OCP_Hub_CMP | MGT_FO_CH_66_OCP_Hub_DIR | MGT_FO_CH_66_OCP_ROD_CMP | MGT_FO_CH_66_OCP_ROD_DIR | | U467 | MGT_FO_CH_67_IN_DIR | MGT_FO_CMR_CH_67 | MGT_FO_CMR_CH_67 | MGT_FO_CH_67_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_67_OCP_ROD_CMP | MGT_FO_CH_67_OCP_ROD_DIR | MGT_FO_CH_67_OCP_HUB_CMP | MGT_FO_CH_67_OCP_HUB_DIR | | U468 | MGT_FO_CH_68_IN_DIR | MGT_FO_CMR_CH_68 | MGT_FO_CMR_CH_68 | MGT_FO_CH_68_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | MGT_FO_CH_68_OCP_Hub_CMP | MGT_FO_CH_68_OCP_Hub_DIR | MGT_FO_CH_68_OCP_ROD_CMP | MGT_FO_CH_68_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| | U469 | MGT_FO_CH_69_IN_DIR | MGT_FO_CMR_CH_69 | MGT_FO_CMR_CH_69 | MGT_FO_CH_69_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_69_OCP_ROD_CMP | MGT_FO_CH_69_OCP_ROD_DIR | MGT_FO_CH_69_OCP_HUB_CMP | MGT_FO_CH_69_OCP_HUB_DIR | | U470 | MGT_FO_CH_70_IN_DIR | MGT_FO_CMR_CH_70 | MGT_FO_CMR_CH_70 | MGT_FO_CH_70_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_70_OCP_Hub_CMP | MGT_FO_CH_70_OCP_Hub_DIR | MGT_FO_CH_70_OCP_ROD_CMP | MGT_FO_CH_70_OCP_ROD_DIR | | U471 | MGT_FO_CH_71_IN_DIR | MGT_FO_CMR_CH_71 | MGT_FO_CMR_CH_71 | MGT_FO_CH_71_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_71_OCP_ROD_CMP | MGT_FO_CH_71_OCP_ROD_DIR | MGT_FO_CH_71_OCP_HUB_CMP | MGT_FO_CH_71_OCP_HUB_DIR | | U472 | MGT_FO_CH_72_IN_DIR | MGT_FO_CMR_CH_72 | MGT_FO_CMR_CH_72 | MGT_FO_CH_72_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_72_OCP_Hub_CMP | MGT_FO_CH_72_OCP_Hub_DIR | MGT_FO_CH_72_OCP_ROD_CMP | MGT_FO_CH_72_OCP_ROD_DIR | | U473 | MGT_FO_CH_73_IN_DIR | MGT_FO_CMR_CH_73 | MGT_FO_CMR_CH_73 | MGT_FO_CH_73_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_73_OCP_ROD_CMP | MGT_FO_CH_73_OCP_ROD_DIR | MGT_FO_CH_73_OCP_HUB_CMP | MGT_FO_CH_73_OCP_HUB_DIR | | U474 | MGT_FO_CH_74_IN_DIR | MGT_FO_CMR_CH_74 | MGT_FO_CMR_CH_74 | MGT_FO_CH_74_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | MGT_FO_CH_74_OCP_Hub_CMP | MGT_FO_CH_74_OCP_Hub_DIR | MGT_FO_CH_74_OCP_ROD_CMP | MGT_FO_CH_74_OCP_ROD_DIR | |------+---------------------+------------------+------------------+---------------------+-----------------------+--------------------------+--------------------------+--------------------------+--------------------------| |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | Ref | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U401 | MGT_FO_CH_1_IN_DIR | MGT_FO_CMR_CH_1 | MGT_FO_CMR_CH_1 | MGT_FO_CH_1_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_1_Pin_6 | No_Conn_FO_CH_1_Pin_7 | FAN_1V8 | MGT_FO_CH_1_OCP_ROD_CMP | MGT_FO_CH_1_OCP_ROD_DIR | MGT_FO_CH_1_OCP_HUB_CMP | MGT_FO_CH_1_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_1_Pin_14 | No_Conn_FO_CH_1_Pin_15 | | U402 | MGT_FO_CH_2_IN_DIR | MGT_FO_CMR_CH_2 | MGT_FO_CMR_CH_2 | MGT_FO_CH_2_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_2_Pin_6 | No_Conn_FO_CH_2_Pin_7 | FAN_1V8 | MGT_FO_CH_2_OCP_Hub_CMP | MGT_FO_CH_2_OCP_Hub_DIR | MGT_FO_CH_2_OCP_ROD_CMP | MGT_FO_CH_2_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_2_Pin_14 | No_Conn_FO_CH_2_Pin_15 | | U403 | MGT_FO_CH_3_IN_DIR | MGT_FO_CMR_CH_3 | MGT_FO_CMR_CH_3 | MGT_FO_CH_3_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_3_Pin_6 | No_Conn_FO_CH_3_Pin_7 | FAN_1V8 | MGT_FO_CH_3_OCP_ROD_CMP | MGT_FO_CH_3_OCP_ROD_DIR | MGT_FO_CH_3_OCP_HUB_CMP | MGT_FO_CH_3_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_3_Pin_14 | No_Conn_FO_CH_3_Pin_15 | | U404 | MGT_FO_CH_4_IN_DIR | MGT_FO_CMR_CH_4 | MGT_FO_CMR_CH_4 | MGT_FO_CH_4_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_4_Pin_6 | No_Conn_FO_CH_4_Pin_7 | FAN_1V8 | MGT_FO_CH_4_OCP_Hub_CMP | MGT_FO_CH_4_OCP_Hub_DIR | MGT_FO_CH_4_OCP_ROD_CMP | MGT_FO_CH_4_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_4_Pin_14 | No_Conn_FO_CH_4_Pin_15 | | U405 | MGT_FO_CH_5_IN_DIR | MGT_FO_CMR_CH_5 | MGT_FO_CMR_CH_5 | MGT_FO_CH_5_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_5_Pin_6 | No_Conn_FO_CH_5_Pin_7 | FAN_1V8 | MGT_FO_CH_5_OCP_ROD_CMP | MGT_FO_CH_5_OCP_ROD_DIR | MGT_FO_CH_5_OCP_HUB_CMP | MGT_FO_CH_5_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_5_Pin_14 | No_Conn_FO_CH_5_Pin_15 | | U406 | MGT_FO_CH_6_IN_DIR | MGT_FO_CMR_CH_6 | MGT_FO_CMR_CH_6 | MGT_FO_CH_6_IN_CMP | MGT_FO_EQU_ENB_GRP_1 | No_Conn_FO_CH_6_Pin_6 | No_Conn_FO_CH_6_Pin_7 | FAN_1V8 | MGT_FO_CH_6_OCP_Hub_CMP | MGT_FO_CH_6_OCP_Hub_DIR | MGT_FO_CH_6_OCP_ROD_CMP | MGT_FO_CH_6_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_6_Pin_14 | No_Conn_FO_CH_6_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U407 | MGT_FO_CH_7_IN_DIR | MGT_FO_CMR_CH_7 | MGT_FO_CMR_CH_7 | MGT_FO_CH_7_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_7_Pin_6 | No_Conn_FO_CH_7_Pin_7 | FAN_1V8 | MGT_FO_CH_7_OCP_ROD_CMP | MGT_FO_CH_7_OCP_ROD_DIR | MGT_FO_CH_7_OCP_HUB_CMP | MGT_FO_CH_7_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_7_Pin_14 | No_Conn_FO_CH_7_Pin_15 | | U408 | MGT_FO_CH_8_IN_DIR | MGT_FO_CMR_CH_8 | MGT_FO_CMR_CH_8 | MGT_FO_CH_8_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_8_Pin_6 | No_Conn_FO_CH_8_Pin_7 | FAN_1V8 | MGT_FO_CH_8_OCP_Hub_CMP | MGT_FO_CH_8_OCP_Hub_DIR | MGT_FO_CH_8_OCP_ROD_CMP | MGT_FO_CH_8_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_8_Pin_14 | No_Conn_FO_CH_8_Pin_15 | | U409 | MGT_FO_CH_9_IN_DIR | MGT_FO_CMR_CH_9 | MGT_FO_CMR_CH_9 | MGT_FO_CH_9_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_9_Pin_6 | No_Conn_FO_CH_9_Pin_7 | FAN_1V8 | MGT_FO_CH_9_OCP_ROD_CMP | MGT_FO_CH_9_OCP_ROD_DIR | MGT_FO_CH_9_OCP_HUB_CMP | MGT_FO_CH_9_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_9_Pin_14 | No_Conn_FO_CH_9_Pin_15 | | U410 | MGT_FO_CH_10_IN_DIR | MGT_FO_CMR_CH_10 | MGT_FO_CMR_CH_10 | MGT_FO_CH_10_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_10_Pin_6 | No_Conn_FO_CH_10_Pin_7 | FAN_1V8 | MGT_FO_CH_10_OCP_Hub_CMP | MGT_FO_CH_10_OCP_Hub_DIR | MGT_FO_CH_10_OCP_ROD_CMP | MGT_FO_CH_10_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_10_Pin_14 | No_Conn_FO_CH_10_Pin_15 | | U411 | MGT_FO_CH_11_IN_DIR | MGT_FO_CMR_CH_11 | MGT_FO_CMR_CH_11 | MGT_FO_CH_11_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_11_Pin_6 | No_Conn_FO_CH_11_Pin_7 | FAN_1V8 | MGT_FO_CH_11_OCP_ROD_CMP | MGT_FO_CH_11_OCP_ROD_DIR | MGT_FO_CH_11_OCP_HUB_CMP | MGT_FO_CH_11_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_11_Pin_14 | No_Conn_FO_CH_11_Pin_15 | | U412 | MGT_FO_CH_12_IN_DIR | MGT_FO_CMR_CH_12 | MGT_FO_CMR_CH_12 | MGT_FO_CH_12_IN_CMP | MGT_FO_EQU_ENB_GRP_2 | No_Conn_FO_CH_12_Pin_6 | No_Conn_FO_CH_12_Pin_7 | FAN_1V8 | MGT_FO_CH_12_OCP_Hub_CMP | MGT_FO_CH_12_OCP_Hub_DIR | MGT_FO_CH_12_OCP_ROD_CMP | MGT_FO_CH_12_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_12_Pin_14 | No_Conn_FO_CH_12_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U413 | MGT_FO_CH_13_IN_DIR | MGT_FO_CMR_CH_13 | MGT_FO_CMR_CH_13 | MGT_FO_CH_13_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_13_Pin_6 | No_Conn_FO_CH_13_Pin_7 | FAN_1V8 | MGT_FO_CH_13_OCP_ROD_CMP | MGT_FO_CH_13_OCP_ROD_DIR | MGT_FO_CH_13_OCP_HUB_CMP | MGT_FO_CH_13_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_13_Pin_14 | No_Conn_FO_CH_13_Pin_15 | | U414 | MGT_FO_CH_14_IN_DIR | MGT_FO_CMR_CH_14 | MGT_FO_CMR_CH_14 | MGT_FO_CH_14_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_14_Pin_6 | No_Conn_FO_CH_14_Pin_7 | FAN_1V8 | MGT_FO_CH_14_OCP_Hub_CMP | MGT_FO_CH_14_OCP_Hub_DIR | MGT_FO_CH_14_OCP_ROD_CMP | MGT_FO_CH_14_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_14_Pin_14 | No_Conn_FO_CH_14_Pin_15 | | U415 | MGT_FO_CH_15_IN_DIR | MGT_FO_CMR_CH_15 | MGT_FO_CMR_CH_15 | MGT_FO_CH_15_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_15_Pin_6 | No_Conn_FO_CH_15_Pin_7 | FAN_1V8 | MGT_FO_CH_15_OCP_ROD_CMP | MGT_FO_CH_15_OCP_ROD_DIR | MGT_FO_CH_15_OCP_HUB_CMP | MGT_FO_CH_15_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_15_Pin_14 | No_Conn_FO_CH_15_Pin_15 | | U416 | MGT_FO_CH_16_IN_DIR | MGT_FO_CMR_CH_16 | MGT_FO_CMR_CH_16 | MGT_FO_CH_16_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_16_Pin_6 | No_Conn_FO_CH_16_Pin_7 | FAN_1V8 | MGT_FO_CH_16_OCP_Hub_CMP | MGT_FO_CH_16_OCP_Hub_DIR | MGT_FO_CH_16_OCP_ROD_CMP | MGT_FO_CH_16_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_16_Pin_14 | No_Conn_FO_CH_16_Pin_15 | | U417 | MGT_FO_CH_17_IN_DIR | MGT_FO_CMR_CH_17 | MGT_FO_CMR_CH_17 | MGT_FO_CH_17_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_17_Pin_6 | No_Conn_FO_CH_17_Pin_7 | FAN_1V8 | MGT_FO_CH_17_OCP_ROD_CMP | MGT_FO_CH_17_OCP_ROD_DIR | MGT_FO_CH_17_OCP_HUB_CMP | MGT_FO_CH_17_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_17_Pin_14 | No_Conn_FO_CH_17_Pin_15 | | U418 | MGT_FO_CH_18_IN_DIR | MGT_FO_CMR_CH_18 | MGT_FO_CMR_CH_18 | MGT_FO_CH_18_IN_CMP | MGT_FO_EQU_ENB_GRP_3 | No_Conn_FO_CH_18_Pin_6 | No_Conn_FO_CH_18_Pin_7 | FAN_1V8 | MGT_FO_CH_18_OCP_Hub_CMP | MGT_FO_CH_18_OCP_Hub_DIR | MGT_FO_CH_18_OCP_ROD_CMP | MGT_FO_CH_18_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_18_Pin_14 | No_Conn_FO_CH_18_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U419 | MGT_FO_CH_19_IN_DIR | MGT_FO_CMR_CH_19 | MGT_FO_CMR_CH_19 | MGT_FO_CH_19_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_19_Pin_6 | No_Conn_FO_CH_19_Pin_7 | FAN_1V8 | MGT_FO_CH_19_OCP_ROD_CMP | MGT_FO_CH_19_OCP_ROD_DIR | MGT_FO_CH_19_OCP_HUB_CMP | MGT_FO_CH_19_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_19_Pin_14 | No_Conn_FO_CH_19_Pin_15 | | U420 | MGT_FO_CH_20_IN_DIR | MGT_FO_CMR_CH_20 | MGT_FO_CMR_CH_20 | MGT_FO_CH_20_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_20_Pin_6 | No_Conn_FO_CH_20_Pin_7 | FAN_1V8 | MGT_FO_CH_20_OCP_Hub_CMP | MGT_FO_CH_20_OCP_Hub_DIR | MGT_FO_CH_20_OCP_ROD_CMP | MGT_FO_CH_20_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_20_Pin_14 | No_Conn_FO_CH_20_Pin_15 | | U421 | MGT_FO_CH_21_IN_DIR | MGT_FO_CMR_CH_21 | MGT_FO_CMR_CH_21 | MGT_FO_CH_21_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_21_Pin_6 | No_Conn_FO_CH_21_Pin_7 | FAN_1V8 | MGT_FO_CH_21_OCP_ROD_CMP | MGT_FO_CH_21_OCP_ROD_DIR | MGT_FO_CH_21_OCP_HUB_CMP | MGT_FO_CH_21_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_21_Pin_14 | No_Conn_FO_CH_21_Pin_15 | | U422 | MGT_FO_CH_22_IN_DIR | MGT_FO_CMR_CH_22 | MGT_FO_CMR_CH_22 | MGT_FO_CH_22_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_22_Pin_6 | No_Conn_FO_CH_22_Pin_7 | FAN_1V8 | MGT_FO_CH_22_OCP_Hub_CMP | MGT_FO_CH_22_OCP_Hub_DIR | MGT_FO_CH_22_OCP_ROD_CMP | MGT_FO_CH_22_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_22_Pin_14 | No_Conn_FO_CH_22_Pin_15 | | U423 | MGT_FO_CH_23_IN_DIR | MGT_FO_CMR_CH_23 | MGT_FO_CMR_CH_23 | MGT_FO_CH_23_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_23_Pin_6 | No_Conn_FO_CH_23_Pin_7 | FAN_1V8 | MGT_FO_CH_23_OCP_ROD_CMP | MGT_FO_CH_23_OCP_ROD_DIR | MGT_FO_CH_23_OCP_HUB_CMP | MGT_FO_CH_23_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_23_Pin_14 | No_Conn_FO_CH_23_Pin_15 | | U424 | MGT_FO_CH_24_IN_DIR | MGT_FO_CMR_CH_24 | MGT_FO_CMR_CH_24 | MGT_FO_CH_24_IN_CMP | MGT_FO_EQU_ENB_GRP_4 | No_Conn_FO_CH_24_Pin_6 | No_Conn_FO_CH_24_Pin_7 | FAN_1V8 | MGT_FO_CH_24_OCP_Hub_CMP | MGT_FO_CH_24_OCP_Hub_DIR | MGT_FO_CH_24_OCP_ROD_CMP | MGT_FO_CH_24_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_24_Pin_14 | No_Conn_FO_CH_24_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U425 | MGT_FO_CH_25_IN_DIR | MGT_FO_CMR_CH_25 | MGT_FO_CMR_CH_25 | MGT_FO_CH_25_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_25_Pin_6 | No_Conn_FO_CH_25_Pin_7 | FAN_1V8 | MGT_FO_CH_25_OCP_ROD_CMP | MGT_FO_CH_25_OCP_ROD_DIR | MGT_FO_CH_25_OCP_HUB_CMP | MGT_FO_CH_25_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_25_Pin_14 | No_Conn_FO_CH_25_Pin_15 | | U426 | MGT_FO_CH_26_IN_DIR | MGT_FO_CMR_CH_26 | MGT_FO_CMR_CH_26 | MGT_FO_CH_26_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_26_Pin_6 | No_Conn_FO_CH_26_Pin_7 | FAN_1V8 | MGT_FO_CH_26_OCP_Hub_CMP | MGT_FO_CH_26_OCP_Hub_DIR | MGT_FO_CH_26_OCP_ROD_CMP | MGT_FO_CH_26_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_26_Pin_14 | No_Conn_FO_CH_26_Pin_15 | | U427 | MGT_FO_CH_27_IN_DIR | MGT_FO_CMR_CH_27 | MGT_FO_CMR_CH_27 | MGT_FO_CH_27_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_27_Pin_6 | No_Conn_FO_CH_27_Pin_7 | FAN_1V8 | MGT_FO_CH_27_OCP_ROD_CMP | MGT_FO_CH_27_OCP_ROD_DIR | MGT_FO_CH_27_OCP_HUB_CMP | MGT_FO_CH_27_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_27_Pin_14 | No_Conn_FO_CH_27_Pin_15 | | U428 | MGT_FO_CH_28_IN_DIR | MGT_FO_CMR_CH_28 | MGT_FO_CMR_CH_28 | MGT_FO_CH_28_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_28_Pin_6 | No_Conn_FO_CH_28_Pin_7 | FAN_1V8 | MGT_FO_CH_28_OCP_Hub_CMP | MGT_FO_CH_28_OCP_Hub_DIR | MGT_FO_CH_28_OCP_ROD_CMP | MGT_FO_CH_28_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_28_Pin_14 | No_Conn_FO_CH_28_Pin_15 | | U429 | MGT_FO_CH_29_IN_DIR | MGT_FO_CMR_CH_29 | MGT_FO_CMR_CH_29 | MGT_FO_CH_29_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_29_Pin_6 | No_Conn_FO_CH_29_Pin_7 | FAN_1V8 | MGT_FO_CH_29_OCP_ROD_CMP | MGT_FO_CH_29_OCP_ROD_DIR | MGT_FO_CH_29_OCP_HUB_CMP | MGT_FO_CH_29_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_29_Pin_14 | No_Conn_FO_CH_29_Pin_15 | | U430 | MGT_FO_CH_30_IN_DIR | MGT_FO_CMR_CH_30 | MGT_FO_CMR_CH_30 | MGT_FO_CH_30_IN_CMP | MGT_FO_EQU_ENB_GRP_5 | No_Conn_FO_CH_30_Pin_6 | No_Conn_FO_CH_30_Pin_7 | FAN_1V8 | MGT_FO_CH_30_OCP_Hub_CMP | MGT_FO_CH_30_OCP_Hub_DIR | MGT_FO_CH_30_OCP_ROD_CMP | MGT_FO_CH_30_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_30_Pin_14 | No_Conn_FO_CH_30_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U431 | MGT_FO_CH_31_IN_DIR | MGT_FO_CMR_CH_31 | MGT_FO_CMR_CH_31 | MGT_FO_CH_31_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_31_Pin_6 | No_Conn_FO_CH_31_Pin_7 | FAN_1V8 | MGT_FO_CH_31_OCP_ROD_CMP | MGT_FO_CH_31_OCP_ROD_DIR | MGT_FO_CH_31_OCP_HUB_CMP | MGT_FO_CH_31_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_31_Pin_14 | No_Conn_FO_CH_31_Pin_15 | | U432 | MGT_FO_CH_32_IN_DIR | MGT_FO_CMR_CH_32 | MGT_FO_CMR_CH_32 | MGT_FO_CH_32_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_32_Pin_6 | No_Conn_FO_CH_32_Pin_7 | FAN_1V8 | MGT_FO_CH_32_OCP_Hub_CMP | MGT_FO_CH_32_OCP_Hub_DIR | MGT_FO_CH_32_OCP_ROD_CMP | MGT_FO_CH_32_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_32_Pin_14 | No_Conn_FO_CH_32_Pin_15 | | U433 | MGT_FO_CH_33_IN_DIR | MGT_FO_CMR_CH_33 | MGT_FO_CMR_CH_33 | MGT_FO_CH_33_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_33_Pin_6 | No_Conn_FO_CH_33_Pin_7 | FAN_1V8 | MGT_FO_CH_33_OCP_ROD_CMP | MGT_FO_CH_33_OCP_ROD_DIR | MGT_FO_CH_33_OCP_HUB_CMP | MGT_FO_CH_33_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_33_Pin_14 | No_Conn_FO_CH_33_Pin_15 | | U434 | MGT_FO_CH_34_IN_DIR | MGT_FO_CMR_CH_34 | MGT_FO_CMR_CH_34 | MGT_FO_CH_34_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_34_Pin_6 | No_Conn_FO_CH_34_Pin_7 | FAN_1V8 | MGT_FO_CH_34_OCP_Hub_CMP | MGT_FO_CH_34_OCP_Hub_DIR | MGT_FO_CH_34_OCP_ROD_CMP | MGT_FO_CH_34_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_34_Pin_14 | No_Conn_FO_CH_34_Pin_15 | | U435 | MGT_FO_CH_35_IN_DIR | MGT_FO_CMR_CH_35 | MGT_FO_CMR_CH_35 | MGT_FO_CH_35_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_35_Pin_6 | No_Conn_FO_CH_35_Pin_7 | FAN_1V8 | MGT_FO_CH_35_OCP_ROD_CMP | MGT_FO_CH_35_OCP_ROD_DIR | MGT_FO_CH_35_OCP_HUB_CMP | MGT_FO_CH_35_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_35_Pin_14 | No_Conn_FO_CH_35_Pin_15 | | U436 | MGT_FO_CH_36_IN_DIR | MGT_FO_CMR_CH_36 | MGT_FO_CMR_CH_36 | MGT_FO_CH_36_IN_CMP | MGT_FO_EQU_ENB_GRP_6 | No_Conn_FO_CH_36_Pin_6 | No_Conn_FO_CH_36_Pin_7 | FAN_1V8 | MGT_FO_CH_36_OCP_Hub_CMP | MGT_FO_CH_36_OCP_Hub_DIR | MGT_FO_CH_36_OCP_ROD_CMP | MGT_FO_CH_36_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_36_Pin_14 | No_Conn_FO_CH_36_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U437 | MGT_FO_CH_37_IN_DIR | MGT_FO_CMR_CH_37 | MGT_FO_CMR_CH_37 | MGT_FO_CH_37_IN_CMP | MGT_FO_EQU_ENB_GRP_7 | No_Conn_FO_CH_37_Pin_6 | No_Conn_FO_CH_37_Pin_7 | FAN_1V8 | MGT_FO_CH_37_OCP_ROD_CMP | MGT_FO_CH_37_OCP_ROD_DIR | MGT_FO_CH_37_OCP_HUB_CMP | MGT_FO_CH_37_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_37_Pin_14 | No_Conn_FO_CH_37_Pin_15 | | U438 | MGT_FO_CH_38_IN_DIR | MGT_FO_CMR_CH_38 | MGT_FO_CMR_CH_38 | MGT_FO_CH_38_IN_CMP | MGT_FO_EQU_ENB_GRP_7 | No_Conn_FO_CH_38_Pin_6 | No_Conn_FO_CH_38_Pin_7 | FAN_1V8 | MGT_FO_CH_38_OCP_Hub_CMP | MGT_FO_CH_38_OCP_Hub_DIR | MGT_FO_CH_38_OCP_ROD_CMP | MGT_FO_CH_38_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_38_Pin_14 | No_Conn_FO_CH_38_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U439 | MGT_FO_CH_39_IN_DIR | MGT_FO_CMR_CH_39 | MGT_FO_CMR_CH_39 | MGT_FO_CH_39_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_39_Pin_6 | No_Conn_FO_CH_39_Pin_7 | FAN_1V8 | MGT_FO_CH_39_OCP_ROD_CMP | MGT_FO_CH_39_OCP_ROD_DIR | MGT_FO_CH_39_OCP_HUB_CMP | MGT_FO_CH_39_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_39_Pin_14 | No_Conn_FO_CH_39_Pin_15 | | U440 | MGT_FO_CH_40_IN_DIR | MGT_FO_CMR_CH_40 | MGT_FO_CMR_CH_40 | MGT_FO_CH_40_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_40_Pin_6 | No_Conn_FO_CH_40_Pin_7 | FAN_1V8 | MGT_FO_CH_40_OCP_Hub_CMP | MGT_FO_CH_40_OCP_Hub_DIR | MGT_FO_CH_40_OCP_ROD_CMP | MGT_FO_CH_40_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_40_Pin_14 | No_Conn_FO_CH_40_Pin_15 | | U441 | MGT_FO_CH_41_IN_DIR | MGT_FO_CMR_CH_41 | MGT_FO_CMR_CH_41 | MGT_FO_CH_41_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_41_Pin_6 | No_Conn_FO_CH_41_Pin_7 | FAN_1V8 | MGT_FO_CH_41_OCP_ROD_CMP | MGT_FO_CH_41_OCP_ROD_DIR | MGT_FO_CH_41_OCP_HUB_CMP | MGT_FO_CH_41_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_41_Pin_14 | No_Conn_FO_CH_41_Pin_15 | | U442 | MGT_FO_CH_42_IN_DIR | MGT_FO_CMR_CH_42 | MGT_FO_CMR_CH_42 | MGT_FO_CH_42_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_42_Pin_6 | No_Conn_FO_CH_42_Pin_7 | FAN_1V8 | MGT_FO_CH_42_OCP_Hub_CMP | MGT_FO_CH_42_OCP_Hub_DIR | MGT_FO_CH_42_OCP_ROD_CMP | MGT_FO_CH_42_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_42_Pin_14 | No_Conn_FO_CH_42_Pin_15 | | U443 | MGT_FO_CH_43_IN_DIR | MGT_FO_CMR_CH_43 | MGT_FO_CMR_CH_43 | MGT_FO_CH_43_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_43_Pin_6 | No_Conn_FO_CH_43_Pin_7 | FAN_1V8 | MGT_FO_CH_43_OCP_ROD_CMP | MGT_FO_CH_43_OCP_ROD_DIR | MGT_FO_CH_43_OCP_HUB_CMP | MGT_FO_CH_43_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_43_Pin_14 | No_Conn_FO_CH_43_Pin_15 | | U444 | MGT_FO_CH_44_IN_DIR | MGT_FO_CMR_CH_44 | MGT_FO_CMR_CH_44 | MGT_FO_CH_44_IN_CMP | MGT_FO_EQU_ENB_GRP_8 | No_Conn_FO_CH_44_Pin_6 | No_Conn_FO_CH_44_Pin_7 | FAN_1V8 | MGT_FO_CH_44_OCP_Hub_CMP | MGT_FO_CH_44_OCP_Hub_DIR | MGT_FO_CH_44_OCP_ROD_CMP | MGT_FO_CH_44_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_44_Pin_14 | No_Conn_FO_CH_44_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U445 | MGT_FO_CH_45_IN_DIR | MGT_FO_CMR_CH_45 | MGT_FO_CMR_CH_45 | MGT_FO_CH_45_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_45_Pin_6 | No_Conn_FO_CH_45_Pin_7 | FAN_1V8 | MGT_FO_CH_45_OCP_ROD_CMP | MGT_FO_CH_45_OCP_ROD_DIR | MGT_FO_CH_45_OCP_HUB_CMP | MGT_FO_CH_45_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_45_Pin_14 | No_Conn_FO_CH_45_Pin_15 | | U446 | MGT_FO_CH_46_IN_DIR | MGT_FO_CMR_CH_46 | MGT_FO_CMR_CH_46 | MGT_FO_CH_46_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_46_Pin_6 | No_Conn_FO_CH_46_Pin_7 | FAN_1V8 | MGT_FO_CH_46_OCP_Hub_CMP | MGT_FO_CH_46_OCP_Hub_DIR | MGT_FO_CH_46_OCP_ROD_CMP | MGT_FO_CH_46_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_46_Pin_14 | No_Conn_FO_CH_46_Pin_15 | | U447 | MGT_FO_CH_47_IN_DIR | MGT_FO_CMR_CH_47 | MGT_FO_CMR_CH_47 | MGT_FO_CH_47_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_47_Pin_6 | No_Conn_FO_CH_47_Pin_7 | FAN_1V8 | MGT_FO_CH_47_OCP_ROD_CMP | MGT_FO_CH_47_OCP_ROD_DIR | MGT_FO_CH_47_OCP_HUB_CMP | MGT_FO_CH_47_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_47_Pin_14 | No_Conn_FO_CH_47_Pin_15 | | U448 | MGT_FO_CH_48_IN_DIR | MGT_FO_CMR_CH_48 | MGT_FO_CMR_CH_48 | MGT_FO_CH_48_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_48_Pin_6 | No_Conn_FO_CH_48_Pin_7 | FAN_1V8 | MGT_FO_CH_48_OCP_Hub_CMP | MGT_FO_CH_48_OCP_Hub_DIR | MGT_FO_CH_48_OCP_ROD_CMP | MGT_FO_CH_48_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_48_Pin_14 | No_Conn_FO_CH_48_Pin_15 | | U449 | MGT_FO_CH_49_IN_DIR | MGT_FO_CMR_CH_49 | MGT_FO_CMR_CH_49 | MGT_FO_CH_49_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_49_Pin_6 | No_Conn_FO_CH_49_Pin_7 | FAN_1V8 | MGT_FO_CH_49_OCP_ROD_CMP | MGT_FO_CH_49_OCP_ROD_DIR | MGT_FO_CH_49_OCP_HUB_CMP | MGT_FO_CH_49_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_49_Pin_14 | No_Conn_FO_CH_49_Pin_15 | | U450 | MGT_FO_CH_50_IN_DIR | MGT_FO_CMR_CH_50 | MGT_FO_CMR_CH_50 | MGT_FO_CH_50_IN_CMP | MGT_FO_EQU_ENB_GRP_9 | No_Conn_FO_CH_50_Pin_6 | No_Conn_FO_CH_50_Pin_7 | FAN_1V8 | MGT_FO_CH_50_OCP_Hub_CMP | MGT_FO_CH_50_OCP_Hub_DIR | MGT_FO_CH_50_OCP_ROD_CMP | MGT_FO_CH_50_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_50_Pin_14 | No_Conn_FO_CH_50_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U451 | MGT_FO_CH_51_IN_DIR | MGT_FO_CMR_CH_51 | MGT_FO_CMR_CH_51 | MGT_FO_CH_51_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_51_Pin_6 | No_Conn_FO_CH_51_Pin_7 | FAN_1V8 | MGT_FO_CH_51_OCP_ROD_CMP | MGT_FO_CH_51_OCP_ROD_DIR | MGT_FO_CH_51_OCP_HUB_CMP | MGT_FO_CH_51_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_51_Pin_14 | No_Conn_FO_CH_51_Pin_15 | | U452 | MGT_FO_CH_52_IN_DIR | MGT_FO_CMR_CH_52 | MGT_FO_CMR_CH_52 | MGT_FO_CH_52_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_52_Pin_6 | No_Conn_FO_CH_52_Pin_7 | FAN_1V8 | MGT_FO_CH_52_OCP_Hub_CMP | MGT_FO_CH_52_OCP_Hub_DIR | MGT_FO_CH_52_OCP_ROD_CMP | MGT_FO_CH_52_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_52_Pin_14 | No_Conn_FO_CH_52_Pin_15 | | U453 | MGT_FO_CH_53_IN_DIR | MGT_FO_CMR_CH_53 | MGT_FO_CMR_CH_53 | MGT_FO_CH_53_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_53_Pin_6 | No_Conn_FO_CH_53_Pin_7 | FAN_1V8 | MGT_FO_CH_53_OCP_ROD_CMP | MGT_FO_CH_53_OCP_ROD_DIR | MGT_FO_CH_53_OCP_HUB_CMP | MGT_FO_CH_53_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_53_Pin_14 | No_Conn_FO_CH_53_Pin_15 | | U454 | MGT_FO_CH_54_IN_DIR | MGT_FO_CMR_CH_54 | MGT_FO_CMR_CH_54 | MGT_FO_CH_54_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_54_Pin_6 | No_Conn_FO_CH_54_Pin_7 | FAN_1V8 | MGT_FO_CH_54_OCP_Hub_CMP | MGT_FO_CH_54_OCP_Hub_DIR | MGT_FO_CH_54_OCP_ROD_CMP | MGT_FO_CH_54_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_54_Pin_14 | No_Conn_FO_CH_54_Pin_15 | | U455 | MGT_FO_CH_55_IN_DIR | MGT_FO_CMR_CH_55 | MGT_FO_CMR_CH_55 | MGT_FO_CH_55_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_55_Pin_6 | No_Conn_FO_CH_55_Pin_7 | FAN_1V8 | MGT_FO_CH_55_OCP_ROD_CMP | MGT_FO_CH_55_OCP_ROD_DIR | MGT_FO_CH_55_OCP_HUB_CMP | MGT_FO_CH_55_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_55_Pin_14 | No_Conn_FO_CH_55_Pin_15 | | U456 | MGT_FO_CH_56_IN_DIR | MGT_FO_CMR_CH_56 | MGT_FO_CMR_CH_56 | MGT_FO_CH_56_IN_CMP | MGT_FO_EQU_ENB_GRP_10 | No_Conn_FO_CH_56_Pin_6 | No_Conn_FO_CH_56_Pin_7 | FAN_1V8 | MGT_FO_CH_56_OCP_Hub_CMP | MGT_FO_CH_56_OCP_Hub_DIR | MGT_FO_CH_56_OCP_ROD_CMP | MGT_FO_CH_56_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_56_Pin_14 | No_Conn_FO_CH_56_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U457 | MGT_FO_CH_57_IN_DIR | MGT_FO_CMR_CH_57 | MGT_FO_CMR_CH_57 | MGT_FO_CH_57_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_57_Pin_6 | No_Conn_FO_CH_57_Pin_7 | FAN_1V8 | MGT_FO_CH_57_OCP_ROD_CMP | MGT_FO_CH_57_OCP_ROD_DIR | MGT_FO_CH_57_OCP_HUB_CMP | MGT_FO_CH_57_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_57_Pin_14 | No_Conn_FO_CH_57_Pin_15 | | U458 | MGT_FO_CH_58_IN_DIR | MGT_FO_CMR_CH_58 | MGT_FO_CMR_CH_58 | MGT_FO_CH_58_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_58_Pin_6 | No_Conn_FO_CH_58_Pin_7 | FAN_1V8 | MGT_FO_CH_58_OCP_Hub_CMP | MGT_FO_CH_58_OCP_Hub_DIR | MGT_FO_CH_58_OCP_ROD_CMP | MGT_FO_CH_58_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_58_Pin_14 | No_Conn_FO_CH_58_Pin_15 | | U459 | MGT_FO_CH_59_IN_DIR | MGT_FO_CMR_CH_59 | MGT_FO_CMR_CH_59 | MGT_FO_CH_59_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_59_Pin_6 | No_Conn_FO_CH_59_Pin_7 | FAN_1V8 | MGT_FO_CH_59_OCP_ROD_CMP | MGT_FO_CH_59_OCP_ROD_DIR | MGT_FO_CH_59_OCP_HUB_CMP | MGT_FO_CH_59_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_59_Pin_14 | No_Conn_FO_CH_59_Pin_15 | | U460 | MGT_FO_CH_60_IN_DIR | MGT_FO_CMR_CH_60 | MGT_FO_CMR_CH_60 | MGT_FO_CH_60_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_60_Pin_6 | No_Conn_FO_CH_60_Pin_7 | FAN_1V8 | MGT_FO_CH_60_OCP_Hub_CMP | MGT_FO_CH_60_OCP_Hub_DIR | MGT_FO_CH_60_OCP_ROD_CMP | MGT_FO_CH_60_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_60_Pin_14 | No_Conn_FO_CH_60_Pin_15 | | U461 | MGT_FO_CH_61_IN_DIR | MGT_FO_CMR_CH_61 | MGT_FO_CMR_CH_61 | MGT_FO_CH_61_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_61_Pin_6 | No_Conn_FO_CH_61_Pin_7 | FAN_1V8 | MGT_FO_CH_61_OCP_ROD_CMP | MGT_FO_CH_61_OCP_ROD_DIR | MGT_FO_CH_61_OCP_HUB_CMP | MGT_FO_CH_61_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_61_Pin_14 | No_Conn_FO_CH_61_Pin_15 | | U462 | MGT_FO_CH_62_IN_DIR | MGT_FO_CMR_CH_62 | MGT_FO_CMR_CH_62 | MGT_FO_CH_62_IN_CMP | MGT_FO_EQU_ENB_GRP_11 | No_Conn_FO_CH_62_Pin_6 | No_Conn_FO_CH_62_Pin_7 | FAN_1V8 | MGT_FO_CH_62_OCP_Hub_CMP | MGT_FO_CH_62_OCP_Hub_DIR | MGT_FO_CH_62_OCP_ROD_CMP | MGT_FO_CH_62_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_62_Pin_14 | No_Conn_FO_CH_62_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U463 | MGT_FO_CH_63_IN_DIR | MGT_FO_CMR_CH_63 | MGT_FO_CMR_CH_63 | MGT_FO_CH_63_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_63_Pin_6 | No_Conn_FO_CH_63_Pin_7 | FAN_1V8 | MGT_FO_CH_63_OCP_ROD_CMP | MGT_FO_CH_63_OCP_ROD_DIR | MGT_FO_CH_63_OCP_HUB_CMP | MGT_FO_CH_63_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_63_Pin_14 | No_Conn_FO_CH_63_Pin_15 | | U464 | MGT_FO_CH_64_IN_DIR | MGT_FO_CMR_CH_64 | MGT_FO_CMR_CH_64 | MGT_FO_CH_64_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_64_Pin_6 | No_Conn_FO_CH_64_Pin_7 | FAN_1V8 | MGT_FO_CH_64_OCP_Hub_CMP | MGT_FO_CH_64_OCP_Hub_DIR | MGT_FO_CH_64_OCP_ROD_CMP | MGT_FO_CH_64_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_64_Pin_14 | No_Conn_FO_CH_64_Pin_15 | | U465 | MGT_FO_CH_65_IN_DIR | MGT_FO_CMR_CH_65 | MGT_FO_CMR_CH_65 | MGT_FO_CH_65_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_65_Pin_6 | No_Conn_FO_CH_65_Pin_7 | FAN_1V8 | MGT_FO_CH_65_OCP_ROD_CMP | MGT_FO_CH_65_OCP_ROD_DIR | MGT_FO_CH_65_OCP_HUB_CMP | MGT_FO_CH_65_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_65_Pin_14 | No_Conn_FO_CH_65_Pin_15 | | U466 | MGT_FO_CH_66_IN_DIR | MGT_FO_CMR_CH_66 | MGT_FO_CMR_CH_66 | MGT_FO_CH_66_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_66_Pin_6 | No_Conn_FO_CH_66_Pin_7 | FAN_1V8 | MGT_FO_CH_66_OCP_Hub_CMP | MGT_FO_CH_66_OCP_Hub_DIR | MGT_FO_CH_66_OCP_ROD_CMP | MGT_FO_CH_66_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_66_Pin_14 | No_Conn_FO_CH_66_Pin_15 | | U467 | MGT_FO_CH_67_IN_DIR | MGT_FO_CMR_CH_67 | MGT_FO_CMR_CH_67 | MGT_FO_CH_67_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_67_Pin_6 | No_Conn_FO_CH_67_Pin_7 | FAN_1V8 | MGT_FO_CH_67_OCP_ROD_CMP | MGT_FO_CH_67_OCP_ROD_DIR | MGT_FO_CH_67_OCP_HUB_CMP | MGT_FO_CH_67_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_67_Pin_14 | No_Conn_FO_CH_67_Pin_15 | | U468 | MGT_FO_CH_68_IN_DIR | MGT_FO_CMR_CH_68 | MGT_FO_CMR_CH_68 | MGT_FO_CH_68_IN_CMP | MGT_FO_EQU_ENB_GRP_12 | No_Conn_FO_CH_68_Pin_6 | No_Conn_FO_CH_68_Pin_7 | FAN_1V8 | MGT_FO_CH_68_OCP_Hub_CMP | MGT_FO_CH_68_OCP_Hub_DIR | MGT_FO_CH_68_OCP_ROD_CMP | MGT_FO_CH_68_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_68_Pin_14 | No_Conn_FO_CH_68_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------| | U469 | MGT_FO_CH_69_IN_DIR | MGT_FO_CMR_CH_69 | MGT_FO_CMR_CH_69 | MGT_FO_CH_69_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_69_Pin_6 | No_Conn_FO_CH_69_Pin_7 | FAN_1V8 | MGT_FO_CH_69_OCP_ROD_CMP | MGT_FO_CH_69_OCP_ROD_DIR | MGT_FO_CH_69_OCP_HUB_CMP | MGT_FO_CH_69_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_69_Pin_14 | No_Conn_FO_CH_69_Pin_15 | | U470 | MGT_FO_CH_70_IN_DIR | MGT_FO_CMR_CH_70 | MGT_FO_CMR_CH_70 | MGT_FO_CH_70_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_70_Pin_6 | No_Conn_FO_CH_70_Pin_7 | FAN_1V8 | MGT_FO_CH_70_OCP_Hub_CMP | MGT_FO_CH_70_OCP_Hub_DIR | MGT_FO_CH_70_OCP_ROD_CMP | MGT_FO_CH_70_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_70_Pin_14 | No_Conn_FO_CH_70_Pin_15 | | U471 | MGT_FO_CH_71_IN_DIR | MGT_FO_CMR_CH_71 | MGT_FO_CMR_CH_71 | MGT_FO_CH_71_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_71_Pin_6 | No_Conn_FO_CH_71_Pin_7 | FAN_1V8 | MGT_FO_CH_71_OCP_ROD_CMP | MGT_FO_CH_71_OCP_ROD_DIR | MGT_FO_CH_71_OCP_HUB_CMP | MGT_FO_CH_71_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_71_Pin_14 | No_Conn_FO_CH_71_Pin_15 | | U472 | MGT_FO_CH_72_IN_DIR | MGT_FO_CMR_CH_72 | MGT_FO_CMR_CH_72 | MGT_FO_CH_72_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_72_Pin_6 | No_Conn_FO_CH_72_Pin_7 | FAN_1V8 | MGT_FO_CH_72_OCP_Hub_CMP | MGT_FO_CH_72_OCP_Hub_DIR | MGT_FO_CH_72_OCP_ROD_CMP | MGT_FO_CH_72_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_72_Pin_14 | No_Conn_FO_CH_72_Pin_15 | | U473 | MGT_FO_CH_73_IN_DIR | MGT_FO_CMR_CH_73 | MGT_FO_CMR_CH_73 | MGT_FO_CH_73_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_73_Pin_6 | No_Conn_FO_CH_73_Pin_7 | FAN_1V8 | MGT_FO_CH_73_OCP_ROD_CMP | MGT_FO_CH_73_OCP_ROD_DIR | MGT_FO_CH_73_OCP_HUB_CMP | MGT_FO_CH_73_OCP_HUB_DIR | FAN_1V8 | No_Conn_FO_CH_73_Pin_14 | No_Conn_FO_CH_73_Pin_15 | | U474 | MGT_FO_CH_74_IN_DIR | MGT_FO_CMR_CH_74 | MGT_FO_CMR_CH_74 | MGT_FO_CH_74_IN_CMP | MGT_FO_EQU_ENB_GRP_13 | No_Conn_FO_CH_74_Pin_6 | No_Conn_FO_CH_74_Pin_7 | FAN_1V8 | MGT_FO_CH_74_OCP_Hub_CMP | MGT_FO_CH_74_OCP_Hub_DIR | MGT_FO_CH_74_OCP_ROD_CMP | MGT_FO_CH_74_OCP_ROD_DIR | FAN_1V8 | No_Conn_FO_CH_74_Pin_14 | No_Conn_FO_CH_74_Pin_15 | |------+---------------------+------------------+------------------+---------------------+-----------------------+------------------------+------------------------+---------+--------------------------+--------------------------+--------------------------+--------------------------+---------+-------------------------+-------------------------|