# # All Other Nets File # # Key In Net List file for the Hub Module # ---------------------------------------------- # # # Original Rev. 17-Apr-2015 # Most Recent Rev. 24-Feb-2016 # # # Currently there is Nothing in the Hub All Other Nets File # # # FPGA_CORE Supply # # DCDC 1 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 1. # # This is the FPGA CORE supply 0.950 V at 40 Amps. # # This Hub Module supply uses a GE_MDT040 converter. # # # Connect the converter's V_Input, V_Output, and Ground terminals: # NET 'ISO_12V' DCDC1-2 NET 'GROUND' DCDC1-4 DCDC1-8 DCDC1-10 NET 'FPGA_CORE' DCDC1-5 # # Connect this converter's INPUT Via Arays: # NET 'ISO_12V' PVA1_DC1-1 PVA1_DC1-2 PVA1_DC1-3 PVA1_DC1-4 NET 'ISO_12V' PVA1_DC1-5 PVA1_DC1-6 PVA1_DC1-7 PVA1_DC1-8 NET 'ISO_12V' PVA1_DC1-9 PVA1_DC1-10 PVA1_DC1-11 PVA1_DC1-12 NET 'ISO_12V' PVA2_DC1-1 PVA2_DC1-2 PVA2_DC1-3 PVA2_DC1-4 NET 'ISO_12V' PVA2_DC1-5 PVA2_DC1-6 PVA2_DC1-7 PVA2_DC1-8 NET 'ISO_12V' PVA2_DC1-9 NET 'ISO_12V' PVA3_DC1-1 PVA3_DC1-2 PVA3_DC1-3 # # Connect this converter's GROUND Via Arays: # NET 'GROUND' PVA4_DC1-1 PVA4_DC1-2 PVA4_DC1-3 PVA4_DC1-4 NET 'GROUND' PVA4_DC1-5 PVA4_DC1-6 PVA4_DC1-7 PVA4_DC1-8 NET 'GROUND' PVA4_DC1-9 PVA4_DC1-10 PVA4_DC1-11 PVA4_DC1-12 NET 'GROUND' PVA5_DC1-1 PVA5_DC1-2 PVA5_DC1-3 NET 'GROUND' PVA6_DC1-1 PVA6_DC1-2 PVA6_DC1-3 PVA6_DC1-4 NET 'GROUND' PVA6_DC1-5 PVA6_DC1-6 PVA6_DC1-7 PVA6_DC1-8 NET 'GROUND' PVA6_DC1-9 PVA6_DC1-10 PVA6_DC1-11 PVA6_DC1-12 NET 'GROUND' PVA7_DC1-1 PVA7_DC1-2 PVA7_DC1-3 PVA7_DC1-4 NET 'GROUND' PVA7_DC1-5 PVA7_DC1-6 PVA7_DC1-7 PVA7_DC1-8 NET 'GROUND' PVA7_DC1-9 PVA7_DC1-10 PVA7_DC1-11 PVA7_DC1-12 NET 'GROUND' PVA8_DC1-1 PVA8_DC1-2 PVA8_DC1-3 PVA8_DC1-4 NET 'GROUND' PVA8_DC1-5 PVA8_DC1-6 NET 'GROUND' PVA9_DC1-1 PVA9_DC1-2 PVA9_DC1-3 PVA9_DC1-4 NET 'GROUND' PVA9_DC1-5 PVA9_DC1-6 # # Connect this converter's OUTPUT Via Arays: # NET 'FPGA_CORE' PVA10_DC1-1 PVA10_DC1-2 PVA10_DC1-3 PVA10_DC1-4 NET 'FPGA_CORE' PVA10_DC1-5 PVA10_DC1-6 PVA10_DC1-7 PVA10_DC1-8 NET 'FPGA_CORE' PVA10_DC1-9 PVA10_DC1-10 PVA10_DC1-11 PVA10_DC1-12 NET 'FPGA_CORE' PVA11_DC1-1 PVA11_DC1-2 PVA11_DC1-3 PVA11_DC1-4 NET 'FPGA_CORE' PVA11_DC1-5 PVA11_DC1-6 PVA11_DC1-7 PVA11_DC1-8 NET 'FPGA_CORE' PVA11_DC1-9 PVA11_DC1-10 PVA11_DC1-11 PVA11_DC1-12 NET 'FPGA_CORE' PVA12_DC1-1 PVA12_DC1-2 PVA12_DC1-3 PVA12_DC1-4 NET 'FPGA_CORE' PVA12_DC1-5 PVA12_DC1-6 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1011-1 NET 'GROUND' C1011-2 NET 'ISO_12V' C1012-1 C1013-1 C1014-1 C1015-1 NET 'GROUND' C1012-2 C1013-2 C1014-2 C1015-2 NET 'ISO_12V' C1016-1 C1017-1 C1018-1 NET 'GROUND' C1016-2 C1017-2 C1018-2 # # Connect this converter's OUTPUT Filter: # NET 'FPGA_CORE' C1021-1 C1022-1 C1023-1 NET 'GROUND' C1021-2 C1022-2 C1023-2 NET 'FPGA_CORE' C1024-1 C1025-1 C1026-1 C1027-1 NET 'GROUND' C1024-2 C1025-2 C1026-2 C1027-2 NET 'FPGA_CORE' C1028-1 C1029-1 NET 'GROUND' C1028-2 C1029-2 NET 'FPGA_CORE' C1030-1 C1031-1 C1032-1 C1033-1 NET 'GROUND' C1030-2 C1031-2 C1032-2 C1033-2 NET 'FPGA_CORE' DZ1001-1 NET 'GROUND' DZ1001-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC1-15 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_1_OFF_ON' DCDC1-1 NET 'DCDC_1_POWER_GOOD' DCDC1-16 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1005 is the 20k Ohm series resistor. # R1006 is the scale shunt resistor to ground. # C1002 is the noise filter capacitor to ground. NET 'CONVERTER_RAMP' R1005-1 NET 'DCDC1_RAMP_SEQUENCE' R1005-2 R1006-2 C1002-2 DCDC1-3 NET 'DCDC1_SIG_GND' R1006-1 C1002-1 # # Declare the unused SHARE terminal: # NET 'NO_CONN_DCDC1_SHARE' DCDC1-9 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC1_TRIM' DCDC1-6 R1002-2 NET 'DCDC1_SIG_GND' DCDC1-11 R1002-1 # # Connect this converter's Remote Sense input # terminals V_SENSE_PLUS and V_SENSE_MINUS: # NET 'FPGA_CORE' DCDC1-7 NET 'GROUND' DCDC1-12 # # Connect this converter's Servo Loop RC components # between the V_SENSE_PLUS and TRIM terminals: # NET 'FPGA_CORE' C1001-2 NET 'DCDC1_LOOP_RC' C1001-1 R1001-1 NET 'DCDC1_TRIM' R1001-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC1-13 NET 'Hub_PMBus_SDA' DCDC1-14 NET 'Hubs_SMB_Alert_B' DCDC1-17 NET 'DCDC1_ADRS_0' DCDC1-18 R1003-1 NET 'DCDC1_ADRS_1' DCDC1-19 R1004-1 NET 'DCDC1_SIG_GND' R1003-2 R1004-2 # # MGT_AVCC Supply # # DCDC 2 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 2. # # This is the MGT_AVCC supply 1.000 V at 20 Amps. # # This Hub Module supply uses a GE_UDT020 converter. # # # Connect the converter's V_Input, Ground, and V_Output terminals: # NET 'ISO_12V' DCDC2-2 NET 'GROUND' DCDC2-4 NET 'MGT_AVCC_pre_L' DCDC2-6 # # Connect this converter's INPUT Via Arays: # NET 'ISO_12V' PVA1_DC2-1 PVA1_DC2-2 PVA1_DC2-3 PVA1_DC2-4 NET 'ISO_12V' PVA1_DC2-5 PVA1_DC2-6 NET 'ISO_12V' PVA2_DC2-1 PVA2_DC2-2 PVA2_DC2-3 PVA2_DC2-4 # # Connect this converter's GROUND and Sync = Ground Via Arays: # NET 'GROUND' PVA3_DC2-1 PVA3_DC2-2 PVA3_DC2-3 PVA3_DC2-4 NET 'GROUND' PVA4_DC2-1 PVA4_DC2-2 PVA4_DC2-3 PVA4_DC2-4 NET 'GROUND' PVA4_DC2-5 PVA4_DC2-6 PVA4_DC2-7 PVA4_DC2-8 NET 'GROUND' PVA4_DC2-9 PVA4_DC2-10 PVA4_DC2-11 PVA4_DC2-12 NET 'GROUND' PVA5_DC2-1 NET 'GROUND' PVA6_DC2-1 NET 'GROUND' PVA7_DC2-1 # # Connect this converter's OUTPUT Via Arays: # NET 'MGT_AVCC_pre_L' PVA8_DC2-1 PVA8_DC2-2 PVA8_DC2-3 PVA8_DC2-4 NET 'MGT_AVCC_pre_L' PVA8_DC2-5 PVA8_DC2-6 PVA8_DC2-7 PVA8_DC2-8 NET 'MGT_AVCC_pre_L' PVA8_DC2-9 PVA8_DC2-10 PVA8_DC2-11 PVA8_DC2-12 NET 'MGT_AVCC_pre_L' PVA9_DC2-1 NET 'MGT_AVCC_pre_L' PVA10_DC2-1 NET 'MGT_AVCC_pre_L' PVA11_DC2-1 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1061-1 C1062-1 C1063-1 C1064-1 NET 'GROUND' C1061-2 C1062-2 C1063-2 C1064-2 NET 'ISO_12V' C1065-1 C1066-1 NET 'GROUND' C1065-2 C1066-2 # # Connect this converter's OUTPUT Filter # and connect the Output Filter Choke: # NET 'MGT_AVCC_pre_L' C1071-1 C1072-1 C1073-1 C1074-1 C1078-1 NET 'GROUND' C1071-2 C1072-2 C1073-2 C1074-2 C1078-2 NET 'MGT_AVCC_pre_L' C1075-1 C1076-1 NET 'GROUND' C1075-2 C1076-2 NET 'MGT_AVCC_pre_L' C1077-1 NET 'GROUND' C1077-2 NET 'MGT_AVCC_pre_L' L1051-1 NET 'MGT_AVCC' L1051-2 NET 'MGT_AVCC' DZ1051-1 NET 'GROUND' DZ1051-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC2-10 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_2_OFF_ON' DCDC2-1 NET 'DCDC_2_POWER_GOOD' DCDC2-9 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1055 is the 20k Ohm series resistor. # R1056 is the scale shunt resistor to ground. NET 'CONVERTER_RAMP' R1055-2 NET 'DCDC2_RAMP_SEQUENCE' R1055-1 R1056-2 C1052-2 DCDC2-3 NET 'DCDC2_SIG_GND' R1056-1 C1052-1 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC2_TRIM' DCDC2-5 R1052-2 NET 'DCDC2_SIG_GND' DCDC2-14 R1052-1 # # Connect this conberter's Feedback Source Point # Select Jumpers to the two possible feedback # source points. # NET 'MGT_AVCC_pre_L' JMP1051-2 JMP1053-1 NET 'MGT_AVCC' JMP1052-2 JMP1054-1 # # Connect this converter's Differential Amp # Remote Sense input terminals V_SENSE_PLUS # and V_SENSE_MINUS: # NET 'DCDC2_DIFF_FDBK' DCDC2-7 JMP1051-1 JMP1052-1 NET 'GROUND' DCDC2-8 # # Connect this converter's Servo Loop RC components # between the Feedback Source Point Select Jumpers # and its TRIM terminal: # NET 'DCDC2_RC_FDBK' C1051-2 JMP1053-2 JMP1054-2 NET 'DCDC2_LOOP_RC' C1051-1 R1051-1 NET 'DCDC2_TRIM' R1051-2 # # Connect this converter's direct capacitor feedback # from before the LC filter to its "Trim" input. # NET 'MGT_AVCC_pre_L' C1053-1 NET 'DCDC2_TRIM' C1053-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC2-11 NET 'Hub_PMBus_SDA' DCDC2-12 NET 'Hubs_SMB_Alert_B' DCDC2-13 NET 'DCDC2_ADRS_0' DCDC2-16 R1053-1 NET 'DCDC2_ADRS_1' DCDC2-15 R1054-1 NET 'DCDC2_SIG_GND' R1053-2 R1054-2 # # Connections to the PVAs Added during routing: # NET 'MGT_AVCC_Pre_L' PVA12_DC2-1 PVA12_DC2-2 PVA12_DC2-3 NET 'MGT_AVCC_Pre_L' PVA12_DC2-4 PVA12_DC2-5 PVA12_DC2-6 NET 'MGT_AVCC_Pre_L' PVA13_DC2-1 PVA13_DC2-2 PVA13_DC2-3 NET 'MGT_AVCC' PVA14_DC2-1 PVA14_DC2-2 PVA14_DC2-3 NET 'MGT_AVCC' PVA14_DC2-4 PVA14_DC2-5 PVA14_DC2-6 NET 'MGT_AVCC' PVA15_DC2-1 PVA15_DC2-2 PVA15_DC2-3 NET 'MGT_AVCC' PVA15_DC2-4 PVA15_DC2-5 PVA15_DC2-6 NET 'MGT_AVCC' PVA16_DC2-1 PVA16_DC2-2 PVA16_DC2-3 PVA16_DC2-4 NET 'MGT_AVCC' PVA17_DC2-1 PVA17_DC2-2 PVA17_DC2-3 PVA17_DC2-4 NET 'MGT_AVCC' PVA18_DC2-1 PVA18_DC2-2 PVA18_DC2-3 NET 'GROUND' PVA19_DC2-1 PVA19_DC2-2 PVA19_DC2-3 NET 'GROUND' PVA20_DC2-1 PVA20_DC2-2 PVA20_DC2-3 NET 'ISO_12V' PVA21_DC2-1 # # MGT_AVTT Supply # # DCDC 3 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 3. # # This is the MGT_AVTT supply 1.200 V at 20 Amps. # # This Hub Module supply uses a GE_UDT020 converter. # # # Connect the converter's V_Input, Ground, and V_Output terminals: # NET 'ISO_12V' DCDC3-2 NET 'GROUND' DCDC3-4 NET 'MGT_AVTT_pre_L' DCDC3-6 # # Connect this converter's INPUT Via Arays: # NET 'ISO_12V' PVA1_DC3-1 PVA1_DC3-2 PVA1_DC3-3 PVA1_DC3-4 NET 'ISO_12V' PVA1_DC3-5 PVA1_DC3-6 NET 'ISO_12V' PVA2_DC3-1 PVA2_DC3-2 PVA2_DC3-3 PVA2_DC3-4 # # Connect this converter's GROUND and Sync = Ground Via Arays: # NET 'GROUND' PVA3_DC3-1 PVA3_DC3-2 PVA3_DC3-3 PVA3_DC3-4 NET 'GROUND' PVA4_DC3-1 PVA4_DC3-2 PVA4_DC3-3 PVA4_DC3-4 NET 'GROUND' PVA4_DC3-5 PVA4_DC3-6 PVA4_DC3-7 PVA4_DC3-8 NET 'GROUND' PVA4_DC3-9 PVA4_DC3-10 PVA4_DC3-11 PVA4_DC3-12 NET 'GROUND' PVA5_DC3-1 NET 'GROUND' PVA6_DC3-1 NET 'GROUND' PVA7_DC3-1 # # Connect this converter's OUTPUT Via Arays: # NET 'MGT_AVTT_pre_L' PVA8_DC3-1 PVA8_DC3-2 PVA8_DC3-3 PVA8_DC3-4 NET 'MGT_AVTT_pre_L' PVA8_DC3-5 PVA8_DC3-6 PVA8_DC3-7 PVA8_DC3-8 NET 'MGT_AVTT_pre_L' PVA8_DC3-9 PVA8_DC3-10 PVA8_DC3-11 PVA8_DC3-12 NET 'MGT_AVTT_pre_L' PVA9_DC3-1 NET 'MGT_AVTT_pre_L' PVA10_DC3-1 NET 'MGT_AVTT_pre_L' PVA11_DC3-1 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1111-1 C1112-1 C1113-1 C1114-1 NET 'GROUND' C1111-2 C1112-2 C1113-2 C1114-2 NET 'ISO_12V' C1115-1 C1116-1 NET 'GROUND' C1115-2 C1116-2 # # Connect this converter's OUTPUT Filter # and connect the Output Filter Choke: # NET 'MGT_AVTT_pre_L' C1121-1 C1122-1 C1123-1 C1124-1 C1128-1 NET 'GROUND' C1121-2 C1122-2 C1123-2 C1124-2 C1128-2 NET 'MGT_AVTT_pre_L' C1125-1 C1126-1 NET 'GROUND' C1125-2 C1126-2 NET 'MGT_AVTT_pre_L' C1127-1 NET 'GROUND' C1127-2 NET 'MGT_AVTT_pre_L' L1101-1 NET 'MGT_AVTT' L1101-2 NET 'MGT_AVTT' DZ1101-1 NET 'GROUND' DZ1101-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC3-10 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_3_OFF_ON' DCDC3-1 NET 'DCDC_3_POWER_GOOD' DCDC3-9 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1105 is the 20k Ohm series resistor. # R1106 is the scale shunt resistor to ground. NET 'CONVERTER_RAMP' R1105-2 NET 'DCDC3_RAMP_SEQUENCE' R1105-1 R1106-2 C1102-2 DCDC3-3 NET 'DCDC3_SIG_GND' R1106-1 C1102-1 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC3_TRIM' DCDC3-5 R1102-2 NET 'DCDC3_SIG_GND' DCDC3-14 R1102-1 # # Connect this conberter's Feedback Source Point # Select Jumpers to the two possible feedback # source points. # NET 'MGT_AVTT_pre_L' JMP1101-2 JMP1103-1 NET 'MGT_AVTT' JMP1102-2 JMP1104-1 # Connect this converter's Differential Amp # Remote Sense input terminals V_SENSE_PLUS # and V_SENSE_MINUS: # NET 'DCDC3_DIFF_FDBK' DCDC3-7 JMP1101-1 JMP1102-1 NET 'GROUND' DCDC3-8 # # Connect this converter's Servo Loop RC components # between the Feedback Source Point Select Jumpers # and its TRIM terminal: # NET 'DCDC3_RC_FDBK' C1101-2 JMP1103-2 JMP1104-2 NET 'DCDC3_LOOP_RC' C1101-1 R1101-1 NET 'DCDC3_TRIM' R1101-2 # # Connect this converter's direct capacitor feedback # from before the LC filter to its "Trim" input. # NET 'MGT_AVTT_pre_L' C1103-1 NET 'DCDC3_TRIM' C1103-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC3-11 NET 'Hub_PMBus_SDA' DCDC3-12 NET 'Hubs_SMB_Alert_B' DCDC3-13 NET 'DCDC3_ADRS_0' DCDC3-16 R1103-1 NET 'DCDC3_ADRS_1' DCDC3-15 R1104-1 NET 'DCDC3_SIG_GND' R1103-2 R1104-2 # # Connections to the PVAs Added during routing: # NET 'MGT_AVTT_Pre_L' PVA12_DC3-1 PVA12_DC3-2 PVA12_DC3-3 NET 'MGT_AVTT_Pre_L' PVA12_DC3-4 PVA12_DC3-5 PVA12_DC3-6 NET 'MGT_AVTT_Pre_L' PVA13_DC3-1 PVA13_DC3-2 PVA13_DC3-3 NET 'MGT_AVTT' PVA14_DC3-1 PVA14_DC3-2 PVA14_DC3-3 NET 'MGT_AVTT' PVA14_DC3-4 PVA14_DC3-5 PVA14_DC3-6 NET 'MGT_AVTT' PVA15_DC3-1 PVA15_DC3-2 PVA15_DC3-3 NET 'MGT_AVTT' PVA15_DC3-4 PVA15_DC3-5 PVA15_DC3-6 NET 'MGT_AVTT' PVA16_DC3-1 PVA16_DC3-2 PVA16_DC3-3 PVA16_DC3-4 NET 'MGT_AVTT' PVA17_DC3-1 PVA17_DC3-2 PVA17_DC3-3 PVA17_DC3-4 NET 'MGT_AVTT' PVA18_DC3-1 PVA18_DC3-2 PVA18_DC3-3 NET 'GROUND' PVA19_DC3-1 PVA19_DC3-2 PVA19_DC3-3 NET 'GROUND' PVA20_DC3-1 PVA20_DC3-2 PVA20_DC3-3 NET 'ISO_12V' PVA21_DC3-1 # # MGT_AVAUX Supply # # DCDC 4 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 12-Jul-2016 # # # # This file holds all of the nets for the DCDC 4 supply. # # This is the MGT_AVAUX supply 1.800 V at 3 Amps. # # This Hub Module supply uses a LT1764A linear # regulator for this supply. # # # Connect the regulator's V_Input, V_Output, and Ground terminals: # NET 'FLTR_3V3_DCDC4' DCDC4-2 NET 'MGT_AVAUX' DCDC4-4 NET 'GROUND' DCDC4-3 DCDC4-6 # # Connect this regulator's Input Filter: # NET 'FLTR_3V3_DCDC4' C1151-2 C1152-2 NET 'GROUND' C1151-1 C1152-1 # # Connect this regulator's Output Filter: # NET 'MGT_AVAUX' C1154-1 C1155-1 DZ1151-1 NET 'GROUND' C1154-2 C1155-2 DZ1151-2 # # Connect this regulator's SHUT_DOWN_B terminal: # NET 'DCDC4_SHDN_B' DCDC4-1 R1151-2 NET 'FLTR_3V3_DCDC4' R1151-1 # # Connect this regulator's SENSE_ADJUST terminal: # NET 'DCDC4_ADJUST' DCDC4-5 R1153-2 C1153-1 NET 'MGT_AVAUX' R1152-2 NET 'DCDC4_TRM_TOP' R1152-1 R1153-1 C1153-2 NET 'DCDC4_TRM_BOT' R1154-1 R1153-3 NET 'GROUND' R1154-2 # # BULK_3V3 Input Filter for high frequency noise # NET 'BULK_3V3' L1151-1 C1150-2 NET 'FLTR_3V3_DCDC4' L1151-2 NET 'GROUND' C1150-1 # # SWCH_1V2 Supply # # DCDC 5 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 5. # # This is the SWCH_1V2 supply 1.200 V at 12 Amps. # # This Hub Module supply uses a GE_PDT012 converter. # # Recall that the SWCH_1V2 rail ramps up after all of # the other power buses are up and stable. # # DCDC_5 does not use the analog Ramp Sequence signal. # # # Connect the converter's V_Input, V_Output, and Ground terminals: # NET 'ISO_12V' DCDC5-2 NET 'GROUND' DCDC5-3 DCDC5-7 NET 'SWCH_1V2' DCDC5-4 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1211-2 C1212-2 C1213-2 C1214-2 NET 'GROUND' C1211-1 C1212-1 C1213-1 C1214-1 NET 'ISO_12V' C1215-2 C1216-2 NET 'GROUND' C1215-1 C1216-1 # # Connect this converter's OUTPUT Filter: # NET 'SWCH_1V2' C1221-1 C1222-1 C1223-1 C1224-1 NET 'GROUND' C1221-2 C1222-2 C1223-2 C1224-2 NET 'SWCH_1V2' C1225-1 C1226-1 C1227-1 DZ1201-1 NET 'GROUND' C1225-2 C1226-2 C1227-2 DZ1201-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC5-11 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_5_OFF_ON' DCDC5-1 NET 'DCDC_5_POWER_GOOD' DCDC5-10 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # DCDC_5 does not use the Ramp Sequence signal. # DCDC_5 ramps up after all of the other DCDC # converters are up and stable. DCDC_5 controls # its own ramp rate. # NET 'No_Conn_DCDC5_Ramp_Sequence' DCDC5-9 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC5_TRIM' DCDC5-6 R1202-2 NET 'DCDC5_SIG_GND' DCDC5-13 R1202-1 # # Connect this converter's Remote Sense input # terminals V_SENSE_PLUS and V_SENSE_MINUS: # NET 'SWCH_1V2' DCDC5-5 NET 'GROUND' DCDC5-12 # # Connect this converter's Servo Loop RC components # between the V_SENSE_PLUS and TRIM terminals: # NET 'SWCH_1V2' C1201-1 NET 'DCDC5_LOOP_RC' C1201-2 R1201-1 NET 'DCDC5_TRIM' R1201-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC5-8 NET 'Hub_PMBus_SDA' DCDC5-15 NET 'Hubs_SMB_Alert_B' DCDC5-14 NET 'DCDC5_ADRS_0' DCDC5-16 R1203-2 NET 'DCDC5_ADRS_1' DCDC5-17 R1204-2 NET 'DCDC5_SIG_GND' R1203-1 R1204-1 # # Connect the Power Via Arrays # # # INPUT Via-Arrays # NET 'ISO_12V' PVA1_dc5-1 PVA1_dc5-2 PVA1_dc5-3 NET 'ISO_12V' PVA1_dc5-4 PVA1_dc5-5 PVA1_dc5-6 NET 'ISO_12V' PVA2_dc5-1 PVA3_dc5-1 # # GROUND Via-Arrays # NET 'GROUND' PVA4_dc5-1 PVA4_dc5-2 PVA4_dc5-3 NET 'GROUND' PVA5_dc5-1 PVA6_dc5-1 PVA7_dc5-1 NET 'GROUND' PVA8_dc5-1 PVA9_dc5-1 # # OUTPUT Via-Arrays # NET 'SWCH_1V2' PVA10_dc5-1 PVA10_dc5-2 PVA10_dc5-3 NET 'SWCH_1V2' PVA10_dc5-4 PVA10_dc5-5 PVA10_dc5-6 NET 'SWCH_1V2' PVA11_dc5-1 PVA11_dc5-2 PVA11_dc5-3 NET 'SWCH_1V2' PVA11_dc5-4 PVA11_dc5-5 PVA11_dc5-6 NET 'SWCH_1V2' PVA12_dc5-1 # # BULK_1V8 Supply # # DCDC 6 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 6. # # This is the BULK_1V8 supply 1.800 V at 12 Amps. # # This Hub Module supply uses a GE_PDT012 converter. # # # Connect the converter's V_Input, V_Output, and Ground terminals: # NET 'ISO_12V' DCDC6-2 NET 'GROUND' DCDC6-3 DCDC6-7 NET 'BULK_1V8' DCDC6-4 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1261-2 C1262-2 C1263-2 C1264-2 NET 'GROUND' C1261-1 C1262-1 C1263-1 C1264-1 NET 'ISO_12V' C1265-2 C1266-2 NET 'GROUND' C1265-1 C1266-1 # # Connect this converter's OUTPUT Filter: # NET 'BULK_1V8' C1271-1 C1272-1 C1273-1 C1274-1 NET 'GROUND' C1271-2 C1272-2 C1273-2 C1274-2 NET 'BULK_1V8' C1275-1 C1276-1 C1277-1 DZ1251-1 NET 'GROUND' C1275-2 C1276-2 C1277-2 DZ1251-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC6-11 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_6_OFF_ON' DCDC6-1 NET 'DCDC_6_POWER_GOOD' DCDC6-10 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1255 is the 20k Ohm series resistor. # R1256 is the scale shunt resistor to ground. NET 'CONVERTER_RAMP' R1255-2 NET 'DCDC6_RAMP_SEQUENCE' R1255-1 R1256-2 C1252-2 DCDC6-9 NET 'DCDC6_SIG_GND' R1256-1 C1252-1 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC6_TRIM' DCDC6-6 R1252-2 NET 'DCDC6_SIG_GND' DCDC6-13 R1252-1 # # Connect this converter's Remote Sense input # terminals V_SENSE_PLUS and V_SENSE_MINUS: # NET 'BULK_1V8' DCDC6-5 NET 'GROUND' DCDC6-12 # # Connect this converter's Servo Loop RC components # between the V_SENSE_PLUS and TRIM terminals: # NET 'BULK_1V8' C1251-1 NET 'DCDC6_LOOP_RC' C1251-2 R1251-1 NET 'DCDC6_TRIM' R1251-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC6-8 NET 'Hub_PMBus_SDA' DCDC6-15 NET 'Hubs_SMB_Alert_B' DCDC6-14 NET 'DCDC6_ADRS_0' DCDC6-16 R1253-2 NET 'DCDC6_ADRS_1' DCDC6-17 R1254-2 NET 'DCDC6_SIG_GND' R1253-1 R1254-1 # # Connect the Power Via Arrays # # # INPUT Via-Arrays # NET 'ISO_12V' PVA1_dc6-1 PVA1_dc6-2 PVA1_dc6-3 NET 'ISO_12V' PVA1_dc6-4 PVA1_dc6-5 PVA1_dc6-6 NET 'ISO_12V' PVA2_dc6-1 PVA3_dc6-1 # # GROUND Via-Arrays # NET 'GROUND' PVA4_dc6-1 PVA4_dc6-2 PVA4_dc6-3 NET 'GROUND' PVA5_dc6-1 PVA6_dc6-1 PVA7_dc6-1 NET 'GROUND' PVA8_dc6-1 PVA9_dc6-1 # # OUTPUT Via-Arrays # NET 'BULK_1V8' PVA10_dc6-1 PVA10_dc6-2 PVA10_dc6-3 NET 'BULK_1V8' PVA10_dc6-4 PVA10_dc6-5 PVA10_dc6-6 NET 'BULK_1V8' PVA11_dc6-1 PVA11_dc6-2 PVA11_dc6-3 NET 'BULK_1V8' PVA11_dc6-4 PVA11_dc6-5 PVA11_dc6-6 NET 'BULK_1V8' PVA12_dc6-1 PVA13_dc6-1 # # FAN_1V8 Supply # # DCDC 7 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 7. # # This is the FAN_1V8 supply 1.800 V at 20 Amps. # # This Hub Module supply uses a GE_UDT020 converter. # # This converter powers the MGT Fanout circuits. # # # Connect the converter's V_Input, V_Output, and Ground terminals: # NET 'ISO_12V' DCDC7-2 NET 'GROUND' DCDC7-4 NET 'FAN_1V8_pre_L' DCDC7-6 # # Connect this converter's INPUT Via Arays: # NET 'ISO_12V' PVA1_DC7-1 PVA1_DC7-2 PVA1_DC7-3 PVA1_DC7-4 NET 'ISO_12V' PVA1_DC7-5 PVA1_DC7-6 NET 'ISO_12V' PVA2_DC7-1 PVA2_DC7-2 PVA2_DC7-3 PVA2_DC7-4 # # Connect this converter's GROUND and Sync = Ground Via Arays: # NET 'GROUND' PVA3_DC7-1 PVA3_DC7-2 PVA3_DC7-3 PVA3_DC7-4 NET 'GROUND' PVA4_DC7-1 PVA4_DC7-2 PVA4_DC7-3 PVA4_DC7-4 NET 'GROUND' PVA4_DC7-5 PVA4_DC7-6 PVA4_DC7-7 PVA4_DC7-8 NET 'GROUND' PVA4_DC7-9 PVA4_DC7-10 PVA4_DC7-11 PVA4_DC7-12 NET 'GROUND' PVA5_DC7-1 NET 'GROUND' PVA6_DC7-1 NET 'GROUND' PVA7_DC7-1 # # Connect this converter's OUTPUT Via Arays: # NET 'FAN_1V8_pre_L' PVA8_DC7-1 PVA8_DC7-2 PVA8_DC7-3 PVA8_DC7-4 NET 'FAN_1V8_pre_L' PVA8_DC7-5 PVA8_DC7-6 PVA8_DC7-7 PVA8_DC7-8 NET 'FAN_1V8_pre_L' PVA8_DC7-9 PVA8_DC7-10 PVA8_DC7-11 PVA8_DC7-12 NET 'FAN_1V8_pre_L' PVA9_DC7-1 NET 'FAN_1V8_pre_L' PVA10_DC7-1 NET 'FAN_1V8_pre_L' PVA11_DC7-1 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1311-1 C1312-1 C1313-1 C1314-1 NET 'GROUND' C1311-2 C1312-2 C1313-2 C1314-2 NET 'ISO_12V' C1315-1 C1316-1 NET 'GROUND' C1315-2 C1316-2 # # Connect this converter's OUTPUT Filter # and connect the Output Filter Choke: # NET 'FAN_1V8_pre_L' C1321-1 C1322-1 C1323-1 C1324-1 C1328-1 NET 'GROUND' C1321-2 C1322-2 C1323-2 C1324-2 C1328-2 NET 'FAN_1V8_pre_L' C1325-1 C1326-1 NET 'GROUND' C1325-2 C1326-2 NET 'FAN_1V8_pre_L' C1327-1 NET 'GROUND' C1327-2 NET 'FAN_1V8_pre_L' L1301-1 NET 'FAN_1V8' L1301-2 NET 'FAN_1V8' DZ1301-1 NET 'GROUND' DZ1301-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC7-10 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_7_OFF_ON' DCDC7-1 NET 'DCDC_7_POWER_GOOD' DCDC7-9 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1105 is the 20k Ohm series resistor. # R1106 is the scale shunt resistor to ground. NET 'CONVERTER_RAMP' R1305-2 NET 'DCDC7_RAMP_SEQUENCE' R1305-1 R1306-2 C1302-2 DCDC7-3 NET 'DCDC7_SIG_GND' R1306-1 C1302-1 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC7_TRIM' DCDC7-5 R1302-2 NET 'DCDC7_SIG_GND' DCDC7-14 R1302-1 # # Connect this conberter's Feedback Source Point # Select Jumpers to the two possible feedback # source points. # NET 'FAN_1V8_pre_L' JMP1301-2 JMP1303-1 NET 'FAN_1V8' JMP1302-2 JMP1304-1 # Connect this converter's Differential Amp # Remote Sense input terminals V_SENSE_PLUS # and V_SENSE_MINUS: # NET 'DCDC7_DIFF_FDBK' DCDC7-7 JMP1301-1 JMP1302-1 NET 'GROUND' DCDC7-8 # # Connect this converter's Servo Loop RC components # between the Feedback Source Point Select Jumpers # and its TRIM terminal: # NET 'DCDC7_RC_FDBK' C1301-2 JMP1303-2 JMP1304-2 NET 'DCDC7_LOOP_RC' C1301-1 R1301-1 NET 'DCDC7_TRIM' R1301-2 # # Connect this converter's direct capacitor feedback # from before the LC filter to its "Trim" input. # NET 'FAN_1V8_pre_L' C1303-1 NET 'DCDC7_TRIM' C1303-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC7-11 NET 'Hub_PMBus_SDA' DCDC7-12 NET 'Hubs_SMB_Alert_B' DCDC7-13 NET 'DCDC7_ADRS_0' DCDC7-16 R1303-1 NET 'DCDC7_ADRS_1' DCDC7-15 R1304-1 NET 'DCDC7_SIG_GND' R1303-2 R1304-2 # # Connections to the PVAs Added during routing: # NET 'FAN_1V8_Pre_L' PVA12_DC7-1 PVA12_DC7-2 PVA12_DC7-3 NET 'FAN_1V8_Pre_L' PVA12_DC7-4 PVA12_DC7-5 PVA12_DC7-6 NET 'FAN_1V8_Pre_L' PVA13_DC7-1 PVA13_DC7-2 PVA13_DC7-3 NET 'FAN_1V8' PVA14_DC7-1 PVA14_DC7-2 PVA14_DC7-3 NET 'FAN_1V8' PVA14_DC7-4 PVA14_DC7-5 PVA14_DC7-6 NET 'FAN_1V8' PVA15_DC7-1 PVA15_DC7-2 PVA15_DC7-3 NET 'FAN_1V8' PVA15_DC7-4 PVA15_DC7-5 PVA15_DC7-6 NET 'FAN_1V8' PVA16_DC7-1 PVA16_DC7-2 PVA16_DC7-3 PVA16_DC7-4 NET 'FAN_1V8' PVA17_DC7-1 PVA17_DC7-2 PVA17_DC7-3 PVA17_DC7-4 NET 'FAN_1V8' PVA18_DC7-1 PVA18_DC7-2 PVA18_DC7-3 NET 'GROUND' PVA19_DC7-1 PVA19_DC7-2 PVA19_DC7-3 NET 'GROUND' PVA20_DC7-1 PVA20_DC7-2 PVA20_DC7-3 NET 'ISO_12V' PVA21_DC7-1 # # BULK_3V3 Supply # # DCDC 8 Converter Nets # ------------------------- # # # Original Rev. 27-Mar-2015 # Current Rev. 2-Dec-2016 # # # # This file holds all of the nets for DCDC Converter 8. # # This is the BULK_3V3 supply 3.300 V at 12 Amps. # # This Hub Module supply uses a GE_PDT012 converter. # # # Connect the converter's V_Input, V_Output, and Ground terminals: # NET 'ISO_12V' DCDC8-2 NET 'GROUND' DCDC8-3 DCDC8-7 NET 'BULK_3V3' DCDC8-4 # # Connect this converter's INPUT Filter: # NET 'ISO_12V' C1361-1 C1362-1 C1363-1 C1364-1 NET 'GROUND' C1361-2 C1362-2 C1363-2 C1364-2 NET 'ISO_12V' C1365-1 C1366-1 NET 'GROUND' C1365-2 C1366-2 # # Connect this converter's OUTPUT Filter: # NET 'BULK_3V3' C1371-1 C1372-1 C1373-1 C1374-1 NET 'GROUND' C1371-2 C1372-2 C1373-2 C1374-2 NET 'BULK_3V3' C1375-1 C1376-1 C1377-1 DZ1351-1 NET 'GROUND' C1375-2 C1376-2 C1377-2 DZ1351-2 # # Ground this converter's unused SYNC terminal: # NET 'GROUND' DCDC8-11 # # Connect the ON_OFF and POWER_GOOD terminals: # # Recall: The ON_OFF pin is Low active, i.e. voltage low --> ON. # The POWER_GOOD is a common open drain signal # NET 'DCDC_8_OFF_ON' DCDC8-1 NET 'DCDC_8_POWER_GOOD' DCDC8-10 # # Connect the RAMP_SEQUENCE terminal: # # Recall: # # The output voltage tracks the scaled Vseq up to set point. # R1355 is the 20k Ohm series resistor. # R1356 is the scale shunt resistor to ground. NET 'CONVERTER_RAMP' R1355-2 NET 'DCDC8_RAMP_SEQUENCE' R1355-1 R1356-2 C1352-2 DCDC8-9 NET 'DCDC8_SIG_GND' R1356-1 C1352-1 # # Connect this converter's Output Voltage Control resistor # between the TRIM and SIG_GND terminals: # NET 'DCDC8_TRIM' DCDC8-6 R1352-2 NET 'DCDC8_SIG_GND' DCDC8-13 R1352-1 # # Connect this converter's Remote Sense input # terminals V_SENSE_PLUS and V_SENSE_MINUS: # NET 'BULK_3V3' DCDC8-5 NET 'GROUND' DCDC8-12 # # Connect this converter's Servo Loop RC components # between the V_SENSE_PLUS and TRIM terminals: # NET 'BULK_3V3' C1351-1 NET 'DCDC8_LOOP_RC' C1351-2 R1351-1 NET 'DCDC8_TRIM' R1351-2 # # Connect the PMBus to this converter and set its address # using the PMBUS_CLK, PMBUS_DATA, SMB_ALERT, ADRS0 # and ADRS1 terminals: # NET 'Hub_PMBus_SCL' DCDC8-8 NET 'Hub_PMBus_SDA' DCDC8-15 NET 'Hubs_SMB_Alert_B' DCDC8-14 NET 'DCDC8_ADRS_0' DCDC8-16 R1353-2 NET 'DCDC8_ADRS_1' DCDC8-17 R1354-2 NET 'DCDC8_SIG_GND' R1353-1 R1354-1 # # Connect the Power Via Arrays # # # INPUT Via-Arrays # NET 'ISO_12V' PVA1_dc8-1 PVA1_dc8-2 PVA1_dc8-3 NET 'ISO_12V' PVA1_dc8-4 PVA1_dc8-5 PVA1_dc8-6 NET 'ISO_12V' PVA2_dc8-1 PVA3_dc8-1 # # GROUND Via-Arrays # NET 'GROUND' PVA4_dc8-1 PVA4_dc8-2 PVA4_dc8-3 NET 'GROUND' PVA5_dc8-1 PVA6_dc8-1 PVA7_dc8-1 NET 'GROUND' PVA8_dc8-1 PVA9_dc8-1 # # OUTPUT Via-Arrays # NET 'BULK_3V3' PVA10_dc8-1 PVA10_dc8-2 PVA10_dc8-3 NET 'BULK_3V3' PVA10_dc8-4 PVA10_dc8-5 PVA10_dc8-6 NET 'BULK_3V3' PVA11_dc8-1 PVA11_dc8-2 PVA11_dc8-3 NET 'BULK_3V3' PVA11_dc8-4 PVA11_dc8-5 PVA11_dc8-6 NET 'BULK_3V3' PVA12_dc8-1 PVA13_dc8-1 # # BULK_2V5 Supply # # DCDC 9 Converter Nets # ------------------------- # # # Original Rev. 22-Jul-2015 # Current Rev. 21-Nov-2016 # # # # This file holds all of the nets for the DCDC 9 supply. # # This is the BULK_2V5 supply 2.500 V at 3 Amps # # for the MiniPODs and Clock Distribution. # # This Hub Module supply uses a LT1764A linear # regulator for this supply. # # # Connect the regulator's V_Input, V_Output, and Ground terminals: # # Note the large number (35) of ground connections to # the Thermal/Ground pad in the geometry for this device. NET 'FLTR_3V3_DCDC9' DCDC9-2 NET 'BULK_2V5' DCDC9-4 NET 'GROUND' DCDC9-3 NET 'GROUND' DCDC9-6 DCDC9-7 DCDC9-8 DCDC9-9 DCDC9-10 NET 'GROUND' DCDC9-11 DCDC9-12 DCDC9-13 DCDC9-14 DCDC9-15 NET 'GROUND' DCDC9-16 DCDC9-17 DCDC9-18 DCDC9-19 DCDC9-20 NET 'GROUND' DCDC9-21 DCDC9-22 DCDC9-23 DCDC9-24 DCDC9-25 NET 'GROUND' DCDC9-26 DCDC9-27 DCDC9-28 DCDC9-29 DCDC9-30 NET 'GROUND' DCDC9-31 DCDC9-32 DCDC9-33 DCDC9-34 DCDC9-35 NET 'GROUND' DCDC9-36 DCDC9-37 DCDC9-38 DCDC9-39 DCDC9-40 # # Connect this regulator's Input Filter: # NET 'FLTR_3V3_DCDC9' C1171-2 C1172-2 NET 'GROUND' C1171-1 C1172-1 # # Connect this regulator's Output Filter: # NET 'BULK_2V5' C1174-1 C1175-1 DZ1171-1 NET 'GROUND' C1174-2 C1175-2 DZ1171-2 # # Connect this regulator's SHUT_DOWN_B terminal: # NET 'DCDC9_SHDN_B' DCDC9-1 R1171-2 NET 'FLTR_3V3_DCDC9' R1171-1 # # Connect this regulator's SENSE_ADJUST terminal: # NET 'DCDC9_ADJUST' DCDC9-5 R1173-2 C1173-1 NET 'BULK_2V5' R1172-2 NET 'DCDC9_TRM_TOP' R1172-1 R1173-1 C1173-2 NET 'DCDC9_TRM_BOT' R1174-1 R1173-3 NET 'GROUND' R1174-2 # # BULK_3V3 Input Filter for high frequency noise # NET 'BULK_3V3' L1171-1 C1170-2 NET 'FLTR_3V3_DCDC9' L1171-2 NET 'GROUND' C1170-1 # # BULK_2V5 feed to the filter # for the Clock Fanout Chips # NET 'BULK_2V5' WTERM51-1 # # DCDC Converter Bulk Input Filter Nets # -------------------------------------------- # # # Original Rev. 27-Jul-2015 # Most Recent Rev. 18-May-2016 # # # # This file holds the nets for all of the shared # Bulk Input Filter capacitors for the DCDC Converters # on the Hub Module. # # These filter capacitors are on the Isolated +12 Volt # bus. # # These filter capacitors also help control the noise # on the Iso +12V bus that runs up to the ROD on MegArray # connector #1. # # Each of the DCDC Converters also has its own private # higher frequency input filter capacitors. # # # Recall that the geometries used for both these D Case # Tant capacitors and these 1206 size ceramic capacitors # are THD devices, i.e. they include their own traces # and vias to reach down into the power and ground planes. # # Note that on these Tant_D_THD capacitors that both # pins #1 and #3 are connected to the positive SMD pad and # pins #2 and #4 are connected to the negative SMD pad. # # First the nets for the main group of the Bulk Input # Filter capacitors to the West of MegArray #1 # # C2601 through C2636 22 uFd Tantalum Capacitors NET 'ISO_12V' C2601-1 C2602-1 C2603-1 C2604-1 C2605-1 NET 'ISO_12V' C2601-3 C2602-3 C2603-3 C2604-3 C2605-3 NET 'GROUND' C2601-2 C2602-2 C2603-2 C2604-2 C2605-2 NET 'GROUND' C2601-4 C2602-4 C2603-4 C2604-4 C2605-4 NET 'ISO_12V' C2606-1 C2607-1 C2608-1 C2609-1 C2610-1 NET 'ISO_12V' C2606-3 C2607-3 C2608-3 C2609-3 C2610-3 NET 'GROUND' C2606-2 C2607-2 C2608-2 C2609-2 C2610-2 NET 'GROUND' C2606-4 C2607-4 C2608-4 C2609-4 C2610-4 NET 'ISO_12V' C2611-1 C2612-1 C2613-1 C2614-1 C2615-1 NET 'ISO_12V' C2611-3 C2612-3 C2613-3 C2614-3 C2615-3 NET 'GROUND' C2611-2 C2612-2 C2613-2 C2614-2 C2615-2 NET 'GROUND' C2611-4 C2612-4 C2613-4 C2614-4 C2615-4 NET 'ISO_12V' C2616-1 C2617-1 C2618-1 C2619-1 C2620-1 NET 'ISO_12V' C2616-3 C2617-3 C2618-3 C2619-3 C2620-3 NET 'GROUND' C2616-2 C2617-2 C2618-2 C2619-2 C2620-2 NET 'GROUND' C2616-4 C2617-4 C2618-4 C2619-4 C2620-4 NET 'ISO_12V' C2621-1 C2622-1 C2623-1 C2624-1 C2625-1 NET 'ISO_12V' C2621-3 C2622-3 C2623-3 C2624-3 C2625-3 NET 'GROUND' C2621-2 C2622-2 C2623-2 C2624-2 C2625-2 NET 'GROUND' C2621-4 C2622-4 C2623-4 C2624-4 C2625-4 NET 'ISO_12V' C2626-1 C2627-1 C2628-1 C2629-1 C2630-1 NET 'ISO_12V' C2626-3 C2627-3 C2628-3 C2629-3 C2630-3 NET 'GROUND' C2626-2 C2627-2 C2628-2 C2629-2 C2630-2 NET 'GROUND' C2626-4 C2627-4 C2628-4 C2629-4 C2630-4 NET 'ISO_12V' C2631-1 C2632-1 C2633-1 C2634-1 C2635-1 NET 'ISO_12V' C2631-3 C2632-3 C2633-3 C2634-3 C2635-3 NET 'GROUND' C2631-2 C2632-2 C2633-2 C2634-2 C2635-2 NET 'GROUND' C2631-4 C2632-4 C2633-4 C2634-4 C2635-4 NET 'ISO_12V' C2636-1 NET 'ISO_12V' C2636-3 NET 'GROUND' C2636-2 NET 'GROUND' C2636-4 # C2701 through C2772 10 uFd Ceramic Capacitors NET 'ISO_12V' C2701-1 C2702-1 C2703-1 C2704-1 C2705-1 NET 'GROUND' C2701-2 C2702-2 C2703-2 C2704-2 C2705-2 NET 'ISO_12V' C2706-1 C2707-1 C2708-1 C2709-1 C2710-1 NET 'GROUND' C2706-2 C2707-2 C2708-2 C2709-2 C2710-2 NET 'ISO_12V' C2711-1 C2712-1 C2713-1 C2714-1 C2715-1 NET 'GROUND' C2711-2 C2712-2 C2713-2 C2714-2 C2715-2 NET 'ISO_12V' C2716-1 C2717-1 C2718-1 C2719-1 C2720-1 NET 'GROUND' C2716-2 C2717-2 C2718-2 C2719-2 C2720-2 NET 'ISO_12V' C2721-1 C2722-1 C2723-1 C2724-1 C2725-1 NET 'GROUND' C2721-2 C2722-2 C2723-2 C2724-2 C2725-2 NET 'ISO_12V' C2726-1 C2727-1 C2728-1 C2729-1 C2730-1 NET 'GROUND' C2726-2 C2727-2 C2728-2 C2729-2 C2730-2 NET 'ISO_12V' C2731-1 C2732-1 C2733-1 C2734-1 C2735-1 NET 'GROUND' C2731-2 C2732-2 C2733-2 C2734-2 C2735-2 NET 'ISO_12V' C2736-1 C2737-1 C2738-1 C2739-1 C2740-1 NET 'GROUND' C2736-2 C2737-2 C2738-2 C2739-2 C2740-2 NET 'ISO_12V' C2741-1 C2742-1 C2743-1 C2744-1 C2745-1 NET 'GROUND' C2741-2 C2742-2 C2743-2 C2744-2 C2745-2 NET 'ISO_12V' C2746-1 C2747-1 C2748-1 C2749-1 C2750-1 NET 'GROUND' C2746-2 C2747-2 C2748-2 C2749-2 C2750-2 NET 'ISO_12V' C2751-1 C2752-1 C2753-1 C2754-1 C2755-1 NET 'GROUND' C2751-2 C2752-2 C2753-2 C2754-2 C2755-2 NET 'ISO_12V' C2756-1 C2757-1 C2758-1 C2759-1 C2760-1 NET 'GROUND' C2756-2 C2757-2 C2758-2 C2759-2 C2760-2 NET 'ISO_12V' C2761-1 C2762-1 C2763-1 C2764-1 C2765-1 NET 'GROUND' C2761-2 C2762-2 C2763-2 C2764-2 C2765-2 NET 'ISO_12V' C2766-1 C2767-1 C2768-1 C2769-1 C2770-1 NET 'GROUND' C2766-2 C2767-2 C2768-2 C2769-2 C2770-2 NET 'ISO_12V' C2771-1 C2772-1 NET 'GROUND' C2771-2 C2772-2 # # Now the smaller group of the Bulk Input Filter # capacitors to the East of MegArray #2 # # C2637 through C2648 22 uFd Tantalum Capacitors NET 'ISO_12V' C2637-1 C2638-1 C2639-1 C2640-1 NET 'ISO_12V' C2637-3 C2638-3 C2639-3 C2640-3 NET 'GROUND' C2637-2 C2638-2 C2639-2 C2640-2 NET 'GROUND' C2637-4 C2638-4 C2639-4 C2640-4 NET 'ISO_12V' C2641-1 C2642-1 C2643-1 C2644-1 C2645-1 NET 'ISO_12V' C2641-3 C2642-3 C2643-3 C2644-3 C2645-3 NET 'GROUND' C2641-2 C2642-2 C2643-2 C2644-2 C2645-2 NET 'GROUND' C2641-4 C2642-4 C2643-4 C2644-4 C2645-4 NET 'ISO_12V' C2646-1 C2647-1 C2648-1 NET 'ISO_12V' C2646-3 C2647-3 C2648-3 NET 'GROUND' C2646-2 C2647-2 C2648-2 NET 'GROUND' C2646-4 C2647-4 C2648-4 # C2773 through C2796 10 uFd Ceramic Capacitors NET 'ISO_12V' C2773-1 C2774-1 C2775-1 NET 'GROUND' C2773-2 C2774-2 C2775-2 NET 'ISO_12V' C2776-1 C2777-1 C2778-1 C2779-1 C2780-1 NET 'GROUND' C2776-2 C2777-2 C2778-2 C2779-2 C2780-2 NET 'ISO_12V' C2781-1 C2782-1 C2783-1 C2784-1 C2785-1 NET 'GROUND' C2781-2 C2782-2 C2783-2 C2784-2 C2785-2 NET 'ISO_12V' C2786-1 C2787-1 C2788-1 C2789-1 C2790-1 NET 'GROUND' C2786-2 C2787-2 C2788-2 C2789-2 C2790-2 NET 'ISO_12V' C2791-1 C2792-1 C2793-1 C2794-1 C2795-1 NET 'GROUND' C2791-2 C2792-2 C2793-2 C2794-2 C2795-2 NET 'ISO_12V' C2796-1 NET 'GROUND' C2796-2 # # Finally the 6 Bulk Input Filter Capacitors under the # ATCA Power Entry Module for the DCDC5 SWCH_1V2 converter. # # C2649 & C2650 22 uFd Tantalum Capacitors NET 'ISO_12V' C2649-1 C2650-1 NET 'ISO_12V' C2649-3 C2650-3 NET 'GROUND' C2649-2 C2650-2 NET 'GROUND' C2649-4 C2650-4 # C2797 through C2800 10 uFd Ceramic Capacitors NET 'ISO_12V' C2797-1 C2798-1 C2799-1 C2800-1 NET 'GROUND' C2797-2 C2798-2 C2799-2 C2800-2 # # IPMC Power and Ground Nets # -====------------------------ # # # Original Rev. 27-Mar-2015 # Current Rev. 25-Jul-2016 # # # # This file holds all of the Power and Ground connections # to the DDR3 VLP Mini-DIMM connector for the IPMC card. # # This file also includes the connections to 9 bypass # capacitors that are immediately next to the IPMC Socket. # # This net list file also contains the No_Conn nets to # the IPMC. # # # # IPMC Ground net 42 Ground pins # NET 'GROUND' IPMC-1 NET 'GROUND' IPMC-12 NET 'GROUND' IPMC-23 NET 'GROUND' IPMC-34 NET 'GROUND' IPMC-45 NET 'GROUND' IPMC-56 NET 'GROUND' IPMC-59 NET 'GROUND' IPMC-62 NET 'GROUND' IPMC-89 NET 'GROUND' IPMC-97 NET 'GROUND' IPMC-102 NET 'GROUND' IPMC-107 NET 'GROUND' IPMC-111 NET 'GROUND' IPMC-114 NET 'GROUND' IPMC-119 NET 'GROUND' IPMC-122 NET 'GROUND' IPMC-123 NET 'GROUND' IPMC-134 NET 'GROUND' IPMC-145 NET 'GROUND' IPMC-156 NET 'GROUND' IPMC-167 NET 'GROUND' IPMC-170 NET 'GROUND' IPMC-173 NET 'GROUND' IPMC-176 NET 'GROUND' IPMC-179 NET 'GROUND' IPMC-182 NET 'GROUND' IPMC-185 NET 'GROUND' IPMC-190 NET 'GROUND' IPMC-193 NET 'GROUND' IPMC-196 NET 'GROUND' IPMC-199 NET 'GROUND' IPMC-202 NET 'GROUND' IPMC-205 NET 'GROUND' IPMC-208 NET 'GROUND' IPMC-211 NET 'GROUND' IPMC-219 NET 'GROUND' IPMC-222 NET 'GROUND' IPMC-230 NET 'GROUND' IPMC-233 NET 'GROUND' IPMC-236 NET 'GROUND' IPMC-241 NET 'GROUND' IPMC-244 # # IPMC IPMC_3V3 net 8 IPMC_3V3 VCC pins # NET 'IPMC_3V3' IPMC-65 NET 'IPMC_3V3' IPMC-68 NET 'IPMC_3V3' IPMC-71 NET 'IPMC_3V3' IPMC-74 NET 'IPMC_3V3' IPMC-77 NET 'IPMC_3V3' IPMC-80 NET 'IPMC_3V3' IPMC-83 NET 'IPMC_3V3' IPMC-86 # # Connect the ByPass Capacitors on the IPMC_3V3 rail # at the IPMC Socket # NET 'IPMC_3V3' C1561-2 C1562-2 C1563-2 C1564-2 NET 'IPMC_3V3' C1565-2 C1566-2 C1567-2 C1568-2 NET 'GROUND' C1561-1 C1562-1 C1563-1 C1564-1 NET 'GROUND' C1565-1 C1566-1 C1567-1 C1568-1 NET 'IPMC_3V3' C1569-1 NET 'GROUND' C1569-2 # # No Connection nets to the IPMC # NET 'No_Conn_IPMC_2' IPMC-2 # PS1#_0 NET 'No_Conn_IPMC_3' IPMC-3 # Enable#_0 NET 'No_Conn_IPMC_4' IPMC-4 # IPMB-L_Enable_0 NET 'No_Conn_IPMC_5' IPMC-5 # MP_Enable_0 NET 'No_Conn_IPMC_6' IPMC-6 # PWR_Enable_0 NET 'No_Conn_IPMC_7' IPMC-7 # MP_Good_0 NET 'No_Conn_IPMC_8' IPMC-8 # PWR_Good_0 NET 'No_Conn_IPMC_9' IPMC-9 # MP_Fault_0 NET 'No_Conn_IPMC_10' IPMC-10 # PWR_Fault_0 NET 'No_Conn_IPMC_11' IPMC-11 # PWR_ORing_0 NET 'No_Conn_IPMC_13' IPMC-13 # PS1#_2 NET 'No_Conn_IPMC_14' IPMC-14 # Enable#_2 NET 'No_Conn_IPMC_15' IPMC-15 # IPMB-L_Enable_2 NET 'No_Conn_IPMC_16' IPMC-16 # MP_Enable_2 NET 'No_Conn_IPMC_17' IPMC-17 # PWR_Enable_2 NET 'No_Conn_IPMC_18' IPMC-18 # MP_Good_2 NET 'No_Conn_IPMC_19' IPMC-19 # PWR_Good_2 NET 'No_Conn_IPMC_20' IPMC-20 # MP_Fault_2 NET 'No_Conn_IPMC_21' IPMC-21 # PWR_Fault_2 NET 'No_Conn_IPMC_22' IPMC-22 # PWR_ORing_2 NET 'No_Conn_IPMC_24' IPMC-24 # PS1#_4 NET 'No_Conn_IPMC_25' IPMC-25 # Enable#_4 NET 'No_Conn_IPMC_26' IPMC-26 # IPMB-L_Enable_4 NET 'No_Conn_IPMC_27' IPMC-27 # MP_Enable_4 NET 'No_Conn_IPMC_28' IPMC-28 # PWR_Enable_4 NET 'No_Conn_IPMC_29' IPMC-29 # MP_Good_4 NET 'No_Conn_IPMC_30' IPMC-30 # PWR_Good_4 NET 'No_Conn_IPMC_31' IPMC-31 # MP_Fault_4 NET 'No_Conn_IPMC_32' IPMC-32 # PWR_Fault_4 NET 'No_Conn_IPMC_33' IPMC-33 # PWR_ORing_4 NET 'No_Conn_IPMC_35' IPMC-35 # PS1#_6 NET 'No_Conn_IPMC_36' IPMC-36 # Enable#_6 NET 'No_Conn_IPMC_37' IPMC-37 # IPMB-L_Enable_6 NET 'No_Conn_IPMC_38' IPMC-38 # MP_Enable_6 NET 'No_Conn_IPMC_39' IPMC-39 # PWR_Enable_6 NET 'No_Conn_IPMC_40' IPMC-40 # MP_Good_6 NET 'No_Conn_IPMC_41' IPMC-41 # PWR_Good_6 NET 'No_Conn_IPMC_42' IPMC-42 # MP_Fault_6 NET 'No_Conn_IPMC_43' IPMC-43 # PWR_Fault_6 NET 'No_Conn_IPMC_44' IPMC-44 # PWR_ORing_6 NET 'No_Conn_IPMC_46' IPMC-46 # PS1#_8 NET 'No_Conn_IPMC_47' IPMC-47 # Enable#_8 NET 'No_Conn_IPMC_48' IPMC-48 # IPMB-L_Enable_8 NET 'No_Conn_IPMC_49' IPMC-49 # MP_Enable_8 NET 'No_Conn_IPMC_50' IPMC-50 # PWR_Enable_8 NET 'No_Conn_IPMC_51' IPMC-51 # MP_Good_8 NET 'No_Conn_IPMC_52' IPMC-52 # PWR_Good_8 NET 'No_Conn_IPMC_53' IPMC-53 # MP_Fault_8 NET 'No_Conn_IPMC_54' IPMC-54 # PWR_Fault_8 NET 'No_Conn_IPMC_55' IPMC-55 # PWR_ORing_8 NET 'No_Conn_IPMC_57' IPMC-57 # Uart_Tx NET 'No_Conn_IPMC_58' IPMC-58 # Uart_CTS NET 'No_Conn_IPMC_60' IPMC-60 # Uart_Rx NET 'No_Conn_IPMC_61' IPMC-61 # Uart_RTS NET 'No_Conn_IPMC_63' IPMC-63 # IPM_IO_0 NET 'No_Conn_IPMC_64' IPMC-64 # IPM_IO_1 NET 'No_Conn_IPMC_66' IPMC-66 # IPM_IO_4 NET 'No_Conn_IPMC_67' IPMC-67 # IPM_IO_5 NET 'No_Conn_IPMC_69' IPMC-69 # IPM_IO_8 NET 'No_Conn_IPMC_70' IPMC-70 # IPM_IO_9 NET 'No_Conn_IPMC_72' IPMC-72 # IPM_IO_12 NET 'No_Conn_IPMC_73' IPMC-73 # IPM_IO_13 NET 'No_Conn_IPMC_75' IPMC-75 # USR_0 NET 'No_Conn_IPMC_76' IPMC-76 # USR_1 NET 'No_Conn_IPMC_78' IPMC-78 # USR_4 NET 'No_Conn_IPMC_79' IPMC-79 # USR_5 NET 'No_Conn_IPMC_81' IPMC-81 # USR_8 NET 'No_Conn_IPMC_82' IPMC-82 # USR_9 NET 'No_Conn_IPMC_84' IPMC-84 # USR_12 NET 'No_Conn_IPMC_85' IPMC-85 # USR_13 NET 'No_Conn_IPMC_87' IPMC-87 # USR_16 NET 'No_Conn_IPMC_88' IPMC-88 # USR_17 NET 'No_Conn_IPMC_90' IPMC-90 # USR_20 NET 'No_Conn_IPMC_91' IPMC-91 # USR_22 NET 'No_Conn_IPMC_92' IPMC-92 # USR_24 NET 'No_Conn_IPMC_93' IPMC-93 # USR_26 NET 'No_Conn_IPMC_94' IPMC-94 # USR_28 NET 'No_Conn_IPMC_95' IPMC-95 # USR_30 NET 'No_Conn_IPMC_96' IPMC-96 # USR_32 NET 'No_Conn_IPMC_98' IPMC-98 # USR_34 NET 'No_Conn_IPMC_99' IPMC-99 # USB_Vbus NET 'No_Conn_IPMC_100' IPMC-100 # USB_Dp NET 'No_Conn_IPMC_101' IPMC-101 # USB_Dn NET 'No_Conn_IPMC_108' IPMC-108 # Master_TRST NET 'No_Conn_IPMC_109' IPMC-109 # Master_TDO NET 'No_Conn_IPMC_110' IPMC-110 # Master_TMS NET 'No_Conn_IPMC_112' IPMC-112 # TDO NET 'No_Conn_IPMC_113' IPMC-113 # TMS NET 'No_Conn_IPMC_124' IPMC-124 # PS1#_1 NET 'No_Conn_IPMC_125' IPMC-125 # Enable#_1 NET 'No_Conn_IPMC_126' IPMC-126 # IPMB-L_Enable_1 NET 'No_Conn_IPMC_127' IPMC-127 # MP_Enable_1 NET 'No_Conn_IPMC_128' IPMC-128 # PWR_Enable_1 NET 'No_Conn_IPMC_129' IPMC-129 # MP_Good_1 NET 'No_Conn_IPMC_130' IPMC-130 # PWR_Good_1 NET 'No_Conn_IPMC_131' IPMC-131 # MP_Fault_1 NET 'No_Conn_IPMC_132' IPMC-132 # PWR_Fault_1 NET 'No_Conn_IPMC_133' IPMC-133 # PWR_ORing_1 NET 'No_Conn_IPMC_135' IPMC-135 # PS1#_3 NET 'No_Conn_IPMC_136' IPMC-136 # Enable#_3 NET 'No_Conn_IPMC_137' IPMC-137 # IPMB-L_Enable_3 NET 'No_Conn_IPMC_138' IPMC-138 # MP_Enable_3 NET 'No_Conn_IPMC_139' IPMC-139 # PWR_Enable_3 NET 'No_Conn_IPMC_140' IPMC-140 # MP_Good_3 NET 'No_Conn_IPMC_141' IPMC-141 # PWR_Good_3 NET 'No_Conn_IPMC_142' IPMC-142 # MP_Fault_3 NET 'No_Conn_IPMC_143' IPMC-143 # PWR_Fault_3 NET 'No_Conn_IPMC_144' IPMC-144 # PWR_ORing_3 NET 'No_Conn_IPMC_146' IPMC-146 # PS1#_5 NET 'No_Conn_IPMC_147' IPMC-147 # Enable#_5 NET 'No_Conn_IPMC_148' IPMC-148 # IPMB-L_Enable_5 NET 'No_Conn_IPMC_149' IPMC-149 # MP_Enable_5 NET 'No_Conn_IPMC_150' IPMC-150 # PWR_Enable_5 NET 'No_Conn_IPMC_151' IPMC-151 # MP_Good_5 NET 'No_Conn_IPMC_152' IPMC-152 # PWR_Good_5 NET 'No_Conn_IPMC_153' IPMC-153 # MP_Fault_5 NET 'No_Conn_IPMC_154' IPMC-154 # PWR_Fault_5 NET 'No_Conn_IPMC_155' IPMC-155 # PWR_ORing_5 NET 'No_Conn_IPMC_157' IPMC-157 # PS1#_7 NET 'No_Conn_IPMC_158' IPMC-158 # Enable#_7 NET 'No_Conn_IPMC_159' IPMC-159 # IPMB-L_Enable_7 NET 'No_Conn_IPMC_160' IPMC-160 # MP_Enable_7 NET 'No_Conn_IPMC_161' IPMC-161 # PWR_Enable_7 NET 'No_Conn_IPMC_162' IPMC-162 # MP_Good_7 NET 'No_Conn_IPMC_163' IPMC-163 # PWR_Good_7 NET 'No_Conn_IPMC_164' IPMC-164 # MP_Fault_7 NET 'No_Conn_IPMC_165' IPMC-165 # PWR_Fault_7 NET 'No_Conn_IPMC_166' IPMC-166 # PWR_ORing_7 NET 'No_Conn_IPMC_168' IPMC-168 # IPMB-L_SCL NET 'No_Conn_IPMC_169' IPMC-169 # IPMB-L_SDA NET 'No_Conn_IPMC_186' IPMC-186 # IPM_IO_2 NET 'No_Conn_IPMC_187' IPMC-187 # IPM_IO_3 NET 'No_Conn_IPMC_188' IPMC-188 # IPM_IO_6 NET 'No_Conn_IPMC_189' IPMC-189 # IPM_IO_7 NET 'No_Conn_IPMC_191' IPMC-191 # IPM_IO_10 NET 'No_Conn_IPMC_192' IPMC-192 # IPM_IO_11 NET 'No_Conn_IPMC_194' IPMC-194 # IPM_IO_14 NET 'No_Conn_IPMC_195' IPMC-195 # IPM_IO_15 NET 'No_Conn_IPMC_209' IPMC-209 # IPM_IO_18 NET 'No_Conn_IPMC_210' IPMC-210 # IPM_IO_19 NET 'No_Conn_IPMC_212' IPMC-212 # IPM_IO_21 NET 'No_Conn_IPMC_213' IPMC-213 # IPM_IO_23 NET 'No_Conn_IPMC_214' IPMC-214 # IPM_IO_25 NET 'No_Conn_IPMC_215' IPMC-215 # IPM_IO_27 NET 'No_Conn_IPMC_216' IPMC-216 # IPM_IO_29 NET 'No_Conn_IPMC_217' IPMC-217 # IPM_IO_31 NET 'No_Conn_IPMC_218' IPMC-218 # IPM_IO_33 NET 'No_Conn_IPMC_223' IPMC-223 # Ext_RST_n NET 'No_Conn_IPMC_228' IPMC-228 # PowerGood_A NET 'No_Conn_IPMC_229' IPMC-229 # PowerGood_B NET 'No_Conn_IPMC_231' IPMC-231 # Master_TCK NET 'No_Conn_IPMC_232' IPMC-232 # Master_TDI NET 'No_Conn_IPMC_234' IPMC-234 # TCK NET 'No_Conn_IPMC_235' IPMC-235 # TDI # # IPMC Socket Mechanical Mounting Pads # NET 'No_Conn_IPMC_MECH1' IPMC-MECH1 NET 'No_Conn_IPMC_MECH2' IPMC-MECH2 NET 'No_Conn_IPMC_MECH3' IPMC-MECH3 NET 'No_Conn_IPMC_MECH4' IPMC-MECH4 # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #1/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #1 # # The components in TOP side Channel #1 MGT Fanout are: # # U401 NB7VQ14M 4 way fanout chip # # C401:C404 100 nFd 0201 Output DC Blocking caps # # C405 10 nFd 0402 VRef Input ByPass cap # # C406 47 nFd 0402 Fanout VCC ByPass cap # C407 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U401-8 U401-13 NET 'FAN_1V8' C406-2 C407-2 NET 'GROUND' U401-16 NET 'GROUND' C406-1 C407-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_1' U401-2 U401-3 NET 'MGT_FO_CMR_CH_1' C405-1 NET 'GROUND' C405-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_1_IN_DIR' U401-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_IN_CMP' U401-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_1_OCP_ROD_DIR' U401-10 C403-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OCP_ROD_CMP' U401-9 C404-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OCP_HUB_DIR' U401-12 C401-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OCP_HUB_CMP' U401-11 C402-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_1_OUT_ROD_DIR' C403-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_ROD_CMP' C404-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_HUB_DIR' C401-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_HUB_CMP' C402-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_1_Pin_6' U401-6 NET 'No_Conn_FO_CH_1_Pin_7' U401-7 NET 'No_Conn_FO_CH_1_Pin_14' U401-14 NET 'No_Conn_FO_CH_1_Pin_15' U401-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_1_OUT_ROD_DIR' DPV403-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_ROD_CMP' DPV403-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV403-1 DPV403-4 NET 'MGT_FO_CH_1_IN_DIR' DPV401-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_IN_CMP' DPV401-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV401-1 # # MGT FanOut Channel #2 # # # The components in BOTTOM side Channel #2 MGT Fanout are: # # U402 NB7VQ14M 4 way fanout chip # # C408:C411 100 nFd 0201 Output DC Blocking caps # # C412 10 nFd 0402 VRef Input ByPass cap # # C413 47 nFd 0402 Fanout VCC ByPass cap # C414 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U402-8 U402-13 NET 'FAN_1V8' C413-2 C414-1 NET 'GROUND' U402-16 NET 'GROUND' C413-1 C414-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_2' U402-2 U402-3 NET 'MGT_FO_CMR_CH_2' C412-1 NET 'GROUND' C412-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_2_IN_DIR' U402-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_IN_CMP' U402-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_2_OCP_HUB_DIR' U402-10 C410-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OCP_HUB_CMP' U402-9 C411-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OCP_ROD_DIR' U402-12 C408-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OCP_ROD_CMP' U402-11 C409-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_2_OUT_HUB_DIR' C410-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_HUB_CMP' C411-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_ROD_DIR' C408-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_ROD_CMP' C409-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_2_Pin_6' U402-6 NET 'No_Conn_FO_CH_2_Pin_7' U402-7 NET 'No_Conn_FO_CH_2_Pin_14' U402-14 NET 'No_Conn_FO_CH_2_Pin_15' U402-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_2_OUT_ROD_DIR' DPV406-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_ROD_CMP' DPV406-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV406-1 DPV406-4 NET 'MGT_FO_CH_2_OUT_HUB_DIR' DPV405-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_HUB_CMP' DPV405-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV405-1 NET 'MGT_FO_CH_2_IN_DIR' DPV404-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_IN_CMP' DPV404-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV404-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #2/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #3 # # The components in TOP side Channel #3 MGT Fanout are: # # U403 NB7VQ14M 4 way fanout chip # # C415:C418 100 nFd 0201 Output DC Blocking caps # # C419 10 nFd 0402 VRef Input ByPass cap # # C420 47 nFd 0402 Fanout VCC ByPass cap # C421 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U403-8 U403-13 NET 'FAN_1V8' C420-2 C421-2 NET 'GROUND' U403-16 NET 'GROUND' C420-1 C421-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_3' U403-2 U403-3 NET 'MGT_FO_CMR_CH_3' C419-1 NET 'GROUND' C419-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_3_IN_DIR' U403-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_IN_CMP' U403-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_3_OCP_ROD_DIR' U403-10 C417-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OCP_ROD_CMP' U403-9 C418-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OCP_HUB_DIR' U403-12 C415-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OCP_HUB_CMP' U403-11 C416-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_3_OUT_ROD_DIR' C417-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_ROD_CMP' C418-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_HUB_DIR' C415-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_HUB_CMP' C416-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_3_Pin_6' U403-6 NET 'No_Conn_FO_CH_3_Pin_7' U403-7 NET 'No_Conn_FO_CH_3_Pin_14' U403-14 NET 'No_Conn_FO_CH_3_Pin_15' U403-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_3_OUT_ROD_DIR' DPV409-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_ROD_CMP' DPV409-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV409-1 DPV409-4 NET 'MGT_FO_CH_3_OUT_HUB_DIR' DPV408-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_HUB_CMP' DPV408-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV408-1 NET 'MGT_FO_CH_3_IN_DIR' DPV407-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_IN_CMP' DPV407-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV407-1 # # MGT FanOut Channel #4 # # # The components in BOTTOM side Channel #4 MGT Fanout are: # # U404 NB7VQ14M 4 way fanout chip # # C422:C425 100 nFd 0201 Output DC Blocking caps # # C426 10 nFd 0402 VRef Input ByPass cap # # C427 47 nFd 0402 Fanout VCC ByPass cap # C428 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U404-8 U404-13 NET 'FAN_1V8' C427-2 C428-1 NET 'GROUND' U404-16 NET 'GROUND' C427-1 C428-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_4' U404-2 U404-3 NET 'MGT_FO_CMR_CH_4' C426-1 NET 'GROUND' C426-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_4_IN_DIR' U404-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_IN_CMP' U404-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_4_OCP_HUB_DIR' U404-10 C424-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OCP_HUB_CMP' U404-9 C425-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OCP_ROD_DIR' U404-12 C422-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OCP_ROD_CMP' U404-11 C423-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_4_OUT_HUB_DIR' C424-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_HUB_CMP' C425-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_ROD_DIR' C422-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_ROD_CMP' C423-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_4_Pin_6' U404-6 NET 'No_Conn_FO_CH_4_Pin_7' U404-7 NET 'No_Conn_FO_CH_4_Pin_14' U404-14 NET 'No_Conn_FO_CH_4_Pin_15' U404-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_4_OUT_ROD_DIR' DPV412-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_ROD_CMP' DPV412-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV412-1 DPV412-4 NET 'MGT_FO_CH_4_OUT_HUB_DIR' DPV411-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_HUB_CMP' DPV411-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV411-1 NET 'MGT_FO_CH_4_IN_DIR' DPV410-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_IN_CMP' DPV410-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV410-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #3/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #5 # # The components in TOP side Channel #5 MGT Fanout are: # # U405 NB7VQ14M 4 way fanout chip # # C429:C432 100 nFd 0201 Output DC Blocking caps # # C433 10 nFd 0402 VRef Input ByPass cap # # C434 47 nFd 0402 Fanout VCC ByPass cap # C435 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U405-8 U405-13 NET 'FAN_1V8' C434-2 C435-2 NET 'GROUND' U405-16 NET 'GROUND' C434-1 C435-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_5' U405-2 U405-3 NET 'MGT_FO_CMR_CH_5' C433-1 NET 'GROUND' C433-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_5_IN_DIR' U405-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_IN_CMP' U405-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_5_OCP_ROD_DIR' U405-10 C431-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OCP_ROD_CMP' U405-9 C432-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OCP_HUB_DIR' U405-12 C429-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OCP_HUB_CMP' U405-11 C430-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_5_OUT_ROD_DIR' C431-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_ROD_CMP' C432-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_HUB_DIR' C429-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_HUB_CMP' C430-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_5_Pin_6' U405-6 NET 'No_Conn_FO_CH_5_Pin_7' U405-7 NET 'No_Conn_FO_CH_5_Pin_14' U405-14 NET 'No_Conn_FO_CH_5_Pin_15' U405-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_5_OUT_ROD_DIR' DPV415-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_ROD_CMP' DPV415-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV415-1 DPV415-4 NET 'MGT_FO_CH_5_OUT_HUB_DIR' DPV414-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_HUB_CMP' DPV414-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV414-1 NET 'MGT_FO_CH_5_IN_DIR' DPV413-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_IN_CMP' DPV413-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV413-1 # # MGT FanOut Channel #6 # # # The components in BOTTOM side Channel #6 MGT Fanout are: # # U406 NB7VQ14M 4 way fanout chip # # C436:C439 100 nFd 0201 Output DC Blocking caps # # C440 10 nFd 0402 VRef Input ByPass cap # # C441 47 nFd 0402 Fanout VCC ByPass cap # C442 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U406-8 U406-13 NET 'FAN_1V8' C441-2 C442-1 NET 'GROUND' U406-16 NET 'GROUND' C441-1 C442-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_6' U406-2 U406-3 NET 'MGT_FO_CMR_CH_6' C440-1 NET 'GROUND' C440-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_6_IN_DIR' U406-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_IN_CMP' U406-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_6_OCP_HUB_DIR' U406-10 C438-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OCP_HUB_CMP' U406-9 C439-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OCP_ROD_DIR' U406-12 C436-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OCP_ROD_CMP' U406-11 C437-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_6_OUT_HUB_DIR' C438-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_HUB_CMP' C439-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_ROD_DIR' C436-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_ROD_CMP' C437-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_6_Pin_6' U406-6 NET 'No_Conn_FO_CH_6_Pin_7' U406-7 NET 'No_Conn_FO_CH_6_Pin_14' U406-14 NET 'No_Conn_FO_CH_6_Pin_15' U406-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_6_OUT_ROD_DIR' DPV418-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_ROD_CMP' DPV418-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV418-1 DPV418-4 NET 'MGT_FO_CH_6_OUT_HUB_DIR' DPV417-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_HUB_CMP' DPV417-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV417-1 NET 'MGT_FO_CH_6_IN_DIR' DPV416-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_IN_CMP' DPV416-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV416-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #4/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #7 # # The components in TOP side Channel #7 MGT Fanout are: # # U407 NB7VQ14M 4 way fanout chip # # C443:C446 100 nFd 0201 Output DC Blocking caps # # C447 10 nFd 0402 VRef Input ByPass cap # # C448 47 nFd 0402 Fanout VCC ByPass cap # C449 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U407-8 U407-13 NET 'FAN_1V8' C448-2 C449-2 NET 'GROUND' U407-16 NET 'GROUND' C448-1 C449-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_7' U407-2 U407-3 NET 'MGT_FO_CMR_CH_7' C447-1 NET 'GROUND' C447-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_7_IN_DIR' U407-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_IN_CMP' U407-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_7_OCP_ROD_DIR' U407-10 C445-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OCP_ROD_CMP' U407-9 C446-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OCP_HUB_DIR' U407-12 C443-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OCP_HUB_CMP' U407-11 C444-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_7_OUT_ROD_DIR' C445-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_ROD_CMP' C446-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_HUB_DIR' C443-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_HUB_CMP' C444-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_7_Pin_6' U407-6 NET 'No_Conn_FO_CH_7_Pin_7' U407-7 NET 'No_Conn_FO_CH_7_Pin_14' U407-14 NET 'No_Conn_FO_CH_7_Pin_15' U407-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_7_OUT_ROD_DIR' DPV421-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_ROD_CMP' DPV421-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV421-1 DPV421-4 NET 'MGT_FO_CH_7_OUT_HUB_DIR' DPV420-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_HUB_CMP' DPV420-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV420-1 NET 'MGT_FO_CH_7_IN_DIR' DPV419-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_IN_CMP' DPV419-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV419-1 # # MGT FanOut Channel #8 # # # The components in BOTTOM side Channel #8 MGT Fanout are: # # U408 NB7VQ14M 4 way fanout chip # # C450:C453 100 nFd 0201 Output DC Blocking caps # # C454 10 nFd 0402 VRef Input ByPass cap # # C455 47 nFd 0402 Fanout VCC ByPass cap # C456 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U408-8 U408-13 NET 'FAN_1V8' C455-2 C456-1 NET 'GROUND' U408-16 NET 'GROUND' C455-1 C456-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_8' U408-2 U408-3 NET 'MGT_FO_CMR_CH_8' C454-1 NET 'GROUND' C454-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_8_IN_DIR' U408-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_IN_CMP' U408-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_8_OCP_HUB_DIR' U408-10 C452-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OCP_HUB_CMP' U408-9 C453-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OCP_ROD_DIR' U408-12 C450-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OCP_ROD_CMP' U408-11 C451-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_8_OUT_HUB_DIR' C452-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_HUB_CMP' C453-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_ROD_DIR' C450-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_ROD_CMP' C451-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_8_Pin_6' U408-6 NET 'No_Conn_FO_CH_8_Pin_7' U408-7 NET 'No_Conn_FO_CH_8_Pin_14' U408-14 NET 'No_Conn_FO_CH_8_Pin_15' U408-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_8_OUT_ROD_DIR' DPV424-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_ROD_CMP' DPV424-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV424-1 DPV424-4 NET 'MGT_FO_CH_8_OUT_HUB_DIR' DPV423-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_HUB_CMP' DPV423-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV423-1 NET 'MGT_FO_CH_8_IN_DIR' DPV422-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_IN_CMP' DPV422-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV422-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #5/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #9 # # The components in TOP side Channel #9 MGT Fanout are: # # U409 NB7VQ14M 4 way fanout chip # # C457:C460 100 nFd 0201 Output DC Blocking caps # # C461 10 nFd 0402 VRef Input ByPass cap # # C462 47 nFd 0402 Fanout VCC ByPass cap # C463 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U409-8 U409-13 NET 'FAN_1V8' C462-2 C463-2 NET 'GROUND' U409-16 NET 'GROUND' C462-1 C463-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_9' U409-2 U409-3 NET 'MGT_FO_CMR_CH_9' C461-1 NET 'GROUND' C461-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_9_IN_DIR' U409-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_IN_CMP' U409-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_9_OCP_ROD_DIR' U409-10 C459-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OCP_ROD_CMP' U409-9 C460-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OCP_HUB_DIR' U409-12 C457-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OCP_HUB_CMP' U409-11 C458-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_9_OUT_ROD_DIR' C459-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_ROD_CMP' C460-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_HUB_DIR' C457-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_HUB_CMP' C458-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_9_Pin_6' U409-6 NET 'No_Conn_FO_CH_9_Pin_7' U409-7 NET 'No_Conn_FO_CH_9_Pin_14' U409-14 NET 'No_Conn_FO_CH_9_Pin_15' U409-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_9_OUT_ROD_DIR' DPV427-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_ROD_CMP' DPV427-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV427-1 DPV427-4 NET 'MGT_FO_CH_9_IN_DIR' DPV425-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_IN_CMP' DPV425-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV425-1 # # MGT FanOut Channel #10 # # # The components in BOTTOM side Channel #10 MGT Fanout are: # # U410 NB7VQ14M 4 way fanout chip # # C464:C467 100 nFd 0201 Output DC Blocking caps # # C468 10 nFd 0402 VRef Input ByPass cap # # C469 47 nFd 0402 Fanout VCC ByPass cap # C470 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U410-8 U410-13 NET 'FAN_1V8' C469-2 C470-1 NET 'GROUND' U410-16 NET 'GROUND' C469-1 C470-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_10' U410-2 U410-3 NET 'MGT_FO_CMR_CH_10' C468-1 NET 'GROUND' C468-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_10_IN_DIR' U410-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_IN_CMP' U410-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_10_OCP_HUB_DIR' U410-10 C466-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OCP_HUB_CMP' U410-9 C467-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OCP_ROD_DIR' U410-12 C464-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OCP_ROD_CMP' U410-11 C465-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_10_OUT_HUB_DIR' C466-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_HUB_CMP' C467-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_ROD_DIR' C464-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_ROD_CMP' C465-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_10_Pin_6' U410-6 NET 'No_Conn_FO_CH_10_Pin_7' U410-7 NET 'No_Conn_FO_CH_10_Pin_14' U410-14 NET 'No_Conn_FO_CH_10_Pin_15' U410-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_10_OUT_ROD_DIR' DPV430-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_ROD_CMP' DPV430-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV430-1 DPV430-4 NET 'MGT_FO_CH_10_OUT_HUB_DIR' DPV429-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_HUB_CMP' DPV429-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV429-1 NET 'MGT_FO_CH_10_IN_DIR' DPV428-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_IN_CMP' DPV428-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV428-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #6/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #11 # # The components in TOP side Channel #11 MGT Fanout are: # # U411 NB7VQ14M 4 way fanout chip # # C471:C474 100 nFd 0201 Output DC Blocking caps # # C475 10 nFd 0402 VRef Input ByPass cap # # C476 47 nFd 0402 Fanout VCC ByPass cap # C477 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U411-8 U411-13 NET 'FAN_1V8' C476-2 C477-2 NET 'GROUND' U411-16 NET 'GROUND' C476-1 C477-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_11' U411-2 U411-3 NET 'MGT_FO_CMR_CH_11' C475-1 NET 'GROUND' C475-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_11_IN_DIR' U411-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_IN_CMP' U411-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_11_OCP_ROD_DIR' U411-10 C473-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OCP_ROD_CMP' U411-9 C474-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OCP_HUB_DIR' U411-12 C471-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OCP_HUB_CMP' U411-11 C472-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_11_OUT_ROD_DIR' C473-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_ROD_CMP' C474-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_HUB_DIR' C471-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_HUB_CMP' C472-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_11_Pin_6' U411-6 NET 'No_Conn_FO_CH_11_Pin_7' U411-7 NET 'No_Conn_FO_CH_11_Pin_14' U411-14 NET 'No_Conn_FO_CH_11_Pin_15' U411-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_11_OUT_ROD_DIR' DPV433-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_ROD_CMP' DPV433-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV433-1 DPV433-4 NET 'MGT_FO_CH_11_OUT_HUB_DIR' DPV432-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_HUB_CMP' DPV432-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV432-1 NET 'MGT_FO_CH_11_IN_DIR' DPV431-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_IN_CMP' DPV431-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV431-1 # # MGT FanOut Channel #12 # # # The components in BOTTOM side Channel #12 MGT Fanout are: # # U412 NB7VQ14M 4 way fanout chip # # C478:C481 100 nFd 0201 Output DC Blocking caps # # C482 10 nFd 0402 VRef Input ByPass cap # # C483 47 nFd 0402 Fanout VCC ByPass cap # C484 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U412-8 U412-13 NET 'FAN_1V8' C483-2 C484-1 NET 'GROUND' U412-16 NET 'GROUND' C483-1 C484-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_12' U412-2 U412-3 NET 'MGT_FO_CMR_CH_12' C482-1 NET 'GROUND' C482-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_12_IN_DIR' U412-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_IN_CMP' U412-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_12_OCP_HUB_DIR' U412-10 C480-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OCP_HUB_CMP' U412-9 C481-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OCP_ROD_DIR' U412-12 C478-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OCP_ROD_CMP' U412-11 C479-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_12_OUT_HUB_DIR' C480-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_HUB_CMP' C481-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_ROD_DIR' C478-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_ROD_CMP' C479-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_12_Pin_6' U412-6 NET 'No_Conn_FO_CH_12_Pin_7' U412-7 NET 'No_Conn_FO_CH_12_Pin_14' U412-14 NET 'No_Conn_FO_CH_12_Pin_15' U412-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_12_OUT_ROD_DIR' DPV436-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_ROD_CMP' DPV436-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV436-1 DPV436-4 NET 'MGT_FO_CH_12_OUT_HUB_DIR' DPV435-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_HUB_CMP' DPV435-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV435-1 NET 'MGT_FO_CH_12_IN_DIR' DPV434-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_IN_CMP' DPV434-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV434-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #7/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #13 # # The components in TOP side Channel #13 MGT Fanout are: # # U413 NB7VQ14M 4 way fanout chip # # C485:C488 100 nFd 0201 Output DC Blocking caps # # C489 10 nFd 0402 VRef Input ByPass cap # # C490 47 nFd 0402 Fanout VCC ByPass cap # C491 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U413-8 U413-13 NET 'FAN_1V8' C490-2 C491-2 NET 'GROUND' U413-16 NET 'GROUND' C490-1 C491-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_13' U413-2 U413-3 NET 'MGT_FO_CMR_CH_13' C489-1 NET 'GROUND' C489-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_13_IN_DIR' U413-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_IN_CMP' U413-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_13_OCP_ROD_DIR' U413-10 C487-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OCP_ROD_CMP' U413-9 C488-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OCP_HUB_DIR' U413-12 C485-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OCP_HUB_CMP' U413-11 C486-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_13_OUT_ROD_DIR' C487-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_ROD_CMP' C488-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_HUB_DIR' C485-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_HUB_CMP' C486-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_13_Pin_6' U413-6 NET 'No_Conn_FO_CH_13_Pin_7' U413-7 NET 'No_Conn_FO_CH_13_Pin_14' U413-14 NET 'No_Conn_FO_CH_13_Pin_15' U413-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_13_OUT_ROD_DIR' DPV439-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_ROD_CMP' DPV439-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV439-1 DPV439-4 NET 'MGT_FO_CH_13_OUT_HUB_DIR' DPV438-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_HUB_CMP' DPV438-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV438-1 NET 'MGT_FO_CH_13_IN_DIR' DPV437-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_IN_CMP' DPV437-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV437-1 # # MGT FanOut Channel #14 # # # The components in BOTTOM side Channel #14 MGT Fanout are: # # U414 NB7VQ14M 4 way fanout chip # # C492:C495 100 nFd 0201 Output DC Blocking caps # # C496 10 nFd 0402 VRef Input ByPass cap # # C497 47 nFd 0402 Fanout VCC ByPass cap # C498 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U414-8 U414-13 NET 'FAN_1V8' C497-2 C498-1 NET 'GROUND' U414-16 NET 'GROUND' C497-1 C498-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_14' U414-2 U414-3 NET 'MGT_FO_CMR_CH_14' C496-1 NET 'GROUND' C496-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_14_IN_DIR' U414-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_IN_CMP' U414-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_14_OCP_HUB_DIR' U414-10 C494-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OCP_HUB_CMP' U414-9 C495-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OCP_ROD_DIR' U414-12 C492-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OCP_ROD_CMP' U414-11 C493-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_14_OUT_HUB_DIR' C494-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_HUB_CMP' C495-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_ROD_DIR' C492-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_ROD_CMP' C493-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_14_Pin_6' U414-6 NET 'No_Conn_FO_CH_14_Pin_7' U414-7 NET 'No_Conn_FO_CH_14_Pin_14' U414-14 NET 'No_Conn_FO_CH_14_Pin_15' U414-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_14_OUT_ROD_DIR' DPV442-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_ROD_CMP' DPV442-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV442-1 DPV442-4 NET 'MGT_FO_CH_14_OUT_HUB_DIR' DPV441-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_HUB_CMP' DPV441-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV441-1 NET 'MGT_FO_CH_14_IN_DIR' DPV440-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_IN_CMP' DPV440-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV440-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #8/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #15 # # The components in TOP side Channel #15 MGT Fanout are: # # U415 NB7VQ14M 4 way fanout chip # # C499:C502 100 nFd 0201 Output DC Blocking caps # # C503 10 nFd 0402 VRef Input ByPass cap # # C504 47 nFd 0402 Fanout VCC ByPass cap # C505 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U415-8 U415-13 NET 'FAN_1V8' C504-2 C505-2 NET 'GROUND' U415-16 NET 'GROUND' C504-1 C505-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_15' U415-2 U415-3 NET 'MGT_FO_CMR_CH_15' C503-1 NET 'GROUND' C503-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_15_IN_DIR' U415-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_IN_CMP' U415-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_15_OCP_ROD_DIR' U415-10 C501-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OCP_ROD_CMP' U415-9 C502-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OCP_HUB_DIR' U415-12 C499-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OCP_HUB_CMP' U415-11 C500-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_15_OUT_ROD_DIR' C501-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_ROD_CMP' C502-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_HUB_DIR' C499-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_HUB_CMP' C500-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_15_Pin_6' U415-6 NET 'No_Conn_FO_CH_15_Pin_7' U415-7 NET 'No_Conn_FO_CH_15_Pin_14' U415-14 NET 'No_Conn_FO_CH_15_Pin_15' U415-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_15_OUT_ROD_DIR' DPV445-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_ROD_CMP' DPV445-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV445-1 DPV445-4 NET 'MGT_FO_CH_15_OUT_HUB_DIR' DPV444-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_HUB_CMP' DPV444-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV444-1 NET 'MGT_FO_CH_15_IN_DIR' DPV443-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_IN_CMP' DPV443-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV443-1 # # MGT FanOut Channel #16 # # # The components in BOTTOM side Channel #16 MGT Fanout are: # # U416 NB7VQ14M 4 way fanout chip # # C506:C509 100 nFd 0201 Output DC Blocking caps # # C510 10 nFd 0402 VRef Input ByPass cap # # C511 47 nFd 0402 Fanout VCC ByPass cap # C512 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U416-8 U416-13 NET 'FAN_1V8' C511-2 C512-1 NET 'GROUND' U416-16 NET 'GROUND' C511-1 C512-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_16' U416-2 U416-3 NET 'MGT_FO_CMR_CH_16' C510-1 NET 'GROUND' C510-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_16_IN_DIR' U416-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_IN_CMP' U416-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_16_OCP_HUB_DIR' U416-10 C508-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OCP_HUB_CMP' U416-9 C509-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OCP_ROD_DIR' U416-12 C506-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OCP_ROD_CMP' U416-11 C507-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_16_OUT_HUB_DIR' C508-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_HUB_CMP' C509-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_ROD_DIR' C506-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_ROD_CMP' C507-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_16_Pin_6' U416-6 NET 'No_Conn_FO_CH_16_Pin_7' U416-7 NET 'No_Conn_FO_CH_16_Pin_14' U416-14 NET 'No_Conn_FO_CH_16_Pin_15' U416-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_16_OUT_ROD_DIR' DPV448-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_ROD_CMP' DPV448-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV448-1 DPV448-4 NET 'MGT_FO_CH_16_OUT_HUB_DIR' DPV447-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_HUB_CMP' DPV447-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV447-1 NET 'MGT_FO_CH_16_IN_DIR' DPV446-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_IN_CMP' DPV446-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV446-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #9/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #17 # # The components in TOP side Channel #17 MGT Fanout are: # # U417 NB7VQ14M 4 way fanout chip # # C513:C516 100 nFd 0201 Output DC Blocking caps # # C517 10 nFd 0402 VRef Input ByPass cap # # C518 47 nFd 0402 Fanout VCC ByPass cap # C519 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U417-8 U417-13 NET 'FAN_1V8' C518-2 C519-2 NET 'GROUND' U417-16 NET 'GROUND' C518-1 C519-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_17' U417-2 U417-3 NET 'MGT_FO_CMR_CH_17' C517-1 NET 'GROUND' C517-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_17_IN_DIR' U417-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_IN_CMP' U417-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_17_OCP_ROD_DIR' U417-10 C515-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OCP_ROD_CMP' U417-9 C516-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OCP_HUB_DIR' U417-12 C513-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OCP_HUB_CMP' U417-11 C514-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_17_OUT_ROD_DIR' C515-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_ROD_CMP' C516-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_HUB_DIR' C513-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_HUB_CMP' C514-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_17_Pin_6' U417-6 NET 'No_Conn_FO_CH_17_Pin_7' U417-7 NET 'No_Conn_FO_CH_17_Pin_14' U417-14 NET 'No_Conn_FO_CH_17_Pin_15' U417-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_17_OUT_ROD_DIR' DPV451-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_ROD_CMP' DPV451-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV451-1 DPV451-4 NET 'MGT_FO_CH_17_IN_DIR' DPV449-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_IN_CMP' DPV449-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV449-1 # # MGT FanOut Channel #18 # # # The components in BOTTOM side Channel #18 MGT Fanout are: # # U418 NB7VQ14M 4 way fanout chip # # C520:C523 100 nFd 0201 Output DC Blocking caps # # C524 10 nFd 0402 VRef Input ByPass cap # # C525 47 nFd 0402 Fanout VCC ByPass cap # C526 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U418-8 U418-13 NET 'FAN_1V8' C525-2 C526-1 NET 'GROUND' U418-16 NET 'GROUND' C525-1 C526-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_18' U418-2 U418-3 NET 'MGT_FO_CMR_CH_18' C524-1 NET 'GROUND' C524-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_18_IN_DIR' U418-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_IN_CMP' U418-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_18_OCP_HUB_DIR' U418-10 C522-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OCP_HUB_CMP' U418-9 C523-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OCP_ROD_DIR' U418-12 C520-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OCP_ROD_CMP' U418-11 C521-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_18_OUT_HUB_DIR' C522-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_HUB_CMP' C523-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_ROD_DIR' C520-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_ROD_CMP' C521-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_18_Pin_6' U418-6 NET 'No_Conn_FO_CH_18_Pin_7' U418-7 NET 'No_Conn_FO_CH_18_Pin_14' U418-14 NET 'No_Conn_FO_CH_18_Pin_15' U418-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_18_OUT_ROD_DIR' DPV454-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_ROD_CMP' DPV454-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV454-1 DPV454-4 NET 'MGT_FO_CH_18_OUT_HUB_DIR' DPV453-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_HUB_CMP' DPV453-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV453-1 NET 'MGT_FO_CH_18_IN_DIR' DPV452-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_IN_CMP' DPV452-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV452-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #10/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #19 # # The components in TOP side Channel #19 MGT Fanout are: # # U419 NB7VQ14M 4 way fanout chip # # C527:C530 100 nFd 0201 Output DC Blocking caps # # C531 10 nFd 0402 VRef Input ByPass cap # # C532 47 nFd 0402 Fanout VCC ByPass cap # C533 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U419-8 U419-13 NET 'FAN_1V8' C532-2 C533-2 NET 'GROUND' U419-16 NET 'GROUND' C532-1 C533-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_19' U419-2 U419-3 NET 'MGT_FO_CMR_CH_19' C531-1 NET 'GROUND' C531-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_19_IN_DIR' U419-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_IN_CMP' U419-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_19_OCP_ROD_DIR' U419-10 C529-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OCP_ROD_CMP' U419-9 C530-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OCP_HUB_DIR' U419-12 C527-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OCP_HUB_CMP' U419-11 C528-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_19_OUT_ROD_DIR' C529-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_ROD_CMP' C530-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_HUB_DIR' C527-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_HUB_CMP' C528-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_19_Pin_6' U419-6 NET 'No_Conn_FO_CH_19_Pin_7' U419-7 NET 'No_Conn_FO_CH_19_Pin_14' U419-14 NET 'No_Conn_FO_CH_19_Pin_15' U419-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_19_OUT_ROD_DIR' DPV457-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_ROD_CMP' DPV457-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV457-1 DPV457-4 NET 'MGT_FO_CH_19_OUT_HUB_DIR' DPV456-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_HUB_CMP' DPV456-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV456-1 NET 'MGT_FO_CH_19_IN_DIR' DPV455-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_IN_CMP' DPV455-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV455-1 # # MGT FanOut Channel #20 # # # The components in BOTTOM side Channel #20 MGT Fanout are: # # U420 NB7VQ14M 4 way fanout chip # # C534:C537 100 nFd 0201 Output DC Blocking caps # # C538 10 nFd 0402 VRef Input ByPass cap # # C539 47 nFd 0402 Fanout VCC ByPass cap # C540 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U420-8 U420-13 NET 'FAN_1V8' C539-2 C540-1 NET 'GROUND' U420-16 NET 'GROUND' C539-1 C540-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_20' U420-2 U420-3 NET 'MGT_FO_CMR_CH_20' C538-1 NET 'GROUND' C538-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_20_IN_DIR' U420-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_IN_CMP' U420-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_20_OCP_HUB_DIR' U420-10 C536-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OCP_HUB_CMP' U420-9 C537-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OCP_ROD_DIR' U420-12 C534-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OCP_ROD_CMP' U420-11 C535-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_20_OUT_HUB_DIR' C536-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_HUB_CMP' C537-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_ROD_DIR' C534-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_ROD_CMP' C535-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_20_Pin_6' U420-6 NET 'No_Conn_FO_CH_20_Pin_7' U420-7 NET 'No_Conn_FO_CH_20_Pin_14' U420-14 NET 'No_Conn_FO_CH_20_Pin_15' U420-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_20_OUT_ROD_DIR' DPV460-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_ROD_CMP' DPV460-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV460-1 DPV460-4 NET 'MGT_FO_CH_20_OUT_HUB_DIR' DPV459-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_HUB_CMP' DPV459-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV459-1 NET 'MGT_FO_CH_20_IN_DIR' DPV458-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_IN_CMP' DPV458-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV458-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #11/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #21 # # The components in TOP side Channel #21 MGT Fanout are: # # U421 NB7VQ14M 4 way fanout chip # # C541:C544 100 nFd 0201 Output DC Blocking caps # # C545 10 nFd 0402 VRef Input ByPass cap # # C546 47 nFd 0402 Fanout VCC ByPass cap # C547 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U421-8 U421-13 NET 'FAN_1V8' C546-2 C547-2 NET 'GROUND' U421-16 NET 'GROUND' C546-1 C547-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_21' U421-2 U421-3 NET 'MGT_FO_CMR_CH_21' C545-1 NET 'GROUND' C545-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_21_IN_DIR' U421-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_IN_CMP' U421-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_21_OCP_ROD_DIR' U421-10 C543-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OCP_ROD_CMP' U421-9 C544-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OCP_HUB_DIR' U421-12 C541-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OCP_HUB_CMP' U421-11 C542-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_21_OUT_ROD_DIR' C543-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_ROD_CMP' C544-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_HUB_DIR' C541-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_HUB_CMP' C542-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_21_Pin_6' U421-6 NET 'No_Conn_FO_CH_21_Pin_7' U421-7 NET 'No_Conn_FO_CH_21_Pin_14' U421-14 NET 'No_Conn_FO_CH_21_Pin_15' U421-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_21_OUT_ROD_DIR' DPV463-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_ROD_CMP' DPV463-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV463-1 DPV463-4 NET 'MGT_FO_CH_21_OUT_HUB_DIR' DPV462-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_HUB_CMP' DPV462-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV462-1 NET 'MGT_FO_CH_21_IN_DIR' DPV461-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_IN_CMP' DPV461-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV461-1 # # MGT FanOut Channel #22 # # # The components in BOTTOM side Channel #22 MGT Fanout are: # # U422 NB7VQ14M 4 way fanout chip # # C548:C551 100 nFd 0201 Output DC Blocking caps # # C552 10 nFd 0402 VRef Input ByPass cap # # C553 47 nFd 0402 Fanout VCC ByPass cap # C554 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U422-8 U422-13 NET 'FAN_1V8' C553-2 C554-1 NET 'GROUND' U422-16 NET 'GROUND' C553-1 C554-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_22' U422-2 U422-3 NET 'MGT_FO_CMR_CH_22' C552-1 NET 'GROUND' C552-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_22_IN_DIR' U422-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_IN_CMP' U422-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_22_OCP_HUB_DIR' U422-10 C550-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OCP_HUB_CMP' U422-9 C551-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OCP_ROD_DIR' U422-12 C548-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OCP_ROD_CMP' U422-11 C549-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_22_OUT_HUB_DIR' C550-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_HUB_CMP' C551-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_ROD_DIR' C548-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_ROD_CMP' C549-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_22_Pin_6' U422-6 NET 'No_Conn_FO_CH_22_Pin_7' U422-7 NET 'No_Conn_FO_CH_22_Pin_14' U422-14 NET 'No_Conn_FO_CH_22_Pin_15' U422-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_22_OUT_ROD_DIR' DPV466-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_ROD_CMP' DPV466-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV466-1 DPV466-4 NET 'MGT_FO_CH_22_OUT_HUB_DIR' DPV465-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_HUB_CMP' DPV465-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV465-1 NET 'MGT_FO_CH_22_IN_DIR' DPV464-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_IN_CMP' DPV464-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV464-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #12/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #23 # # The components in TOP side Channel #23 MGT Fanout are: # # U423 NB7VQ14M 4 way fanout chip # # C555:C558 100 nFd 0201 Output DC Blocking caps # # C559 10 nFd 0402 VRef Input ByPass cap # # C560 47 nFd 0402 Fanout VCC ByPass cap # C561 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U423-8 U423-13 NET 'FAN_1V8' C560-2 C561-2 NET 'GROUND' U423-16 NET 'GROUND' C560-1 C561-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_23' U423-2 U423-3 NET 'MGT_FO_CMR_CH_23' C559-1 NET 'GROUND' C559-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_23_IN_DIR' U423-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_IN_CMP' U423-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_23_OCP_ROD_DIR' U423-10 C557-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OCP_ROD_CMP' U423-9 C558-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OCP_HUB_DIR' U423-12 C555-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OCP_HUB_CMP' U423-11 C556-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_23_OUT_ROD_DIR' C557-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_ROD_CMP' C558-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_HUB_DIR' C555-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_HUB_CMP' C556-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_23_Pin_6' U423-6 NET 'No_Conn_FO_CH_23_Pin_7' U423-7 NET 'No_Conn_FO_CH_23_Pin_14' U423-14 NET 'No_Conn_FO_CH_23_Pin_15' U423-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_23_OUT_ROD_DIR' DPV469-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_ROD_CMP' DPV469-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV469-1 DPV469-4 NET 'MGT_FO_CH_23_OUT_HUB_DIR' DPV468-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_HUB_CMP' DPV468-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV468-1 NET 'MGT_FO_CH_23_IN_DIR' DPV467-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_IN_CMP' DPV467-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV467-1 # # MGT FanOut Channel #24 # # # The components in BOTTOM side Channel #24 MGT Fanout are: # # U424 NB7VQ14M 4 way fanout chip # # C562:C565 100 nFd 0201 Output DC Blocking caps # # C566 10 nFd 0402 VRef Input ByPass cap # # C567 47 nFd 0402 Fanout VCC ByPass cap # C568 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U424-8 U424-13 NET 'FAN_1V8' C567-2 C568-1 NET 'GROUND' U424-16 NET 'GROUND' C567-1 C568-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_24' U424-2 U424-3 NET 'MGT_FO_CMR_CH_24' C566-1 NET 'GROUND' C566-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_24_IN_DIR' U424-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_IN_CMP' U424-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_24_OCP_HUB_DIR' U424-10 C564-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OCP_HUB_CMP' U424-9 C565-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OCP_ROD_DIR' U424-12 C562-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OCP_ROD_CMP' U424-11 C563-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_24_OUT_HUB_DIR' C564-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_HUB_CMP' C565-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_ROD_DIR' C562-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_ROD_CMP' C563-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_24_Pin_6' U424-6 NET 'No_Conn_FO_CH_24_Pin_7' U424-7 NET 'No_Conn_FO_CH_24_Pin_14' U424-14 NET 'No_Conn_FO_CH_24_Pin_15' U424-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_24_OUT_ROD_DIR' DPV472-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_ROD_CMP' DPV472-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV472-1 DPV472-4 NET 'MGT_FO_CH_24_OUT_HUB_DIR' DPV471-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_HUB_CMP' DPV471-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV471-1 NET 'MGT_FO_CH_24_IN_DIR' DPV470-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_IN_CMP' DPV470-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV470-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #13/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #25 # # The components in TOP side Channel #25 MGT Fanout are: # # U425 NB7VQ14M 4 way fanout chip # # C569:C572 100 nFd 0201 Output DC Blocking caps # # C573 10 nFd 0402 VRef Input ByPass cap # # C574 47 nFd 0402 Fanout VCC ByPass cap # C575 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U425-8 U425-13 NET 'FAN_1V8' C574-2 C575-2 NET 'GROUND' U425-16 NET 'GROUND' C574-1 C575-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_25' U425-2 U425-3 NET 'MGT_FO_CMR_CH_25' C573-1 NET 'GROUND' C573-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_25_IN_DIR' U425-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_IN_CMP' U425-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_25_OCP_ROD_DIR' U425-10 C571-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OCP_ROD_CMP' U425-9 C572-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OCP_HUB_DIR' U425-12 C569-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OCP_HUB_CMP' U425-11 C570-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_25_OUT_ROD_DIR' C571-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_ROD_CMP' C572-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_HUB_DIR' C569-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_HUB_CMP' C570-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_25_Pin_6' U425-6 NET 'No_Conn_FO_CH_25_Pin_7' U425-7 NET 'No_Conn_FO_CH_25_Pin_14' U425-14 NET 'No_Conn_FO_CH_25_Pin_15' U425-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_25_OUT_ROD_DIR' DPV475-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_ROD_CMP' DPV475-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV475-1 DPV475-4 NET 'MGT_FO_CH_25_IN_DIR' DPV473-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_IN_CMP' DPV473-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV473-1 # # MGT FanOut Channel #26 # # # The components in BOTTOM side Channel #26 MGT Fanout are: # # U426 NB7VQ14M 4 way fanout chip # # C576:C579 100 nFd 0201 Output DC Blocking caps # # C580 10 nFd 0402 VRef Input ByPass cap # # C581 47 nFd 0402 Fanout VCC ByPass cap # C582 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U426-8 U426-13 NET 'FAN_1V8' C581-2 C582-1 NET 'GROUND' U426-16 NET 'GROUND' C581-1 C582-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_26' U426-2 U426-3 NET 'MGT_FO_CMR_CH_26' C580-1 NET 'GROUND' C580-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_26_IN_DIR' U426-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_IN_CMP' U426-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_26_OCP_HUB_DIR' U426-10 C578-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OCP_HUB_CMP' U426-9 C579-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OCP_ROD_DIR' U426-12 C576-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OCP_ROD_CMP' U426-11 C577-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_26_OUT_HUB_DIR' C578-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_HUB_CMP' C579-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_ROD_DIR' C576-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_ROD_CMP' C577-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_26_Pin_6' U426-6 NET 'No_Conn_FO_CH_26_Pin_7' U426-7 NET 'No_Conn_FO_CH_26_Pin_14' U426-14 NET 'No_Conn_FO_CH_26_Pin_15' U426-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_26_OUT_ROD_DIR' DPV478-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_ROD_CMP' DPV478-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV478-1 DPV478-4 NET 'MGT_FO_CH_26_OUT_HUB_DIR' DPV477-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_HUB_CMP' DPV477-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV477-1 NET 'MGT_FO_CH_26_IN_DIR' DPV476-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_IN_CMP' DPV476-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV476-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #14/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #27 # # The components in TOP side Channel #27 MGT Fanout are: # # U427 NB7VQ14M 4 way fanout chip # # C583:C586 100 nFd 0201 Output DC Blocking caps # # C587 10 nFd 0402 VRef Input ByPass cap # # C588 47 nFd 0402 Fanout VCC ByPass cap # C589 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U427-8 U427-13 NET 'FAN_1V8' C588-2 C589-2 NET 'GROUND' U427-16 NET 'GROUND' C588-1 C589-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_27' U427-2 U427-3 NET 'MGT_FO_CMR_CH_27' C587-1 NET 'GROUND' C587-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_27_IN_DIR' U427-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_IN_CMP' U427-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_27_OCP_ROD_DIR' U427-10 C585-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OCP_ROD_CMP' U427-9 C586-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OCP_HUB_DIR' U427-12 C583-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OCP_HUB_CMP' U427-11 C584-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_27_OUT_ROD_DIR' C585-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_ROD_CMP' C586-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_HUB_DIR' C583-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_HUB_CMP' C584-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_27_Pin_6' U427-6 NET 'No_Conn_FO_CH_27_Pin_7' U427-7 NET 'No_Conn_FO_CH_27_Pin_14' U427-14 NET 'No_Conn_FO_CH_27_Pin_15' U427-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_27_OUT_ROD_DIR' DPV481-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_ROD_CMP' DPV481-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV481-1 DPV481-4 NET 'MGT_FO_CH_27_OUT_HUB_DIR' DPV480-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_HUB_CMP' DPV480-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV480-1 NET 'MGT_FO_CH_27_IN_DIR' DPV479-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_IN_CMP' DPV479-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV479-1 # # MGT FanOut Channel #28 # # # The components in BOTTOM side Channel #28 MGT Fanout are: # # U428 NB7VQ14M 4 way fanout chip # # C590:C593 100 nFd 0201 Output DC Blocking caps # # C594 10 nFd 0402 VRef Input ByPass cap # # C595 47 nFd 0402 Fanout VCC ByPass cap # C596 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U428-8 U428-13 NET 'FAN_1V8' C595-2 C596-1 NET 'GROUND' U428-16 NET 'GROUND' C595-1 C596-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_28' U428-2 U428-3 NET 'MGT_FO_CMR_CH_28' C594-1 NET 'GROUND' C594-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_28_IN_DIR' U428-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_IN_CMP' U428-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_28_OCP_HUB_DIR' U428-10 C592-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OCP_HUB_CMP' U428-9 C593-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OCP_ROD_DIR' U428-12 C590-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OCP_ROD_CMP' U428-11 C591-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_28_OUT_HUB_DIR' C592-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_HUB_CMP' C593-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_ROD_DIR' C590-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_ROD_CMP' C591-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_28_Pin_6' U428-6 NET 'No_Conn_FO_CH_28_Pin_7' U428-7 NET 'No_Conn_FO_CH_28_Pin_14' U428-14 NET 'No_Conn_FO_CH_28_Pin_15' U428-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_28_OUT_ROD_DIR' DPV484-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_ROD_CMP' DPV484-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV484-1 DPV484-4 NET 'MGT_FO_CH_28_OUT_HUB_DIR' DPV483-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_HUB_CMP' DPV483-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV483-1 NET 'MGT_FO_CH_28_IN_DIR' DPV482-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_IN_CMP' DPV482-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV482-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #15/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #29 # # The components in TOP side Channel #29 MGT Fanout are: # # U429 NB7VQ14M 4 way fanout chip # # C597:C600 100 nFd 0201 Output DC Blocking caps # # C601 10 nFd 0402 VRef Input ByPass cap # # C602 47 nFd 0402 Fanout VCC ByPass cap # C603 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U429-8 U429-13 NET 'FAN_1V8' C602-2 C603-2 NET 'GROUND' U429-16 NET 'GROUND' C602-1 C603-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_29' U429-2 U429-3 NET 'MGT_FO_CMR_CH_29' C601-1 NET 'GROUND' C601-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_29_IN_DIR' U429-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_IN_CMP' U429-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_29_OCP_ROD_DIR' U429-10 C599-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OCP_ROD_CMP' U429-9 C600-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OCP_HUB_DIR' U429-12 C597-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OCP_HUB_CMP' U429-11 C598-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_29_OUT_ROD_DIR' C599-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_ROD_CMP' C600-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_HUB_DIR' C597-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_HUB_CMP' C598-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_29_Pin_6' U429-6 NET 'No_Conn_FO_CH_29_Pin_7' U429-7 NET 'No_Conn_FO_CH_29_Pin_14' U429-14 NET 'No_Conn_FO_CH_29_Pin_15' U429-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_29_OUT_ROD_DIR' DPV487-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_ROD_CMP' DPV487-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV487-1 DPV487-4 NET 'MGT_FO_CH_29_OUT_HUB_DIR' DPV486-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_HUB_CMP' DPV486-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV486-1 NET 'MGT_FO_CH_29_IN_DIR' DPV485-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_IN_CMP' DPV485-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV485-1 # # MGT FanOut Channel #30 # # # The components in BOTTOM side Channel #30 MGT Fanout are: # # U430 NB7VQ14M 4 way fanout chip # # C604:C607 100 nFd 0201 Output DC Blocking caps # # C608 10 nFd 0402 VRef Input ByPass cap # # C609 47 nFd 0402 Fanout VCC ByPass cap # C610 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U430-8 U430-13 NET 'FAN_1V8' C609-2 C610-1 NET 'GROUND' U430-16 NET 'GROUND' C609-1 C610-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_30' U430-2 U430-3 NET 'MGT_FO_CMR_CH_30' C608-1 NET 'GROUND' C608-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_30_IN_DIR' U430-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_IN_CMP' U430-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_30_OCP_HUB_DIR' U430-10 C606-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OCP_HUB_CMP' U430-9 C607-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OCP_ROD_DIR' U430-12 C604-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OCP_ROD_CMP' U430-11 C605-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_30_OUT_HUB_DIR' C606-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_HUB_CMP' C607-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_ROD_DIR' C604-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_ROD_CMP' C605-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_30_Pin_6' U430-6 NET 'No_Conn_FO_CH_30_Pin_7' U430-7 NET 'No_Conn_FO_CH_30_Pin_14' U430-14 NET 'No_Conn_FO_CH_30_Pin_15' U430-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_30_OUT_ROD_DIR' DPV490-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_ROD_CMP' DPV490-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV490-1 DPV490-4 NET 'MGT_FO_CH_30_OUT_HUB_DIR' DPV489-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_HUB_CMP' DPV489-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV489-1 NET 'MGT_FO_CH_30_IN_DIR' DPV488-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_IN_CMP' DPV488-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV488-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #16/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #31 # # The components in TOP side Channel #31 MGT Fanout are: # # U431 NB7VQ14M 4 way fanout chip # # C611:C614 100 nFd 0201 Output DC Blocking caps # # C615 10 nFd 0402 VRef Input ByPass cap # # C616 47 nFd 0402 Fanout VCC ByPass cap # C617 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U431-8 U431-13 NET 'FAN_1V8' C616-2 C617-2 NET 'GROUND' U431-16 NET 'GROUND' C616-1 C617-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_31' U431-2 U431-3 NET 'MGT_FO_CMR_CH_31' C615-1 NET 'GROUND' C615-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_31_IN_DIR' U431-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_IN_CMP' U431-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_31_OCP_ROD_DIR' U431-10 C613-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OCP_ROD_CMP' U431-9 C614-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OCP_HUB_DIR' U431-12 C611-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OCP_HUB_CMP' U431-11 C612-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_31_OUT_ROD_DIR' C613-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_ROD_CMP' C614-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_HUB_DIR' C611-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_HUB_CMP' C612-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_31_Pin_6' U431-6 NET 'No_Conn_FO_CH_31_Pin_7' U431-7 NET 'No_Conn_FO_CH_31_Pin_14' U431-14 NET 'No_Conn_FO_CH_31_Pin_15' U431-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_31_OUT_ROD_DIR' DPV493-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_ROD_CMP' DPV493-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV493-1 DPV493-4 NET 'MGT_FO_CH_31_OUT_HUB_DIR' DPV492-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_HUB_CMP' DPV492-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV492-1 NET 'MGT_FO_CH_31_IN_DIR' DPV491-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_IN_CMP' DPV491-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV491-1 # # MGT FanOut Channel #32 # # # The components in BOTTOM side Channel #32 MGT Fanout are: # # U432 NB7VQ14M 4 way fanout chip # # C618:C621 100 nFd 0201 Output DC Blocking caps # # C622 10 nFd 0402 VRef Input ByPass cap # # C623 47 nFd 0402 Fanout VCC ByPass cap # C624 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U432-8 U432-13 NET 'FAN_1V8' C623-2 C624-1 NET 'GROUND' U432-16 NET 'GROUND' C623-1 C624-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_32' U432-2 U432-3 NET 'MGT_FO_CMR_CH_32' C622-1 NET 'GROUND' C622-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_32_IN_DIR' U432-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_IN_CMP' U432-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_32_OCP_HUB_DIR' U432-10 C620-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OCP_HUB_CMP' U432-9 C621-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OCP_ROD_DIR' U432-12 C618-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OCP_ROD_CMP' U432-11 C619-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_32_OUT_HUB_DIR' C620-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_HUB_CMP' C621-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_ROD_DIR' C618-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_ROD_CMP' C619-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_32_Pin_6' U432-6 NET 'No_Conn_FO_CH_32_Pin_7' U432-7 NET 'No_Conn_FO_CH_32_Pin_14' U432-14 NET 'No_Conn_FO_CH_32_Pin_15' U432-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_32_OUT_ROD_DIR' DPV496-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_ROD_CMP' DPV496-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV496-1 DPV496-4 NET 'MGT_FO_CH_32_OUT_HUB_DIR' DPV495-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_HUB_CMP' DPV495-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV495-1 NET 'MGT_FO_CH_32_IN_DIR' DPV494-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_IN_CMP' DPV494-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV494-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #17/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #33 # # The components in TOP side Channel #33 MGT Fanout are: # # U433 NB7VQ14M 4 way fanout chip # # C625:C628 100 nFd 0201 Output DC Blocking caps # # C629 10 nFd 0402 VRef Input ByPass cap # # C630 47 nFd 0402 Fanout VCC ByPass cap # C631 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U433-8 U433-13 NET 'FAN_1V8' C630-2 C631-2 NET 'GROUND' U433-16 NET 'GROUND' C630-1 C631-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_33' U433-2 U433-3 NET 'MGT_FO_CMR_CH_33' C629-1 NET 'GROUND' C629-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_33_IN_DIR' U433-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_IN_CMP' U433-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_33_OCP_ROD_DIR' U433-10 C627-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OCP_ROD_CMP' U433-9 C628-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OCP_HUB_DIR' U433-12 C625-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OCP_HUB_CMP' U433-11 C626-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_33_OUT_ROD_DIR' C627-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_ROD_CMP' C628-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_HUB_DIR' C625-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_HUB_CMP' C626-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_33_Pin_6' U433-6 NET 'No_Conn_FO_CH_33_Pin_7' U433-7 NET 'No_Conn_FO_CH_33_Pin_14' U433-14 NET 'No_Conn_FO_CH_33_Pin_15' U433-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_33_OUT_ROD_DIR' DPV499-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_ROD_CMP' DPV499-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV499-1 DPV499-4 NET 'MGT_FO_CH_33_IN_DIR' DPV497-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_IN_CMP' DPV497-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV497-1 # # MGT FanOut Channel #34 # # # The components in BOTTOM side Channel #34 MGT Fanout are: # # U434 NB7VQ14M 4 way fanout chip # # C632:C635 100 nFd 0201 Output DC Blocking caps # # C636 10 nFd 0402 VRef Input ByPass cap # # C637 47 nFd 0402 Fanout VCC ByPass cap # C638 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U434-8 U434-13 NET 'FAN_1V8' C637-2 C638-1 NET 'GROUND' U434-16 NET 'GROUND' C637-1 C638-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_34' U434-2 U434-3 NET 'MGT_FO_CMR_CH_34' C636-1 NET 'GROUND' C636-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_34_IN_DIR' U434-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_IN_CMP' U434-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_34_OCP_HUB_DIR' U434-10 C634-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OCP_HUB_CMP' U434-9 C635-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OCP_ROD_DIR' U434-12 C632-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OCP_ROD_CMP' U434-11 C633-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_34_OUT_HUB_DIR' C634-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_HUB_CMP' C635-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_ROD_DIR' C632-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_ROD_CMP' C633-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_34_Pin_6' U434-6 NET 'No_Conn_FO_CH_34_Pin_7' U434-7 NET 'No_Conn_FO_CH_34_Pin_14' U434-14 NET 'No_Conn_FO_CH_34_Pin_15' U434-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_34_OUT_ROD_DIR' DPV502-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_ROD_CMP' DPV502-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV502-1 DPV502-4 NET 'MGT_FO_CH_34_OUT_HUB_DIR' DPV501-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_HUB_CMP' DPV501-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV501-1 NET 'MGT_FO_CH_34_IN_DIR' DPV500-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_IN_CMP' DPV500-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV500-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #18/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #35 # # The components in TOP side Channel #35 MGT Fanout are: # # U435 NB7VQ14M 4 way fanout chip # # C639:C642 100 nFd 0201 Output DC Blocking caps # # C643 10 nFd 0402 VRef Input ByPass cap # # C644 47 nFd 0402 Fanout VCC ByPass cap # C645 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U435-8 U435-13 NET 'FAN_1V8' C644-2 C645-2 NET 'GROUND' U435-16 NET 'GROUND' C644-1 C645-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_35' U435-2 U435-3 NET 'MGT_FO_CMR_CH_35' C643-1 NET 'GROUND' C643-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_35_IN_DIR' U435-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_IN_CMP' U435-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_35_OCP_ROD_DIR' U435-10 C641-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OCP_ROD_CMP' U435-9 C642-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OCP_HUB_DIR' U435-12 C639-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OCP_HUB_CMP' U435-11 C640-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_35_OUT_ROD_DIR' C641-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_ROD_CMP' C642-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_HUB_DIR' C639-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_HUB_CMP' C640-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_35_Pin_6' U435-6 NET 'No_Conn_FO_CH_35_Pin_7' U435-7 NET 'No_Conn_FO_CH_35_Pin_14' U435-14 NET 'No_Conn_FO_CH_35_Pin_15' U435-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_35_OUT_ROD_DIR' DPV505-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_ROD_CMP' DPV505-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV505-1 DPV505-4 NET 'MGT_FO_CH_35_OUT_HUB_DIR' DPV504-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_HUB_CMP' DPV504-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV504-1 NET 'MGT_FO_CH_35_IN_DIR' DPV503-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_IN_CMP' DPV503-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV503-1 # # MGT FanOut Channel #36 # # # The components in BOTTOM side Channel #36 MGT Fanout are: # # U436 NB7VQ14M 4 way fanout chip # # C646:C649 100 nFd 0201 Output DC Blocking caps # # C650 10 nFd 0402 VRef Input ByPass cap # # C651 47 nFd 0402 Fanout VCC ByPass cap # C652 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U436-8 U436-13 NET 'FAN_1V8' C651-2 C652-1 NET 'GROUND' U436-16 NET 'GROUND' C651-1 C652-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_36' U436-2 U436-3 NET 'MGT_FO_CMR_CH_36' C650-1 NET 'GROUND' C650-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_36_IN_DIR' U436-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_IN_CMP' U436-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_36_OCP_HUB_DIR' U436-10 C648-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OCP_HUB_CMP' U436-9 C649-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OCP_ROD_DIR' U436-12 C646-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OCP_ROD_CMP' U436-11 C647-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_36_OUT_HUB_DIR' C648-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_HUB_CMP' C649-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_ROD_DIR' C646-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_ROD_CMP' C647-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_36_Pin_6' U436-6 NET 'No_Conn_FO_CH_36_Pin_7' U436-7 NET 'No_Conn_FO_CH_36_Pin_14' U436-14 NET 'No_Conn_FO_CH_36_Pin_15' U436-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_36_OUT_ROD_DIR' DPV508-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_ROD_CMP' DPV508-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV508-1 DPV508-4 NET 'MGT_FO_CH_36_OUT_HUB_DIR' DPV507-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_HUB_CMP' DPV507-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV507-1 NET 'MGT_FO_CH_36_IN_DIR' DPV506-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_IN_CMP' DPV506-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV506-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #19/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #37 # # The components in TOP side Channel #37 MGT Fanout are: # # U437 NB7VQ14M 4 way fanout chip # # C653:C656 100 nFd 0201 Output DC Blocking caps # # C657 10 nFd 0402 VRef Input ByPass cap # # C658 47 nFd 0402 Fanout VCC ByPass cap # C659 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U437-8 U437-13 NET 'FAN_1V8' C658-2 C659-2 NET 'GROUND' U437-16 NET 'GROUND' C658-1 C659-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_37' U437-2 U437-3 NET 'MGT_FO_CMR_CH_37' C657-1 NET 'GROUND' C657-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_37_IN_DIR' U437-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_IN_CMP' U437-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_37_OCP_ROD_DIR' U437-10 C655-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OCP_ROD_CMP' U437-9 C656-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OCP_HUB_DIR' U437-12 C653-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OCP_HUB_CMP' U437-11 C654-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_37_OUT_ROD_DIR' C655-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_ROD_CMP' C656-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_HUB_DIR' C653-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_HUB_CMP' C654-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_37_Pin_6' U437-6 NET 'No_Conn_FO_CH_37_Pin_7' U437-7 NET 'No_Conn_FO_CH_37_Pin_14' U437-14 NET 'No_Conn_FO_CH_37_Pin_15' U437-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_37_OUT_ROD_DIR' DPV511-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_ROD_CMP' DPV511-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV511-1 DPV511-4 NET 'MGT_FO_CH_37_OUT_HUB_DIR' DPV510-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_HUB_CMP' DPV510-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV510-1 NET 'MGT_FO_CH_37_IN_DIR' DPV509-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_IN_CMP' DPV509-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV509-1 # # MGT FanOut Channel #38 # # # The components in BOTTOM side Channel #38 MGT Fanout are: # # U438 NB7VQ14M 4 way fanout chip # # C660:C663 100 nFd 0201 Output DC Blocking caps # # C664 10 nFd 0402 VRef Input ByPass cap # # C665 47 nFd 0402 Fanout VCC ByPass cap # C666 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U438-8 U438-13 NET 'FAN_1V8' C665-2 C666-1 NET 'GROUND' U438-16 NET 'GROUND' C665-1 C666-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_38' U438-2 U438-3 NET 'MGT_FO_CMR_CH_38' C664-1 NET 'GROUND' C664-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_38_IN_DIR' U438-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_IN_CMP' U438-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_38_OCP_HUB_DIR' U438-10 C662-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OCP_HUB_CMP' U438-9 C663-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OCP_ROD_DIR' U438-12 C660-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OCP_ROD_CMP' U438-11 C661-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_38_OUT_HUB_DIR' C662-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_HUB_CMP' C663-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_ROD_DIR' C660-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_ROD_CMP' C661-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_38_Pin_6' U438-6 NET 'No_Conn_FO_CH_38_Pin_7' U438-7 NET 'No_Conn_FO_CH_38_Pin_14' U438-14 NET 'No_Conn_FO_CH_38_Pin_15' U438-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_38_OUT_ROD_DIR' DPV514-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_ROD_CMP' DPV514-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV514-1 DPV514-4 NET 'MGT_FO_CH_38_OUT_HUB_DIR' DPV513-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_HUB_CMP' DPV513-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV513-1 NET 'MGT_FO_CH_38_IN_DIR' DPV512-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_IN_CMP' DPV512-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV512-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #20/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #39 # # The components in TOP side Channel #39 MGT Fanout are: # # U439 NB7VQ14M 4 way fanout chip # # C667:C670 100 nFd 0201 Output DC Blocking caps # # C671 10 nFd 0402 VRef Input ByPass cap # # C672 47 nFd 0402 Fanout VCC ByPass cap # C673 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U439-8 U439-13 NET 'FAN_1V8' C672-2 C673-2 NET 'GROUND' U439-16 NET 'GROUND' C672-1 C673-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_39' U439-2 U439-3 NET 'MGT_FO_CMR_CH_39' C671-1 NET 'GROUND' C671-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_39_IN_DIR' U439-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_IN_CMP' U439-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_39_OCP_ROD_DIR' U439-10 C669-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OCP_ROD_CMP' U439-9 C670-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OCP_HUB_DIR' U439-12 C667-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OCP_HUB_CMP' U439-11 C668-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_39_OUT_ROD_DIR' C669-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_ROD_CMP' C670-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_HUB_DIR' C667-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_HUB_CMP' C668-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_39_Pin_6' U439-6 NET 'No_Conn_FO_CH_39_Pin_7' U439-7 NET 'No_Conn_FO_CH_39_Pin_14' U439-14 NET 'No_Conn_FO_CH_39_Pin_15' U439-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_39_OUT_ROD_DIR' DPV517-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_ROD_CMP' DPV517-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV517-1 DPV517-4 NET 'MGT_FO_CH_39_OUT_HUB_DIR' DPV516-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_HUB_CMP' DPV516-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV516-1 NET 'MGT_FO_CH_39_IN_DIR' DPV515-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_IN_CMP' DPV515-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV515-1 # # MGT FanOut Channel #40 # # # The components in BOTTOM side Channel #40 MGT Fanout are: # # U440 NB7VQ14M 4 way fanout chip # # C674:C677 100 nFd 0201 Output DC Blocking caps # # C678 10 nFd 0402 VRef Input ByPass cap # # C679 47 nFd 0402 Fanout VCC ByPass cap # C680 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U440-8 U440-13 NET 'FAN_1V8' C679-2 C680-1 NET 'GROUND' U440-16 NET 'GROUND' C679-1 C680-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_40' U440-2 U440-3 NET 'MGT_FO_CMR_CH_40' C678-1 NET 'GROUND' C678-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_40_IN_DIR' U440-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_IN_CMP' U440-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_40_OCP_HUB_DIR' U440-10 C676-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OCP_HUB_CMP' U440-9 C677-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OCP_ROD_DIR' U440-12 C674-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OCP_ROD_CMP' U440-11 C675-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_40_OUT_HUB_DIR' C676-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_HUB_CMP' C677-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_ROD_DIR' C674-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_ROD_CMP' C675-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_40_Pin_6' U440-6 NET 'No_Conn_FO_CH_40_Pin_7' U440-7 NET 'No_Conn_FO_CH_40_Pin_14' U440-14 NET 'No_Conn_FO_CH_40_Pin_15' U440-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_40_OUT_ROD_DIR' DPV520-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_ROD_CMP' DPV520-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV520-1 DPV520-4 NET 'MGT_FO_CH_40_OUT_HUB_DIR' DPV519-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_HUB_CMP' DPV519-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV519-1 NET 'MGT_FO_CH_40_IN_DIR' DPV518-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_IN_CMP' DPV518-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV518-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #21/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #41 # # The components in TOP side Channel #41 MGT Fanout are: # # U441 NB7VQ14M 4 way fanout chip # # C681:C684 100 nFd 0201 Output DC Blocking caps # # C685 10 nFd 0402 VRef Input ByPass cap # # C686 47 nFd 0402 Fanout VCC ByPass cap # C687 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U441-8 U441-13 NET 'FAN_1V8' C686-2 C687-2 NET 'GROUND' U441-16 NET 'GROUND' C686-1 C687-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_41' U441-2 U441-3 NET 'MGT_FO_CMR_CH_41' C685-1 NET 'GROUND' C685-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_41_IN_DIR' U441-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_IN_CMP' U441-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_41_OCP_ROD_DIR' U441-10 C683-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OCP_ROD_CMP' U441-9 C684-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OCP_HUB_DIR' U441-12 C681-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OCP_HUB_CMP' U441-11 C682-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_41_OUT_ROD_DIR' C683-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_ROD_CMP' C684-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_HUB_DIR' C681-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_HUB_CMP' C682-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_41_Pin_6' U441-6 NET 'No_Conn_FO_CH_41_Pin_7' U441-7 NET 'No_Conn_FO_CH_41_Pin_14' U441-14 NET 'No_Conn_FO_CH_41_Pin_15' U441-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_41_OUT_ROD_DIR' DPV523-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_ROD_CMP' DPV523-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV523-1 DPV523-4 NET 'MGT_FO_CH_41_IN_DIR' DPV521-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_IN_CMP' DPV521-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV521-1 # # MGT FanOut Channel #42 # # # The components in BOTTOM side Channel #42 MGT Fanout are: # # U442 NB7VQ14M 4 way fanout chip # # C688:C691 100 nFd 0201 Output DC Blocking caps # # C692 10 nFd 0402 VRef Input ByPass cap # # C693 47 nFd 0402 Fanout VCC ByPass cap # C694 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U442-8 U442-13 NET 'FAN_1V8' C693-2 C694-1 NET 'GROUND' U442-16 NET 'GROUND' C693-1 C694-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_42' U442-2 U442-3 NET 'MGT_FO_CMR_CH_42' C692-1 NET 'GROUND' C692-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_42_IN_DIR' U442-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_IN_CMP' U442-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_42_OCP_HUB_DIR' U442-10 C690-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OCP_HUB_CMP' U442-9 C691-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OCP_ROD_DIR' U442-12 C688-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OCP_ROD_CMP' U442-11 C689-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_42_OUT_HUB_DIR' C690-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_HUB_CMP' C691-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_ROD_DIR' C688-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_ROD_CMP' C689-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_42_Pin_6' U442-6 NET 'No_Conn_FO_CH_42_Pin_7' U442-7 NET 'No_Conn_FO_CH_42_Pin_14' U442-14 NET 'No_Conn_FO_CH_42_Pin_15' U442-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_42_OUT_ROD_DIR' DPV526-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_ROD_CMP' DPV526-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV526-1 DPV526-4 NET 'MGT_FO_CH_42_OUT_HUB_DIR' DPV525-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_HUB_CMP' DPV525-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV525-1 NET 'MGT_FO_CH_42_IN_DIR' DPV524-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_IN_CMP' DPV524-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV524-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #22/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #43 # # The components in TOP side Channel #43 MGT Fanout are: # # U443 NB7VQ14M 4 way fanout chip # # C695:C698 100 nFd 0201 Output DC Blocking caps # # C699 10 nFd 0402 VRef Input ByPass cap # # C700 47 nFd 0402 Fanout VCC ByPass cap # C701 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U443-8 U443-13 NET 'FAN_1V8' C700-2 C701-2 NET 'GROUND' U443-16 NET 'GROUND' C700-1 C701-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_43' U443-2 U443-3 NET 'MGT_FO_CMR_CH_43' C699-1 NET 'GROUND' C699-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_43_IN_DIR' U443-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_IN_CMP' U443-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_43_OCP_ROD_DIR' U443-10 C697-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OCP_ROD_CMP' U443-9 C698-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OCP_HUB_DIR' U443-12 C695-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OCP_HUB_CMP' U443-11 C696-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_43_OUT_ROD_DIR' C697-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_ROD_CMP' C698-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_HUB_DIR' C695-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_HUB_CMP' C696-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_43_Pin_6' U443-6 NET 'No_Conn_FO_CH_43_Pin_7' U443-7 NET 'No_Conn_FO_CH_43_Pin_14' U443-14 NET 'No_Conn_FO_CH_43_Pin_15' U443-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_43_OUT_ROD_DIR' DPV529-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_ROD_CMP' DPV529-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV529-1 DPV529-4 NET 'MGT_FO_CH_43_OUT_HUB_DIR' DPV528-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_HUB_CMP' DPV528-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV528-1 NET 'MGT_FO_CH_43_IN_DIR' DPV527-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_IN_CMP' DPV527-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV527-1 # # MGT FanOut Channel #44 # # # The components in BOTTOM side Channel #44 MGT Fanout are: # # U444 NB7VQ14M 4 way fanout chip # # C702:C705 100 nFd 0201 Output DC Blocking caps # # C706 10 nFd 0402 VRef Input ByPass cap # # C707 47 nFd 0402 Fanout VCC ByPass cap # C708 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U444-8 U444-13 NET 'FAN_1V8' C707-2 C708-1 NET 'GROUND' U444-16 NET 'GROUND' C707-1 C708-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_44' U444-2 U444-3 NET 'MGT_FO_CMR_CH_44' C706-1 NET 'GROUND' C706-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_44_IN_DIR' U444-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_IN_CMP' U444-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_44_OCP_HUB_DIR' U444-10 C704-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OCP_HUB_CMP' U444-9 C705-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OCP_ROD_DIR' U444-12 C702-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OCP_ROD_CMP' U444-11 C703-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_44_OUT_HUB_DIR' C704-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_HUB_CMP' C705-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_ROD_DIR' C702-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_ROD_CMP' C703-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_44_Pin_6' U444-6 NET 'No_Conn_FO_CH_44_Pin_7' U444-7 NET 'No_Conn_FO_CH_44_Pin_14' U444-14 NET 'No_Conn_FO_CH_44_Pin_15' U444-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_44_OUT_ROD_DIR' DPV532-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_ROD_CMP' DPV532-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV532-1 DPV532-4 NET 'MGT_FO_CH_44_OUT_HUB_DIR' DPV531-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_HUB_CMP' DPV531-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV531-1 NET 'MGT_FO_CH_44_IN_DIR' DPV530-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_IN_CMP' DPV530-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV530-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #23/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #45 # # The components in TOP side Channel #45 MGT Fanout are: # # U445 NB7VQ14M 4 way fanout chip # # C709:C712 100 nFd 0201 Output DC Blocking caps # # C713 10 nFd 0402 VRef Input ByPass cap # # C714 47 nFd 0402 Fanout VCC ByPass cap # C715 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U445-8 U445-13 NET 'FAN_1V8' C714-2 C715-2 NET 'GROUND' U445-16 NET 'GROUND' C714-1 C715-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_45' U445-2 U445-3 NET 'MGT_FO_CMR_CH_45' C713-1 NET 'GROUND' C713-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_45_IN_DIR' U445-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_IN_CMP' U445-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_45_OCP_ROD_DIR' U445-10 C711-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OCP_ROD_CMP' U445-9 C712-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OCP_HUB_DIR' U445-12 C709-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OCP_HUB_CMP' U445-11 C710-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_45_OUT_ROD_DIR' C711-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_ROD_CMP' C712-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_HUB_DIR' C709-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_HUB_CMP' C710-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_45_Pin_6' U445-6 NET 'No_Conn_FO_CH_45_Pin_7' U445-7 NET 'No_Conn_FO_CH_45_Pin_14' U445-14 NET 'No_Conn_FO_CH_45_Pin_15' U445-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_45_OUT_ROD_DIR' DPV535-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_ROD_CMP' DPV535-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV535-1 DPV535-4 NET 'MGT_FO_CH_45_OUT_HUB_DIR' DPV534-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_HUB_CMP' DPV534-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV534-1 NET 'MGT_FO_CH_45_IN_DIR' DPV533-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_IN_CMP' DPV533-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV533-1 # # MGT FanOut Channel #46 # # # The components in BOTTOM side Channel #46 MGT Fanout are: # # U446 NB7VQ14M 4 way fanout chip # # C716:C719 100 nFd 0201 Output DC Blocking caps # # C720 10 nFd 0402 VRef Input ByPass cap # # C721 47 nFd 0402 Fanout VCC ByPass cap # C722 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U446-8 U446-13 NET 'FAN_1V8' C721-2 C722-1 NET 'GROUND' U446-16 NET 'GROUND' C721-1 C722-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_46' U446-2 U446-3 NET 'MGT_FO_CMR_CH_46' C720-1 NET 'GROUND' C720-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_46_IN_DIR' U446-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_IN_CMP' U446-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_46_OCP_HUB_DIR' U446-10 C718-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OCP_HUB_CMP' U446-9 C719-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OCP_ROD_DIR' U446-12 C716-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OCP_ROD_CMP' U446-11 C717-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_46_OUT_HUB_DIR' C718-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_HUB_CMP' C719-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_ROD_DIR' C716-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_ROD_CMP' C717-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_46_Pin_6' U446-6 NET 'No_Conn_FO_CH_46_Pin_7' U446-7 NET 'No_Conn_FO_CH_46_Pin_14' U446-14 NET 'No_Conn_FO_CH_46_Pin_15' U446-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_46_OUT_ROD_DIR' DPV538-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_ROD_CMP' DPV538-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV538-1 DPV538-4 NET 'MGT_FO_CH_46_OUT_HUB_DIR' DPV537-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_HUB_CMP' DPV537-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV537-1 NET 'MGT_FO_CH_46_IN_DIR' DPV536-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_IN_CMP' DPV536-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV536-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #24/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #47 # # The components in TOP side Channel #47 MGT Fanout are: # # U447 NB7VQ14M 4 way fanout chip # # C723:C726 100 nFd 0201 Output DC Blocking caps # # C727 10 nFd 0402 VRef Input ByPass cap # # C728 47 nFd 0402 Fanout VCC ByPass cap # C729 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U447-8 U447-13 NET 'FAN_1V8' C728-2 C729-2 NET 'GROUND' U447-16 NET 'GROUND' C728-1 C729-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_47' U447-2 U447-3 NET 'MGT_FO_CMR_CH_47' C727-1 NET 'GROUND' C727-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_47_IN_DIR' U447-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_IN_CMP' U447-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_47_OCP_ROD_DIR' U447-10 C725-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OCP_ROD_CMP' U447-9 C726-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OCP_HUB_DIR' U447-12 C723-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OCP_HUB_CMP' U447-11 C724-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_47_OUT_ROD_DIR' C725-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_ROD_CMP' C726-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_HUB_DIR' C723-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_HUB_CMP' C724-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_47_Pin_6' U447-6 NET 'No_Conn_FO_CH_47_Pin_7' U447-7 NET 'No_Conn_FO_CH_47_Pin_14' U447-14 NET 'No_Conn_FO_CH_47_Pin_15' U447-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_47_OUT_ROD_DIR' DPV541-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_ROD_CMP' DPV541-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV541-1 DPV541-4 NET 'MGT_FO_CH_47_OUT_HUB_DIR' DPV540-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_HUB_CMP' DPV540-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV540-1 NET 'MGT_FO_CH_47_IN_DIR' DPV539-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_IN_CMP' DPV539-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV539-1 # # MGT FanOut Channel #48 # # # The components in BOTTOM side Channel #48 MGT Fanout are: # # U448 NB7VQ14M 4 way fanout chip # # C730:C733 100 nFd 0201 Output DC Blocking caps # # C734 10 nFd 0402 VRef Input ByPass cap # # C735 47 nFd 0402 Fanout VCC ByPass cap # C736 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U448-8 U448-13 NET 'FAN_1V8' C735-2 C736-1 NET 'GROUND' U448-16 NET 'GROUND' C735-1 C736-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_48' U448-2 U448-3 NET 'MGT_FO_CMR_CH_48' C734-1 NET 'GROUND' C734-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_48_IN_DIR' U448-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_IN_CMP' U448-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_48_OCP_HUB_DIR' U448-10 C732-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OCP_HUB_CMP' U448-9 C733-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OCP_ROD_DIR' U448-12 C730-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OCP_ROD_CMP' U448-11 C731-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_48_OUT_HUB_DIR' C732-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_HUB_CMP' C733-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_ROD_DIR' C730-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_ROD_CMP' C731-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_48_Pin_6' U448-6 NET 'No_Conn_FO_CH_48_Pin_7' U448-7 NET 'No_Conn_FO_CH_48_Pin_14' U448-14 NET 'No_Conn_FO_CH_48_Pin_15' U448-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_48_OUT_ROD_DIR' DPV544-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_ROD_CMP' DPV544-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV544-1 DPV544-4 NET 'MGT_FO_CH_48_OUT_HUB_DIR' DPV543-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_HUB_CMP' DPV543-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV543-1 NET 'MGT_FO_CH_48_IN_DIR' DPV542-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_IN_CMP' DPV542-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV542-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #25/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #49 # # The components in TOP side Channel #49 MGT Fanout are: # # U449 NB7VQ14M 4 way fanout chip # # C737:C740 100 nFd 0201 Output DC Blocking caps # # C741 10 nFd 0402 VRef Input ByPass cap # # C742 47 nFd 0402 Fanout VCC ByPass cap # C743 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U449-8 U449-13 NET 'FAN_1V8' C742-2 C743-2 NET 'GROUND' U449-16 NET 'GROUND' C742-1 C743-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_49' U449-2 U449-3 NET 'MGT_FO_CMR_CH_49' C741-1 NET 'GROUND' C741-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_49_IN_DIR' U449-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_IN_CMP' U449-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_49_OCP_ROD_DIR' U449-10 C739-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OCP_ROD_CMP' U449-9 C740-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OCP_HUB_DIR' U449-12 C737-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OCP_HUB_CMP' U449-11 C738-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_49_OUT_ROD_DIR' C739-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_ROD_CMP' C740-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_HUB_DIR' C737-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_HUB_CMP' C738-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_49_Pin_6' U449-6 NET 'No_Conn_FO_CH_49_Pin_7' U449-7 NET 'No_Conn_FO_CH_49_Pin_14' U449-14 NET 'No_Conn_FO_CH_49_Pin_15' U449-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_49_OUT_ROD_DIR' DPV547-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_ROD_CMP' DPV547-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV547-1 DPV547-4 NET 'MGT_FO_CH_49_IN_DIR' DPV545-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_IN_CMP' DPV545-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV545-1 # # MGT FanOut Channel #50 # # # The components in BOTTOM side Channel #50 MGT Fanout are: # # U450 NB7VQ14M 4 way fanout chip # # C744:C747 100 nFd 0201 Output DC Blocking caps # # C748 10 nFd 0402 VRef Input ByPass cap # # C749 47 nFd 0402 Fanout VCC ByPass cap # C750 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U450-8 U450-13 NET 'FAN_1V8' C749-2 C750-1 NET 'GROUND' U450-16 NET 'GROUND' C749-1 C750-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_50' U450-2 U450-3 NET 'MGT_FO_CMR_CH_50' C748-1 NET 'GROUND' C748-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_50_IN_DIR' U450-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_IN_CMP' U450-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_50_OCP_HUB_DIR' U450-10 C746-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OCP_HUB_CMP' U450-9 C747-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OCP_ROD_DIR' U450-12 C744-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OCP_ROD_CMP' U450-11 C745-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_50_OUT_HUB_DIR' C746-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_HUB_CMP' C747-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_ROD_DIR' C744-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_ROD_CMP' C745-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_50_Pin_6' U450-6 NET 'No_Conn_FO_CH_50_Pin_7' U450-7 NET 'No_Conn_FO_CH_50_Pin_14' U450-14 NET 'No_Conn_FO_CH_50_Pin_15' U450-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_50_OUT_ROD_DIR' DPV550-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_ROD_CMP' DPV550-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV550-1 DPV550-4 NET 'MGT_FO_CH_50_OUT_HUB_DIR' DPV549-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_HUB_CMP' DPV549-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV549-1 NET 'MGT_FO_CH_50_IN_DIR' DPV548-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_IN_CMP' DPV548-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV548-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #26/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #51 # # The components in TOP side Channel #51 MGT Fanout are: # # U451 NB7VQ14M 4 way fanout chip # # C751:C754 100 nFd 0201 Output DC Blocking caps # # C755 10 nFd 0402 VRef Input ByPass cap # # C756 47 nFd 0402 Fanout VCC ByPass cap # C757 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U451-8 U451-13 NET 'FAN_1V8' C756-2 C757-2 NET 'GROUND' U451-16 NET 'GROUND' C756-1 C757-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_51' U451-2 U451-3 NET 'MGT_FO_CMR_CH_51' C755-1 NET 'GROUND' C755-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_51_IN_DIR' U451-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_IN_CMP' U451-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_51_OCP_ROD_DIR' U451-10 C753-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OCP_ROD_CMP' U451-9 C754-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OCP_HUB_DIR' U451-12 C751-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OCP_HUB_CMP' U451-11 C752-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_51_OUT_ROD_DIR' C753-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_ROD_CMP' C754-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_HUB_DIR' C751-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_HUB_CMP' C752-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_51_Pin_6' U451-6 NET 'No_Conn_FO_CH_51_Pin_7' U451-7 NET 'No_Conn_FO_CH_51_Pin_14' U451-14 NET 'No_Conn_FO_CH_51_Pin_15' U451-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_51_OUT_ROD_DIR' DPV553-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_ROD_CMP' DPV553-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV553-1 DPV553-4 NET 'MGT_FO_CH_51_OUT_HUB_DIR' DPV552-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_HUB_CMP' DPV552-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV552-1 NET 'MGT_FO_CH_51_IN_DIR' DPV551-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_IN_CMP' DPV551-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV551-1 # # MGT FanOut Channel #52 # # # The components in BOTTOM side Channel #52 MGT Fanout are: # # U452 NB7VQ14M 4 way fanout chip # # C758:C761 100 nFd 0201 Output DC Blocking caps # # C762 10 nFd 0402 VRef Input ByPass cap # # C763 47 nFd 0402 Fanout VCC ByPass cap # C764 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U452-8 U452-13 NET 'FAN_1V8' C763-2 C764-1 NET 'GROUND' U452-16 NET 'GROUND' C763-1 C764-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_52' U452-2 U452-3 NET 'MGT_FO_CMR_CH_52' C762-1 NET 'GROUND' C762-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_52_IN_DIR' U452-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_IN_CMP' U452-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_52_OCP_HUB_DIR' U452-10 C760-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OCP_HUB_CMP' U452-9 C761-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OCP_ROD_DIR' U452-12 C758-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OCP_ROD_CMP' U452-11 C759-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_52_OUT_HUB_DIR' C760-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_HUB_CMP' C761-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_ROD_DIR' C758-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_ROD_CMP' C759-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_52_Pin_6' U452-6 NET 'No_Conn_FO_CH_52_Pin_7' U452-7 NET 'No_Conn_FO_CH_52_Pin_14' U452-14 NET 'No_Conn_FO_CH_52_Pin_15' U452-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_52_OUT_ROD_DIR' DPV556-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_ROD_CMP' DPV556-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV556-1 DPV556-4 NET 'MGT_FO_CH_52_OUT_HUB_DIR' DPV555-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_HUB_CMP' DPV555-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV555-1 NET 'MGT_FO_CH_52_IN_DIR' DPV554-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_IN_CMP' DPV554-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV554-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #27/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #53 # # The components in TOP side Channel #53 MGT Fanout are: # # U453 NB7VQ14M 4 way fanout chip # # C765:C768 100 nFd 0201 Output DC Blocking caps # # C769 10 nFd 0402 VRef Input ByPass cap # # C770 47 nFd 0402 Fanout VCC ByPass cap # C771 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U453-8 U453-13 NET 'FAN_1V8' C770-2 C771-2 NET 'GROUND' U453-16 NET 'GROUND' C770-1 C771-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_53' U453-2 U453-3 NET 'MGT_FO_CMR_CH_53' C769-1 NET 'GROUND' C769-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_53_IN_DIR' U453-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_IN_CMP' U453-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_53_OCP_ROD_DIR' U453-10 C767-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OCP_ROD_CMP' U453-9 C768-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OCP_HUB_DIR' U453-12 C765-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OCP_HUB_CMP' U453-11 C766-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_53_OUT_ROD_DIR' C767-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_ROD_CMP' C768-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_HUB_DIR' C765-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_HUB_CMP' C766-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_53_Pin_6' U453-6 NET 'No_Conn_FO_CH_53_Pin_7' U453-7 NET 'No_Conn_FO_CH_53_Pin_14' U453-14 NET 'No_Conn_FO_CH_53_Pin_15' U453-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_53_OUT_ROD_DIR' DPV559-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_ROD_CMP' DPV559-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV559-1 DPV559-4 NET 'MGT_FO_CH_53_OUT_HUB_DIR' DPV558-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_HUB_CMP' DPV558-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV558-1 NET 'MGT_FO_CH_53_IN_DIR' DPV557-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_IN_CMP' DPV557-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV557-1 # # MGT FanOut Channel #54 # # # The components in BOTTOM side Channel #54 MGT Fanout are: # # U454 NB7VQ14M 4 way fanout chip # # C772:C775 100 nFd 0201 Output DC Blocking caps # # C776 10 nFd 0402 VRef Input ByPass cap # # C777 47 nFd 0402 Fanout VCC ByPass cap # C778 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U454-8 U454-13 NET 'FAN_1V8' C777-2 C778-1 NET 'GROUND' U454-16 NET 'GROUND' C777-1 C778-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_54' U454-2 U454-3 NET 'MGT_FO_CMR_CH_54' C776-1 NET 'GROUND' C776-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_54_IN_DIR' U454-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_IN_CMP' U454-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_54_OCP_HUB_DIR' U454-10 C774-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OCP_HUB_CMP' U454-9 C775-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OCP_ROD_DIR' U454-12 C772-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OCP_ROD_CMP' U454-11 C773-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_54_OUT_HUB_DIR' C774-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_HUB_CMP' C775-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_ROD_DIR' C772-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_ROD_CMP' C773-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_54_Pin_6' U454-6 NET 'No_Conn_FO_CH_54_Pin_7' U454-7 NET 'No_Conn_FO_CH_54_Pin_14' U454-14 NET 'No_Conn_FO_CH_54_Pin_15' U454-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_54_OUT_ROD_DIR' DPV562-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_ROD_CMP' DPV562-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV562-1 DPV562-4 NET 'MGT_FO_CH_54_OUT_HUB_DIR' DPV561-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_HUB_CMP' DPV561-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV561-1 NET 'MGT_FO_CH_54_IN_DIR' DPV560-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_IN_CMP' DPV560-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV560-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #28/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #55 # # The components in TOP side Channel #55 MGT Fanout are: # # U455 NB7VQ14M 4 way fanout chip # # C779:C782 100 nFd 0201 Output DC Blocking caps # # C783 10 nFd 0402 VRef Input ByPass cap # # C784 47 nFd 0402 Fanout VCC ByPass cap # C785 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U455-8 U455-13 NET 'FAN_1V8' C784-2 C785-2 NET 'GROUND' U455-16 NET 'GROUND' C784-1 C785-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_55' U455-2 U455-3 NET 'MGT_FO_CMR_CH_55' C783-1 NET 'GROUND' C783-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_55_IN_DIR' U455-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_IN_CMP' U455-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_55_OCP_ROD_DIR' U455-10 C781-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OCP_ROD_CMP' U455-9 C782-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OCP_HUB_DIR' U455-12 C779-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OCP_HUB_CMP' U455-11 C780-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_55_OUT_ROD_DIR' C781-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_ROD_CMP' C782-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_HUB_DIR' C779-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_HUB_CMP' C780-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_55_Pin_6' U455-6 NET 'No_Conn_FO_CH_55_Pin_7' U455-7 NET 'No_Conn_FO_CH_55_Pin_14' U455-14 NET 'No_Conn_FO_CH_55_Pin_15' U455-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_55_OUT_ROD_DIR' DPV565-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_ROD_CMP' DPV565-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV565-1 DPV565-4 NET 'MGT_FO_CH_55_OUT_HUB_DIR' DPV564-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_HUB_CMP' DPV564-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV564-1 NET 'MGT_FO_CH_55_IN_DIR' DPV563-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_IN_CMP' DPV563-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV563-1 # # MGT FanOut Channel #56 # # # The components in BOTTOM side Channel #56 MGT Fanout are: # # U456 NB7VQ14M 4 way fanout chip # # C786:C789 100 nFd 0201 Output DC Blocking caps # # C790 10 nFd 0402 VRef Input ByPass cap # # C791 47 nFd 0402 Fanout VCC ByPass cap # C792 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U456-8 U456-13 NET 'FAN_1V8' C791-2 C792-1 NET 'GROUND' U456-16 NET 'GROUND' C791-1 C792-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_56' U456-2 U456-3 NET 'MGT_FO_CMR_CH_56' C790-1 NET 'GROUND' C790-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_56_IN_DIR' U456-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_IN_CMP' U456-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_56_OCP_HUB_DIR' U456-10 C788-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OCP_HUB_CMP' U456-9 C789-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OCP_ROD_DIR' U456-12 C786-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OCP_ROD_CMP' U456-11 C787-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_56_OUT_HUB_DIR' C788-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_HUB_CMP' C789-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_ROD_DIR' C786-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_ROD_CMP' C787-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_56_Pin_6' U456-6 NET 'No_Conn_FO_CH_56_Pin_7' U456-7 NET 'No_Conn_FO_CH_56_Pin_14' U456-14 NET 'No_Conn_FO_CH_56_Pin_15' U456-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_56_OUT_ROD_DIR' DPV568-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_ROD_CMP' DPV568-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV568-1 DPV568-4 NET 'MGT_FO_CH_56_OUT_HUB_DIR' DPV567-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_HUB_CMP' DPV567-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV567-1 NET 'MGT_FO_CH_56_IN_DIR' DPV566-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_IN_CMP' DPV566-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV566-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #29/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #57 # # The components in TOP side Channel #57 MGT Fanout are: # # U457 NB7VQ14M 4 way fanout chip # # C793:C796 100 nFd 0201 Output DC Blocking caps # # C797 10 nFd 0402 VRef Input ByPass cap # # C798 47 nFd 0402 Fanout VCC ByPass cap # C799 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U457-8 U457-13 NET 'FAN_1V8' C798-2 C799-2 NET 'GROUND' U457-16 NET 'GROUND' C798-1 C799-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_57' U457-2 U457-3 NET 'MGT_FO_CMR_CH_57' C797-1 NET 'GROUND' C797-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_57_IN_DIR' U457-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_IN_CMP' U457-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_57_OCP_ROD_DIR' U457-10 C795-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OCP_ROD_CMP' U457-9 C796-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OCP_HUB_DIR' U457-12 C793-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OCP_HUB_CMP' U457-11 C794-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_57_OUT_ROD_DIR' C795-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_ROD_CMP' C796-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_HUB_DIR' C793-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_HUB_CMP' C794-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_57_Pin_6' U457-6 NET 'No_Conn_FO_CH_57_Pin_7' U457-7 NET 'No_Conn_FO_CH_57_Pin_14' U457-14 NET 'No_Conn_FO_CH_57_Pin_15' U457-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_57_OUT_ROD_DIR' DPV571-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_ROD_CMP' DPV571-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV571-1 DPV571-4 NET 'MGT_FO_CH_57_IN_DIR' DPV569-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_IN_CMP' DPV569-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV569-1 # # MGT FanOut Channel #58 # # # The components in BOTTOM side Channel #58 MGT Fanout are: # # U458 NB7VQ14M 4 way fanout chip # # C800:C803 100 nFd 0201 Output DC Blocking caps # # C804 10 nFd 0402 VRef Input ByPass cap # # C805 47 nFd 0402 Fanout VCC ByPass cap # C806 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U458-8 U458-13 NET 'FAN_1V8' C805-2 C806-1 NET 'GROUND' U458-16 NET 'GROUND' C805-1 C806-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_58' U458-2 U458-3 NET 'MGT_FO_CMR_CH_58' C804-1 NET 'GROUND' C804-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_58_IN_DIR' U458-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_IN_CMP' U458-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_58_OCP_HUB_DIR' U458-10 C802-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OCP_HUB_CMP' U458-9 C803-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OCP_ROD_DIR' U458-12 C800-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OCP_ROD_CMP' U458-11 C801-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_58_OUT_HUB_DIR' C802-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_HUB_CMP' C803-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_ROD_DIR' C800-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_ROD_CMP' C801-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_58_Pin_6' U458-6 NET 'No_Conn_FO_CH_58_Pin_7' U458-7 NET 'No_Conn_FO_CH_58_Pin_14' U458-14 NET 'No_Conn_FO_CH_58_Pin_15' U458-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_58_OUT_ROD_DIR' DPV574-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_ROD_CMP' DPV574-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV574-1 DPV574-4 NET 'MGT_FO_CH_58_OUT_HUB_DIR' DPV573-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_HUB_CMP' DPV573-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV573-1 NET 'MGT_FO_CH_58_IN_DIR' DPV572-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_IN_CMP' DPV572-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV572-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #30/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #59 # # The components in TOP side Channel #59 MGT Fanout are: # # U459 NB7VQ14M 4 way fanout chip # # C807:C810 100 nFd 0201 Output DC Blocking caps # # C811 10 nFd 0402 VRef Input ByPass cap # # C812 47 nFd 0402 Fanout VCC ByPass cap # C813 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U459-8 U459-13 NET 'FAN_1V8' C812-2 C813-2 NET 'GROUND' U459-16 NET 'GROUND' C812-1 C813-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_59' U459-2 U459-3 NET 'MGT_FO_CMR_CH_59' C811-1 NET 'GROUND' C811-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_59_IN_DIR' U459-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_IN_CMP' U459-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_59_OCP_ROD_DIR' U459-10 C809-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OCP_ROD_CMP' U459-9 C810-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OCP_HUB_DIR' U459-12 C807-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OCP_HUB_CMP' U459-11 C808-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_59_OUT_ROD_DIR' C809-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_ROD_CMP' C810-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_HUB_DIR' C807-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_HUB_CMP' C808-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_59_Pin_6' U459-6 NET 'No_Conn_FO_CH_59_Pin_7' U459-7 NET 'No_Conn_FO_CH_59_Pin_14' U459-14 NET 'No_Conn_FO_CH_59_Pin_15' U459-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_59_OUT_ROD_DIR' DPV577-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_ROD_CMP' DPV577-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV577-1 DPV577-4 NET 'MGT_FO_CH_59_OUT_HUB_DIR' DPV576-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_HUB_CMP' DPV576-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV576-1 NET 'MGT_FO_CH_59_IN_DIR' DPV575-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_IN_CMP' DPV575-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV575-1 # # MGT FanOut Channel #60 # # # The components in BOTTOM side Channel #60 MGT Fanout are: # # U460 NB7VQ14M 4 way fanout chip # # C814:C817 100 nFd 0201 Output DC Blocking caps # # C818 10 nFd 0402 VRef Input ByPass cap # # C819 47 nFd 0402 Fanout VCC ByPass cap # C820 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U460-8 U460-13 NET 'FAN_1V8' C819-2 C820-1 NET 'GROUND' U460-16 NET 'GROUND' C819-1 C820-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_60' U460-2 U460-3 NET 'MGT_FO_CMR_CH_60' C818-1 NET 'GROUND' C818-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_60_IN_DIR' U460-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_IN_CMP' U460-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_60_OCP_HUB_DIR' U460-10 C816-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OCP_HUB_CMP' U460-9 C817-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OCP_ROD_DIR' U460-12 C814-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OCP_ROD_CMP' U460-11 C815-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_60_OUT_HUB_DIR' C816-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_HUB_CMP' C817-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_ROD_DIR' C814-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_ROD_CMP' C815-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_60_Pin_6' U460-6 NET 'No_Conn_FO_CH_60_Pin_7' U460-7 NET 'No_Conn_FO_CH_60_Pin_14' U460-14 NET 'No_Conn_FO_CH_60_Pin_15' U460-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_60_OUT_ROD_DIR' DPV580-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_ROD_CMP' DPV580-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV580-1 DPV580-4 NET 'MGT_FO_CH_60_OUT_HUB_DIR' DPV579-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_HUB_CMP' DPV579-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV579-1 NET 'MGT_FO_CH_60_IN_DIR' DPV578-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_IN_CMP' DPV578-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV578-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #31/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #61 # # The components in TOP side Channel #61 MGT Fanout are: # # U461 NB7VQ14M 4 way fanout chip # # C821:C824 100 nFd 0201 Output DC Blocking caps # # C825 10 nFd 0402 VRef Input ByPass cap # # C826 47 nFd 0402 Fanout VCC ByPass cap # C827 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U461-8 U461-13 NET 'FAN_1V8' C826-2 C827-2 NET 'GROUND' U461-16 NET 'GROUND' C826-1 C827-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_61' U461-2 U461-3 NET 'MGT_FO_CMR_CH_61' C825-1 NET 'GROUND' C825-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_61_IN_DIR' U461-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_IN_CMP' U461-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_61_OCP_ROD_DIR' U461-10 C823-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OCP_ROD_CMP' U461-9 C824-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OCP_HUB_DIR' U461-12 C821-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OCP_HUB_CMP' U461-11 C822-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_61_OUT_ROD_DIR' C823-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_ROD_CMP' C824-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_HUB_DIR' C821-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_HUB_CMP' C822-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_61_Pin_6' U461-6 NET 'No_Conn_FO_CH_61_Pin_7' U461-7 NET 'No_Conn_FO_CH_61_Pin_14' U461-14 NET 'No_Conn_FO_CH_61_Pin_15' U461-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_61_OUT_ROD_DIR' DPV583-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_ROD_CMP' DPV583-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV583-1 DPV583-4 NET 'MGT_FO_CH_61_OUT_HUB_DIR' DPV582-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_HUB_CMP' DPV582-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV582-1 NET 'MGT_FO_CH_61_IN_DIR' DPV581-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_IN_CMP' DPV581-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV581-1 # # MGT FanOut Channel #62 # # # The components in BOTTOM side Channel #62 MGT Fanout are: # # U462 NB7VQ14M 4 way fanout chip # # C828:C831 100 nFd 0201 Output DC Blocking caps # # C832 10 nFd 0402 VRef Input ByPass cap # # C833 47 nFd 0402 Fanout VCC ByPass cap # C834 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U462-8 U462-13 NET 'FAN_1V8' C833-2 C834-1 NET 'GROUND' U462-16 NET 'GROUND' C833-1 C834-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_62' U462-2 U462-3 NET 'MGT_FO_CMR_CH_62' C832-1 NET 'GROUND' C832-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_62_IN_DIR' U462-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_IN_CMP' U462-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_62_OCP_HUB_DIR' U462-10 C830-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OCP_HUB_CMP' U462-9 C831-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OCP_ROD_DIR' U462-12 C828-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OCP_ROD_CMP' U462-11 C829-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_62_OUT_HUB_DIR' C830-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_HUB_CMP' C831-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_ROD_DIR' C828-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_ROD_CMP' C829-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_62_Pin_6' U462-6 NET 'No_Conn_FO_CH_62_Pin_7' U462-7 NET 'No_Conn_FO_CH_62_Pin_14' U462-14 NET 'No_Conn_FO_CH_62_Pin_15' U462-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_62_OUT_ROD_DIR' DPV586-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_ROD_CMP' DPV586-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV586-1 DPV586-4 NET 'MGT_FO_CH_62_OUT_HUB_DIR' DPV585-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_HUB_CMP' DPV585-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV585-1 NET 'MGT_FO_CH_62_IN_DIR' DPV584-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_IN_CMP' DPV584-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV584-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #32/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #63 # # The components in TOP side Channel #63 MGT Fanout are: # # U463 NB7VQ14M 4 way fanout chip # # C835:C838 100 nFd 0201 Output DC Blocking caps # # C839 10 nFd 0402 VRef Input ByPass cap # # C840 47 nFd 0402 Fanout VCC ByPass cap # C841 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U463-8 U463-13 NET 'FAN_1V8' C840-2 C841-2 NET 'GROUND' U463-16 NET 'GROUND' C840-1 C841-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_63' U463-2 U463-3 NET 'MGT_FO_CMR_CH_63' C839-1 NET 'GROUND' C839-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_63_IN_DIR' U463-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_IN_CMP' U463-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_63_OCP_ROD_DIR' U463-10 C837-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OCP_ROD_CMP' U463-9 C838-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OCP_HUB_DIR' U463-12 C835-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OCP_HUB_CMP' U463-11 C836-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_63_OUT_ROD_DIR' C837-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_ROD_CMP' C838-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_HUB_DIR' C835-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_HUB_CMP' C836-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_63_Pin_6' U463-6 NET 'No_Conn_FO_CH_63_Pin_7' U463-7 NET 'No_Conn_FO_CH_63_Pin_14' U463-14 NET 'No_Conn_FO_CH_63_Pin_15' U463-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_63_OUT_ROD_DIR' DPV589-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_ROD_CMP' DPV589-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV589-1 DPV589-4 NET 'MGT_FO_CH_63_OUT_HUB_DIR' DPV588-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_HUB_CMP' DPV588-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV588-1 NET 'MGT_FO_CH_63_IN_DIR' DPV587-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_IN_CMP' DPV587-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV587-1 # # MGT FanOut Channel #64 # # # The components in BOTTOM side Channel #64 MGT Fanout are: # # U464 NB7VQ14M 4 way fanout chip # # C842:C845 100 nFd 0201 Output DC Blocking caps # # C846 10 nFd 0402 VRef Input ByPass cap # # C847 47 nFd 0402 Fanout VCC ByPass cap # C848 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U464-8 U464-13 NET 'FAN_1V8' C847-2 C848-1 NET 'GROUND' U464-16 NET 'GROUND' C847-1 C848-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_64' U464-2 U464-3 NET 'MGT_FO_CMR_CH_64' C846-1 NET 'GROUND' C846-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_64_IN_DIR' U464-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_IN_CMP' U464-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_64_OCP_HUB_DIR' U464-10 C844-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OCP_HUB_CMP' U464-9 C845-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OCP_ROD_DIR' U464-12 C842-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OCP_ROD_CMP' U464-11 C843-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_64_OUT_HUB_DIR' C844-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_HUB_CMP' C845-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_ROD_DIR' C842-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_ROD_CMP' C843-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_64_Pin_6' U464-6 NET 'No_Conn_FO_CH_64_Pin_7' U464-7 NET 'No_Conn_FO_CH_64_Pin_14' U464-14 NET 'No_Conn_FO_CH_64_Pin_15' U464-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_64_OUT_ROD_DIR' DPV592-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_ROD_CMP' DPV592-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV592-1 DPV592-4 NET 'MGT_FO_CH_64_OUT_HUB_DIR' DPV591-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_HUB_CMP' DPV591-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV591-1 NET 'MGT_FO_CH_64_IN_DIR' DPV590-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_IN_CMP' DPV590-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV590-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #33/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #65 # # The components in TOP side Channel #65 MGT Fanout are: # # U465 NB7VQ14M 4 way fanout chip # # C849:C852 100 nFd 0201 Output DC Blocking caps # # C853 10 nFd 0402 VRef Input ByPass cap # # C854 47 nFd 0402 Fanout VCC ByPass cap # C855 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U465-8 U465-13 NET 'FAN_1V8' C854-2 C855-2 NET 'GROUND' U465-16 NET 'GROUND' C854-1 C855-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_65' U465-2 U465-3 NET 'MGT_FO_CMR_CH_65' C853-1 NET 'GROUND' C853-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_65_IN_DIR' U465-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_IN_CMP' U465-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_65_OCP_ROD_DIR' U465-10 C851-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OCP_ROD_CMP' U465-9 C852-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OCP_HUB_DIR' U465-12 C849-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OCP_HUB_CMP' U465-11 C850-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_65_OUT_ROD_DIR' C851-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_ROD_CMP' C852-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_HUB_DIR' C849-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_HUB_CMP' C850-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_65_Pin_6' U465-6 NET 'No_Conn_FO_CH_65_Pin_7' U465-7 NET 'No_Conn_FO_CH_65_Pin_14' U465-14 NET 'No_Conn_FO_CH_65_Pin_15' U465-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_65_OUT_ROD_DIR' DPV595-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_ROD_CMP' DPV595-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV595-1 DPV595-4 NET 'MGT_FO_CH_65_IN_DIR' DPV593-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_IN_CMP' DPV593-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV593-1 # # MGT FanOut Channel #66 # # # The components in BOTTOM side Channel #66 MGT Fanout are: # # U466 NB7VQ14M 4 way fanout chip # # C856:C859 100 nFd 0201 Output DC Blocking caps # # C860 10 nFd 0402 VRef Input ByPass cap # # C861 47 nFd 0402 Fanout VCC ByPass cap # C862 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U466-8 U466-13 NET 'FAN_1V8' C861-2 C862-1 NET 'GROUND' U466-16 NET 'GROUND' C861-1 C862-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_66' U466-2 U466-3 NET 'MGT_FO_CMR_CH_66' C860-1 NET 'GROUND' C860-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_66_IN_DIR' U466-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_IN_CMP' U466-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_66_OCP_HUB_DIR' U466-10 C858-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OCP_HUB_CMP' U466-9 C859-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OCP_ROD_DIR' U466-12 C856-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OCP_ROD_CMP' U466-11 C857-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_66_OUT_HUB_DIR' C858-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_HUB_CMP' C859-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_ROD_DIR' C856-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_ROD_CMP' C857-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_66_Pin_6' U466-6 NET 'No_Conn_FO_CH_66_Pin_7' U466-7 NET 'No_Conn_FO_CH_66_Pin_14' U466-14 NET 'No_Conn_FO_CH_66_Pin_15' U466-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_66_OUT_ROD_DIR' DPV598-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_ROD_CMP' DPV598-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV598-1 DPV598-4 NET 'MGT_FO_CH_66_OUT_HUB_DIR' DPV597-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_HUB_CMP' DPV597-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV597-1 NET 'MGT_FO_CH_66_IN_DIR' DPV596-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_IN_CMP' DPV596-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV596-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #34/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #67 # # The components in TOP side Channel #67 MGT Fanout are: # # U467 NB7VQ14M 4 way fanout chip # # C863:C866 100 nFd 0201 Output DC Blocking caps # # C867 10 nFd 0402 VRef Input ByPass cap # # C868 47 nFd 0402 Fanout VCC ByPass cap # C869 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U467-8 U467-13 NET 'FAN_1V8' C868-2 C869-2 NET 'GROUND' U467-16 NET 'GROUND' C868-1 C869-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_67' U467-2 U467-3 NET 'MGT_FO_CMR_CH_67' C867-1 NET 'GROUND' C867-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_67_IN_DIR' U467-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_IN_CMP' U467-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_67_OCP_ROD_DIR' U467-10 C865-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OCP_ROD_CMP' U467-9 C866-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OCP_HUB_DIR' U467-12 C863-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OCP_HUB_CMP' U467-11 C864-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_67_OUT_ROD_DIR' C865-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_ROD_CMP' C866-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_HUB_DIR' C863-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_HUB_CMP' C864-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_67_Pin_6' U467-6 NET 'No_Conn_FO_CH_67_Pin_7' U467-7 NET 'No_Conn_FO_CH_67_Pin_14' U467-14 NET 'No_Conn_FO_CH_67_Pin_15' U467-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_67_OUT_ROD_DIR' DPV601-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_ROD_CMP' DPV601-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV601-1 DPV601-4 NET 'MGT_FO_CH_67_OUT_HUB_DIR' DPV600-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_HUB_CMP' DPV600-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV600-1 NET 'MGT_FO_CH_67_IN_DIR' DPV599-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_IN_CMP' DPV599-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV599-1 # # MGT FanOut Channel #68 # # # The components in BOTTOM side Channel #68 MGT Fanout are: # # U468 NB7VQ14M 4 way fanout chip # # C870:C873 100 nFd 0201 Output DC Blocking caps # # C874 10 nFd 0402 VRef Input ByPass cap # # C875 47 nFd 0402 Fanout VCC ByPass cap # C876 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U468-8 U468-13 NET 'FAN_1V8' C875-2 C876-1 NET 'GROUND' U468-16 NET 'GROUND' C875-1 C876-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_68' U468-2 U468-3 NET 'MGT_FO_CMR_CH_68' C874-1 NET 'GROUND' C874-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_68_IN_DIR' U468-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_IN_CMP' U468-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_68_OCP_HUB_DIR' U468-10 C872-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OCP_HUB_CMP' U468-9 C873-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OCP_ROD_DIR' U468-12 C870-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OCP_ROD_CMP' U468-11 C871-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_68_OUT_HUB_DIR' C872-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_HUB_CMP' C873-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_ROD_DIR' C870-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_ROD_CMP' C871-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_68_Pin_6' U468-6 NET 'No_Conn_FO_CH_68_Pin_7' U468-7 NET 'No_Conn_FO_CH_68_Pin_14' U468-14 NET 'No_Conn_FO_CH_68_Pin_15' U468-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_68_OUT_ROD_DIR' DPV604-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_ROD_CMP' DPV604-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV604-1 DPV604-4 NET 'MGT_FO_CH_68_OUT_HUB_DIR' DPV603-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_HUB_CMP' DPV603-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV603-1 NET 'MGT_FO_CH_68_IN_DIR' DPV602-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_IN_CMP' DPV602-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV602-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #35/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #69 # # The components in TOP side Channel #69 MGT Fanout are: # # U469 NB7VQ14M 4 way fanout chip # # C877:C880 100 nFd 0201 Output DC Blocking caps # # C881 10 nFd 0402 VRef Input ByPass cap # # C882 47 nFd 0402 Fanout VCC ByPass cap # C883 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U469-8 U469-13 NET 'FAN_1V8' C882-2 C883-2 NET 'GROUND' U469-16 NET 'GROUND' C882-1 C883-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_69' U469-2 U469-3 NET 'MGT_FO_CMR_CH_69' C881-1 NET 'GROUND' C881-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_69_IN_DIR' U469-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_IN_CMP' U469-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_69_OCP_ROD_DIR' U469-10 C879-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OCP_ROD_CMP' U469-9 C880-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OCP_HUB_DIR' U469-12 C877-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OCP_HUB_CMP' U469-11 C878-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_69_OUT_ROD_DIR' C879-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_ROD_CMP' C880-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_HUB_DIR' C877-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_HUB_CMP' C878-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_69_Pin_6' U469-6 NET 'No_Conn_FO_CH_69_Pin_7' U469-7 NET 'No_Conn_FO_CH_69_Pin_14' U469-14 NET 'No_Conn_FO_CH_69_Pin_15' U469-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_69_OUT_ROD_DIR' DPV607-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_ROD_CMP' DPV607-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV607-1 DPV607-4 NET 'MGT_FO_CH_69_OUT_HUB_DIR' DPV606-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_HUB_CMP' DPV606-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV606-1 NET 'MGT_FO_CH_69_IN_DIR' DPV605-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_IN_CMP' DPV605-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV605-1 # # MGT FanOut Channel #70 # # # The components in BOTTOM side Channel #70 MGT Fanout are: # # U470 NB7VQ14M 4 way fanout chip # # C884:C887 100 nFd 0201 Output DC Blocking caps # # C888 10 nFd 0402 VRef Input ByPass cap # # C889 47 nFd 0402 Fanout VCC ByPass cap # C890 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U470-8 U470-13 NET 'FAN_1V8' C889-2 C890-1 NET 'GROUND' U470-16 NET 'GROUND' C889-1 C890-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_70' U470-2 U470-3 NET 'MGT_FO_CMR_CH_70' C888-1 NET 'GROUND' C888-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_70_IN_DIR' U470-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_IN_CMP' U470-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_70_OCP_HUB_DIR' U470-10 C886-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OCP_HUB_CMP' U470-9 C887-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OCP_ROD_DIR' U470-12 C884-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OCP_ROD_CMP' U470-11 C885-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_70_OUT_HUB_DIR' C886-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_HUB_CMP' C887-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_ROD_DIR' C884-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_ROD_CMP' C885-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_70_Pin_6' U470-6 NET 'No_Conn_FO_CH_70_Pin_7' U470-7 NET 'No_Conn_FO_CH_70_Pin_14' U470-14 NET 'No_Conn_FO_CH_70_Pin_15' U470-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_70_OUT_ROD_DIR' DPV610-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_ROD_CMP' DPV610-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV610-1 DPV610-4 NET 'MGT_FO_CH_70_OUT_HUB_DIR' DPV609-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_HUB_CMP' DPV609-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV609-1 NET 'MGT_FO_CH_70_IN_DIR' DPV608-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_IN_CMP' DPV608-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV608-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #36/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #71 # # The components in TOP side Channel #71 MGT Fanout are: # # U471 NB7VQ14M 4 way fanout chip # # C891:C894 100 nFd 0201 Output DC Blocking caps # # C895 10 nFd 0402 VRef Input ByPass cap # # C896 47 nFd 0402 Fanout VCC ByPass cap # C897 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U471-8 U471-13 NET 'FAN_1V8' C896-2 C897-2 NET 'GROUND' U471-16 NET 'GROUND' C896-1 C897-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_71' U471-2 U471-3 NET 'MGT_FO_CMR_CH_71' C895-1 NET 'GROUND' C895-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_71_IN_DIR' U471-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_IN_CMP' U471-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_71_OCP_ROD_DIR' U471-10 C893-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OCP_ROD_CMP' U471-9 C894-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OCP_HUB_DIR' U471-12 C891-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OCP_HUB_CMP' U471-11 C892-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_71_OUT_ROD_DIR' C893-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_ROD_CMP' C894-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_HUB_DIR' C891-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_HUB_CMP' C892-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_71_Pin_6' U471-6 NET 'No_Conn_FO_CH_71_Pin_7' U471-7 NET 'No_Conn_FO_CH_71_Pin_14' U471-14 NET 'No_Conn_FO_CH_71_Pin_15' U471-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_71_OUT_ROD_DIR' DPV613-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_ROD_CMP' DPV613-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV613-1 DPV613-4 NET 'MGT_FO_CH_71_OUT_HUB_DIR' DPV612-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_HUB_CMP' DPV612-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV612-1 NET 'MGT_FO_CH_71_IN_DIR' DPV611-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_IN_CMP' DPV611-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV611-1 # # MGT FanOut Channel #72 # # # The components in BOTTOM side Channel #72 MGT Fanout are: # # U472 NB7VQ14M 4 way fanout chip # # C898:C901 100 nFd 0201 Output DC Blocking caps # # C902 10 nFd 0402 VRef Input ByPass cap # # C903 47 nFd 0402 Fanout VCC ByPass cap # C904 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U472-8 U472-13 NET 'FAN_1V8' C903-2 C904-1 NET 'GROUND' U472-16 NET 'GROUND' C903-1 C904-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_72' U472-2 U472-3 NET 'MGT_FO_CMR_CH_72' C902-1 NET 'GROUND' C902-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_72_IN_DIR' U472-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_IN_CMP' U472-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_72_OCP_HUB_DIR' U472-10 C900-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OCP_HUB_CMP' U472-9 C901-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OCP_ROD_DIR' U472-12 C898-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OCP_ROD_CMP' U472-11 C899-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_72_OUT_HUB_DIR' C900-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_HUB_CMP' C901-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_ROD_DIR' C898-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_ROD_CMP' C899-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_72_Pin_6' U472-6 NET 'No_Conn_FO_CH_72_Pin_7' U472-7 NET 'No_Conn_FO_CH_72_Pin_14' U472-14 NET 'No_Conn_FO_CH_72_Pin_15' U472-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_72_OUT_ROD_DIR' DPV616-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_ROD_CMP' DPV616-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV616-1 DPV616-4 NET 'MGT_FO_CH_72_OUT_HUB_DIR' DPV615-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_HUB_CMP' DPV615-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV615-1 NET 'MGT_FO_CH_72_IN_DIR' DPV614-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_IN_CMP' DPV614-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV614-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Tue Jan 17 13:04:52 2017 # MIGT> begin substituting from -- instance #37/37 # MIGT>---------------------------------------------- # # Hub Module # # MGT Fanout Nets Template File # --------------------------------------- # # # Original Rev. 24-Mar-2015 # Most Recent Rev. 17-Jan-2017 # # # This file is the Nets for two channels of the Hub Module MGT Fanout. # One channel (e.g. Ch #1) is on the Top side of the card and # the other channel (e.g. Ch #2) is on the Bottom side of the card. # # # NOTE: The Ground connections to pins 17, 18, 19, 20 # of the fanout chips are not made in this file. # There is a separate nets file that holds just # these fanout chip DAP pad ground connections. # # # MGT FanOut Channel #73 # # The components in TOP side Channel #73 MGT Fanout are: # # U473 NB7VQ14M 4 way fanout chip # # C905:C908 100 nFd 0201 Output DC Blocking caps # # C909 10 nFd 0402 VRef Input ByPass cap # # C910 47 nFd 0402 Fanout VCC ByPass cap # C911 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U473-8 U473-13 NET 'FAN_1V8' C910-2 C911-2 NET 'GROUND' U473-16 NET 'GROUND' C910-1 C911-1 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_73' U473-2 U473-3 NET 'MGT_FO_CMR_CH_73' C909-1 NET 'GROUND' C909-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_73_IN_DIR' U473-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_IN_CMP' U473-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_73_OCP_ROD_DIR' U473-10 C907-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OCP_ROD_CMP' U473-9 C908-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OCP_HUB_DIR' U473-12 C905-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OCP_HUB_CMP' U473-11 C906-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_73_OUT_ROD_DIR' C907-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_ROD_CMP' C908-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_HUB_DIR' C905-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_HUB_CMP' C906-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_73_Pin_6' U473-6 NET 'No_Conn_FO_CH_73_Pin_7' U473-7 NET 'No_Conn_FO_CH_73_Pin_14' U473-14 NET 'No_Conn_FO_CH_73_Pin_15' U473-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_73_OUT_ROD_DIR' DPV619-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_ROD_CMP' DPV619-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV619-1 DPV619-4 NET 'MGT_FO_CH_73_OUT_HUB_DIR' DPV618-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_HUB_CMP' DPV618-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV618-1 NET 'MGT_FO_CH_73_IN_DIR' DPV617-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_IN_CMP' DPV617-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV617-1 # # MGT FanOut Channel #74 # # # The components in BOTTOM side Channel #74 MGT Fanout are: # # U474 NB7VQ14M 4 way fanout chip # # C912:C915 100 nFd 0201 Output DC Blocking caps # # C916 10 nFd 0402 VRef Input ByPass cap # # C917 47 nFd 0402 Fanout VCC ByPass cap # C918 100 nFd 0402 Fanout VCC ByPass cap # # # Connect the 2.5 Volt VCC power, bypass caps, and grounds # NET 'FAN_1V8' U474-8 U474-13 NET 'FAN_1V8' C917-2 C918-1 NET 'GROUND' U474-16 NET 'GROUND' C917-1 C918-2 # # Connect the Input Common Mode Reference and its ByPass Cap # NET 'MGT_FO_CMR_CH_74' U474-2 U474-3 NET 'MGT_FO_CMR_CH_74' C916-1 NET 'GROUND' C916-2 # # Define the Input Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_74_IN_DIR' U474-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_IN_CMP' U474-4 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect the Fanout Chip's Outputs to the DC Blocking Caps # NET 'MGT_FO_CH_74_OCP_HUB_DIR' U474-10 C914-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OCP_HUB_CMP' U474-9 C915-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OCP_ROD_DIR' U474-12 C912-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OCP_ROD_CMP' U474-11 C913-1 (NET_TYPE, 'DIFF_PAIR_HS') # # Define the Output Net-Name to this Channel of the MGT Fanout # NET 'MGT_FO_CH_74_OUT_HUB_DIR' C914-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_HUB_CMP' C915-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_ROD_DIR' C912-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_ROD_CMP' C913-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Assign Net-Names to the UnUsed Pins on the Fanout Chip # NET 'No_Conn_FO_CH_74_Pin_6' U474-6 NET 'No_Conn_FO_CH_74_Pin_7' U474-7 NET 'No_Conn_FO_CH_74_Pin_14' U474-14 NET 'No_Conn_FO_CH_74_Pin_15' U474-15 # # Define the connections to the Via Arrays # NET 'MGT_FO_CH_74_OUT_ROD_DIR' DPV622-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_ROD_CMP' DPV622-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV622-1 DPV622-4 NET 'MGT_FO_CH_74_OUT_HUB_DIR' DPV621-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_HUB_CMP' DPV621-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV621-1 NET 'MGT_FO_CH_74_IN_DIR' DPV620-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_IN_CMP' DPV620-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'GROUND' DPV620-1 # MIGT>---------------------------------------------- # MIGT> done substituting from # # Additional Statements for the # # MGT Fanout Nets File # # # # Original Version: 23-Apr_2016 # Current Version: 23-Nov-2016 GTH->MGT # # # # This file contains additional statements that are needed # in the discription of the MGT Fanout Nets. # # Most of these nets statements have to do with # components at the edges of the MGT Fanout Array, # e.g. the ground vias at the East and West edges # of the array that complete the ground returns on # both sides of a differential via pair. # # These nets statements are not included in the # aa_build_gth_fanout_nets.sh file because the # sed editor called by that script seems to have # trouble with append comands that include appenging # a line that includes single quotes, i.e. '. # The single quotes are needed around netnames in # the net statements. # # ## ## ADD to the end of the MGT Fanout netlist some ## one-of-a-kind connections that were not generated ## during the Mighty multiple instances process. ## ## Ground the "Single Ground" needed at the ## end of a string of 3 pin DPVs to put 2 grounds ## around each differential pair via. NET 'GROUND' DPVSG419-1 NET 'GROUND' DPVSG443-1 NET 'GROUND' DPVSG467-1 NET 'GROUND' DPVSG491-1 NET 'GROUND' DPVSG515-1 NET 'GROUND' DPVSG539-1 NET 'GROUND' DPVSG563-1 NET 'GROUND' DPVSG587-1 NET 'GROUND' DPVSG617-1 ## ## Pulled from the above Add List the following on 11-Apr-2016 ## ## DPVSG414-1, 438, 462, 486, 510, 534, 558, 582, 606, 618 ## ## ## Re-Connect the Lower DPV just along the West edge ## now with their signal pins in the right order. ## ## These DPV pins had been disconnected above. ## NET 'MGT_FO_CH_1_OUT_HUB_DIR' DPV402-2 NET 'MGT_FO_CH_1_OUT_HUB_CMP' DPV402-3 NET 'GROUND' DPV402-1 NET 'MGT_FO_CH_9_OUT_HUB_DIR' DPV426-2 NET 'MGT_FO_CH_9_OUT_HUB_CMP' DPV426-3 NET 'GROUND' DPV426-1 NET 'MGT_FO_CH_17_OUT_HUB_DIR' DPV450-2 NET 'MGT_FO_CH_17_OUT_HUB_CMP' DPV450-3 NET 'GROUND' DPV450-1 NET 'MGT_FO_CH_25_OUT_HUB_DIR' DPV474-2 NET 'MGT_FO_CH_25_OUT_HUB_CMP' DPV474-3 NET 'GROUND' DPV474-1 NET 'MGT_FO_CH_33_OUT_HUB_DIR' DPV498-2 NET 'MGT_FO_CH_33_OUT_HUB_CMP' DPV498-3 NET 'GROUND' DPV498-1 NET 'MGT_FO_CH_41_OUT_HUB_DIR' DPV522-2 NET 'MGT_FO_CH_41_OUT_HUB_CMP' DPV522-3 NET 'GROUND' DPV522-1 NET 'MGT_FO_CH_49_OUT_HUB_DIR' DPV546-2 NET 'MGT_FO_CH_49_OUT_HUB_CMP' DPV546-3 NET 'GROUND' DPV546-1 NET 'MGT_FO_CH_57_OUT_HUB_DIR' DPV570-2 NET 'MGT_FO_CH_57_OUT_HUB_CMP' DPV570-3 NET 'GROUND' DPV570-1 NET 'MGT_FO_CH_65_OUT_HUB_DIR' DPV594-2 NET 'MGT_FO_CH_65_OUT_HUB_CMP' DPV594-3 NET 'GROUND' DPV594-1 ## ## Ground Pin #4 of the Differential Pair Via components ## at the East end of each of the rows. These are INPUTs ## to the FEX FanOut. In the regular section of the ## FanOut Array a component is used with only one Ground ## pin. Along the East edge a Diff Pair Via component ## is used that has 2 Ground pins and this 2nd Ground ## pin must be explicitly connected. ## NET 'GROUND' DPV422-4 NET 'GROUND' DPV446-4 NET 'GROUND' DPV470-4 NET 'GROUND' DPV494-4 NET 'GROUND' DPV518-4 NET 'GROUND' DPV542-4 NET 'GROUND' DPV566-4 NET 'GROUND' DPV590-4 NET 'GROUND' DPV620-4 # # MGT Fanout Equalizer Enable Groups # ---------------------------------------- # # # Original Rev. 24-Mar-2015 # Current Rev. 23-Nov-2016 GTH->MGT # # # This section of the MGT Fanout nets defines a net for # each of the 13 sections of the MGT Fanout that is used # to Enable or Disable the Equalizers in the Fanout Chips # of that section of the overall 74 Channel MGT Fanout. # # That is, we can enable/disable the equalizers on a # per Source Slot basis - not on a per Lane basis. # # The equalizers on all 6 of the Lanes from a given # Source Slot in the ATCA crate are either all enabled # or else all disabled. # # The Equalizer Enable signals are driven by the Hub FPGA's # HP IO Bank 71 which has 1.8 Volt CMOS outputs. # # The equalizer is enabled when the control pin on the # NB7VQ14M is voltage HI. The threshold levels of the # equalizer enable control input pins are: < 0.35 x Vcc # and > 0.65 x Vcc. # # The guaranteed minimum output voltage from the FPGA's # Bank 71 HP Select IO pins with 1.8 Volt Vcco is # Vcc - 0.450 Volts or 1.350 minimum HI state output # voltage. 1.350 Volts is 0.65 of 2.077 Volts. # # Thus with the NB7VQ14M running on 1.8 Volt Vcc (or any # reasonable range around 1.8 Volts) its Equalizer Enable # control input can be directly driven by the FPGA. # # # Recall which MGT Fanout Channels handle # which FEX Data Source: # # FEX Data MGT Fanout # Source Channels # -------- ---------- # # 3 1 : 6 # 4 7 : 12 # 5 13 : 18 # 6 19 : 24 # 7 25 : 30 # 8 31 : 36 # # Other Hub 37 : 38 # # 9 39 : 44 # 10 45 : 50 # 11 51 : 56 # 12 57 : 62 # 13 63 : 68 # 14 69 : 74 # # # Recall that the U4xy Reference Designator of a NB7VQ14M # fanout chip is the same plus 400 as the MGT Fanout Channel # Number serviced by that fanout chip. # # # # The assignment of the "Equalizer Enable Groups" is: # # EQU_ENB_GRP_1 FEX_3 # EQU_ENB_GRP_2 FEX_4 # EQU_ENB_GRP_3 FEX_5 # EQU_ENB_GRP_4 FEX_6 # EQU_ENB_GRP_5 FEX_7 # EQU_ENB_GRP_6 FEX_8 # # EQU_ENB_GRP_7 Other Hub's 2 readout lanes # # EQU_ENB_GRP_8 FEX_9 # EQU_ENB_GRP_9 FEX_10 # EQU_ENB_GRP_10 FEX_11 # EQU_ENB_GRP_11 FEX_12 # EQU_ENB_GRP_12 FEX_13 # EQU_ENB_GRP_13 FEX_14 # # # Assign Net-Names to the Equalizer Enable Groups # NET 'MGT_FO_EQU_ENB_GRP_1' U401-5 U402-5 U403-5 NET 'MGT_FO_EQU_ENB_GRP_1' U404-5 U405-5 U406-5 NET 'MGT_FO_EQU_ENB_GRP_2' U407-5 U408-5 U409-5 NET 'MGT_FO_EQU_ENB_GRP_2' U410-5 U411-5 U412-5 NET 'MGT_FO_EQU_ENB_GRP_3' U413-5 U414-5 U415-5 NET 'MGT_FO_EQU_ENB_GRP_3' U416-5 U417-5 U418-5 NET 'MGT_FO_EQU_ENB_GRP_4' U419-5 U420-5 U421-5 NET 'MGT_FO_EQU_ENB_GRP_4' U422-5 U423-5 U424-5 NET 'MGT_FO_EQU_ENB_GRP_5' U425-5 U426-5 U427-5 NET 'MGT_FO_EQU_ENB_GRP_5' U428-5 U429-5 U430-5 NET 'MGT_FO_EQU_ENB_GRP_6' U431-5 U432-5 U433-5 NET 'MGT_FO_EQU_ENB_GRP_6' U434-5 U435-5 U436-5 NET 'MGT_FO_EQU_ENB_GRP_7' U437-5 U438-5 NET 'MGT_FO_EQU_ENB_GRP_8' U439-5 U440-5 U441-5 NET 'MGT_FO_EQU_ENB_GRP_8' U442-5 U443-5 U444-5 NET 'MGT_FO_EQU_ENB_GRP_9' U445-5 U446-5 U447-5 NET 'MGT_FO_EQU_ENB_GRP_9' U448-5 U449-5 U450-5 NET 'MGT_FO_EQU_ENB_GRP_10' U451-5 U452-5 U453-5 NET 'MGT_FO_EQU_ENB_GRP_10' U454-5 U455-5 U456-5 NET 'MGT_FO_EQU_ENB_GRP_11' U457-5 U458-5 U459-5 NET 'MGT_FO_EQU_ENB_GRP_11' U460-5 U461-5 U462-5 NET 'MGT_FO_EQU_ENB_GRP_12' U463-5 U464-5 U465-5 NET 'MGT_FO_EQU_ENB_GRP_12' U466-5 U467-5 U468-5 NET 'MGT_FO_EQU_ENB_GRP_13' U469-5 U470-5 U471-5 NET 'MGT_FO_EQU_ENB_GRP_13' U472-5 U473-5 U474-5 # # Assign Net-Names to the Hub FPGA Select I/O pins # that control the MGT Fanout Equalizer Enable Groups. # NET 'MGT_FO_EQU_ENB_GRP_1' U1-C25 # IO_L21N_T3L_N5_AD8N_71 NET 'MGT_FO_EQU_ENB_GRP_2' U1-A25 # IO_L23N_T3U_N9_71 NET 'MGT_FO_EQU_ENB_GRP_3' U1-B25 # IO_L23P_T3U_N8_71 NET 'MGT_FO_EQU_ENB_GRP_4' U1-A24 # IO_L20P_T3L_N2_AD1P_71 NET 'MGT_FO_EQU_ENB_GRP_5' U1-C24 # IO_L19N_T3L_N1_DBC_AD9N_71 NET 'MGT_FO_EQU_ENB_GRP_6' U1-B22 # IO_L24N_T3U_N11_71 NET 'MGT_FO_EQU_ENB_GRP_7' U1-D20 # IO_L20P_T3L_N2_AD1P_72 NET 'MGT_FO_EQU_ENB_GRP_8' U1-C20 # IO_L19P_T3L_N0_DBC_AD9P_72 NET 'MGT_FO_EQU_ENB_GRP_9' U1-A23 # IO_L20N_T3L_N3_AD1N_71 NET 'MGT_FO_EQU_ENB_GRP_10' U1-A21 # IO_L21N_T3L_N5_AD8N_72 NET 'MGT_FO_EQU_ENB_GRP_11' U1-A20 # IO_L23P_T3U_N8_72 NET 'MGT_FO_EQU_ENB_GRP_12' U1-A19 # IO_L23N_T3U_N9_72 NET 'MGT_FO_EQU_ENB_GRP_13' U1-A18 # IO_L24N_T3U_N11_72 # # Wait Here # ## B23 # IO_L22N_T3U_N7_DBC_AD0N_71 ## C23 # IO_L22P_T3U_N6_DBC_AD0P_71 ## C22 # IO_L24P_T3U_N10_71 ## D22 # IO_T3U_N12_71 ## Return ## E23 # IO_L16N_T2U_N7_QBC_AD3N_71 ## D24 # IO_L19P_T3L_N0_DBC_AD9P_71 ## E22 # IO_T2U_N12_71 # # Hub Module # # MGT Fanout Chip DAP Pad Ground Net Connections # -------------------------------------------------- # # # Original Rev. 13-Apr-2015 # Most Recent Rev. 23-Nov-2016 GTH->MGT # # # This file is the Ground Net connections the the 4 # Through Holes in the DAP Pad for the MGT Fanout Chips. # # The Ground connections to pins 17, 18, 19, 20, # i.e. the 4 DAP Pad Through Holes, are not made # in the MGT Fanout Multi Instance Template file. # # NET 'GROUND' U401-17 U401-18 NET 'GROUND' U401-19 U401-20 NET 'GROUND' U402-17 U402-18 NET 'GROUND' U402-19 U402-20 NET 'GROUND' U403-17 U403-18 NET 'GROUND' U403-19 U403-20 NET 'GROUND' U404-17 U404-18 NET 'GROUND' U404-19 U404-20 NET 'GROUND' U405-17 U405-18 NET 'GROUND' U405-19 U405-20 NET 'GROUND' U406-17 U406-18 NET 'GROUND' U406-19 U406-20 NET 'GROUND' U407-17 U407-18 NET 'GROUND' U407-19 U407-20 NET 'GROUND' U408-17 U408-18 NET 'GROUND' U408-19 U408-20 NET 'GROUND' U409-17 U409-18 NET 'GROUND' U409-19 U409-20 NET 'GROUND' U410-17 U410-18 NET 'GROUND' U410-19 U410-20 NET 'GROUND' U411-17 U411-18 NET 'GROUND' U411-19 U411-20 NET 'GROUND' U412-17 U412-18 NET 'GROUND' U412-19 U412-20 NET 'GROUND' U413-17 U413-18 NET 'GROUND' U413-19 U413-20 NET 'GROUND' U414-17 U414-18 NET 'GROUND' U414-19 U414-20 NET 'GROUND' U415-17 U415-18 NET 'GROUND' U415-19 U415-20 NET 'GROUND' U416-17 U416-18 NET 'GROUND' U416-19 U416-20 NET 'GROUND' U417-17 U417-18 NET 'GROUND' U417-19 U417-20 NET 'GROUND' U418-17 U418-18 NET 'GROUND' U418-19 U418-20 NET 'GROUND' U419-17 U419-18 NET 'GROUND' U419-19 U419-20 NET 'GROUND' U420-17 U420-18 NET 'GROUND' U420-19 U420-20 NET 'GROUND' U421-17 U421-18 NET 'GROUND' U421-19 U421-20 NET 'GROUND' U422-17 U422-18 NET 'GROUND' U422-19 U422-20 NET 'GROUND' U423-17 U423-18 NET 'GROUND' U423-19 U423-20 NET 'GROUND' U424-17 U424-18 NET 'GROUND' U424-19 U424-20 NET 'GROUND' U425-17 U425-18 NET 'GROUND' U425-19 U425-20 NET 'GROUND' U426-17 U426-18 NET 'GROUND' U426-19 U426-20 NET 'GROUND' U427-17 U427-18 NET 'GROUND' U427-19 U427-20 NET 'GROUND' U428-17 U428-18 NET 'GROUND' U428-19 U428-20 NET 'GROUND' U429-17 U429-18 NET 'GROUND' U429-19 U429-20 NET 'GROUND' U430-17 U430-18 NET 'GROUND' U430-19 U430-20 NET 'GROUND' U431-17 U431-18 NET 'GROUND' U431-19 U431-20 NET 'GROUND' U432-17 U432-18 NET 'GROUND' U432-19 U432-20 NET 'GROUND' U433-17 U433-18 NET 'GROUND' U433-19 U433-20 NET 'GROUND' U434-17 U434-18 NET 'GROUND' U434-19 U434-20 NET 'GROUND' U435-17 U435-18 NET 'GROUND' U435-19 U435-20 NET 'GROUND' U436-17 U436-18 NET 'GROUND' U436-19 U436-20 NET 'GROUND' U437-17 U437-18 NET 'GROUND' U437-19 U437-20 NET 'GROUND' U438-17 U438-18 NET 'GROUND' U438-19 U438-20 NET 'GROUND' U439-17 U439-18 NET 'GROUND' U439-19 U439-20 NET 'GROUND' U440-17 U440-18 NET 'GROUND' U440-19 U440-20 NET 'GROUND' U441-17 U441-18 NET 'GROUND' U441-19 U441-20 NET 'GROUND' U442-17 U442-18 NET 'GROUND' U442-19 U442-20 NET 'GROUND' U443-17 U443-18 NET 'GROUND' U443-19 U443-20 NET 'GROUND' U444-17 U444-18 NET 'GROUND' U444-19 U444-20 NET 'GROUND' U445-17 U445-18 NET 'GROUND' U445-19 U445-20 NET 'GROUND' U446-17 U446-18 NET 'GROUND' U446-19 U446-20 NET 'GROUND' U447-17 U447-18 NET 'GROUND' U447-19 U447-20 NET 'GROUND' U448-17 U448-18 NET 'GROUND' U448-19 U448-20 NET 'GROUND' U449-17 U449-18 NET 'GROUND' U449-19 U449-20 NET 'GROUND' U450-17 U450-18 NET 'GROUND' U450-19 U450-20 NET 'GROUND' U451-17 U451-18 NET 'GROUND' U451-19 U451-20 NET 'GROUND' U452-17 U452-18 NET 'GROUND' U452-19 U452-20 NET 'GROUND' U453-17 U453-18 NET 'GROUND' U453-19 U453-20 NET 'GROUND' U454-17 U454-18 NET 'GROUND' U454-19 U454-20 NET 'GROUND' U455-17 U455-18 NET 'GROUND' U455-19 U455-20 NET 'GROUND' U456-17 U456-18 NET 'GROUND' U456-19 U456-20 NET 'GROUND' U457-17 U457-18 NET 'GROUND' U457-19 U457-20 NET 'GROUND' U458-17 U458-18 NET 'GROUND' U458-19 U458-20 NET 'GROUND' U459-17 U459-18 NET 'GROUND' U459-19 U459-20 NET 'GROUND' U460-17 U460-18 NET 'GROUND' U460-19 U460-20 NET 'GROUND' U461-17 U461-18 NET 'GROUND' U461-19 U461-20 NET 'GROUND' U462-17 U462-18 NET 'GROUND' U462-19 U462-20 NET 'GROUND' U463-17 U463-18 NET 'GROUND' U463-19 U463-20 NET 'GROUND' U464-17 U464-18 NET 'GROUND' U464-19 U464-20 NET 'GROUND' U465-17 U465-18 NET 'GROUND' U465-19 U465-20 NET 'GROUND' U466-17 U466-18 NET 'GROUND' U466-19 U466-20 NET 'GROUND' U467-17 U467-18 NET 'GROUND' U467-19 U467-20 NET 'GROUND' U468-17 U468-18 NET 'GROUND' U468-19 U468-20 NET 'GROUND' U469-17 U469-18 NET 'GROUND' U469-19 U469-20 NET 'GROUND' U470-17 U470-18 NET 'GROUND' U470-19 U470-20 NET 'GROUND' U471-17 U471-18 NET 'GROUND' U471-19 U471-20 NET 'GROUND' U472-17 U472-18 NET 'GROUND' U472-19 U472-20 NET 'GROUND' U473-17 U473-18 NET 'GROUND' U473-19 U473-20 NET 'GROUND' U474-17 U474-18 NET 'GROUND' U474-19 U474-20 # # MGT Fanout Zone 2 Input Nets # ----------------------------------- # # # Original Rev. 13-Apr-2015 # Current Rev. 23-Nov-2016 GTH->MGT # # # # # This section of the MGT Fanout nets defines the # inputs to the fanout chips from the ATCA Zone 2 # backplane connectors. # # Recall that the input pins to each fanout chip # were assigned a "MGT Fanout Channel Number" based # netname during the fanout multi-instance net generation # process. In this file we just need to assign the # Zone 2 connector end of these traces. # # These 148 nets are listed in order of MGT Fanout Channel Number. # # # The new aggrement with Ed and Ian is: # # - use the 6 lane Aurora setup from the FEX cards assigned # to the ATCA Channel Ports in the following way: # # Aurora Lane 0, 1, 2, 3, 4, 5 # # FEX End ATCA Tx0, Tx1, Tx2, Tx3, Rx2, Rx3 # # Hub End ATCA Rx0, Rx1, Rx2, Rx3, Tx2, Tx3 # # Hub Zone 2 Pins c,d g,h c,d g,h a,b e,f # Hub Zone 2 Row low low up up up up # # # - Can no longer mix the FEX and Hub pins on the # MegArray connectors to the ROD. # # - At a minimum must land each FEX on the ROD # as a contiguous group of 6 ROD inputs. # # # Note that some signals are "inverted" as they leave # this net list file. This is to eliminate the need # to flip these traces during routing. # # - In the lower physical half of the MGT Fanout Array, # i.e. FEX-03 through FEX-08, the EVEN numbered # MGT Fanout Channel inputs are inverted. # # That is, in the MGT Fanout Channel range 1:36, # the EVEN numbered MGT Fanout Channel have inverted # inputs. # # # - In the upper physical half of the MGT Fanout Array, # i.e. FEX-09 through FEX-12, the ODD numbered # MGT Fanout Channel inputs are inverted. # # That is, in the MGT Fanout Channel range 39:74, # the ODD numbered MGT Fanout Channel have inverted # inputs. # # # - NOTE that MGT Fanout Ch #72, i.e. FEX-12 Lane 3 # is an exception. MGT Fanout Ch #72 is inverted to # allow a clean route into the 10 cells in the top, # i.e. 9th row of the MGT Fanout Array. # # # - From the "Other Hub" the input to MGT Fanout # Channel 37 was inverted to facilitate routing. # # # The main difference between the upper and lower halves # (i.e. between FEX-03:FEX-08 and FEX-09:FEX12) is # caused by routing out of Zone 2 connectors either # above or under the connector pins. # # Both of the Other Hub readout channels are handled # in the middle of this MGT Fanout Array. # # # # FEX-03 Logical Slot Number 3 # # MGT Fanout Channel 1 is the FEX-03 Aurora Lane 0 ATCA Rx0[02] Sig_7 NET 'MGT_FO_CH_1_IN_DIR' J23-C2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_IN_CMP' J23-D2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 2 is the FEX-03 Aurora Lane 1 ATCA Rx1[02] Sig_8 NET 'MGT_FO_CH_2_IN_CMP' J23-G2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_IN_DIR' J23-H2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 3 is the FEX-03 Aurora Lane 2 ATCA Rx2[02] Sig_9 NET 'MGT_FO_CH_3_IN_DIR' J23-C1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_IN_CMP' J23-D1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 4 is the FEX-03 Aurora Lane 3 ATCA Rx3[02] Sig_10 NET 'MGT_FO_CH_4_IN_CMP' J23-G1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_IN_DIR' J23-H1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 5 is the FEX-03 Aurora Lane 4 ATCA Tx2[02] Sig_7 NET 'MGT_FO_CH_5_IN_DIR' J23-A1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_IN_CMP' J23-B1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 6 is the FEX-03 Aurora Lane 5 ATCA Tx3[02] Sig_8 NET 'MGT_FO_CH_6_IN_CMP' J23-E1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_IN_DIR' J23-F1 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-04 Logical Slot Number 4 # # MGT Fanout Channel 7 is the FEX-04 Aurora Lane 0 ATCA Rx0[03] Sig_9 NET 'MGT_FO_CH_7_IN_DIR' J22-C10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_IN_CMP' J22-D10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 8 is the FEX-04 Aurora Lane 1 ATCA Rx1[03] Sig_10 NET 'MGT_FO_CH_8_IN_CMP' J22-G10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_IN_DIR' J22-H10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 9 is the FEX-04 Aurora Lane 2 ATCA Rx2[03] Sig_7 NET 'MGT_FO_CH_9_IN_DIR' J22-C9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_IN_CMP' J22-D9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 10 is the FEX-04 Aurora Lane 3 ATCA Rx3[03] Sig_8 NET 'MGT_FO_CH_10_IN_CMP' J22-G9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_IN_DIR' J22-H9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 11 is the FEX-04 Aurora Lane 4 ATCA Tx2[03] Sig_9 NET 'MGT_FO_CH_11_IN_DIR' J22-A9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_IN_CMP' J22-B9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 12 is the FEX-04 Aurora Lane 5 ATCA Tx3[03] Sig_10 NET 'MGT_FO_CH_12_IN_CMP' J22-E9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_IN_DIR' J22-F9 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-05 Logical Slot Number 5 # # MGT Fanout Channel 13 is the FEX-05 Aurora Lane 0 ATCA Rx0[04] Sig_7 NET 'MGT_FO_CH_13_IN_DIR' J22-C8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_IN_CMP' J22-D8 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 14 is the FEX-05 Aurora Lane 1 ATCA Rx1[04] Sig_8 NET 'MGT_FO_CH_14_IN_CMP' J22-G8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_IN_DIR' J22-H8 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 15 is the FEX-05 Aurora Lane 2 ATCA Rx2[04] Sig_9 NET 'MGT_FO_CH_15_IN_DIR' J22-C7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_IN_CMP' J22-D7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 16 is the FEX-05 Aurora Lane 3 ATCA Rx3[04] Sig_10 NET 'MGT_FO_CH_16_IN_CMP' J22-G7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_IN_DIR' J22-H7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 17 is the FEX-05 Aurora Lane 4 ATCA Tx2[04] Sig_7 NET 'MGT_FO_CH_17_IN_DIR' J22-A7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_IN_CMP' J22-B7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 18 is the FEX-05 Aurora Lane 5 ATCA Tx3[04] Sig_8 NET 'MGT_FO_CH_18_IN_CMP' J22-E7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_IN_DIR' J22-F7 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-06 Logical Slot Number 6 # # MGT Fanout Channel 19 is the FEX-06 Aurora Lane 0 ATCA Rx0[05] Sig_9 NET 'MGT_FO_CH_19_IN_DIR' J22-C6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_IN_CMP' J22-D6 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 20 is the FEX-06 Aurora Lane 1 ATCA Rx1[05] Sig_10 NET 'MGT_FO_CH_20_IN_CMP' J22-G6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_IN_DIR' J22-H6 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 21 is the FEX-06 Aurora Lane 2 ATCA Rx2[05] Sig_7 NET 'MGT_FO_CH_21_IN_DIR' J22-C5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_IN_CMP' J22-D5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 22 is the FEX-06 Aurora Lane 3 ATCA Rx3[05] Sig_8 NET 'MGT_FO_CH_22_IN_CMP' J22-G5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_IN_DIR' J22-H5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 23 is the FEX-06 Aurora Lane 4 ATCA Tx2[05] Sig_9 NET 'MGT_FO_CH_23_IN_DIR' J22-A5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_IN_CMP' J22-B5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 24 is the FEX-06 Aurora Lane 5 ATCA Tx3[05] Sig_10 NET 'MGT_FO_CH_24_IN_CMP' J22-E5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_IN_DIR' J22-F5 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-07 Logical Slot Number 7 # # MGT Fanout Channel 25 is the FEX-07 Aurora Lane 0 ATCA Rx0[06] Sig_7 NET 'MGT_FO_CH_25_IN_DIR' J22-C4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_IN_CMP' J22-D4 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 26 is the FEX-07 Aurora Lane 1 ATCA Rx1[06] Sig_8 NET 'MGT_FO_CH_26_IN_CMP' J22-G4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_IN_DIR' J22-H4 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 27 is the FEX-07 Aurora Lane 2 ATCA Rx2[06] Sig_9 NET 'MGT_FO_CH_27_IN_DIR' J22-C3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_IN_CMP' J22-D3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 28 is the FEX-07 Aurora Lane 3 ATCA Rx3[06] Sig_10 NET 'MGT_FO_CH_28_IN_CMP' J22-G3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_IN_DIR' J22-H3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 29 is the FEX-07 Aurora Lane 4 ATCA Tx2[06] Sig_7 NET 'MGT_FO_CH_29_IN_DIR' J22-A3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_IN_CMP' J22-B3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 30 is the FEX-07 Aurora Lane 5 ATCA Tx3[06] Sig_8 NET 'MGT_FO_CH_30_IN_CMP' J22-E3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_IN_DIR' J22-F3 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-08 Logical Slot Number 8 # # MGT Fanout Channel 31 is the FEX-08 Aurora Lane 0 ATCA Rx0[07] Sig_9 NET 'MGT_FO_CH_31_IN_DIR' J22-C2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_IN_CMP' J22-D2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 32 is the FEX-08 Aurora Lane 1 ATCA Rx1[07] Sig_10 NET 'MGT_FO_CH_32_IN_CMP' J22-G2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_IN_DIR' J22-H2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 33 is the FEX-08 Aurora Lane 2 ATCA Rx2[07] Sig_7 NET 'MGT_FO_CH_33_IN_DIR' J22-C1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_IN_CMP' J22-D1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 34 is the FEX-08 Aurora Lane 3 ATCA Rx3[07] Sig_8 NET 'MGT_FO_CH_34_IN_CMP' J22-G1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_IN_DIR' J22-H1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 35 is the FEX-08 Aurora Lane 4 ATCA Tx2[07] Sig_9 NET 'MGT_FO_CH_35_IN_DIR' J22-A1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_IN_CMP' J22-B1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 36 is the FEX-08 Aurora Lane 5 ATCA Tx3[07] Sig_10 NET 'MGT_FO_CH_36_IN_CMP' J22-E1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_IN_DIR' J22-F1 (NET_TYPE, 'DIFF_PAIR_HS') # # Other Hub # # MGT Fanout Channel 37 is the Other Hub's Aurora Lane 0 ATCA Rx2[01] Sig_7 NET 'MGT_FO_CH_37_IN_CMP' J23-C3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_IN_DIR' J23-D3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 38 is the Other Hub's Aurora Lane 1 ATCA Rx3[01] Sig_8 NET 'MGT_FO_CH_38_IN_DIR' J23-G3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_IN_CMP' J23-H3 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-09 Logical Slot Number 9 # # MGT Fanout Channel 39 is the FEX-09 Aurora Lane 0 ATCA Rx0[08] Sig_9 NET 'MGT_FO_CH_39_IN_CMP' J21-C10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_IN_DIR' J21-D10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 40 is the FEX-09 Aurora Lane 1 ATCA Rx1[08] Sig_10 NET 'MGT_FO_CH_40_IN_DIR' J21-G10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_IN_CMP' J21-H10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 41 is the FEX-09 Aurora Lane 2 ATCA Rx2[08] Sig_7 NET 'MGT_FO_CH_41_IN_CMP' J21-C9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_IN_DIR' J21-D9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 42 is the FEX-09 Aurora Lane 3 ATCA Rx3[08] Sig_8 NET 'MGT_FO_CH_42_IN_DIR' J21-G9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_IN_CMP' J21-H9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 43 is the FEX-09 Aurora Lane 4 ATCA Tx2[08] Sig_9 NET 'MGT_FO_CH_43_IN_CMP' J21-A9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_IN_DIR' J21-B9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 44 is the FEX-09 Aurora Lane 5 ATCA Tx3[08] Sig_10 NET 'MGT_FO_CH_44_IN_DIR' J21-E9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_IN_CMP' J21-F9 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-10 Logical Slot Number 10 # # MGT Fanout Channel 45 is the FEX-10 Aurora Lane 0 ATCA Rx0[09] Sig_7 NET 'MGT_FO_CH_45_IN_CMP' J21-C8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_IN_DIR' J21-D8 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 46 is the FEX-10 Aurora Lane 1 ATCA Rx1[09] Sig_8 NET 'MGT_FO_CH_46_IN_DIR' J21-G8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_IN_CMP' J21-H8 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 47 is the FEX-10 Aurora Lane 2 ATCA Rx2[09] Sig_9 NET 'MGT_FO_CH_47_IN_CMP' J21-C7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_IN_DIR' J21-D7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 48 is the FEX-10 Aurora Lane 3 ATCA Rx3[09] Sig_10 NET 'MGT_FO_CH_48_IN_DIR' J21-G7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_IN_CMP' J21-H7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 49 is the FEX-10 Aurora Lane 4 ATCA Tx2[09] Sig_7 NET 'MGT_FO_CH_49_IN_CMP' J21-A7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_IN_DIR' J21-B7 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 50 is the FEX-10 Aurora Lane 5 ATCA Tx3[09] Sig_8 NET 'MGT_FO_CH_50_IN_DIR' J21-E7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_IN_CMP' J21-F7 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-11 Logical Slot Number 11 # # MGT Fanout Channel 51 is the FEX-11 Aurora Lane 0 ATCA Rx0[10] Sig_9 NET 'MGT_FO_CH_51_IN_CMP' J21-C6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_IN_DIR' J21-D6 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 52 is the FEX-11 Aurora Lane 1 ATCA Rx1[10] Sig_10 NET 'MGT_FO_CH_52_IN_DIR' J21-G6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_IN_CMP' J21-H6 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 53 is the FEX-11 Aurora Lane 2 ATCA Rx2[10] Sig_7 NET 'MGT_FO_CH_53_IN_CMP' J21-C5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_IN_DIR' J21-D5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 54 is the FEX-11 Aurora Lane 3 ATCA Rx3[10] Sig_8 NET 'MGT_FO_CH_54_IN_DIR' J21-G5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_IN_CMP' J21-H5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 55 is the FEX-11 Aurora Lane 4 ATCA Tx2[10] Sig_9 NET 'MGT_FO_CH_55_IN_CMP' J21-A5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_IN_DIR' J21-B5 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 56 is the FEX-11 Aurora Lane 5 ATCA Tx3[10] Sig_10 NET 'MGT_FO_CH_56_IN_DIR' J21-E5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_IN_CMP' J21-F5 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-12 Logical Slot Number 12 # # MGT Fanout Channel 57 is the FEX-12 Aurora Lane 0 ATCA Rx0[11] Sig_7 NET 'MGT_FO_CH_57_IN_CMP' J21-C4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_IN_DIR' J21-D4 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 58 is the FEX-12 Aurora Lane 1 ATCA Rx1[11] Sig_8 NET 'MGT_FO_CH_58_IN_DIR' J21-G4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_IN_CMP' J21-H4 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 59 is the FEX-12 Aurora Lane 2 ATCA Rx2[11] Sig_9 NET 'MGT_FO_CH_59_IN_CMP' J21-C3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_IN_DIR' J21-D3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 60 is the FEX-12 Aurora Lane 3 ATCA Rx3[11] Sig_10 NET 'MGT_FO_CH_60_IN_DIR' J21-G3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_IN_CMP' J21-H3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 61 is the FEX-12 Aurora Lane 4 ATCA Tx2[11] Sig_7 NET 'MGT_FO_CH_61_IN_CMP' J21-A3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_IN_DIR' J21-B3 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 62 is the FEX-12 Aurora Lane 5 ATCA Tx3[11] Sig_8 NET 'MGT_FO_CH_62_IN_DIR' J21-E3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_IN_CMP' J21-F3 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-13 Logical Slot Number 13 # # MGT Fanout Channel 63 is the FEX-13 Aurora Lane 0 ATCA Rx0[12] Sig_9 NET 'MGT_FO_CH_63_IN_CMP' J21-C2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_IN_DIR' J21-D2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 64 is the FEX-13 Aurora Lane 1 ATCA Rx1[12] Sig_10 NET 'MGT_FO_CH_64_IN_DIR' J21-G2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_IN_CMP' J21-H2 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 65 is the FEX-13 Aurora Lane 2 ATCA Rx2[12] Sig_7 NET 'MGT_FO_CH_65_IN_CMP' J21-C1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_IN_DIR' J21-D1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 66 is the FEX-13 Aurora Lane 3 ATCA Rx3[12] Sig_8 NET 'MGT_FO_CH_66_IN_DIR' J21-G1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_IN_CMP' J21-H1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 67 is the FEX-13 Aurora Lane 4 ATCA Tx2[12] Sig_9 NET 'MGT_FO_CH_67_IN_CMP' J21-A1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_IN_DIR' J21-B1 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 68 is the FEX-13 Aurora Lane 5 ATCA Tx3[12] Sig_10 NET 'MGT_FO_CH_68_IN_DIR' J21-E1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_IN_CMP' J21-F1 (NET_TYPE, 'DIFF_PAIR_HS') # # FEX-14 Logical Slot Number 14 # # MGT Fanout Channel 69 is the FEX-14 Aurora Lane 0 ATCA Rx0[13] Sig_7 NET 'MGT_FO_CH_69_IN_CMP' J20-C10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_IN_DIR' J20-D10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 70 is the FEX-14 Aurora Lane 1 ATCA Rx1[13] Sig_8 NET 'MGT_FO_CH_70_IN_DIR' J20-G10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_IN_CMP' J20-H10 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 71 is the FEX-14 Aurora Lane 2 ATCA Rx2[13] Sig_9 NET 'MGT_FO_CH_71_IN_CMP' J20-C9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_IN_DIR' J20-D9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 72 is the FEX-14 Aurora Lane 3 ATCA Rx3[13] Sig_10 NET 'MGT_FO_CH_72_IN_CMP' J20-G9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_IN_DIR' J20-H9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 73 is the FEX-14 Aurora Lane 4 ATCA Tx2[13] Sig_7 NET 'MGT_FO_CH_73_IN_CMP' J20-A9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_IN_DIR' J20-B9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Channel 74 is the FEX-14 Aurora Lane 5 ATCA Tx3[13] Sig_10 NET 'MGT_FO_CH_74_IN_DIR' J20-E9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_IN_CMP' J20-F9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout DC-Blocking Caps to Meg-Array Connector Nets # ------------------------------------------------------------ # # # Original Rev. 29-Apr-2015 # Current Rev. 23-Nov-2016 GTH->MGT # # # This Net List File contain the connections from the # MGT Fanout DC-Blocking Capacitors to the Meg-Array # connectors. # # This file defines just the end of these nets that # connects to the Meg-Array connector. # # The starting point of these nets at the DC-Blocking # capacitors at the output of the fanout chips as defined in: # # gth_fanout_nets_template.txt gth_fanout_nets_config.txt # # # Note that these nets are named in terms of # MGT Fanout "Channel Number" and not in terms of # ATCA Fabric Interface Port-Channel or in terms of # Meg-Array to ROD connection number. # # # # # Inverted Channels on the Run # from MGT Fanout to MegArrays # -------------------------------- # # Recall that some of the signals coming from the MGT Fanout # will be inverted because the Zone 2 input to these channels # was inverted to facilitate high-speed signal routing. # # The Channels that come out of the MGT Fanout will be # inverted again on their run to the MegArray connectors. # This is done so that all inputs to the ROD card will be # "right side up". # # The inversion on the run from MGT Fanout to MegArray is done # by which of the MegArray diff pair BGA pads uses the signal # via above the BGA pad pair and which uses the via below the # BGA pad pair. So this will take a lot of editing of the # S1 and S2 MegArray geometries to get right. # # # Reacall the MGT Fanout Channels with Inverted Inputs: # # Note that some signals are "inverted" as they leave # this net list file. This is to eliminate the need # to flip these traces during routing. # # - In the lower physical half of the MGT Fanout Array, # i.e. FEX-03 through FEX-08, the EVEN numbered # MGT Fanout Channel inputs are inverted. # # That is, in the MGT Fanout Channel range 1:36, # the EVEN numbered MGT Fanout Channel have inverted # inputs. # # - In the upper physical half of the MGT Fanout Array, # i.e. FEX-09 through FEX-12, the ODD numbered # MGT Fanout Channel inputs are inverted. # # That is, in the MGT Fanout Channel range 39:74, # the ODD numbered MGT Fanout Channel have inverted # inputs. # # - NOTE that MGT Fanout Ch #72, i.e. FEX-12 Lane 3 # is an exception. MGT Fanout Ch #72 is inverted to # allow a clean route into the 10 cells in the top, # i.e. 9th row of the MGT Fanout Array. # # - From the "Other Hub" the input to MGT Fanout # Channel 37 was inverted to facilitate routing. # # # List of signals that will be inverted on their run from # MGT Fanout to the MegArray S1 & S2 Connectors: # # MGT Channels 2, 4, 6, 8, 10, 12, 14, 16, 18, # Inverted 20, 22, 24, 26, 28, 30, 32, 34, 36 # on their run # to the 37 # MegArray # Connectors: 39, 41, 43, 45, 47, 49, 51, 53, 55, # 57, 59, 61, 63, 65, 67, 69, 71, # 72, # 73 # # # #------------------------------------------------- # # Start with MegArray Connector S1 # #------------------------------------------------- # # MGT Fanout Ch 1:6 services FEX-03 Aurora Lanes 0:5 ROD FEX Inputs 0:5 # NET 'MGT_FO_CH_1_OUT_ROD_DIR' Meg_S1-F39 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_ROD_CMP' Meg_S1-E39 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_ROD_CMP' Meg_S1-J38 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_ROD_DIR' Meg_S1-H38 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_ROD_DIR' Meg_S1-F37 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_ROD_CMP' Meg_S1-E37 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_ROD_CMP' Meg_S1-J36 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_ROD_DIR' Meg_S1-H36 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_ROD_DIR' Meg_S1-F35 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_ROD_CMP' Meg_S1-E35 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_ROD_CMP' Meg_S1-J34 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_ROD_DIR' Meg_S1-H34 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 7:12 services FEX-04 Aurora Lanes 0:5 ROD FEX Inputs 6:11 # NET 'MGT_FO_CH_7_OUT_ROD_DIR' Meg_S1-F33 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_ROD_CMP' Meg_S1-E33 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_ROD_CMP' Meg_S1-J32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_8_OUT_ROD_DIR' Meg_S1-H32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_ROD_DIR' Meg_S1-F31 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_ROD_CMP' Meg_S1-E31 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_ROD_CMP' Meg_S1-J30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_ROD_DIR' Meg_S1-H30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_ROD_DIR' Meg_S1-F29 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_ROD_CMP' Meg_S1-E29 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_ROD_CMP' Meg_S1-J28 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_ROD_DIR' Meg_S1-H28 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 13:18 services FEX-05 Aurora Lanes 0:5 ROD FEX Inputs 12:17 # NET 'MGT_FO_CH_13_OUT_ROD_DIR' Meg_S1-F27 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_ROD_CMP' Meg_S1-E27 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_ROD_CMP' Meg_S1-J26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_ROD_DIR' Meg_S1-H26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_ROD_DIR' Meg_S1-F25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_ROD_CMP' Meg_S1-E25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_ROD_CMP' Meg_S1-J24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_ROD_DIR' Meg_S1-H24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_ROD_DIR' Meg_S1-F23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_ROD_CMP' Meg_S1-E23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_ROD_CMP' Meg_S1-J22 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_ROD_DIR' Meg_S1-H22 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 19:24 services FEX-06 Aurora Lanes 0:5 ROD FEX Inputs 18:23 # NET 'MGT_FO_CH_19_OUT_ROD_DIR' Meg_S1-J20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_ROD_CMP' Meg_S1-H20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_ROD_CMP' Meg_S1-F19 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_ROD_DIR' Meg_S1-E19 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_ROD_DIR' Meg_S1-J18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_ROD_CMP' Meg_S1-H18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_ROD_CMP' Meg_S1-F17 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_ROD_DIR' Meg_S1-E17 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_ROD_DIR' Meg_S1-J16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_ROD_CMP' Meg_S1-H16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_ROD_CMP' Meg_S1-F15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_ROD_DIR' Meg_S1-E15 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 25:30 services FEX-07 Aurora Lanes 0:5 ROD FEX Inputs 24:29 # NET 'MGT_FO_CH_25_OUT_ROD_DIR' Meg_S1-J14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_ROD_CMP' Meg_S1-H14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_ROD_CMP' Meg_S1-F13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_ROD_DIR' Meg_S1-E13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_ROD_DIR' Meg_S1-J12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_ROD_CMP' Meg_S1-H12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_ROD_CMP' Meg_S1-F11 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_ROD_DIR' Meg_S1-E11 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_ROD_DIR' Meg_S1-J10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_ROD_CMP' Meg_S1-H10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_ROD_CMP' Meg_S1-F9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_ROD_DIR' Meg_S1-E9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 31:36 services FEX-08 Aurora Lanes 0:5 ROD FEX Inputs 30:35 # NET 'MGT_FO_CH_31_OUT_ROD_DIR' Meg_S1-J8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_ROD_CMP' Meg_S1-H8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_ROD_CMP' Meg_S1-F7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_ROD_DIR' Meg_S1-E7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_ROD_DIR' Meg_S1-J6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_ROD_CMP' Meg_S1-H6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_ROD_CMP' Meg_S1-F5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_34_OUT_ROD_DIR' Meg_S1-E5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_ROD_DIR' Meg_S1-J4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_ROD_CMP' Meg_S1-H4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_ROD_CMP' Meg_S1-F3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_ROD_DIR' Meg_S1-E3 (NET_TYPE, 'DIFF_PAIR_HS') #------------------------------------------------- # # Now switch to MegArray Connector S2 # #------------------------------------------------- # # MGT Fanout Ch 37:38 services Other-HUB Aurora Lanes 0:1 # # ROD FEX Inputs: HRD0 and HRD2 # NET 'MGT_FO_CH_37_OUT_ROD_CMP' Meg_S2-E3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_ROD_DIR' Meg_S2-F3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_ROD_DIR' Meg_S2-H8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_ROD_CMP' Meg_S2-J8 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 39:44 services FEX-09 Aurora Lanes 0:5 ROD FEX Inputs 71:66 # NET 'MGT_FO_CH_39_OUT_ROD_CMP' Meg_S2-B4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_ROD_DIR' Meg_S2-C4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_ROD_DIR' Meg_S2-E5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_ROD_CMP' Meg_S2-F5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_ROD_CMP' Meg_S2-B6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_ROD_DIR' Meg_S2-C6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_ROD_DIR' Meg_S2-E7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_ROD_CMP' Meg_S2-F7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_ROD_CMP' Meg_S2-B8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_ROD_DIR' Meg_S2-C8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_ROD_DIR' Meg_S2-E9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_ROD_CMP' Meg_S2-F9 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 45:50 services FEX-10 Aurora Lanes 0:5 ROD FEX Inputs 65:60 # NET 'MGT_FO_CH_45_OUT_ROD_CMP' Meg_S2-B10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_ROD_DIR' Meg_S2-C10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_ROD_DIR' Meg_S2-E11 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_ROD_CMP' Meg_S2-F11 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_ROD_CMP' Meg_S2-B12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_ROD_DIR' Meg_S2-C12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_ROD_DIR' Meg_S2-E13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_ROD_CMP' Meg_S2-F13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_ROD_CMP' Meg_S2-B14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_ROD_DIR' Meg_S2-C14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_ROD_DIR' Meg_S2-E15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_ROD_CMP' Meg_S2-F15 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 51:56 services FEX-11 Aurora Lanes 0:5 ROD FEX Inputs 59:54 # NET 'MGT_FO_CH_51_OUT_ROD_CMP' Meg_S2-B16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_ROD_DIR' Meg_S2-C16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_ROD_DIR' Meg_S2-E17 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_ROD_CMP' Meg_S2-F17 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_ROD_CMP' Meg_S2-B18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_ROD_DIR' Meg_S2-C18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_ROD_DIR' Meg_S2-E19 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_ROD_CMP' Meg_S2-F19 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_ROD_CMP' Meg_S2-B20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_ROD_DIR' Meg_S2-C20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_ROD_DIR' Meg_S2-E21 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_ROD_CMP' Meg_S2-F21 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 57:62 services FEX-12 Aurora Lanes 0:5 ROD FEX Inputs 53:48 # NET 'MGT_FO_CH_57_OUT_ROD_CMP' Meg_S2-B22 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_ROD_DIR' Meg_S2-C22 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_ROD_DIR' Meg_S2-E23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_ROD_CMP' Meg_S2-F23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_ROD_CMP' Meg_S2-B24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_ROD_DIR' Meg_S2-C24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_ROD_DIR' Meg_S2-E25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_ROD_CMP' Meg_S2-F25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_ROD_CMP' Meg_S2-B26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_ROD_DIR' Meg_S2-C26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_ROD_DIR' Meg_S2-E27 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_ROD_CMP' Meg_S2-F27 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 63:68 services FEX-13 Aurora Lanes 0:5 ROD FEX Inputs 47:42 # NET 'MGT_FO_CH_63_OUT_ROD_CMP' Meg_S2-B28 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_ROD_DIR' Meg_S2-C28 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_ROD_DIR' Meg_S2-E29 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_ROD_CMP' Meg_S2-F29 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_ROD_CMP' Meg_S2-B30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_ROD_DIR' Meg_S2-C30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_ROD_DIR' Meg_S2-E31 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_ROD_CMP' Meg_S2-F31 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_ROD_CMP' Meg_S2-B32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_ROD_DIR' Meg_S2-C32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_ROD_DIR' Meg_S2-E33 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_ROD_CMP' Meg_S2-F33 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout Ch 69:74 services FEX-14 Aurora Lanes 0:5 ROD FEX Inputs 41:36 # NET 'MGT_FO_CH_69_OUT_ROD_CMP' Meg_S2-B34 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_ROD_DIR' Meg_S2-C34 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_ROD_DIR' Meg_S2-E35 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_ROD_CMP' Meg_S2-F35 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_ROD_CMP' Meg_S2-B36 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_ROD_DIR' Meg_S2-C36 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_ROD_CMP' Meg_S2-E37 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_ROD_DIR' Meg_S2-F37 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_ROD_CMP' Meg_S2-B38 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_ROD_DIR' Meg_S2-C38 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_ROD_DIR' Meg_S2-E39 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_ROD_CMP' Meg_S2-F39 (NET_TYPE, 'DIFF_PAIR_HS') # # MGT Fanout DC-Blocking Caps to Hub FPGA Nets # ------------------------------------------------- # # # Original Rev. 29-Apr-2015 # Current Rev. 23-Nov-2016 GTH->MGT # # # This Net List File contain the connections from the # MGT Fanout DC-Blocking Capacitors to the Hub FPGA. # # This file is now setup for the XCVU125-1FLVC2104C Ultra-Scale. # # This file defines just the end of these nets that # connects to the Hub FPGA. # # The starting point of these nets at the DC-Blocking # capacitors is defined in # # mgt_fanout_channel_nets which comes from # # gth_fanout_channel_nets_config # gth_fanout_channel_nets_template # # Note that these nets are named in terms of # "MGT Fanout "Channel Number" and not in terms of # Hub FPGA Transceiver ID or FEX source ID. # # # This file is basically in the order of the MGT Receiver # Input pin pairs, going around the BGA CCW, starting at # Quad 124, which is in the SW cornet on the Hub Module. # # This order is all simple rational and makes sense # until you reach near the Row A end of the device. # Once near the Row A end of the device there are # many choices, nothing makes sense, and the device # pins are harder to reach. # # # Recall that there are other users of the GTH/GTY # Transmitters and Receivers. # # Recall that the Hub Module uses all 80 of the GTH/GTY Receivers. # # - The FEX Data uses 74 of the 80 available GTH/GTY Receivers. # # - The Receiver MiniPOD uses 4 of the GTH Receivers. # # - The Readout Control Data from the ROD on # This Hub uses 1 of the GTH Receivers. # # - The Combined Data from the Other Hub uses 1 # of the GTY Receivers. # # This list accounts for all 80 GTH/GTY Receivers. # # Just the 74 FEX data inputs are defined in this file # but the 6 additional GTH/GTY Receiver Inputs are noted # in comments. # # # Start at the SW corner (as placed on the Hub) and move CCW # # # Quad 124 Receiver Port 0 is not used for FEX data. # Quad 124 Receiver Port 0 is used to Receive MiniPOD Fiber No. 8 # which is one of the 4 active MiniPOD # Receiver channels on the Hub. # # This net is defined in the file: hub_all_other_mgt_nets # # # Quad 124 Receiver Port 1 is not used for FEX data. # Quad 124 Receiver Port 1 is used to receive the Other Hub's Combined Data. # # This net is defined in the file: hub_all_other_mgt_nets # NET 'MGT_FO_CH_8_OUT_Hub_DIR' U1-AN45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-124 NET 'MGT_FO_CH_8_OUT_Hub_CMP' U1-AN46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_7_OUT_Hub_CMP' U1-AM43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-124 FLIPPED NET 'MGT_FO_CH_7_OUT_Hub_DIR' U1-AM44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_6_OUT_Hub_DIR' U1-AL45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-125 NET 'MGT_FO_CH_6_OUT_Hub_CMP' U1-AL46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_5_OUT_Hub_CMP' U1-AK43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-125 FLIPPED NET 'MGT_FO_CH_5_OUT_Hub_DIR' U1-AK44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_4_OUT_Hub_DIR' U1-AJ45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-125 NET 'MGT_FO_CH_4_OUT_Hub_CMP' U1-AJ46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_3_OUT_Hub_CMP' U1-AH43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-125 FLIPPED NET 'MGT_FO_CH_3_OUT_Hub_DIR' U1-AH44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_2_OUT_Hub_DIR' U1-AG45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-126 NET 'MGT_FO_CH_2_OUT_Hub_CMP' U1-AG46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_1_OUT_Hub_CMP' U1-AF43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-126 FLIPPED NET 'MGT_FO_CH_1_OUT_Hub_DIR' U1-AF44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_16_OUT_Hub_DIR' U1-AE45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-126 NET 'MGT_FO_CH_16_OUT_Hub_CMP' U1-AE46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_15_OUT_Hub_CMP' U1-AD43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-126 FLIPPED NET 'MGT_FO_CH_15_OUT_Hub_DIR' U1-AD44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_14_OUT_Hub_DIR' U1-AC45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-127 NET 'MGT_FO_CH_14_OUT_Hub_CMP' U1-AC46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_13_OUT_Hub_CMP' U1-AB43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-127 FLIPPED NET 'MGT_FO_CH_13_OUT_Hub_DIR' U1-AB44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_12_OUT_Hub_DIR' U1-AA45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-127 NET 'MGT_FO_CH_12_OUT_Hub_CMP' U1-AA46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_11_OUT_Hub_CMP' U1-Y43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-127 FLIPPED NET 'MGT_FO_CH_11_OUT_Hub_DIR' U1-Y44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_10_OUT_Hub_DIR' U1-W45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-128 NET 'MGT_FO_CH_10_OUT_Hub_CMP' U1-W46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_9_OUT_Hub_CMP' U1-V43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-128 FLIPPED NET 'MGT_FO_CH_9_OUT_Hub_DIR' U1-V44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_24_OUT_Hub_DIR' U1-U45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-128 NET 'MGT_FO_CH_24_OUT_Hub_CMP' U1-U46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_23_OUT_Hub_CMP' U1-T43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-128 FLIPPED NET 'MGT_FO_CH_23_OUT_Hub_DIR' U1-T44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_22_OUT_Hub_DIR' U1-R45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-129 NET 'MGT_FO_CH_22_OUT_Hub_CMP' U1-R46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_21_OUT_Hub_CMP' U1-P43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-129 FLIPPED NET 'MGT_FO_CH_21_OUT_Hub_DIR' U1-P44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_20_OUT_Hub_DIR' U1-N45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-129 NET 'MGT_FO_CH_20_OUT_Hub_CMP' U1-N46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_19_OUT_Hub_CMP' U1-M43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-129 FLIPPED NET 'MGT_FO_CH_19_OUT_Hub_DIR' U1-M44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_18_OUT_Hub_DIR' U1-L45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-130 NET 'MGT_FO_CH_18_OUT_Hub_CMP' U1-L46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_17_OUT_Hub_CMP' U1-K43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-130 FLIPPED NET 'MGT_FO_CH_17_OUT_Hub_DIR' U1-K44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_32_OUT_Hub_DIR' U1-J45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-130 NET 'MGT_FO_CH_32_OUT_Hub_CMP' U1-J46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_31_OUT_Hub_CMP' U1-H43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-130 FLIPPED NET 'MGT_FO_CH_31_OUT_Hub_DIR' U1-H44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_30_OUT_Hub_DIR' U1-G45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-131 NET 'MGT_FO_CH_30_OUT_Hub_CMP' U1-G46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_29_OUT_Hub_CMP' U1-F43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-131 FLIPPED NET 'MGT_FO_CH_29_OUT_Hub_DIR' U1-F44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_28_OUT_Hub_DIR' U1-E45 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-132 NET 'MGT_FO_CH_28_OUT_Hub_CMP' U1-E46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_27_OUT_Hub_CMP' U1-D43 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-132 FLIPPED NET 'MGT_FO_CH_27_OUT_Hub_DIR' U1-D44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_26_OUT_Hub_DIR' U1-C45 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-132 NET 'MGT_FO_CH_26_OUT_Hub_CMP' U1-C46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_25_OUT_Hub_CMP' U1-B43 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-132 FLIPPED NET 'MGT_FO_CH_25_OUT_Hub_DIR' U1-B44 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_40_OUT_Hub_DIR' U1-D33 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-133 NET 'MGT_FO_CH_40_OUT_Hub_CMP' U1-D34 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_39_OUT_Hub_CMP' U1-C31 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-133 FLIPPED NET 'MGT_FO_CH_39_OUT_Hub_DIR' U1-C32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_38_OUT_Hub_DIR' U1-B33 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-133 NET 'MGT_FO_CH_38_OUT_Hub_CMP' U1-B34 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_37_OUT_Hub_DIR' U1-A31 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-133 NET 'MGT_FO_CH_37_OUT_Hub_CMP' U1-A32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_36_OUT_Hub_DIR' U1-G31 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-131 NET 'MGT_FO_CH_36_OUT_Hub_CMP' U1-G32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_35_OUT_Hub_CMP' U1-E31 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-131 FLIPPED for Test NET 'MGT_FO_CH_35_OUT_Hub_DIR' U1-E32 (NET_TYPE, 'DIFF_PAIR_HS') # # Now at the SE corner # #****************************** # # Move to the NE corner # NET 'MGT_FO_CH_34_OUT_Hub_CMP' U1-E16 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-231 FLIPPED for Test NET 'MGT_FO_CH_34_OUT_Hub_DIR' U1-E15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_33_OUT_Hub_DIR' U1-G16 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-231 NET 'MGT_FO_CH_33_OUT_Hub_CMP' U1-G15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_48_OUT_Hub_DIR' U1-A16 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-233 NET 'MGT_FO_CH_48_OUT_Hub_CMP' U1-A15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_47_OUT_Hub_DIR' U1-B14 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-233 NET 'MGT_FO_CH_47_OUT_Hub_CMP' U1-B13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_46_OUT_Hub_CMP' U1-C16 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-233 FLIPPED NET 'MGT_FO_CH_46_OUT_Hub_DIR' U1-C15 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_45_OUT_Hub_DIR' U1-D14 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-233 NET 'MGT_FO_CH_45_OUT_Hub_CMP' U1-D13 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_44_OUT_Hub_CMP' U1-B4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-232 FLIPPED NET 'MGT_FO_CH_44_OUT_Hub_DIR' U1-B3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_43_OUT_Hub_DIR' U1-C2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-232 NET 'MGT_FO_CH_43_OUT_Hub_CMP' U1-C1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_42_OUT_Hub_CMP' U1-D4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-232 FLIPPED NET 'MGT_FO_CH_42_OUT_Hub_DIR' U1-D3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_41_OUT_Hub_DIR' U1-E2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-232 NET 'MGT_FO_CH_41_OUT_Hub_CMP' U1-E1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_56_OUT_Hub_CMP' U1-F4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-231 FLIPPED NET 'MGT_FO_CH_56_OUT_Hub_DIR' U1-F3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_55_OUT_Hub_DIR' U1-G2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-231 NET 'MGT_FO_CH_55_OUT_Hub_CMP' U1-G1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_54_OUT_Hub_CMP' U1-H4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-230 FLIPPED NET 'MGT_FO_CH_54_OUT_Hub_DIR' U1-H3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_53_OUT_Hub_DIR' U1-J2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-230 NET 'MGT_FO_CH_53_OUT_Hub_CMP' U1-J1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_52_OUT_Hub_CMP' U1-K4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-230 FLIPPED NET 'MGT_FO_CH_52_OUT_Hub_DIR' U1-K3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_51_OUT_Hub_DIR' U1-L2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-230 NET 'MGT_FO_CH_51_OUT_Hub_CMP' U1-L1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_50_OUT_Hub_CMP' U1-M4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-229 FLIPPED NET 'MGT_FO_CH_50_OUT_Hub_DIR' U1-M3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_49_OUT_Hub_DIR' U1-N2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-229 NET 'MGT_FO_CH_49_OUT_Hub_CMP' U1-N1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_64_OUT_Hub_CMP' U1-P4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-229 FLIPPED NET 'MGT_FO_CH_64_OUT_Hub_DIR' U1-P3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_63_OUT_Hub_DIR' U1-R2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-229 NET 'MGT_FO_CH_63_OUT_Hub_CMP' U1-R1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_62_OUT_Hub_CMP' U1-T4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-228 FLIPPED NET 'MGT_FO_CH_62_OUT_Hub_DIR' U1-T3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_61_OUT_Hub_DIR' U1-U2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-228 NET 'MGT_FO_CH_61_OUT_Hub_CMP' U1-U1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_60_OUT_Hub_CMP' U1-V4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-228 FLIPPED NET 'MGT_FO_CH_60_OUT_Hub_DIR' U1-V3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_59_OUT_Hub_DIR' U1-W2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-228 NET 'MGT_FO_CH_59_OUT_Hub_CMP' U1-W1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_58_OUT_Hub_CMP' U1-Y4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-227 FLIPPED NET 'MGT_FO_CH_58_OUT_Hub_DIR' U1-Y3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_57_OUT_Hub_DIR' U1-AA2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-227 NET 'MGT_FO_CH_57_OUT_Hub_CMP' U1-AA1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_74_OUT_Hub_CMP' U1-AB4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-227 FLIPPED NET 'MGT_FO_CH_74_OUT_Hub_DIR' U1-AB3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_73_OUT_Hub_DIR' U1-AC2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-227 NET 'MGT_FO_CH_73_OUT_Hub_CMP' U1-AC1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_72_OUT_Hub_CMP' U1-AD4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-226 FLIPPED NET 'MGT_FO_CH_72_OUT_Hub_DIR' U1-AD3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_71_OUT_Hub_DIR' U1-AE2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-226 NET 'MGT_FO_CH_71_OUT_Hub_CMP' U1-AE1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_70_OUT_Hub_CMP' U1-AF4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-226 FLIPPED NET 'MGT_FO_CH_70_OUT_Hub_DIR' U1-AF3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_69_OUT_Hub_DIR' U1-AG2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-226 NET 'MGT_FO_CH_69_OUT_Hub_CMP' U1-AG1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_68_OUT_Hub_CMP' U1-AH4 (NET_TYPE, 'DIFF_PAIR_HS') # RX3-225 FLIPPED NET 'MGT_FO_CH_68_OUT_Hub_DIR' U1-AH3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_67_OUT_Hub_DIR' U1-AJ2 (NET_TYPE, 'DIFF_PAIR_HS') # RX2-225 NET 'MGT_FO_CH_67_OUT_Hub_CMP' U1-AJ1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_66_OUT_Hub_CMP' U1-AK4 (NET_TYPE, 'DIFF_PAIR_HS') # RX1-225 FLIPPED NET 'MGT_FO_CH_66_OUT_Hub_DIR' U1-AK3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_FO_CH_65_OUT_Hub_DIR' U1-AL2 (NET_TYPE, 'DIFF_PAIR_HS') # RX0-225 NET 'MGT_FO_CH_65_OUT_Hub_CMP' U1-AL1 (NET_TYPE, 'DIFF_PAIR_HS') # # Quad 224 Receiver Port 3 is used to receive the Readout Control Data # from the ROD on This Hub card. # # This net is defined in the file: hub_all_other_mgt_nets # # # Quad 224 Receiver Ports: 2, 1, 0 are used to service the MiniPOD # Receiver Fibers: 2, 4, 6 # # These nets are defined in the file: hub_all_other_mgt_nets # # Recall that MiniPOD Receiver Fiber 8 is over on Quad 124 Receiver Port 0. # # # End near the NW corner # # # This is the Key In Net List file for the # # Hub Module Power Entry Nets # ------------------------------------------------ # # # Original Rev. 17-Apr-2014 # Most Recent Rev. 17-Jan-2017 # # # ATCA Power Entry Module Nets: # # # -48V Entry A & B Buses # NET 'A_BUS_N48V_BP' P10-33 F6-2 NET 'A_BUS_N48V' F6-1 Power_Entry-1 NET 'A_BUS_EARLY_48_BP' P10-30 R951-1 NET 'A_BUS_N48V_BP' R951-2 NET 'B_BUS_N48V_BP' P10-34 F5-2 NET 'B_BUS_N48V' F5-1 Power_Entry-2 NET 'B_BUS_EARLY_48_BP' P10-31 R952-1 NET 'B_BUS_N48V_BP' R952-2 # # Power Returns A & B Buses # NET 'A_BUS_RETURN_BP' P10-28 F4-2 NET 'A_BUS_RETURN' F4-1 Power_Entry-3 NET 'B_BUS_RETURN_BP' P10-29 F3-2 NET 'B_BUS_RETURN' F3-1 Power_Entry-4 # # Power Enables A & B Buses # NET 'A_BUS_ENABLE_BP' P10-32 F2-2 NET 'A_BUS_ENABLE' F2-1 Power_Entry-5 NET 'B_BUS_ENABLE_BP' P10-27 F1-2 NET 'B_BUS_ENABLE' F1-1 Power_Entry-6 # # ATCA "Entered" 48V Power to 12V Converter # NET 'ENTERED_N48V' Power_Entry-15 NET 'ENTERED_48V_RTN' Power_Entry-17 # # Shelf Ground # NET 'SHELF_GND' P10-25 Power_Entry-7 # # LOGIC Ground # NET 'GROUND' P10-26 Power_Entry-13 # # Hold-Up Capacitors on the Power Entry Module # # Power Entry Module pin #18 must connect to the Positive # side of the Hold-Up Capacitors. # # The Negative side of the Hold-Up Capacitors must be # connected to pin #15 on the Power Entry Module, i.e. # the Entered Negative 48 Volt pin. # # - Power Entry Module pin #18 is connected by a pcb # trace to Wire-Terminal 41. A discrete wire connects # Wire-Terminal 41 to Wire-Terminal 42. Wire-Terminal 42 # connects to the Positive side of the Hold-Up Capacitors. # # - Power Entry Module pin #15 is connected by a pcb # trace to Wire-Terminal 31. Wire-Terminal 31 is connected # by a discrete wire to Wire-Terminal 32. Wire-Terminal 32 # connects to the Negative side of the Hold-Up Capacitors. NET 'Hold_Cap_Pos_Pow_enter' Power_Entry-18 NET 'Hold_Cap_Pos_Pow_enter' WTERM41-1 NET 'Hold_Cap_Positive' WTERM42-1 NET 'Hold_Cap_Positive' C951-1 C952-1 NET 'ENTERED_N48V' WTERM31-1 NET 'Hold_Cap_Negative' WTERM32-1 NET 'Hold_Cap_Negative' C951-2 C952-2 # # Hold-Up Voltage Trim Resistor # NET 'Hold_Up_Volt_Trim' R953-1 Power_Entry-16 NET 'ENTERED_N48V' R953-2 # # IPMC 3V3 Power Connections to ATCA Power Entered Module # # The IPMC 3V3 Power comes out of the Power Entry Module # on its pin #9. # # From this pin there is a connection to the front panel # Handle Switch. This connection is in the nets file: # ipmc_hw_adrs_handle_switch_ipmb_nets # # From this pin there is also a connection to R954 the # pull-up on the alarm signal from the power entry module # to the IPMC. # # The main connection of IPMC 3V3 Power up to the IPMC # Module happens through a discrete wire connection. # # Wire-Terminal 1 is connected by a discrete wire to # Wire-Terminal 2. # # Wire-Terminal 2 feeds 3V3 power to the IPMC and to # on of the other loads on the IPMC_3V3 rail. # NET 'IPMC_3V3_SRC' Power_Entry-9 NET 'IPMC_3V3_SRC' R954-2 NET 'IPMC_3V3_SRC' WTERM1-1 NET 'IPMC_3V3' WTERM2-1 # # Other IPMC Connections to ATCA Power Entered Module # NET 'IPMC_Power_Entry_ALARM' Power_Entry-14 R954-1 NET 'IPMC_Power_Entry_ALARM' IPMC-226 IPMC-227 NET 'IPMC_MGT_I2C_SCK' Power_Entry-12 NET 'IPMC_MGT_I2C_SDA' Power_Entry-11 NET 'Power_Entry_I2C_ADRS' Power_Entry-10 R955-2 NET 'GROUND' R955-1 # # The ATCA Power Entry Module's supply of # +5 Volt "Always ON" power. # # The Constant 5V power comes out of the Power Entry # Module on its pin #8. This is routed by pcb trace # to Wire-Terminal 11. Wire-Terminal 11 is connected # by a discrete wire to Wire-Terminal 12. Wire-Terminal 12 # delivers the Constant 5V power to all of its loads. # NET 'CNST_5V0_SRC' Power_Entry-8 NET 'CNST_5V0_SRC' WTERM11-1 NET 'CNST_5V0' WTERM12-1 # # This is the Key In Net List file for the # # Hub Module Isolated +12V Power Supply Nets # ------------------------------------------------ # # # Original Rev. 17-Apr-2014 # Most Recent Rev. 21-Oct-2016 # # # # ATCA "Entered" 48V Power to the 12V Converter # NET 'ENTERED_N48V' C954-2 C955-2 NET 'ENTERED_48V_RTN' C954-1 C955-1 NET 'ENTERED_N48V' Power_12V-3 NET 'ENTERED_48V_RTN' Power_12V-1 # # Pay Load Enable Signal to the Isolated +12V Converter # # OPT1-1 LED Anode OPT1-2 LED Cathode # OPT1-3 Transistor Emitter OPT1-4 Transistor Collector # NET 'ENABLE_INTO_ISO_12V_B' Power_12V-2 OPT1-4 NET 'ENTERED_N48V' OPT1-3 NET 'GROUND' OPT1-2 NET 'Enable_LED_Anode' OPT1-1 # # Isolated +12V Power from the Converter # NET 'Iso_12V' Power_12V-8 NET 'GROUND' Power_12V-4 # # Remote Sense Feedback Connections: # Iso_12V and then Ground # and the Output Trim Connection # for the Isolated +12V Supply # NET 'Iso_12V' Power_12V-7 NET 'REMOTE_SENSE_GND_ISO_12V' Power_12V-5 AKA1-2 NET 'GROUND' AKA1-1 NET 'No_Conn_Trim_12V' Power_12V-6 # # Filter the Isolated +12V Power from the Converter # NET 'Iso_12V' C957-2 C958-2 C959-2 C960-2 NET 'Iso_12V' C961-1 C962-1 C963-1 C964-1 NET 'GROUND' C957-1 C958-1 C959-1 C960-1 NET 'GROUND' C961-2 C962-2 C963-2 C964-2 # # Wire Terminals for the discrete wire runs # that carry the Iso_12V up to the DCDC Converters # and their Bulk Input Filter Capacitors. # NET 'Iso_12V' WTERM21-1 WTERM22-1 WTERM23-1 NET 'Iso_12V' WTERM25-1 WTERM26-1 WTERM27-1 # # This is the Key In Net List file for the # # Hub Module ESD Strip Nets # ------------------------------------------------ # # # Original Rev. 2-Apr-2015 # Most Recent Rev. 6-Dec-2016 # # # # This file now includes the SHELF_GND connections # to the two Guide Pin Receptacles. # # # # ESD Strip Nets to the Shelf Ground: # NET 'ESD_STRIP_ONE' ESD_Strip_MB-1 R958-1 NET 'SHELF_GND' R958-2 NET 'SHELF_GND' ESD_Strip_FO-3 # # ESD Strip Net to the LOGIC Ground # NET 'ESD_STRIP_TWO' ESD_Strip_MB-2 R957-1 NET 'GROUND' R957-2 # # Optional Req. 4.96 Tie Shelf Gnd to Logic Gnd # NET 'SHELF_GND' R959-1 NET 'GROUND' R959-2 # # Guide Pin Rreceptacle to Shelf Ground connections # NET 'SHELF_GND' K1-1 K1-2 K1-3 NET 'SHELF_GND' K2-1 K2-2 K2-3 # # Zone 2 Connector Grounds # -------------------------- # # Rev. 19-Aug-2016 # # # This file holds all of the Ground connections for # the 5 Zone 2 connectors. # # Each of these ADFplus connectors has 80 ground # connections pins and 80 signal pins that make # up 40 differential pairs. # # The 5 Zone 2 connectors have Reference Designators # J20 through J24. # # # Connector J20 # NET 'GROUND' J20-AG3 J20-AG4 J20-AG5 NET 'GROUND' J20-AG6 J20-AG7 J20-AG8 J20-AG9 J20-AG10 NET 'GROUND' J20-BG3 J20-BG4 J20-BG5 NET 'GROUND' J20-BG6 J20-BG7 J20-BG8 J20-BG9 J20-BG10 NET 'GROUND' J20-CG3 J20-CG4 J20-CG5 NET 'GROUND' J20-CG6 J20-CG7 J20-CG8 J20-CG9 J20-CG10 NET 'GROUND' J20-DG3 J20-DG4 J20-DG5 NET 'GROUND' J20-DG6 J20-DG7 J20-DG8 J20-DG9 J20-DG10 NET 'GROUND' J20-EG3 J20-EG4 J20-EG5 NET 'GROUND' J20-EG6 J20-EG7 J20-EG8 J20-EG9 J20-EG10 NET 'GROUND' J20-FG3 J20-FG4 J20-FG5 NET 'GROUND' J20-FG6 J20-FG7 J20-FG8 J20-FG9 J20-FG10 NET 'GROUND' J20-GG3 J20-GG4 J20-GG5 NET 'GROUND' J20-GG6 J20-GG7 J20-GG8 J20-GG9 J20-GG10 NET 'GROUND' J20-HG3 J20-HG4 J20-HG5 NET 'GROUND' J20-HG6 J20-HG7 J20-HG8 J20-HG9 J20-HG10 # # Connector J21 # NET 'GROUND' J21-AG1 J21-AG2 J21-AG3 J21-AG4 J21-AG5 NET 'GROUND' J21-AG6 J21-AG7 J21-AG8 J21-AG9 J21-AG10 NET 'GROUND' J21-BG1 J21-BG2 J21-BG3 J21-BG4 J21-BG5 NET 'GROUND' J21-BG6 J21-BG7 J21-BG8 J21-BG9 J21-BG10 NET 'GROUND' J21-CG1 J21-CG2 J21-CG3 J21-CG4 J21-CG5 NET 'GROUND' J21-CG6 J21-CG7 J21-CG8 J21-CG9 J21-CG10 NET 'GROUND' J21-DG1 J21-DG2 J21-DG3 J21-DG4 J21-DG5 NET 'GROUND' J21-DG6 J21-DG7 J21-DG8 J21-DG9 J21-DG10 NET 'GROUND' J21-EG1 J21-EG2 J21-EG3 J21-EG4 J21-EG5 NET 'GROUND' J21-EG6 J21-EG7 J21-EG8 J21-EG9 J21-EG10 NET 'GROUND' J21-FG1 J21-FG2 J21-FG3 J21-FG4 J21-FG5 NET 'GROUND' J21-FG6 J21-FG7 J21-FG8 J21-FG9 J21-FG10 NET 'GROUND' J21-GG1 J21-GG2 J21-GG3 J21-GG4 J21-GG5 NET 'GROUND' J21-GG6 J21-GG7 J21-GG8 J21-GG9 J21-GG10 NET 'GROUND' J21-HG1 J21-HG2 J21-HG3 J21-HG4 J21-HG5 NET 'GROUND' J21-HG6 J21-HG7 J21-HG8 J21-HG9 J21-HG10 # # Connector J22 # NET 'GROUND' J22-AG1 J22-AG2 J22-AG3 J22-AG4 J22-AG5 NET 'GROUND' J22-AG6 J22-AG7 J22-AG8 J22-AG9 J22-AG10 NET 'GROUND' J22-BG1 J22-BG2 J22-BG3 J22-BG4 J22-BG5 NET 'GROUND' J22-BG6 J22-BG7 J22-BG8 J22-BG9 J22-BG10 NET 'GROUND' J22-CG1 J22-CG2 J22-CG3 J22-CG4 J22-CG5 NET 'GROUND' J22-CG6 J22-CG7 J22-CG8 J22-CG9 J22-CG10 NET 'GROUND' J22-DG1 J22-DG2 J22-DG3 J22-DG4 J22-DG5 NET 'GROUND' J22-DG6 J22-DG7 J22-DG8 J22-DG9 J22-DG10 NET 'GROUND' J22-EG1 J22-EG2 J22-EG3 J22-EG4 J22-EG5 NET 'GROUND' J22-EG6 J22-EG7 J22-EG8 J22-EG9 J22-EG10 NET 'GROUND' J22-FG1 J22-FG2 J22-FG3 J22-FG4 J22-FG5 NET 'GROUND' J22-FG6 J22-FG7 J22-FG8 J22-FG9 J22-FG10 NET 'GROUND' J22-GG1 J22-GG2 J22-GG3 J22-GG4 J22-GG5 NET 'GROUND' J22-GG6 J22-GG7 J22-GG8 J22-GG9 J22-GG10 NET 'GROUND' J22-HG1 J22-HG2 J22-HG3 J22-HG4 J22-HG5 NET 'GROUND' J22-HG6 J22-HG7 J22-HG8 J22-HG9 J22-HG10 # # Connector J23 # NET 'GROUND' J23-AG1 J23-AG2 J23-AG3 J23-AG4 J23-AG5 NET 'GROUND' J23-AG6 J23-AG7 J23-AG8 J23-AG9 J23-AG10 NET 'GROUND' J23-BG1 J23-BG2 J23-BG3 J23-BG4 J23-BG5 NET 'GROUND' J23-BG6 J23-BG7 J23-BG8 J23-BG9 J23-BG10 NET 'GROUND' J23-CG1 J23-CG2 J23-CG3 J23-CG4 J23-CG5 NET 'GROUND' J23-CG6 J23-CG7 J23-CG8 J23-CG9 J23-CG10 NET 'GROUND' J23-DG1 J23-DG2 J23-DG3 J23-DG4 J23-DG5 NET 'GROUND' J23-DG6 J23-DG7 J23-DG8 J23-DG9 J23-DG10 NET 'GROUND' J23-EG1 J23-EG2 J23-EG3 J23-EG4 J23-EG5 NET 'GROUND' J23-EG6 J23-EG7 J23-EG8 J23-EG9 J23-EG10 NET 'GROUND' J23-FG1 J23-FG2 J23-FG3 J23-FG4 J23-FG5 NET 'GROUND' J23-FG6 J23-FG7 J23-FG8 J23-FG9 J23-FG10 NET 'GROUND' J23-GG1 J23-GG2 J23-GG3 J23-GG4 J23-GG5 NET 'GROUND' J23-GG6 J23-GG7 J23-GG8 J23-GG9 J23-GG10 NET 'GROUND' J23-HG1 J23-HG2 J23-HG3 J23-HG4 J23-HG5 NET 'GROUND' J23-HG6 J23-HG7 J23-HG8 J23-HG9 J23-HG10 # # Connector J24 # NET 'GROUND' J24-AG1 J24-AG2 J24-AG3 J24-AG4 J24-AG5 NET 'GROUND' J24-AG6 J24-AG7 J24-AG8 NET 'GROUND' J24-BG1 J24-BG2 J24-BG3 J24-BG4 J24-BG5 NET 'GROUND' J24-BG6 J24-BG7 J24-BG8 NET 'GROUND' J24-CG1 J24-CG2 J24-CG3 J24-CG4 J24-CG5 NET 'GROUND' J24-CG6 J24-CG7 J24-CG8 NET 'GROUND' J24-DG1 J24-DG2 J24-DG3 J24-DG4 J24-DG5 NET 'GROUND' J24-DG6 J24-DG7 J24-DG8 NET 'GROUND' J24-EG1 J24-EG2 J24-EG3 J24-EG4 J24-EG5 NET 'GROUND' J24-EG6 J24-EG7 J24-EG8 NET 'GROUND' J24-FG1 J24-FG2 J24-FG3 J24-FG4 J24-FG5 NET 'GROUND' J24-FG6 J24-FG7 J24-FG8 NET 'GROUND' J24-GG1 J24-GG2 J24-GG3 J24-GG4 J24-GG5 NET 'GROUND' J24-GG6 J24-GG7 J24-GG8 NET 'GROUND' J24-HG1 J24-HG2 J24-HG3 J24-HG4 J24-HG5 NET 'GROUND' J24-HG6 J24-HG7 J24-HG8 # # IPMC: Hardware Address, Handle Switch, IPMBuses # ---------------------------------------------------- # # # Original Rev. 15-Apr-2015 # Current Rev. 17-Jan-2017 # # # # This file holds all of the nets for the IPMC: # # - Hardware Slot Address from the Zone 1 Connector. # # - The Handle Switch for card hot-swap. # # - The "A" and "B" IPMBus connections through the # Zone 1 Connector to the Shelf Manager. # # - The Management I2C Bus from the IPMC to the # FRU&SDR EEPROM and to the Power Entry Module. # # - All of the associated connections to the # M24256 I2C Serial EEPROM the FRU&SDR EEPROM. # # # # Slot Hardware Address Lines # NET 'HW_ADRS_0' P10-5 IPMC-115 NET 'HW_ADRS_1' P10-6 IPMC-237 NET 'HW_ADRS_2' P10-7 IPMC-116 NET 'HW_ADRS_3' P10-8 IPMC-238 NET 'HW_ADRS_4' P10-9 IPMC-117 NET 'HW_ADRS_5' P10-10 IPMC-239 NET 'HW_ADRS_6' P10-11 IPMC-118 NET 'HW_ADRS_7' P10-12 IPMC-240 # # And the Filters on the Hardware Addres Signals. # NET 'HW_ADRS_0' C1551-1 R1551-2 NET 'HW_ADRS_1' C1552-2 R1552-1 NET 'HW_ADRS_2' C1553-1 R1553-2 NET 'HW_ADRS_3' C1554-2 R1554-1 NET 'HW_ADRS_4' C1555-1 R1555-2 NET 'HW_ADRS_5' C1556-2 R1556-1 NET 'HW_ADRS_6' C1557-1 R1557-2 NET 'HW_ADRS_7' C1558-2 R1558-1 NET 'GROUND' C1551-2 C1552-1 NET 'GROUND' C1553-2 C1554-1 NET 'GROUND' C1555-2 C1556-1 NET 'GROUND' C1557-2 C1558-1 NET 'IPMC_3V3' R1551-1 R1552-2 NET 'IPMC_3V3' R1553-1 R1554-2 NET 'IPMC_3V3' R1555-1 R1556-2 NET 'IPMC_3V3' R1557-1 R1558-2 # # Handle Switch Connection to the IPMC # # On 5-Dec-16 the pcb mount handle switch scheme was # abandon in favor of the Elma type of front panel with # the switch in the handle and the connection to the pcb # made with discrete wire runs to a Molex connector. # # I will use a Molex 53047-0310 connector on the Hub pcb. # # This mates with the Molex 51021-0300 on the Elma switch # assembly. # # There is still the issue of the required polarity of the # switch to work with the supplied IPMC module and the # major problem that the people who made the IPMC want you # to run the switch on the Hot side of the line - a stupid # dangerous setup. R961 is to limit worst case current # from IPMC_3V3_SRC into the handle switch circuit. # # Because I do not understand the switch polarity I'm mounting # it in 3 vias so that I can rotate it by 180 deg as necassary. # # The assembly house will not install this connector. # This is a through-hole part that we can install during # MSU Final Assembly. # NET 'IPMC_3V3_SRC' R961-1 NET 'Handle_SW_SRC' R961-2 Wterm72-1 NET 'Handle_Switch' Wterm71-1 IPMC-224 NET 'Handle_Switch' C1559-2 R1559-1 NET 'GROUND' C1559-1 R1559-2 NET 'No_Conn_Wterm63' Wterm73-1 # # IPMBus connections: Zone 1 Connector to IPMC # NET 'IPMBus_A_SCL' P10-13 IPMC-120 NET 'IPMBus_A_SDA' P10-14 IPMC-121 NET 'IPMBus_B_SCL' P10-15 IPMC-242 NET 'IPMBus_B_SDA' P10-16 IPMC-243 # # The +12V Isolated Power Supply Module # Enable Signal from the IPMC # # Note that jumpers JMP5 and JMP6 are used to control # whether the IPMC controls the power supply startup # on the Hub Module in the normal way or whether the # enable signal is always given to the Isolated +12V # supply and to the Hub's power supply control logic. # # - Install JMP5 for normal IPMC control of startup. # # - Install JMP6 for immediate startup of the Hub # i.e. ignore the IPMC's Payload Power Control. # NET 'IPMC_Enable_12V' IPMC-225 JMP5-1 NET 'Hub_Power_Enable' JMP6-2 JMP5-2 R956-2 NET 'IPMC_3V3' JMP6-1 NET 'Enable_LED_Anode' R956-1 # # The Management I2C Bus and its connection to the # FRU&SDR EEPROM and to the Power Entry Module. # # Note that the actual net connections to the # Power Entry Module are defined in the nets file # atca_power_entry_nets # NET 'IPMC_MGT_I2C_SDA' IPMC-221 U41-5 NET 'IPMC_MGT_I2C_SCK' IPMC-220 U41-6 # # Associated connections to the FRU&SDR EEPROM # and its bypass capacitor. NET 'IPMC_3V3' U41-8 C1570-1 NET 'GROUND' U41-4 C1570-2 NET 'GROUND' U41-1 U41-2 U41-3 NET 'No_Conn_U41_pin_WC' U41-7 # # This is the Key In Net List file for the Hub Module # # Clock 40.08 MHz Distribution Nets # ------------------------------------------------------ # # # Original Rev. 16-Apr-2015 # Most Recent Rev. 20-Jul-2016 # # # This file holds the Nets involved with the Distribution # of the 40.08 MHz LHC Clock signals. # # Specifically this nets file describes the outputs from # both the First and the Second 40.08 MHz Fanout chips, # i.e. the 4 way fanout U503 and the 16 way fanout U504. # # The outputs from the 4 way fanout U503 are always active # and they will be listed first. # # The outputs from the 16 way fanout U504 are only active # if this is the Hub Module that receives the FELIX Optical # TTC clock signal and distributes it over the backplane to # the 12 FEX cards and to the Other Hub. # # # #=========================================================== # # # Outputs from the 4 Way 40.08 MHz Fanout U503 # # # 40.08 MHz LHC Clock to the ROD Mezzanine. # NET 'Clk_to_Cap_to_ROD_Dir' U503-13 C1627-1 NET 'Clk_to_Cap_to_ROD_Cmp' U503-14 C1628-1 NET 'ROD_LHC_CLK_Dir' C1627-2 Meg_S1-C39 NET 'ROD_LHC_CLK_Cmp' C1628-2 Meg_S1-B39 # # 40.08 MHz Logic Clock to a Global Clock Input # on This Hub's Virtex FPGA. # NET 'Clk_40_to_Cap_to_FPGA_Logic_Dir' U503-15 C1629-1 NET 'Clk_40_to_Cap_to_FPGA_Logic_Cmp' U503-16 C1630-1 NET 'Logic_Clk_40.08_MHz_to_FPGA_Dir' C1629-2 U1-J24 # IO_L12P_T1U_N10_GC_71 NET 'Logic_Clk_40.08_MHz_to_FPGA_Cmp' C1630-2 U1-H24 # IO_L12N_T1U_N11_GC_71 # # 40.08 MHz Reference to the 320.64 MHz PLL # the high frequency clock generator for the Hub's # Virtex FPGA MGT Transceivers. # NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Dir' U503-9 NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Cmp' U503-10 # # 40.08 MHz Clock output from the First Fanout that # drives the Input 0 of the Second 40.08 MHz Fanout. # NET 'Drive_to_Second_40.08_MHz_Fanout_Dir' U503-11 NET 'Drive_to_Second_40.08_MHz_Fanout_Cmp' U503-12 # # There are no spare outputs from the First 40.08 MHz # Fanout so there are no "No_Conn" pins in this section. # # #=========================================================== # # # Outputs from the 16 Way 40.08 MHz Fanout U504 # # # Nets to carry the 40.08 MHz LHC Clock from the # 16 Way Clock Fanout Chip to the AC Coupling Caps # for the Backplane Zone 2 distribution to FEX cards # and to the Other Hub. # NET 'Clk_to_Cap_to_Other_Hub_Dir' U504-18 C1601-1 NET 'Clk_to_Cap_to_Other_Hub_Cmp' U504-19 C1602-1 NET 'Clk_to_Cap_to_FEX_03_Dir' U504-20 C1603-1 NET 'Clk_to_Cap_to_FEX_03_Cmp' U504-21 C1604-1 NET 'Clk_to_Cap_to_FEX_04_Dir' U504-22 C1605-1 NET 'Clk_to_Cap_to_FEX_04_Cmp' U504-23 C1606-1 NET 'Clk_to_Cap_to_FEX_05_Dir' U504-25 C1607-1 NET 'Clk_to_Cap_to_FEX_05_Cmp' U504-26 C1608-1 NET 'Clk_to_Cap_to_FEX_06_Dir' U504-27 C1609-1 NET 'Clk_to_Cap_to_FEX_06_Cmp' U504-28 C1610-1 NET 'Clk_to_Cap_to_FEX_07_Dir' U504-29 C1611-1 NET 'Clk_to_Cap_to_FEX_07_Cmp' U504-30 C1612-1 NET 'Clk_to_Cap_to_FEX_08_Dir' U504-31 C1613-1 NET 'Clk_to_Cap_to_FEX_08_Cmp' U504-32 C1614-1 NET 'Clk_to_Cap_to_FEX_09_Dir' U504-33 C1615-1 NET 'Clk_to_Cap_to_FEX_09_Cmp' U504-34 C1616-1 NET 'Clk_to_Cap_to_FEX_10_Dir' U504-35 C1617-1 NET 'Clk_to_Cap_to_FEX_10_Cmp' U504-36 C1618-1 NET 'Clk_to_Cap_to_FEX_11_Dir' U504-38 C1619-1 NET 'Clk_to_Cap_to_FEX_11_Cmp' U504-39 C1620-1 NET 'Clk_to_Cap_to_FEX_12_Dir' U504-40 C1621-1 NET 'Clk_to_Cap_to_FEX_12_Cmp' U504-41 C1622-1 NET 'Clk_to_Cap_to_FEX_13_Dir' U504-42 C1623-1 NET 'Clk_to_Cap_to_FEX_13_Cmp' U504-43 C1624-1 NET 'Clk_to_Cap_to_FEX_14_Dir' U504-44 C1625-1 NET 'Clk_to_Cap_to_FEX_14_Cmp' U504-45 C1626-1 # # There are 3 spare outputs on the Second 40.08 MHz Fanout. # These 3 pairs are defined here as No_Conn pins. # NET 'No_Conn_Second_40_MHz_FO_Out_0_Dir' U504-14 NET 'No_Conn_Second_40_MHz_FO_Out_0_Cmp' U504-15 NET 'No_Conn_Second_40_MHz_FO_Out_1_Dir' U504-16 NET 'No_Conn_Second_40_MHz_FO_Out_1_Cmp' U504-17 NET 'No_Conn_Second_40_MHz_FO_Out_15_Dir' U504-46 NET 'No_Conn_Second_40_MHz_FO_Out_15_Cmp' U504-47 # #=========================================================== # # # AC Coupling Capacitor to Zone 2 Connector Nets # # In all cases the 40.08 MHz LHC Clock is carried over # the backplane on the Fabric Interface Tx Port 0 # to the 12 FEX cards and to the Other Hub Module. # # # Clock to Other Hub ATCA Tx0[01] NET 'Clk_to_Other_Hub_Dir' C1601-2 J23-A4 NET 'Clk_to_Other_Hub_Cmp' C1602-2 J23-B4 # # Clock to FEX-03 Logical Slot 3 ATCA Tx0[02] NET 'Clk_to_FEX_03_Dir' C1603-2 J23-A2 NET 'Clk_to_FEX_03_Cmp' C1604-2 J23-B2 # # Clock to FEX-04 Logical Slot 4 ATCA Tx0[03] NET 'Clk_to_FEX_04_Dir' C1605-2 J22-A10 NET 'Clk_to_FEX_04_Cmp' C1606-2 J22-B10 # # Clock to FEX-05 Logical Slot 5 ATCA Tx0[04] NET 'Clk_to_FEX_05_Dir' C1607-2 J22-A8 NET 'Clk_to_FEX_05_Cmp' C1608-2 J22-B8 # # Clock to FEX-06 Logical Slot 6 ATCA Tx0[05] NET 'Clk_to_FEX_06_Dir' C1609-2 J22-A6 NET 'Clk_to_FEX_06_Cmp' C1610-2 J22-B6 # # Clock to FEX-07 Logical Slot 7 ATCA Tx0[06] NET 'Clk_to_FEX_07_Dir' C1611-2 J22-A4 NET 'Clk_to_FEX_07_Cmp' C1612-2 J22-B4 # # Clock to FEX-08 Logical Slot 8 ATCA Tx0[07] NET 'Clk_to_FEX_08_Dir' C1613-2 J22-A2 NET 'Clk_to_FEX_08_Cmp' C1614-2 J22-B2 # # Clock to FEX-09 Logical Slot 9 ATCA Tx0[08] NET 'Clk_to_FEX_09_Dir' C1615-2 J21-A10 NET 'Clk_to_FEX_09_Cmp' C1616-2 J21-B10 # # Clock to FEX-10 Logical Slot 10 ATCA Tx0[09] NET 'Clk_to_FEX_10_Dir' C1617-2 J21-A8 NET 'Clk_to_FEX_10_Cmp' C1618-2 J21-B8 # # Clock to FEX-11 Logical Slot 11 ATCA Tx0[10] NET 'Clk_to_FEX_11_Dir' C1619-2 J21-A6 NET 'Clk_to_FEX_11_Cmp' C1620-2 J21-B6 # # Clock to FEX-12 Logical Slot 12 ATCA Tx0[11] NET 'Clk_to_FEX_12_Dir' C1621-2 J21-A4 NET 'Clk_to_FEX_12_Cmp' C1622-2 J21-B4 # # Clock to FEX-13 Logical Slot 13 ATCA Tx0[12] NET 'Clk_to_FEX_13_Dir' C1623-2 J21-A2 NET 'Clk_to_FEX_13_Cmp' C1624-2 J21-B2 # # Clock to FEX-14 Logical Slot 14 ATCA Tx0[13] NET 'Clk_to_FEX_14_Dir' C1625-2 J20-A10 NET 'Clk_to_FEX_14_Cmp' C1626-2 J20-B10 # # Clock Generation Nets File # ------------------------------- # # # Original Rev. 22-May-2015 # Current Rev. 17-Jan-2017 # # # # This file holds the nets involved in the Generation # of the various Clock signals on the Hub Module. # # The Clock signals include: # # - 25.00 MHz crystal clock for the Ethernet Phys chips, # for the Ethernet Switch chips, and send to # the FPGA as a Logic Clock. # # - 40.08 MHz LHC locked clock that is sent to the # 12 FEX cards, to the Other Hub, to # the ROD mezzanine, to This Hub's FPGA # as a Logic Clock, and sent as a reference # to the high frequency clock generators # for the two MTG reference clocks. # # - 320.64 MHz LHC locked clock that is sent to the # FPGA as both a Transceiver Reference # Clock and as a Logic Clock. # # # This file also includes the distribution networks # for most of these clock signals. Typically the # section of the distribution network that is included # in this file includes just the fanout chip, and any # AC Coupling Capacitors or Termination Resistors. # The actual net list connection to the pin on the # load (e.g. a Reference Clock Input on the FPGA) # is called out in a separate file. # # # # The 25.000 MHz Crystal Clock and its Distribution Network # ------------------------------------------------------------ # # # The components included in the 25 MHz crystal clock and # its distribution network are the following: # # U38 25 MHz Crystal Oscillator ConWin 813 25 MHz # # U39 6 way Single Ended CMOS Fanout TI CDCLVC1106 # # L391 and C391 are power filters to make the ECLK_3V3 rail. # # C392:C395 ByPass Capacitors on the ECLK_3V3 rail # # R2019, R2119, R2219 the series terminators to the Switch Chips # # R1916, R1966 are the series terminators to the Phys Chips # # R501 is the series terminator to the Hub FPGA # 25 MHz Global Clock Input # # This file defines the Global Clock input pin on the Hub's # FPGA for the 25 MHz Ethernet Clock signal. Note that # this is a 3V3 pin in a 3V3 Select I/O Bank. # # # Start with the 3V3 Ethernet Clock power noise/isolation filters. # NET 'BULK_3V3' L391-1 C391-1 NET 'ECLK_3V3' L391-2 NET 'GROUND' C391-2 # # The 25.000 MHz Crystal Oscillator # NET 'ECLK_3V3' U38-4 U38-1 C392-1 C393-1 NET 'GROUND' U38-2 C392-2 C393-2 # # The 25.000 Mhz Fanout # NET 'ECLK_3V3' U39-5 U39-8 U39-12 C394-1 C395-1 NET 'GROUND' U39-4 U39-7 U39-10 C394-2 C395-2 NET 'ECLK_3V3' U39-2 NET 'CLOCK_25_MHz_to_Fanout' U38-3 U39-1 NET 'CLOCK_for_Phys_U21' U39-14 R1916-1 NET 'CLOCK_for_Phys_U22' U39-13 R1966-1 NET 'Phys_U22_X1' R1916-2 NET 'Phys_U21_X1' R1966-2 NET 'CLOCK_25_MHz_Series_Term_FPGA' U39-3 R501-1 NET 'CLOCK_25_MHz_FPGA' R501-2 U1-AT15 # IO_L14P_T2L_N2_GC_84 NET 'CLOCK_for_SW_C' U39-6 R2219-2 NET 'CLOCK_for_SW_B' U39-11 R2119-2 NET 'CLOCK_for_SW_A' U39-9 R2019-2 NET 'SW_C_CLOCK' R2219-1 NET 'SW_B_CLOCK' R2119-1 NET 'SW_A_CLOCK' R2019-1 # # The 40.08 MHz Clock Generation and Distribution Feed: # -------------------------------------------------------- # # # The components in the 40.08 MHz LHC Locked Clock include: # # U501 an LVDS Receiver that receives the 40.08 MHz reference # from the Hub FPGA and delivers a back terminated singled # ended 3.3 Volt CMOS level copy of this reference to # the 40.08 MHz PLL. # # # U502 a 40.0787 MHz PLL with a Quartz Crystal VCXO. # The Reference for this PLL comes from either: # # - the recovered clock from the optical TTC signal that # is received by the Hub and processed by its FPGA or # # - it comes from the Other Hub and is received on # backplane connector J23 pins C4, D4. # # Note that the MUX to select which reference clock is # sent to the 40.08 MHz PLL is in the Hub's FPGA itself. # # # U503 a 4 way LVDS Clock Fanout chip that runs on 2V5 # power. The output nets from this Fanout Chip are # in a separate nets file named, "clock_40.08_MHz_distribution_nets". # This chips feeds the 40.08 MHz LHC Locked clock # to the following consumers located on this Hub Module: # # - to the ROD on This Hub # - to the 320.64 MHz PLL # - to a Global Logic Clock input on This Hub's FPGA # - to the U504 16 way fanout chip for the 40.08 MHz Clk # # # U504 a 16 way LVDS Clock Fanout chip that runs on 2V5 # power. The output nets from this Fanout Chip are # in a separate nets file named, "clock_40.08_MHz_distribution_nets". # This chips feeds the 40.08 MHz LHC Locked clock # over the backplane to the following consumers: # # - to the 12 FEX cards # - to the Other Hub # # Note that the U504 outputs can be put into a still # driven but quiescent state under the control of this # Hub Module's FPGA. # # # Start with the 2V5 and 3V3 Clock power noise/isolation filters. # # The BULK_2V5 feed to L352 will arrive via discrete wire # to the wire terminal component WTERM52 and uses # Power Via Arrays to get down to the CLK_2V5 Area Fill. # NET 'BULK_3V3' L351-1 C351-1 PVA11_CLK-1 PVA12_CLK-1 PVA13_CLK-1 NET 'CLK_3V3' L351-2 PVA14_CLK-1 PVA15_CLK-1 PVA16_CLK-1 NET 'GROUND' C351-2 NET 'BULK_2V5_Wire' L352-1 C352-1 WTERM52-1 PVA4_CLK-1 NET 'CLK_2V5' L352-2 PVA1_CLK-1 PVA2_CLK-1 PVA3_CLK-1 NET 'GROUND' C352-2 # # Nets that receiver the 40.08 MHz Reference Clock # from the Other Hub. Note that these runs from # the Backplane to the FPGA involve a Diff Pair Via. # NET 'Ref_40.08_MHz_from_Other_Hub_Dir' J23-C4 U1-H23 # IO_L14P_T2L_N2_GC_71 NET 'Ref_40.08_MHz_from_Other_Hub_Cmp' J23-D4 U1-G23 # IO_L14N_T2L_N3_GC_71 NET 'Ref_40.08_MHz_from_Other_Hub_Dir' DPV701-2 # Differential Pair NET 'Ref_40.08_MHz_from_Other_Hub_Cmp' DPV701-3 # Via in run from the NET 'GROUND' DPV701-1 DPV701-4 # Backplane to the FPGA # # Nets that connect the 40.08 MHz LVDS Reference from the # Hub FPGA, through a LVDS Receiver, and then to the # 40.08 MHz PLL's reference input. # NET 'Ref_40.08_MHz_from_FPGA_to_Rec_Dir' U501-3 U1-AV31 # IO_L7P_T1L_N0_QBC_AD13P_68 NET 'Ref_40.08_MHz_from_FPGA_to_Rec_Cmp' U501-4 U1-AW31 # IO_L7N_T1L_N1_QBC_AD13N_68 NET 'Ref_40.08_MHz_from_Rec_to_Term' U501-5 R1607-1 NET 'Ref_40.08_MHz_from_Term_to_PLL' R1607-2 U502-1 # # Nets that connect the U502 40.08 MHz PLL Output # to Input 0 of the U503 4x LVDS fanout chip, # i.e. the FIRST 40.08 MHz Fanout. # # Note that I'm using Back Termination in the form of # R1613 and R1614 to make the conversion from an LVPECL # swing to the LVDS swing that is required at the input # to this Fanout chip, the FIRST 40.08 MHz Fanout. # # INPUT #0 is being used on this Fanout. # NET 'PLL_40.08_MHz_Output_Dir' U502-6 R1613-1 NET 'PLL_40.08_MHz_Output_Cmp' U502-7 R1614-1 NET 'PLL_40.08_MHz_R_to_C_Dir' R1613-2 C1651-1 NET 'PLL_40.08_MHz_R_to_C_Cmp' R1614-2 C1652-1 NET 'Fanout_40.08_MHz_Input_Dir' C1651-2 U503-6 R1615-1 NET 'Fanout_40.08_MHz_Input_Cmp' C1652-2 U503-7 R1616-1 NET 'First_Fanout_CMM_Ref' U503-8 R1615-2 R1616-2 C374-1 NET 'GROUND' C374-2 # # Nets that tell the FIRST 40.08 MHz Fanout chip # to use its Input 0. Grounding the U503 In_Sel # pin #2 selects its Input 0. # NET 'Select_Input_First_40_Fanout' U503-2 R1611-1 NET 'GROUND' R1611-2 # # Nets to Tie Off the IN #1 input on the FIRST 40.08 MHz Fanout. # NET 'First_Fanout_CMM_Ref' U503-4 NET 'Tie_Off_1st_40_FO_IN1_P' U503-3 R1620-1 NET 'GROUND' R1620-2 # # Input to the SECOND 40.08 MHz Fanout Chip # comes from the FIRST 40.08 MHz Fanout Chip. # # Show here the termination / DC operating point resistors # and the AC Coupling Capacitors. # # This is Input 0 on the Second 40.08 MHz Fanout U504 # # The input signal source for this Second Fanout is given # in the nets file: clock_40.08_MHz_distribution_nets # # Note that I'm using the #1 Common Mode Voltage Reference # even though I'm using Input #0. This is for routing. # # Note that the Input #1 is not left floating. One side # is tied to the Common Mode Reference Voltage Source and # the other side is tied to Ground through a 1k Ohm resistor. # NET 'Drive_to_Second_40.08_MHz_Fanout_Dir' C1655-1 NET 'Drive_to_Second_40.08_MHz_Fanout_Cmp' C1656-1 NET 'Second_Fanout_40.08_MHz_Input_Dir' C1655-2 U504-10 R1601-1 NET 'Second_Fanout_40.08_MHz_Input_Cmp' C1656-2 U504-9 R1602-1 NET 'Second_Fanout_CMM_Ref' U504-5 C372-1 R1601-2 R1602-2 NET 'GROUND' C372-2 # Tie off Input #1 of the SECOND 40.08 MHz Fanout NET 'Second_Fanout_CMM_Ref' U504-4 NET 'Tie_Off_2nd_40_FO_IN1_P' U504-3 R1619-1 NET 'GROUND' R1619-2 # # Nets that tell the SECOND 40.08 MHz Fanout chip # to follow the instructions and select either its # Input 0 or not to select either input. # # When the U504 In_Sel pin #2 is Low then this # fanout chip selects its Input 0. # # When the U504 In_Sel pin #2 is in the Middle of # its 2V5 Vcc range then it selects neither of # its inputs and thus its output is static. # # The control information to the U504 fanout chip # In_Sel pin comes from this Hub Module's FPGA # (and Open Drain pin in a 1V8 I/O Bank) and # a pair of 5k Ohm resistors between BULK_2V5 # and Ground/ # NET 'Select_Input_Second_40_Fanout' U504-2 R1617-1 R1618-1 NET 'CLK_2V5' R1617-2 NET 'GROUND' R1618-2 NET 'Select_Input_Second_40_Fanout' U1-A26 # IO_L24N_T3U_N11_70 # # Nets to connect the 40.08 MHz PLL Lock Detect # signal from the PLL to the Hub's FPGA. # NET 'PLL_40.08_MHz_Lock_Detect_Output' U502-10 R1609-1 NET 'PLL_40.08_MHz_Lock_Detect_to_FPGA' R1609-2 U1-B27 # IO_L22P_T3U_N6_DBC_AD0P_70 # # Power and Ground: to the U501 65LVDT2 Receiver for the FPGA Ref Signal # in the to the U502 40.08 MHz PLL # 40.08 MHz to The U503 4x Fanout of the 40.08 MHz clock # section to The U504 16x Fanout of the 40.08 MHz clock # NET 'CLK_3V3' U501-1 C370-1 NET 'GROUND' U501-2 C370-2 NET 'CLK_3V3' U502-9 NET 'GROUND' U502-2 U502-8 NET 'CLK_3V3' C353-1 C354-1 C355-1 NET 'GROUND' C353-2 C354-2 C355-2 NET 'CLK_2V5' U503-5 NET 'GROUND' U503-1 U503-17 U503-18 U503-19 U503-20 NET 'CLK_2V5' C375-1 C376-1 C377-1 NET 'GROUND' C375-2 C376-2 C377-2 NET 'CLK_2V5' U504-6 U504-7 U504-13 U504-24 U504-37 U504-48 NET 'GROUND' U504-1 U504-12 NET 'GROUND' U504-49 U504-50 U504-51 U504-52 NET 'GROUND' U504-53 U504-54 U504-55 U504-56 NET 'GROUND' U504-57 U504-58 U504-59 U504-60 NET 'GROUND' U504-61 U504-62 U504-63 U504-64 NET 'CLK_2V5' C359-1 C360-1 C361-1 C362-1 C363-1 C364-1 NET 'GROUND' C359-2 C360-2 C361-2 C362-2 C363-2 C364-2 # # No_Connect pins on the 40.08 MHz PLL and its Fanout Chips: # NET 'No_Conn_40_PLL_pin_3' U502-3 NET 'No_Conn_40_PLL_pin_4' U502-4 NET 'No_Conn_40_PLL_pin_5' U502-5 NET 'No_Conn_2nd_40_FO_Ref_8' U504-8 NET 'No_Conn_2nd_40_FO_11' U504-11 # # The 320.64 MHz Clock Generation: # ----------------------------------- # # # The components in the 320.64 MHz LHC Locked Clock include: # # U505 an LVDS Receiver that receives the 40.08 MHz reference # from the 40.08 MHz PLL distribution and delivers a back # terminated singled ended 2.5 Volt CMOS level copy of # this reference to the 320.64 MHz PLL. # # U506 a 320.6296 MHz PLL with a Quartz Crystal VCXO. # The Reference for this PLL comes from the distribution # fanout for the 40.08 MHz PLL. # # U507 a 10 way LVPECL Clock Fanout chip that runs on 2V5 # power. The output nets from this Fanout Chip are # at the end of this file. # This chips feeds the 320.64 MHz LHC Locked clock to: # # - up to 8 Reference Clock inputs to the # MGT Transceivers on the Hub FPGA # # - to a Global Logic Clock input on the Hub's FPGA # # # Nets that connect the 40.08 MHz LVDS Reference from the # Fanout of the 40.08 MHz PLL, through a LVDS Receiver, # and then to the 320.64 MHz PLL's reference input. # NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Dir' U505-3 NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Cmp' U505-4 NET 'HF_PLL_Ref_from_Rec_to_Term' U505-5 R1608-1 NET 'HF_PLL_Ref_from_Term_to_PLL' R1608-2 U506-1 # # Nets that connect the U506 320.64 MHz PLL Output # to Input 0 of the U507 10x LVPECL Fanout chip: # NET 'PLL_320.64_MHz_Output_Dir' U506-6 C1654-1 # Polarity Flip NET 'PLL_320.64_MHz_Output_Cmp' U506-7 C1653-1 # for Routing NET 'Fanout_320.64_MHz_Input_Dir' C1653-2 U507-3 R1603-1 NET 'Fanout_320.64_MHz_Input_Cmp' C1654-2 U507-4 R1604-1 NET 'Fanout_320.64_MHz_CMM_Ref' R1603-2 R1604-2 C373-1 NET 'GROUND' R1606-1 C373-2 NET 'CLK_2V5' R1605-1 NET 'Fanout_320.64_MHz_CMM_Ref' R1606-2 R1605-2 # # Nets to connect the 320.64 MHz PLL Lock Detect # signal from the PLL to the Hub's FPGA. # NET 'PLL_320.64_MHz_Lock_Detect_Output' U506-10 R1610-1 NET 'PLL_320.64_MHz_Lock_Detect_to_FPGA' R1610-2 U1-B26 # IO_L24P_T3U_N10_70 # # Nets that tell the 320.64 MHz Fanout chip to use its Input 0. # Grounding U507 In_Sel pin #2 selects its Input 0. # NET 'Select_Input_320_Fanout' U507-2 R1612-1 NET 'GROUND' R1612-2 # # Power and Ground: to the U505 65LVDT2 Receiver for the 40.08 Fanout Ref Signal # to the U506 320.64 MHz PLL # to The U507 10x Fanout of the 320.64 MHz clock # NET 'CLK_3V3' U505-1 C371-1 NET 'GROUND' U505-2 C371-2 NET 'CLK_3V3' U506-9 NET 'GROUND' U506-2 U506-8 NET 'CLK_3V3' C356-1 C357-1 C358-1 NET 'GROUND' C356-2 C357-2 C358-2 NET 'CLK_2V5' U507-1 U507-9 U507-16 U507-25 U507-32 NET 'GROUND' U507-8 U507-33 U507-34 U507-35 U507-36 NET 'GROUND' U507-37 U507-38 U507-39 U507-40 U507-41 NET 'CLK_2V5' C365-1 C366-1 C367-1 C368-1 C369-1 NET 'GROUND' C365-2 C366-2 C367-2 C368-2 C369-2 # # No_Connect pins on the 320.64 MHz PLL and its Fanout Chip: # NET 'No_Conn_320_PLL_pin_3' U506-3 NET 'No_Conn_320_PLL_pin_4' U506-4 NET 'No_Conn_320_PLL_pin_5' U506-5 NET 'No_Conn_320_Fanout_Ref_5' U507-5 NET 'No_Conn_320_Fanout_Clk_1' U507-6 NET 'No_Conn_320_Fanout_Clk_1_b' U507-7 NET 'No_Conn_320_Fanout_Q0_B' U507-30 NET 'No_Conn_320_Fanout_Q0' U507-31 # # The 320.64 MHz Clock Distribution: # ------------------------------------- # # # This section of the netlist contains the outputs # from the U507 LVPECL Fanout chip for the # 320.64 MHz clock signal. # # 8 of these AC Coupled LVPECL 320.64 MHz Fanout signals # are Reference Clocks to the MGT Transceivers. # # 1 of these AC Coupled LVPECL 320.64 MHz Fanout signals # is a Logic Clock to a Global Clock Input in HP IO Bank 71. # Note that in this case the LVPECL clock signal is back # terminated with R1651/R1652 so that it can correctly drive # the LVDS input in HP IO Bank 71. # NET 'MHz_320.64_Fan_Ouput_1_Dir' U507-29 C1631-2 R1631-2 NET 'MHz_320.64_Fan_Ouput_1_Cmp' U507-28 C1632-2 R1632-2 NET 'MHz_320.64_COPY_0_DIR' C1631-1 U1-AE36 # MGTREFCLK0P_125 NET 'MHz_320.64_COPY_0_CMP' C1632-1 U1-AE37 # MGTREFCLK0N_125 NET 'GROUND' R1631-1 R1632-1 NET 'MHz_320.64_Fan_Ouput_2_Dir' U507-27 C1633-2 R1633-2 NET 'MHz_320.64_Fan_Ouput_2_Cmp' U507-26 C1634-2 R1634-2 NET 'MHz_320.64_COPY_1_DIR' C1633-1 U1-R36 # MGTREFCLK0P_130 NET 'MHz_320.64_COPY_1_CMP' C1634-1 U1-R37 # MGTREFCLK0N_130 NET 'GROUND' R1633-1 R1634-1 NET 'MHz_320.64_Fan_Ouput_3_Dir' U507-24 C1635-2 R1635-2 NET 'MHz_320.64_Fan_Ouput_3_Cmp' U507-23 C1636-2 R1636-2 NET 'MHz_320.64_COPY_2_DIR' C1635-1 U1-K34 # MGTREFCLK1P_132 NET 'MHz_320.64_COPY_2_CMP' C1636-1 U1-K35 # MGTREFCLK1N_132 NET 'GROUND' R1635-1 R1636-1 NET 'MHz_320.64_Fan_Ouput_4_Dir' U507-22 C1637-2 R1637-2 NET 'MHz_320.64_Fan_Ouput_4_Cmp' U507-21 C1638-2 R1638-2 NET 'MHz_320.64_COPY_3_DIR' C1637-1 U1-Y34 # MGTREFCLK1P_127 NET 'MHz_320.64_COPY_3_CMP' C1638-1 U1-Y35 # MGTREFCLK1N_127 NET 'GROUND' R1637-1 R1638-1 NET 'MHz_320.64_Fan_Ouput_5_Dir' U507-20 C1639-2 R1639-2 NET 'MHz_320.64_Fan_Ouput_5_Cmp' U507-19 C1640-2 R1640-2 NET 'Logic_Clk_320.64_MHz_Back_Term_Dir' C1639-1 R1651-1 NET 'Logic_Clk_320.64_MHz_Back_Term_Cmp' C1640-1 R1652-1 NET 'Logic_Clk_320.64_MHz_to_FPGA_Dir' R1651-2 U1-K22 # IO_L11P_T1U_N8_GC_71 NET 'Logic_Clk_320.64_MHz_to_FPGA_Cmp' R1652-2 U1-J22 # IO_L11N_T1U_N9_GC_71 NET 'GROUND' R1639-1 R1640-1 NET 'MHz_320.64_Fan_Ouput_6_Dir' U507-18 C1641-2 R1641-2 NET 'MHz_320.64_Fan_Ouput_6_Cmp' U507-17 C1642-2 R1642-2 NET 'MHz_320.64_COPY_6_DIR' C1641-1 U1-Y13 # MGTREFCLK1P_227 NET 'MHz_320.64_COPY_6_CMP' C1642-1 U1-Y12 # MGTREFCLK1N_227 NET 'GROUND' R1641-1 R1642-1 NET 'MHz_320.64_Fan_Ouput_7_Dir' U507-15 C1643-2 R1643-2 NET 'MHz_320.64_Fan_Ouput_7_Cmp' U507-14 C1644-2 R1644-2 NET 'MHz_320.64_COPY_7_DIR' C1643-1 U1-K13 # MGTREFCLK1P_232 NET 'MHz_320.64_COPY_7_CMP' C1644-1 U1-K12 # MGTREFCLK1N_232 NET 'GROUND' R1643-1 R1644-1 NET 'MHz_320.64_Fan_Ouput_8_Dir' U507-13 C1645-2 R1645-2 NET 'MHz_320.64_Fan_Ouput_8_Cmp' U507-12 C1646-2 R1646-2 NET 'MHz_320.64_COPY_8_DIR' C1645-1 U1-R11 # MGTREFCLK0P_230 NET 'MHz_320.64_COPY_8_CMP' C1646-1 U1-R10 # MGTREFCLK0N_230 NET 'GROUND' R1645-1 R1646-1 NET 'MHz_320.64_Fan_Ouput_9_Dir' U507-11 C1647-2 R1647-2 NET 'MHz_320.64_Fan_Ouput_9_Cmp' U507-10 C1648-2 R1648-2 NET 'MHz_320.64_COPY_9_DIR' C1647-1 U1-AE11 # MGTREFCLK0P_225 NET 'MHz_320.64_COPY_9_CMP' C1648-1 U1-AE10 # MGTREFCLK0N_225 NET 'GROUND' R1647-1 R1648-1 # # This is a Hub-Module Key In Net List file # # Combined Data Distribution Nets # ---------------------------------------------- # # # Original Rev. 16-Apr-2015 # Most Recent Rev. 14-Dec-2016 # # # This file holds the nets involved with the Distribution # of the "Combined Data". The Combined Data is the # TTC Data plus the ROD Back-Channel Data aka the ROD # Readout Control information. # # The Combined Data is carried on MGT links from the # Hub Module over ATCA Channels Port 1 Tx. # # The Combined Data runs to the 12 FEX Cards, to the # Other Hub Module, and to the ROD on This Hub Module. # # Recall that MGT Links are AC Coupled at their # source end. # # This file is now setup for the xcvu125-FLVC2104 part. # # # Nets from the Hub FPGA source of the Combined Data # to the AC Coupling Caps - just the FPGA end. # NET 'Comb_Data_to_Cap_to_ROD_Cmp' U1-W6 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 0 Bank 228 NET 'Comb_Data_to_Cap_to_ROD_Dir' U1-W7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_14_Dir' U1-N6 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 2 Bank 229 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_14_Cmp' U1-N7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_13_Dir' U1-L6 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 0 Bank 230 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_13_Cmp' U1-L7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_12_Dir' U1-J6 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 2 Bank 230 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_12_Cmp' U1-J7 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_11_Cmp' U1-A7 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 3 Bank 232 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_11_Dir' U1-A6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_10_Cmp' U1-B9 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 2 Bank 233 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_10_Dir' U1-B8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_09_Cmp' U1-A11 (NET_TYPE, 'DIFF_PAIR_HS') #GTH Tx 3 Bank 223 FLIPPED NET 'Comb_Data_to_Cap_to_FEX_09_Dir' U1-A10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_08_Dir' U1-A36 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 3 Bank 133 NET 'Comb_Data_to_Cap_to_FEX_08_Cmp' U1-A37 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_07_Dir' U1-B38 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 2 Bank 133 NET 'Comb_Data_to_Cap_to_FEX_07_Cmp' U1-B39 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_06_Dir' U1-A40 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 3 Bank 132 NET 'Comb_Data_to_Cap_to_FEX_06_Cmp' U1-A41 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_05_Dir' U1-J40 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 2 Bank 130 NET 'Comb_Data_to_Cap_to_FEX_05_Cmp' U1-J41 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_04_Dir' U1-L40 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 0 Bank 130 NET 'Comb_Data_to_Cap_to_FEX_04_Cmp' U1-L41 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_FEX_03_Dir' U1-N40 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 2 Bank 129 NET 'Comb_Data_to_Cap_to_FEX_03_Cmp' U1-N41 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Cap_to_Other_Hub_Dir' U1-R40 (NET_TYPE, 'DIFF_PAIR_HS') #GTY Tx 0 Bank 129 NET 'Comb_Data_to_Cap_to_Other_Hub_Cmp' U1-R41 (NET_TYPE, 'DIFF_PAIR_HS') # # Nets from the Hub FPGA source of the Combined Data # to the AC Coupling Caps - just the Cap end. # NET 'Comb_Data_to_Cap_to_Other_Hub_Dir' C1672-1 NET 'Comb_Data_to_Cap_to_Other_Hub_Cmp' C1671-1 NET 'Comb_Data_to_Cap_to_FEX_03_Dir' C1674-1 NET 'Comb_Data_to_Cap_to_FEX_03_Cmp' C1673-1 NET 'Comb_Data_to_Cap_to_FEX_04_Dir' C1676-1 NET 'Comb_Data_to_Cap_to_FEX_04_Cmp' C1675-1 NET 'Comb_Data_to_Cap_to_FEX_05_Dir' C1678-1 NET 'Comb_Data_to_Cap_to_FEX_05_Cmp' C1677-1 NET 'Comb_Data_to_Cap_to_FEX_06_Dir' C1680-1 NET 'Comb_Data_to_Cap_to_FEX_06_Cmp' C1679-1 NET 'Comb_Data_to_Cap_to_FEX_07_Dir' C1682-1 NET 'Comb_Data_to_Cap_to_FEX_07_Cmp' C1681-1 NET 'Comb_Data_to_Cap_to_FEX_08_Dir' C1684-1 NET 'Comb_Data_to_Cap_to_FEX_08_Cmp' C1683-1 NET 'Comb_Data_to_Cap_to_FEX_09_Dir' C1686-1 NET 'Comb_Data_to_Cap_to_FEX_09_Cmp' C1685-1 NET 'Comb_Data_to_Cap_to_FEX_10_Dir' C1688-1 NET 'Comb_Data_to_Cap_to_FEX_10_Cmp' C1687-1 NET 'Comb_Data_to_Cap_to_FEX_11_Dir' C1690-1 NET 'Comb_Data_to_Cap_to_FEX_11_Cmp' C1689-1 NET 'Comb_Data_to_Cap_to_FEX_12_Dir' C1692-1 NET 'Comb_Data_to_Cap_to_FEX_12_Cmp' C1691-1 NET 'Comb_Data_to_Cap_to_FEX_13_Dir' C1694-1 NET 'Comb_Data_to_Cap_to_FEX_13_Cmp' C1693-1 NET 'Comb_Data_to_Cap_to_FEX_14_Dir' C1696-1 NET 'Comb_Data_to_Cap_to_FEX_14_Cmp' C1695-1 NET 'Comb_Data_to_Cap_to_ROD_Dir' C1698-1 NET 'Comb_Data_to_Cap_to_ROD_Cmp' C1697-1 # # AC Coupling Capacitor to Zone 2 Connector Nets # for the Combined Data. # # In all cases the Combined Data is carried over # the backplane on the Fabric Interface Tx Port 1 # except to the ROD on This Hub it is carried on # MegArray connector S1 pins J2 (Dir) and H2 (Cmp). # # # Combined Data to Other Hub ATCA Tx1[01] NET 'Comb_Data_to_Other_Hub_Dir' C1672-2 J23-E4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_Other_Hub_Cmp' C1671-2 J23-F4 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-03 Logical Slot 3 ATCA Tx1[02] NET 'Comb_Data_to_FEX_03_Dir' C1674-2 J23-E2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_03_Cmp' C1673-2 J23-F2 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-04 Logical Slot 4 ATCA Tx1[03] NET 'Comb_Data_to_FEX_04_Dir' C1676-2 J22-E10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_04_Cmp' C1675-2 J22-F10 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-05 Logical Slot 5 ATCA Tx1[04] NET 'Comb_Data_to_FEX_05_Dir' C1678-2 J22-E8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_05_Cmp' C1677-2 J22-F8 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-06 Logical Slot 6 ATCA Tx1[05] NET 'Comb_Data_to_FEX_06_Dir' C1680-2 J22-E6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_06_Cmp' C1679-2 J22-F6 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-07 Logical Slot 7 ATCA Tx1[06] NET 'Comb_Data_to_FEX_07_Dir' C1682-2 J22-E4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_07_Cmp' C1681-2 J22-F4 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-08 Logical Slot 8 ATCA Tx1[07] NET 'Comb_Data_to_FEX_08_Dir' C1684-2 J22-E2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_08_Cmp' C1683-2 J22-F2 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-09 Logical Slot 9 ATCA Tx1[08] NET 'Comb_Data_to_FEX_09_Dir' C1686-2 J21-E10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_09_Cmp' C1685-2 J21-F10 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-10 Logical Slot 10 ATCA Tx1[09] NET 'Comb_Data_to_FEX_10_Dir' C1688-2 J21-E8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_10_Cmp' C1687-2 J21-F8 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-11 Logical Slot 11 ATCA Tx1[10] NET 'Comb_Data_to_FEX_11_Dir' C1690-2 J21-E6 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_11_Cmp' C1689-2 J21-F6 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-12 Logical Slot 12 ATCA Tx1[11] NET 'Comb_Data_to_FEX_12_Dir' C1692-2 J21-E4 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_12_Cmp' C1691-2 J21-F4 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-13 Logical Slot 13 ATCA Tx1[12] NET 'Comb_Data_to_FEX_13_Dir' C1694-2 J21-E2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_13_Cmp' C1693-2 J21-F2 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to FEX-14 Logical Slot 14 ATCA Tx1[13] NET 'Comb_Data_to_FEX_14_Dir' C1696-2 J20-E10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_FEX_14_Cmp' C1695-2 J20-F10 (NET_TYPE, 'DIFF_PAIR_HS') # # Combined Data to the ROD on This Hub Module via MegArray S1 NET 'Comb_Data_to_ROD_Dir' C1697-2 Meg_S1-J2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Comb_Data_to_ROD_Cmp' C1698-2 Meg_S1-H2 (NET_TYPE, 'DIFF_PAIR_HS') # # This is the Key In Net List file for the Hub Module # # Meg-Array #1 Power and Ground Nets # -------------------------------------------------------- # # # Original Rev. 17-Apr-2015 # Most Recent Rev. 28-Jun-2015 # # # This file holds the Power and Ground Nets # connected to Meg-Array Connector #1. # # The nets listed in this file are based on Ed's note # hub_rod_connectors_v1p3.pdf from 24-March-2015. # # # # Isolated +12 Volt Power Nets to Meg-Array Connector #1 Column "A" # NET 'ISO_12V' Meg_S1-A1 Meg_S1-A2 Meg_S1-A3 Meg_S1-A4 Meg_S1-A5 NET 'ISO_12V' Meg_S1-A6 Meg_S1-A7 Meg_S1-A8 Meg_S1-A9 Meg_S1-A10 NET 'ISO_12V' Meg_S1-A11 Meg_S1-A12 Meg_S1-A13 Meg_S1-A14 Meg_S1-A15 NET 'ISO_12V' Meg_S1-A16 Meg_S1-A17 Meg_S1-A18 Meg_S1-A19 Meg_S1-A20 NET 'ISO_12V' Meg_S1-A21 Meg_S1-A22 Meg_S1-A23 Meg_S1-A24 Meg_S1-A25 NET 'ISO_12V' Meg_S1-A26 Meg_S1-A27 Meg_S1-A28 Meg_S1-A29 Meg_S1-A30 NET 'ISO_12V' Meg_S1-A31 Meg_S1-A32 Meg_S1-A33 Meg_S1-A34 Meg_S1-A35 NET 'ISO_12V' Meg_S1-A36 Meg_S1-A37 Meg_S1-A38 Meg_S1-A39 Meg_S1-A40 # # Ground Nets to Meg-Array Connector #1 Column "B" # NET 'GROUND' Meg_S1-B5 NET 'GROUND' Meg_S1-B7 Meg_S1-B9 NET 'GROUND' Meg_S1-B11 Meg_S1-B13 Meg_S1-B15 NET 'GROUND' Meg_S1-B17 Meg_S1-B19 NET 'GROUND' Meg_S1-B21 Meg_S1-B23 NET 'GROUND' Meg_S1-B28 Meg_S1-B30 NET 'GROUND' Meg_S1-B32 Meg_S1-B34 NET 'GROUND' Meg_S1-B36 Meg_S1-B38 Meg_S1-B40 # # Ground Nets to Meg-Array Connector #1 Column "C" # NET 'GROUND' Meg_S1-C5 NET 'GROUND' Meg_S1-C7 Meg_S1-C9 NET 'GROUND' Meg_S1-C11 Meg_S1-C13 Meg_S1-C15 NET 'GROUND' Meg_S1-C17 Meg_S1-C19 NET 'GROUND' Meg_S1-C21 Meg_S1-C23 NET 'GROUND' Meg_S1-C28 Meg_S1-C30 NET 'GROUND' Meg_S1-C32 Meg_S1-C34 NET 'GROUND' Meg_S1-C36 Meg_S1-C38 Meg_S1-C40 # # Ground Nets to Meg-Array Connector #1 Column "D" # NET 'GROUND' Meg_S1-D1 Meg_S1-D2 Meg_S1-D3 Meg_S1-D4 Meg_S1-D5 NET 'GROUND' Meg_S1-D6 Meg_S1-D7 Meg_S1-D8 Meg_S1-D9 Meg_S1-D10 NET 'GROUND' Meg_S1-D11 Meg_S1-D12 Meg_S1-D13 Meg_S1-D14 Meg_S1-D15 NET 'GROUND' Meg_S1-D16 Meg_S1-D17 Meg_S1-D18 Meg_S1-D19 Meg_S1-D20 NET 'GROUND' Meg_S1-D21 Meg_S1-D22 Meg_S1-D23 Meg_S1-D24 Meg_S1-D25 NET 'GROUND' Meg_S1-D26 Meg_S1-D27 Meg_S1-D28 Meg_S1-D29 Meg_S1-D30 NET 'GROUND' Meg_S1-D31 Meg_S1-D32 Meg_S1-D33 Meg_S1-D34 Meg_S1-D35 NET 'GROUND' Meg_S1-D36 Meg_S1-D37 Meg_S1-D38 Meg_S1-D39 Meg_S1-D40 # # Ground Nets to Meg-Array Connector #1 Column "E" # NET 'GROUND' Meg_S1-E1 Meg_S1-E2 Meg_S1-E4 NET 'GROUND' Meg_S1-E6 Meg_S1-E8 Meg_S1-E10 NET 'GROUND' Meg_S1-E12 Meg_S1-E14 NET 'GROUND' Meg_S1-E16 Meg_S1-E18 Meg_S1-E20 NET 'GROUND' Meg_S1-E22 Meg_S1-E24 NET 'GROUND' Meg_S1-E26 Meg_S1-E28 Meg_S1-E30 NET 'GROUND' Meg_S1-E32 Meg_S1-E34 NET 'GROUND' Meg_S1-E36 Meg_S1-E38 Meg_S1-E40 # # Ground Nets to Meg-Array Connector #1 Column "F" # NET 'GROUND' Meg_S1-F1 Meg_S1-F2 Meg_S1-F4 NET 'GROUND' Meg_S1-F6 Meg_S1-F8 Meg_S1-F10 NET 'GROUND' Meg_S1-F12 Meg_S1-F14 NET 'GROUND' Meg_S1-F16 Meg_S1-F18 Meg_S1-F20 NET 'GROUND' Meg_S1-F22 Meg_S1-F24 NET 'GROUND' Meg_S1-F26 Meg_S1-F28 Meg_S1-F30 NET 'GROUND' Meg_S1-F32 Meg_S1-F34 NET 'GROUND' Meg_S1-F36 Meg_S1-F38 Meg_S1-F40 # # Ground Nets to Meg-Array Connector #1 Column "G" # NET 'GROUND' Meg_S1-G1 Meg_S1-G2 Meg_S1-G3 Meg_S1-G4 Meg_S1-G5 NET 'GROUND' Meg_S1-G6 Meg_S1-G7 Meg_S1-G8 Meg_S1-G9 Meg_S1-G10 NET 'GROUND' Meg_S1-G11 Meg_S1-G12 Meg_S1-G13 Meg_S1-G14 Meg_S1-G15 NET 'GROUND' Meg_S1-G16 Meg_S1-G17 Meg_S1-G18 Meg_S1-G19 Meg_S1-G20 NET 'GROUND' Meg_S1-G21 Meg_S1-G22 Meg_S1-G23 Meg_S1-G24 Meg_S1-G25 NET 'GROUND' Meg_S1-G26 Meg_S1-G27 Meg_S1-G28 Meg_S1-G29 Meg_S1-G30 NET 'GROUND' Meg_S1-G31 Meg_S1-G32 Meg_S1-G33 Meg_S1-G34 Meg_S1-G35 NET 'GROUND' Meg_S1-G36 Meg_S1-G37 Meg_S1-G38 Meg_S1-G39 Meg_S1-G40 # # Ground Nets to Meg-Array Connector #1 Column "H" # NET 'GROUND' Meg_S1-H1 Meg_S1-H3 Meg_S1-H5 NET 'GROUND' Meg_S1-H7 Meg_S1-H9 NET 'GROUND' Meg_S1-H11 Meg_S1-H13 Meg_S1-H15 NET 'GROUND' Meg_S1-H17 Meg_S1-H19 NET 'GROUND' Meg_S1-H21 Meg_S1-H23 Meg_S1-H25 NET 'GROUND' Meg_S1-H27 Meg_S1-H29 NET 'GROUND' Meg_S1-H31 Meg_S1-H33 Meg_S1-H35 NET 'GROUND' Meg_S1-H37 Meg_S1-H39 Meg_S1-H40 # # Ground Nets to Meg-Array Connector #1 Column "J" # NET 'GROUND' Meg_S1-J1 Meg_S1-J3 Meg_S1-J5 NET 'GROUND' Meg_S1-J7 Meg_S1-J9 NET 'GROUND' Meg_S1-J11 Meg_S1-J13 Meg_S1-J15 NET 'GROUND' Meg_S1-J17 Meg_S1-J19 NET 'GROUND' Meg_S1-J21 Meg_S1-J23 Meg_S1-J25 NET 'GROUND' Meg_S1-J27 Meg_S1-J29 NET 'GROUND' Meg_S1-J31 Meg_S1-J33 Meg_S1-J35 NET 'GROUND' Meg_S1-J37 Meg_S1-J39 Meg_S1-J40 # # Ground Nets to Meg-Array Connector #1 Column "K" # NET 'GROUND' Meg_S1-K1 Meg_S1-K2 Meg_S1-K3 Meg_S1-K4 Meg_S1-K5 NET 'GROUND' Meg_S1-K6 Meg_S1-K7 Meg_S1-K8 Meg_S1-K9 Meg_S1-K10 NET 'GROUND' Meg_S1-K11 Meg_S1-K12 Meg_S1-K13 Meg_S1-K14 Meg_S1-K15 NET 'GROUND' Meg_S1-K16 Meg_S1-K17 Meg_S1-K18 Meg_S1-K19 Meg_S1-K20 NET 'GROUND' Meg_S1-K21 Meg_S1-K22 Meg_S1-K23 Meg_S1-K24 Meg_S1-K25 NET 'GROUND' Meg_S1-K26 Meg_S1-K27 Meg_S1-K28 Meg_S1-K29 Meg_S1-K30 NET 'GROUND' Meg_S1-K31 Meg_S1-K32 Meg_S1-K33 Meg_S1-K34 Meg_S1-K35 NET 'GROUND' Meg_S1-K36 Meg_S1-K37 Meg_S1-K38 Meg_S1-K39 Meg_S1-K40 # # This is the Key In Net List file for the Hub Module # # Meg-Array #2 Ground Nets # -------------------------------------------------------- # # # Original Rev. 17-Apr-2015 # Most Recent Rev. 28-Jun-2015 # # # This file holds the Ground Nets # connected to Meg-Array Connector #2. # # The nets listed in this file are based on Ed's note # hub_rod_connectors_v1p3.pdf from 24-March-2015. # # # # Ground Nets to Meg-Array Connector #2 Column "A" # NET 'GROUND' Meg_S2-A1 Meg_S2-A2 Meg_S2-A3 Meg_S2-A4 Meg_S2-A5 NET 'GROUND' Meg_S2-A6 Meg_S2-A7 Meg_S2-A8 Meg_S2-A9 Meg_S2-A10 NET 'GROUND' Meg_S2-A11 Meg_S2-A12 Meg_S2-A13 Meg_S2-A14 Meg_S2-A15 NET 'GROUND' Meg_S2-A16 Meg_S2-A17 Meg_S2-A18 Meg_S2-A19 Meg_S2-A20 NET 'GROUND' Meg_S2-A21 Meg_S2-A22 Meg_S2-A23 Meg_S2-A24 Meg_S2-A25 NET 'GROUND' Meg_S2-A26 Meg_S2-A27 Meg_S2-A28 Meg_S2-A29 Meg_S2-A30 NET 'GROUND' Meg_S2-A31 Meg_S2-A32 Meg_S2-A33 Meg_S2-A34 Meg_S2-A35 NET 'GROUND' Meg_S2-A36 Meg_S2-A37 Meg_S2-A38 Meg_S2-A39 Meg_S2-A40 # # Ground Nets to Meg-Array Connector #2 Column "B" # NET 'GROUND' Meg_S2-B1 Meg_S2-B3 Meg_S2-B5 NET 'GROUND' Meg_S2-B7 Meg_S2-B9 NET 'GROUND' Meg_S2-B11 Meg_S2-B13 Meg_S2-B15 NET 'GROUND' Meg_S2-B17 Meg_S2-B19 NET 'GROUND' Meg_S2-B21 Meg_S2-B23 Meg_S2-B25 NET 'GROUND' Meg_S2-B27 Meg_S2-B29 NET 'GROUND' Meg_S2-B31 Meg_S2-B33 Meg_S2-B35 NET 'GROUND' Meg_S2-B37 Meg_S2-B39 Meg_S2-B40 # # Ground Nets to Meg-Array Connector #2 Column "C" # NET 'GROUND' Meg_S2-C1 Meg_S2-C3 Meg_S2-C5 NET 'GROUND' Meg_S2-C7 Meg_S2-C9 NET 'GROUND' Meg_S2-C11 Meg_S2-C13 Meg_S2-C15 NET 'GROUND' Meg_S2-C17 Meg_S2-C19 NET 'GROUND' Meg_S2-C21 Meg_S2-C23 Meg_S2-C25 NET 'GROUND' Meg_S2-C27 Meg_S2-C29 NET 'GROUND' Meg_S2-C31 Meg_S2-C33 Meg_S2-C35 NET 'GROUND' Meg_S2-C37 Meg_S2-C39 Meg_S2-C40 # # Ground Nets to Meg-Array Connector #2 Column "D" # NET 'GROUND' Meg_S2-D1 Meg_S2-D2 Meg_S2-D3 Meg_S2-D4 Meg_S2-D5 NET 'GROUND' Meg_S2-D6 Meg_S2-D7 Meg_S2-D8 Meg_S2-D9 Meg_S2-D10 NET 'GROUND' Meg_S2-D11 Meg_S2-D12 Meg_S2-D13 Meg_S2-D14 Meg_S2-D15 NET 'GROUND' Meg_S2-D16 Meg_S2-D17 Meg_S2-D18 Meg_S2-D19 Meg_S2-D20 NET 'GROUND' Meg_S2-D21 Meg_S2-D22 Meg_S2-D23 Meg_S2-D24 Meg_S2-D25 NET 'GROUND' Meg_S2-D26 Meg_S2-D27 Meg_S2-D28 Meg_S2-D29 Meg_S2-D30 NET 'GROUND' Meg_S2-D31 Meg_S2-D32 Meg_S2-D33 Meg_S2-D34 Meg_S2-D35 NET 'GROUND' Meg_S2-D36 Meg_S2-D37 Meg_S2-D38 Meg_S2-D39 Meg_S2-D40 # # Ground Nets to Meg-Array Connector #2 Column "E" # NET 'GROUND' Meg_S2-E1 Meg_S2-E2 Meg_S2-E4 NET 'GROUND' Meg_S2-E6 Meg_S2-E8 Meg_S2-E10 NET 'GROUND' Meg_S2-E12 Meg_S2-E14 NET 'GROUND' Meg_S2-E16 Meg_S2-E18 Meg_S2-E20 NET 'GROUND' Meg_S2-E22 Meg_S2-E24 NET 'GROUND' Meg_S2-E26 Meg_S2-E28 Meg_S2-E30 NET 'GROUND' Meg_S2-E32 Meg_S2-E34 NET 'GROUND' Meg_S2-E36 Meg_S2-E38 Meg_S2-E40 # # Ground Nets to Meg-Array Connector #2 Column "F" # NET 'GROUND' Meg_S2-F1 Meg_S2-F2 Meg_S2-F4 NET 'GROUND' Meg_S2-F6 Meg_S2-F8 Meg_S2-F10 NET 'GROUND' Meg_S2-F12 Meg_S2-F14 NET 'GROUND' Meg_S2-F16 Meg_S2-F18 Meg_S2-F20 NET 'GROUND' Meg_S2-F22 Meg_S2-F24 NET 'GROUND' Meg_S2-F26 Meg_S2-F28 Meg_S2-F30 NET 'GROUND' Meg_S2-F32 Meg_S2-F34 NET 'GROUND' Meg_S2-F36 Meg_S2-F38 Meg_S2-F40 # # Ground Nets to Meg-Array Connector #2 Column "G" # NET 'GROUND' Meg_S2-G1 Meg_S2-G2 Meg_S2-G3 Meg_S2-G4 Meg_S2-G5 NET 'GROUND' Meg_S2-G6 Meg_S2-G7 Meg_S2-G8 Meg_S2-G9 Meg_S2-G10 NET 'GROUND' Meg_S2-G11 Meg_S2-G12 Meg_S2-G13 Meg_S2-G14 Meg_S2-G15 NET 'GROUND' Meg_S2-G16 Meg_S2-G17 Meg_S2-G18 Meg_S2-G19 Meg_S2-G20 NET 'GROUND' Meg_S2-G21 Meg_S2-G22 Meg_S2-G23 Meg_S2-G24 Meg_S2-G25 NET 'GROUND' Meg_S2-G26 Meg_S2-G27 Meg_S2-G28 Meg_S2-G29 Meg_S2-G30 NET 'GROUND' Meg_S2-G31 Meg_S2-G32 Meg_S2-G33 Meg_S2-G34 Meg_S2-G35 NET 'GROUND' Meg_S2-G36 Meg_S2-G37 Meg_S2-G38 Meg_S2-G39 Meg_S2-G40 # # Ground Nets to Meg-Array Connector #2 Column "H" # NET 'GROUND' Meg_S2-H5 NET 'GROUND' Meg_S2-H7 Meg_S2-H9 NET 'GROUND' Meg_S2-H11 Meg_S2-H13 Meg_S2-H15 NET 'GROUND' Meg_S2-H17 Meg_S2-H19 NET 'GROUND' Meg_S2-H21 Meg_S2-H23 NET 'GROUND' Meg_S2-H28 Meg_S2-H30 NET 'GROUND' Meg_S2-H32 Meg_S2-H34 NET 'GROUND' Meg_S2-H36 Meg_S2-H38 Meg_S2-H40 # # Ground Nets to Meg-Array Connector #2 Column "J" # NET 'GROUND' Meg_S2-J5 NET 'GROUND' Meg_S2-J7 Meg_S2-J9 NET 'GROUND' Meg_S2-J11 Meg_S2-J13 Meg_S2-J15 NET 'GROUND' Meg_S2-J17 Meg_S2-J19 NET 'GROUND' Meg_S2-J21 Meg_S2-J23 NET 'GROUND' Meg_S2-J28 Meg_S2-J30 NET 'GROUND' Meg_S2-J32 Meg_S2-J34 NET 'GROUND' Meg_S2-J36 Meg_S2-J38 Meg_S2-J40 # # Ground Nets to Meg-Array Connector #2 Column "K" # NET 'GROUND' Meg_S2-K1 Meg_S2-K2 Meg_S2-K3 Meg_S2-K4 Meg_S2-K5 NET 'GROUND' Meg_S2-K6 Meg_S2-K7 Meg_S2-K8 Meg_S2-K9 Meg_S2-K10 NET 'GROUND' Meg_S2-K11 Meg_S2-K12 Meg_S2-K13 Meg_S2-K14 Meg_S2-K15 NET 'GROUND' Meg_S2-K16 Meg_S2-K17 Meg_S2-K18 Meg_S2-K19 Meg_S2-K20 NET 'GROUND' Meg_S2-K21 Meg_S2-K22 Meg_S2-K23 Meg_S2-K24 Meg_S2-K25 NET 'GROUND' Meg_S2-K26 Meg_S2-K27 Meg_S2-K28 Meg_S2-K29 Meg_S2-K30 NET 'GROUND' Meg_S2-K31 Meg_S2-K32 Meg_S2-K33 Meg_S2-K34 Meg_S2-K35 NET 'GROUND' Meg_S2-K36 Meg_S2-K37 Meg_S2-K38 Meg_S2-K39 Meg_S2-K40 # # This is the Key In Net List file for the Hub Module # # Meg-Array Reserved and Spare Pin Nets # -------------------------------------------------------- # # # Original Rev. 28-Sept-2015 # Most Recent Rev. 28-June-2016 # # # This file holds all of the Reserved and Spare and UnUsed pins # in both of the MegArray Connectors to the ROD. # # # # Reserved and Spare Pins in MegArray Connector S1 # NET 'No_Conn_MegArray_S1_PIN_B6' Meg_S1-B6 NET 'No_Conn_MegArray_S1_PIN_C6' Meg_S1-C6 NET 'No_Conn_MegArray_S1_PIN_B8' Meg_S1-B8 NET 'No_Conn_MegArray_S1_PIN_C8' Meg_S1-C8 NET 'No_Conn_MegArray_S1_PIN_B10' Meg_S1-B10 NET 'No_Conn_MegArray_S1_PIN_C10' Meg_S1-C10 NET 'No_Conn_MegArray_S1_PIN_B12' Meg_S1-B12 NET 'No_Conn_MegArray_S1_PIN_C12' Meg_S1-C12 NET 'No_Conn_MegArray_S1_PIN_B14' Meg_S1-B14 NET 'No_Conn_MegArray_S1_PIN_C14' Meg_S1-C14 NET 'No_Conn_MegArray_S1_PIN_B24' Meg_S1-B24 NET 'No_Conn_MegArray_S1_PIN_C24' Meg_S1-C24 NET 'No_Conn_MegArray_S1_PIN_B25' Meg_S1-B25 NET 'No_Conn_MegArray_S1_PIN_C25' Meg_S1-C25 NET 'No_Conn_MegArray_S1_PIN_C27' Meg_S1-C27 NET 'No_Conn_MegArray_S1_PIN_B37' Meg_S1-B37 NET 'No_Conn_MegArray_S1_Pin_E21' Meg_S1-E21 NET 'No_Conn_MegArray_S1_Pin_F21' Meg_S1-F21 # # Reserved and Spare Pins in MegArray Connector S2 # NET 'No_Conn_MegArray_S2_PIN_H10' Meg_S2-H10 NET 'No_Conn_MegArray_S2_PIN_J10' Meg_S2-J10 NET 'No_Conn_MegArray_S2_PIN_H12' Meg_S2-H12 NET 'No_Conn_MegArray_S2_PIN_J12' Meg_S2-J12 NET 'No_Conn_MegArray_S2_PIN_H14' Meg_S2-H14 NET 'No_Conn_MegArray_S2_PIN_J14' Meg_S2-J14 NET 'No_Conn_MegArray_S2_PIN_H16' Meg_S2-H16 NET 'No_Conn_MegArray_S2_PIN_J16' Meg_S2-J16 NET 'No_Conn_MegArray_S2_PIN_H18' Meg_S2-H18 NET 'No_Conn_MegArray_S2_PIN_J18' Meg_S2-J18 NET 'No_Conn_MegArray_S2_PIN_H20' Meg_S2-H20 NET 'No_Conn_MegArray_S2_PIN_J20' Meg_S2-J20 NET 'No_Conn_MegArray_S2_PIN_H22' Meg_S2-H22 NET 'No_Conn_MegArray_S2_PIN_J22' Meg_S2-J22 NET 'No_Conn_MegArray_S2_PIN_H29' Meg_S2-H29 NET 'No_Conn_MegArray_S2_PIN_J29' Meg_S2-J29 NET 'No_Conn_MegArray_S2_PIN_H31' Meg_S2-H31 NET 'No_Conn_MegArray_S2_PIN_J31' Meg_S2-J31 NET 'No_Conn_MegArray_S2_PIN_H33' Meg_S2-H33 NET 'No_Conn_MegArray_S2_PIN_J33' Meg_S2-J33 NET 'No_Conn_MegArray_S2_PIN_H35' Meg_S2-H35 NET 'No_Conn_MegArray_S2_PIN_J35' Meg_S2-J35 NET 'No_Conn_MegArray_S2_PIN_H37' Meg_S2-H37 NET 'No_Conn_MegArray_S2_PIN_J37' Meg_S2-J37 # # Switch Chip Power and Ground Connections # ---------------------------------------------- # # # Original Rev. 28-Feb-2015 # Current Rev. 26-May-2016 # # # Recall that the BCM53128 switch chip uses a 1.2 Volt Core, # and 3.3 Volt I/O for all ports except for the GMII, RGMII # port. The GMII, RGMII port can run with either 2.5 Volt or # 3.3 Volt signal levels. This signal level is controlled by # strapping pins and the voltage supplies to the OVDD pins. # # # This nets file holds the power and ground connections # for all 3 Switch Chips: "A" U31, "B" U32, "C" U33. # # # # 1 power rail comes directly from the SWCH_1V2 bus. # # DVDD 1.2V # # # # 3 power rails come directly from Bulk_3V3 bus. # # AVDDH 3.3V # OVDD 3.3V # OVDD2 3.3V # # # # 4 power rails are filtered from the SWCH_1V2 bus. # # AVDDL 1.2V # PLL_AVDD 1.2V # GPHY1_PLLDVDD 1.2V # GPHY2_PLLDVDD 1.2V # # # # 3 power rails are filtered from the BULK_3V3 bus. # # GPHY1_BAVDD 3.3V # GPHY2_BAVDD 3.3V # XTAL_AVDD 3.3V # # #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Switch "A" aka U31 Power and Ground Nets # # # Switch "A" Net AVDDH 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U31-74 U31-80 U31-86 U31-92 U31-103 NET 'BULK_3V3' U31-109 U31-115 U31-121 U31-203 U31-209 NET 'BULK_3V3' U31-215 U31-221 U31-232 U31-238 U31-244 NET 'BULK_3V3' U31-250 # # Switch "A" Net AVDDL 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'AVDDL_Fltr_A' U31-71 U31-77 U31-83 U31-89 U31-95 NET 'AVDDL_Fltr_A' U31-100 U31-106 U31-112 U31-118 U31-124 NET 'AVDDL_Fltr_A' U31-200 U31-206 U31-212 U31-218 U31-224 NET 'AVDDL_Fltr_A' U31-229 U31-235 U31-241 U31-247 U31-253 # # Switch "A" Net DVDD 1.2V Direct from the SWCH_1V2 DCDC Converter. NET 'SWCH_1V2' U31-16 U31-27 U31-31 U31-40 U31-53 NET 'SWCH_1V2' U31-135 U31-148 U31-162 U31-169 U31-183 # # Switch "A" Net OVDD 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U31-125 U31-129 U31-133 U31-138 U31-142 NET 'BULK_3V3' U31-145 U31-153 # # Switch "A" Net OVDD2 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U31-3 U31-11 U31-19 U31-43 U31-44 NET 'BULK_3V3' U31-57 U31-63 U31-68 U31-165 U31-173 NET 'BULK_3V3' U31-180 U31-187 U31-193 # # Switch "A" Net XTAL_AVDD 3.3V Filtered from BULK_3V3. NET 'XTAL_AVDD_Fltr_A' U31-35 # # Switch "A" Net PLL_AVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'PLL_AVDD_Fltr_A' U31-29 # # Switch "A" Net GPHY1_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY1_PLLDVDD_Fltr_A' U31-226 # # Switch "A" Net GPHY2_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY2_PLLDVDD_Fltr_A' U31-98 # # Switch "A" Net GPHY1_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY1_BAVDD_Fltr_A' U31-227 # # Switch "A" Net GPHY2_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY2_BAVDD_Fltr_A' U31-97 # # Switch "A" Grounds: PLL_AVSS, XTAL_AVSS, 72x THERMAL_PAD # NET 'GROUND' U31-30 U31-32 NET 'GROUND' U31-257 U31-258 U31-259 NET 'GROUND' U31-260 U31-261 U31-262 U31-263 U31-264 NET 'GROUND' U31-265 U31-266 U31-267 U31-268 U31-269 NET 'GROUND' U31-270 U31-271 U31-272 U31-273 U31-274 NET 'GROUND' U31-275 U31-276 U31-277 U31-278 U31-279 NET 'GROUND' U31-280 U31-281 U31-282 U31-283 U31-284 NET 'GROUND' U31-285 U31-286 U31-287 U31-288 U31-289 NET 'GROUND' U31-290 U31-291 U31-292 U31-293 U31-294 NET 'GROUND' U31-295 U31-296 U31-297 U31-298 U31-299 NET 'GROUND' U31-300 U31-301 U31-302 U31-303 U31-304 NET 'GROUND' U31-305 U31-306 U31-307 U31-308 U31-309 NET 'GROUND' U31-310 U31-311 U31-312 U31-313 U31-314 NET 'GROUND' U31-315 U31-316 U31-317 U31-318 U31-319 NET 'GROUND' U31-320 U31-321 U31-322 U31-323 U31-324 NET 'GROUND' U31-325 U31-326 U31-327 U31-328 #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Switch "B" aka U32 Power and Ground Nets # # # Switch "B" Net AVDDH 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U32-74 U32-80 U32-86 U32-92 U32-103 NET 'BULK_3V3' U32-109 U32-115 U32-121 U32-203 U32-209 NET 'BULK_3V3' U32-215 U32-221 U32-232 U32-238 U32-244 NET 'BULK_3V3' U32-250 # # Switch "B" Net AVDDL 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'AVDDL_Fltr_B' U32-71 U32-77 U32-83 U32-89 U32-95 NET 'AVDDL_Fltr_B' U32-100 U32-106 U32-112 U32-118 U32-124 NET 'AVDDL_Fltr_B' U32-200 U32-206 U32-212 U32-218 U32-224 NET 'AVDDL_Fltr_B' U32-229 U32-235 U32-241 U32-247 U32-253 # # Switch "B" Net DVDD 1.2V Direct from the SWCH_1V2 DCDC Converter. NET 'SWCH_1V2' U32-16 U32-27 U32-31 U32-40 U32-53 NET 'SWCH_1V2' U32-135 U32-148 U32-162 U32-169 U32-183 # # Switch "B" Net OVDD 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U32-125 U32-129 U32-133 U32-138 U32-142 NET 'BULK_3V3' U32-145 U32-153 # # Switch "B" Net OVDD2 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U32-3 U32-11 U32-19 U32-43 U32-44 NET 'BULK_3V3' U32-57 U32-63 U32-68 U32-165 U32-173 NET 'BULK_3V3' U32-180 U32-187 U32-193 # # Switch "B" Net XTAL_AVDD 3.3V Filtered from BULK_3V3. NET 'XTAL_AVDD_Fltr_B' U32-35 # # Switch "B" Net PLL_AVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'PLL_AVDD_Fltr_B' U32-29 # # Switch "B" Net GPHY1_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY1_PLLDVDD_Fltr_B' U32-226 # # Switch "B" Net GPHY2_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY2_PLLDVDD_Fltr_B' U32-98 # # Switch "B" Net GPHY1_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY1_BAVDD_Fltr_B' U32-227 # # Switch "B" Net GPHY2_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY2_BAVDD_Fltr_B' U32-97 # # Switch "B" Grounds: PLL_AVSS, XTAL_AVSS, 72x THERMAL_PAD # NET 'GROUND' U32-30 U32-32 NET 'GROUND' U32-257 U32-258 U32-259 NET 'GROUND' U32-260 U32-261 U32-262 U32-263 U32-264 NET 'GROUND' U32-265 U32-266 U32-267 U32-268 U32-269 NET 'GROUND' U32-270 U32-271 U32-272 U32-273 U32-274 NET 'GROUND' U32-275 U32-276 U32-277 U32-278 U32-279 NET 'GROUND' U32-280 U32-281 U32-282 U32-283 U32-284 NET 'GROUND' U32-285 U32-286 U32-287 U32-288 U32-289 NET 'GROUND' U32-290 U32-291 U32-292 U32-293 U32-294 NET 'GROUND' U32-295 U32-296 U32-297 U32-298 U32-299 NET 'GROUND' U32-300 U32-301 U32-302 U32-303 U32-304 NET 'GROUND' U32-305 U32-306 U32-307 U32-308 U32-309 NET 'GROUND' U32-310 U32-311 U32-312 U32-313 U32-314 NET 'GROUND' U32-315 U32-316 U32-317 U32-318 U32-319 NET 'GROUND' U32-320 U32-321 U32-322 U32-323 U32-324 NET 'GROUND' U32-325 U32-326 U32-327 U32-328 #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Switch "C" aka U33 Power and Ground Nets # # # Switch "C" Net AVDDH 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U33-74 U33-80 U33-86 U33-92 U33-103 NET 'BULK_3V3' U33-109 U33-115 U33-121 U33-203 U33-209 NET 'BULK_3V3' U33-215 U33-221 U33-232 U33-238 U33-244 NET 'BULK_3V3' U33-250 # # Switch "C" Net AVDDL 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'AVDDL_Fltr_C' U33-71 U33-77 U33-83 U33-89 U33-95 NET 'AVDDL_Fltr_C' U33-100 U33-106 U33-112 U33-118 U33-124 NET 'AVDDL_Fltr_C' U33-200 U33-206 U33-212 U33-218 U33-224 NET 'AVDDL_Fltr_C' U33-229 U33-235 U33-241 U33-247 U33-253 # # Switch "C" Net DVDD 1.2V Direct from the SWCH_1V2 DCDC Converter. NET 'SWCH_1V2' U33-16 U33-27 U33-31 U33-40 U33-53 NET 'SWCH_1V2' U33-135 U33-148 U33-162 U33-169 U33-183 # # Switch "C" Net OVDD 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U33-125 U33-129 U33-133 U33-138 U33-142 NET 'BULK_3V3' U33-145 U33-153 # # Switch "C" Net OVDD2 3.3V Direct from BULK_3V3. NET 'BULK_3V3' U33-3 U33-11 U33-19 U33-43 U33-44 NET 'BULK_3V3' U33-57 U33-63 U33-68 U33-165 U33-173 NET 'BULK_3V3' U33-180 U33-187 U33-193 # # Switch "C" Net XTAL_AVDD 3.3V Filtered from BULK_3V3. NET 'XTAL_AVDD_Fltr_C' U33-35 # # Switch "C" Net PLL_AVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'PLL_AVDD_Fltr_C' U33-29 # # Switch "C" Net GPHY1_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY1_PLLDVDD_Fltr_C' U33-226 # # Switch "C" Net GPHY2_PLLDVDD 1.2V Filtered from the SWCH_1V2 DCDC Converter. NET 'GPHY2_PLLDVDD_Fltr_C' U33-98 # # Switch "C" Net GPHY1_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY1_BAVDD_Fltr_C' U33-227 # # Switch "C" Net GPHY2_BAVDD 3.3V Filtered from BULK_3V3. NET 'GPHY2_BAVDD_Fltr_C' U33-97 # # Switch "C" Grounds: PLL_AVSS, XTAL_AVSS, 72x THERMAL_PAD # NET 'GROUND' U33-30 U33-32 NET 'GROUND' U33-257 U33-258 U33-259 NET 'GROUND' U33-260 U33-261 U33-262 U33-263 U33-264 NET 'GROUND' U33-265 U33-266 U33-267 U33-268 U33-269 NET 'GROUND' U33-270 U33-271 U33-272 U33-273 U33-274 NET 'GROUND' U33-275 U33-276 U33-277 U33-278 U33-279 NET 'GROUND' U33-280 U33-281 U33-282 U33-283 U33-284 NET 'GROUND' U33-285 U33-286 U33-287 U33-288 U33-289 NET 'GROUND' U33-290 U33-291 U33-292 U33-293 U33-294 NET 'GROUND' U33-295 U33-296 U33-297 U33-298 U33-299 NET 'GROUND' U33-300 U33-301 U33-302 U33-303 U33-304 NET 'GROUND' U33-305 U33-306 U33-307 U33-308 U33-309 NET 'GROUND' U33-310 U33-311 U33-312 U33-313 U33-314 NET 'GROUND' U33-315 U33-316 U33-317 U33-318 U33-319 NET 'GROUND' U33-320 U33-321 U33-322 U33-323 U33-324 NET 'GROUND' U33-325 U33-326 U33-327 U33-328 #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # # Note on the Removed Switch Chip Bypass Capacitors # --------------------------------------------------- # # Starting in March 2016 when the bulk of the BI Switch layout # was placed and routed some "spare" bypass capactitors where # not placed in the immediate area of the Switch chips because # the was no space for them. # # On 26-May-2016 I finally completely pulled these bypass # capacitors were pulled out of the comps files and pulled # out of this net-list file. # # The capacitors that are now removed from the design are: # # C2x32 1V2 AVDDL Bus 10 uFd 10V 0805 # C2x33 # C2x34 # C2x35 # # C2x63 BULK_3V3 1 uFd 0603 # C2x64 # C2x65 # C2x66 # # C2x67 BULK_3V3 10 uFd 10V 0805 # C2x68 # # C2x69 BULK_3V3 100 nFd & 200 nFd 0603 # C2x70 # C2x71 # C2x72 # C2x73 # C2x74 # C2x75 # # C2x76 BULK_3V3 10 uFd 10V 0805 # C2x77 # # C2x86 BULK_3V3 100 nFd & 200 nFd 0603 # C2x87 # C2x88 # C2x89 # C2x90 # # #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Now start the Bypass Capacitors and Ferrite Choke Filters # on the 11 power rails to Switch Chip "B" U32. # # # Filter and Bypass PLL_AVDD to 1 pin Chip "B" U32 # # C2101 is 10 uFd C2102 is 100 nFd NET 'SWCH_1V2' L2101-1 NET 'PLL_AVDD_Fltr_B' L2101-2 C2101-1 C2102-1 NET 'GROUND' C2101-2 C2102-2 # # Filter and Bypass GPHY1_PLLDVDD to 1 pin Chip "B" U32 # # C2103 is 10 uFd C2104 is 100 nFd NET 'SWCH_1V2' L2102-1 NET 'GPHY1_PLLDVDD_Fltr_B' L2102-2 C2103-1 C2104-1 NET 'GROUND' C2103-2 C2104-2 # # Filter and Bypass GPHY2_PLLDVDD to 1 pin Chip "B" U32 # # C2105 is 10 uFd C2106 is 100 nFd NET 'SWCH_1V2' L2103-1 NET 'GPHY2_PLLDVDD_Fltr_B' L2103-2 C2105-1 C2106-1 NET 'GROUND' C2105-2 C2106-2 # # Filter and Bypass GPHY1_BAVDD to 1 pin Chip "B" U32 # # C2107 is 10 uFd C2108 is 100 nFd NET 'BULK_3V3' L2104-1 NET 'GPHY1_BAVDD_Fltr_B' L2104-2 C2107-1 C2108-1 NET 'GROUND' C2107-2 C2108-2 # # Filter and Bypass GPHY2_BAVDD to 1 pin Chip "B" U32 # # C2109 is 10 uFd C2110 is 100 nFd NET 'BULK_3V3' L2105-1 NET 'GPHY2_BAVDD_Fltr_B' L2105-2 C2109-1 C2110-1 NET 'GROUND' C2109-2 C2110-2 # # Filter and Bypass XTAL_AVDD to 1 pin on Chip "B" U32 # # C2111 is 10 uFd C2112 is 100 nFd NET 'BULK_3V3' L2106-1 NET 'XTAL_AVDD_Fltr_B' L2106-2 C2111-1 C2112-1 NET 'GROUND' C2111-2 C2112-2 # # Filter and Bypass AVDDL to 20 pins on Chip "B" U32 # # C2113, C2114, C2115 are 10 uFd # C2116 : C2135 are 1 uFd NET 'SWCH_1V2' L2107-1 NET 'AVDDL_Fltr_B' L2107-2 C2113-1 C2114-1 C2115-1 NET 'GROUND' C2113-2 C2114-2 C2115-2 NET 'AVDDL_Fltr_B' C2116-1 C2117-1 C2118-1 C2119-1 C2120-1 NET 'GROUND' C2116-2 C2117-2 C2118-2 C2119-2 C2120-2 NET 'AVDDL_Fltr_B' C2121-1 C2122-1 C2123-1 C2124-1 C2125-1 NET 'GROUND' C2121-2 C2122-2 C2123-2 C2124-2 C2125-2 NET 'AVDDL_Fltr_B' C2126-1 C2127-1 C2128-1 C2129-1 C2130-1 NET 'GROUND' C2126-2 C2127-2 C2128-2 C2129-2 C2130-2 NET 'AVDDL_Fltr_B' C2131-1 NET 'GROUND' C2131-2 # # Bypass DVDD to 10 pins on Chip "B" U32 # # C2136, C2137, C2192 are 10 uFd # C2138 : C2147 are 100 nFd NET 'SWCH_1V2' C2136-1 C2137-1 C2192-1 NET 'GROUND' C2136-2 C2137-2 C2192-2 NET 'SWCH_1V2' C2138-1 C2139-1 C2140-1 C2141-1 C2142-1 NET 'GROUND' C2138-2 C2139-2 C2140-2 C2141-2 C2142-2 NET 'SWCH_1V2' C2143-1 C2144-1 C2145-1 C2146-1 C2147-1 NET 'GROUND' C2143-2 C2144-2 C2145-2 C2146-2 C2147-2 # # Bypass AVDDH to 16 pins on Chip "B" U32 # # C2148, C2149, C2150 are 10 uFd # C2151 : C2166 are 1 uFd NET 'BULK_3V3' C2148-1 C2149-1 C2150-1 NET 'GROUND' C2148-2 C2149-2 C2150-2 NET 'BULK_3V3' C2151-1 C2152-1 C2153-1 C2154-1 C2155-1 NET 'GROUND' C2151-2 C2152-2 C2153-2 C2154-2 C2155-2 NET 'BULK_3V3' C2156-1 C2157-1 C2158-1 C2159-1 C2160-1 NET 'GROUND' C2156-2 C2157-2 C2158-2 C2159-2 C2160-2 NET 'BULK_3V3' C2161-1 C2162-1 NET 'GROUND' C2161-2 C2162-2 # # Bypass OVDD to 7 pins on Chip "B" U32 # # C2167, C2168 are 10 uFd # C2169 : C2175 are 100 nFd # # Bypass OVDD2 to 13 pins on Chip "B" U32 # # C2176, C2177 are 10 uFd # C2178 : C2190 are 100 nFd NET 'BULK_3V3' C2178-1 C2179-1 C2180-1 C2181-1 C2182-1 NET 'GROUND' C2178-2 C2179-2 C2180-2 C2181-2 C2182-2 NET 'BULK_3V3' C2183-1 C2184-1 C2185-1 NET 'GROUND' C2183-2 C2184-2 C2185-2 #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Now start the Bypass Capacitors and Ferrite Choke Filters # on the 11 power rails to Switch Chip "A" U31. # # # Filter and Bypass PLL_AVDD to 1 pin Chip "A" U31 # # C2001 is 10 uFd C2002 is 100 nFd NET 'SWCH_1V2' L2001-1 NET 'PLL_AVDD_Fltr_A' L2001-2 C2001-1 C2002-1 NET 'GROUND' C2001-2 C2002-2 # # Filter and Bypass GPHY1_PLLDVDD to 1 pin Chip "A" U31 # # C2003 is 10 uFd C2004 is 100 nFd NET 'SWCH_1V2' L2002-1 NET 'GPHY1_PLLDVDD_Fltr_A' L2002-2 C2003-1 C2004-1 NET 'GROUND' C2003-2 C2004-2 # # Filter and Bypass GPHY2_PLLDVDD to 1 pin Chip "A" U31 # # C2005 is 10 uFd C2006 is 100 nFd NET 'SWCH_1V2' L2003-1 NET 'GPHY2_PLLDVDD_Fltr_A' L2003-2 C2005-1 C2006-1 NET 'GROUND' C2005-2 C2006-2 # # Filter and Bypass GPHY1_BAVDD to 1 pin Chip "A" U31 # # C2007 is 10 uFd C2008 is 100 nFd NET 'BULK_3V3' L2004-1 NET 'GPHY1_BAVDD_Fltr_A' L2004-2 C2007-1 C2008-1 NET 'GROUND' C2007-2 C2008-2 # # Filter and Bypass GPHY2_BAVDD to 1 pin Chip "A" U31 # # C2009 is 10 uFd C2010 is 100 nFd NET 'BULK_3V3' L2005-1 NET 'GPHY2_BAVDD_Fltr_A' L2005-2 C2009-1 C2010-1 NET 'GROUND' C2009-2 C2010-2 # # Filter and Bypass XTAL_AVDD to 1 pin on Chip "A" U31 # # C2011 is 10 uFd C2012 is 100 nFd NET 'BULK_3V3' L2006-1 NET 'XTAL_AVDD_Fltr_A' L2006-2 C2011-1 C2012-1 NET 'GROUND' C2011-2 C2012-2 # # Filter and Bypass AVDDL to 20 pins on Chip "A" U31 # # C2013, C2014, C2015 are 10 uFd # C2016 : C2035 are 1 uFd NET 'SWCH_1V2' L2007-1 NET 'AVDDL_Fltr_A' L2007-2 C2013-1 C2014-1 C2015-1 NET 'GROUND' C2013-2 C2014-2 C2015-2 NET 'AVDDL_Fltr_A' C2016-1 C2017-1 C2018-1 C2019-1 C2020-1 NET 'GROUND' C2016-2 C2017-2 C2018-2 C2019-2 C2020-2 NET 'AVDDL_Fltr_A' C2021-1 C2022-1 C2023-1 C2024-1 C2025-1 NET 'GROUND' C2021-2 C2022-2 C2023-2 C2024-2 C2025-2 NET 'AVDDL_Fltr_A' C2026-1 C2027-1 C2028-1 C2029-1 C2030-1 NET 'GROUND' C2026-2 C2027-2 C2028-2 C2029-2 C2030-2 NET 'AVDDL_Fltr_A' C2031-1 NET 'GROUND' C2031-2 # # Bypass DVDD to 10 pins on Chip "A" U31 # # C2036, C2037, C2092 are 10 uFd # C2038 : C2047 are 100 nFd NET 'SWCH_1V2' C2036-1 C2037-1 C2092-1 NET 'GROUND' C2036-2 C2037-2 C2092-2 NET 'SWCH_1V2' C2038-1 C2039-1 C2040-1 C2041-1 C2042-1 NET 'GROUND' C2038-2 C2039-2 C2040-2 C2041-2 C2042-2 NET 'SWCH_1V2' C2043-1 C2044-1 C2045-1 C2046-1 C2047-1 NET 'GROUND' C2043-2 C2044-2 C2045-2 C2046-2 C2047-2 # # Bypass AVDDH to 16 pins on Chip "A" U31 # # C2048, C2049, C2050 are 10 uFd # C2051 : C2066 are 1 uFd NET 'BULK_3V3' C2048-1 C2049-1 C2050-1 NET 'GROUND' C2048-2 C2049-2 C2050-2 NET 'BULK_3V3' C2051-1 C2052-1 C2053-1 C2054-1 C2055-1 NET 'GROUND' C2051-2 C2052-2 C2053-2 C2054-2 C2055-2 NET 'BULK_3V3' C2056-1 C2057-1 C2058-1 C2059-1 C2060-1 NET 'GROUND' C2056-2 C2057-2 C2058-2 C2059-2 C2060-2 NET 'BULK_3V3' C2061-1 C2062-1 NET 'GROUND' C2061-2 C2062-2 # # Bypass OVDD to 7 pins on Chip "A" U31 # # C2067, C2068 are 10 uFd # C2069 : C2075 are 100 nFd # # Bypass OVDD2 to 13 pins on Chip "A" U31 # # C2076, C2077 are 10 uFd # C2078 : C2090 are 100 nFd NET 'BULK_3V3' C2078-1 C2079-1 C2080-1 C2081-1 C2082-1 NET 'GROUND' C2078-2 C2079-2 C2080-2 C2081-2 C2082-2 NET 'BULK_3V3' C2083-1 C2084-1 C2085-1 NET 'GROUND' C2083-2 C2084-2 C2085-2 #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= #-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- # # Now start the Bypass Capacitors and Ferrite Choke Filters # on the 11 power rails to Switch Chip "C" U33. # # # Filter and Bypass PLL_AVDD to 1 pin Chip "C" U33 # # C2201 is 10 uFd C2202 is 100 nFd NET 'SWCH_1V2' L2201-1 NET 'PLL_AVDD_Fltr_C' L2201-2 C2201-1 C2202-1 NET 'GROUND' C2201-2 C2202-2 # # Filter and Bypass GPHY1_PLLDVDD to 1 pin Chip "C" U33 # # C2203 is 10 uFd C2204 is 100 nFd NET 'SWCH_1V2' L2202-1 NET 'GPHY1_PLLDVDD_Fltr_C' L2202-2 C2203-1 C2204-1 NET 'GROUND' C2203-2 C2204-2 # # Filter and Bypass GPHY2_PLLDVDD to 1 pin Chip "C" U33 # # C2205 is 10 uFd C2206 is 100 nFd NET 'SWCH_1V2' L2203-1 NET 'GPHY2_PLLDVDD_Fltr_C' L2203-2 C2205-1 C2206-1 NET 'GROUND' C2205-2 C2206-2 # # Filter and Bypass GPHY1_BAVDD to 1 pin Chip "C" U33 # # C2207 is 10 uFd C2208 is 100 nFd NET 'BULK_3V3' L2204-1 NET 'GPHY1_BAVDD_Fltr_C' L2204-2 C2207-1 C2208-1 NET 'GROUND' C2207-2 C2208-2 # # Filter and Bypass GPHY2_BAVDD to 1 pin Chip "C" U33 # # C2209 is 10 uFd C2210 is 100 nFd NET 'BULK_3V3' L2205-1 NET 'GPHY2_BAVDD_Fltr_C' L2205-2 C2209-1 C2210-1 NET 'GROUND' C2209-2 C2210-2 # # Filter and Bypass XTAL_AVDD to 1 pin on Chip "C" U33 # # C2211 is 10 uFd C2212 is 100 nFd NET 'BULK_3V3' L2206-1 NET 'XTAL_AVDD_Fltr_C' L2206-2 C2211-1 C2212-1 NET 'GROUND' C2211-2 C2212-2 # # Filter and Bypass AVDDL to 20 pins on Chip "C" U33 # # C2213, C2214, C2215 are 10 uFd # C2216 : C2235 are 1 uFd NET 'SWCH_1V2' L2207-1 NET 'AVDDL_Fltr_C' L2207-2 C2213-1 C2214-1 C2215-1 NET 'GROUND' C2213-2 C2214-2 C2215-2 NET 'AVDDL_Fltr_C' C2216-1 C2217-1 C2218-1 C2219-1 C2220-1 NET 'GROUND' C2216-2 C2217-2 C2218-2 C2219-2 C2220-2 NET 'AVDDL_Fltr_C' C2221-1 C2222-1 C2223-1 C2224-1 C2225-1 NET 'GROUND' C2221-2 C2222-2 C2223-2 C2224-2 C2225-2 NET 'AVDDL_Fltr_C' C2226-1 C2227-1 C2228-1 C2229-1 C2230-1 NET 'GROUND' C2226-2 C2227-2 C2228-2 C2229-2 C2230-2 NET 'AVDDL_Fltr_C' C2231-1 NET 'GROUND' C2231-2 # # Bypass DVDD to 10 pins on Chip "C" U33 # # C2236, C2237, C2292 are 10 uFd # C2238 : C2247 are 100 nFd NET 'SWCH_1V2' C2236-1 C2237-1 C2292-1 NET 'GROUND' C2236-2 C2237-2 C2292-2 NET 'SWCH_1V2' C2238-1 C2239-1 C2240-1 C2241-1 C2242-1 NET 'GROUND' C2238-2 C2239-2 C2240-2 C2241-2 C2242-2 NET 'SWCH_1V2' C2243-1 C2244-1 C2245-1 C2246-1 C2247-1 NET 'GROUND' C2243-2 C2244-2 C2245-2 C2246-2 C2247-2 # # Bypass AVDDH to 16 pins on Chip "C" U33 # # C2248, C2249, C2250 are 10 uFd # C2251 : C2266 are 1 uFd NET 'BULK_3V3' C2248-1 C2249-1 C2250-1 NET 'GROUND' C2248-2 C2249-2 C2250-2 NET 'BULK_3V3' C2251-1 C2252-1 C2253-1 C2254-1 C2255-1 NET 'GROUND' C2251-2 C2252-2 C2253-2 C2254-2 C2255-2 NET 'BULK_3V3' C2256-1 C2257-1 C2258-1 C2259-1 C2260-1 NET 'GROUND' C2256-2 C2257-2 C2258-2 C2259-2 C2260-2 NET 'BULK_3V3' C2261-1 C2262-1 NET 'GROUND' C2261-2 C2262-2 # # Bypass OVDD to 7 pins on Chip "C" U33 # # C2267, C2268 are 10 uFd # C2269 : C2275 are 100 nFd # # Bypass OVDD2 to 13 pins on Chip "C" U33 # # C2276, C2277 are 10 uFd # C2278 : C2290 are 100 nFd NET 'BULK_3V3' C2278-1 C2279-1 C2280-1 C2281-1 C2282-1 NET 'GROUND' C2278-2 C2279-2 C2280-2 C2281-2 C2282-2 NET 'BULK_3V3' C2283-1 C2284-1 C2285-1 NET 'GROUND' C2283-2 C2284-2 C2285-2 # # Ethernet Transformer Primary # from Ports on Switch Chips A, B, and C # and the Phys Chip U21 for this Hub's FPGA # # Ethernet Transformer Secondary # to Base Interface Backplane ADFplus Connectors # ------------------------------------------------ # # # Original Rev. 9-Mar-2015 # Current Rev. 30-Mar-2016 # # # # This Nets File has the connections from Ports on Switch # Chips A, B, and C to the Primary side of the Ethernet # Magnets TRNS4 through TRNS10. These are the links to # the FPGA on the Other Hub and to the 12 FEX cards. # # This Nets File also has the nets that connect the Base # Interface Ethernet Magnetics to the backplane ADFplus # connectors J23 and J24. # # These nets are the Seconday side of the transformers. # # Note that our Hub is for use in 14 Slot ATCA Shelves # thus Base Interface Channels 15 and 16 are not connected # to ports on our Hub's Ethernet Switch. # # Recall: Channel 2 is the link to the Other Hub. # Channels 3:14 are the links to Logical Slots 3:14. # # # For Better or for Worse I'm putting the Primary and # Secondary sides of the Ethernet Magnetics in the same # Nets File so that it is easier to check and change the # circuits as necessary to facilitate PCB routing. # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Swch Pri Sec ADFplus # ATCA Chip Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # To Facilitate routing one may: # # - Swap transformers within a given side of a module. # For example R1, R3, R7, R9 could be # swapped with R4, R6, R10, R12. # # - It is probably best not to wire things up so that # for a given ethernet link some of its transformers # are in the R side of the module and some of its # transformers are in the L side of the module. # # - Swap the polarity of a given transformer. For # example one may swap R1 with R3 while also # swapping R7 with R9. # # # To facilitate understanding how the magnetics for a # given Ethernet link are wired up I'm putting the nets # for the Primary and Seconday sides of a given link # next to each other in this file. # # Note that the RC components attached to the magnetics # have net names that are independed of the Etherent link # that they service. These Center Tap (CT) nets are # listed at the end of this file. These magnetics RC # nets do not have to be disturbed if the Primary and # Seconday nets are swapped for routing. # # # # Current Wiring from Switches "A" and "C" # # to FEX Logical Slots 3 through 14 # # # FEX # Switch-Port Slot Magnetics # ----------- ---- --------- # # C-0 8 7R # C-1 7 7L # C-2 6 6R # C-3 5 6L # C-4 4 5R # C-5 3 5L # # A-0 14 10R # A-1 13 10L # A-2 12 9R # A-3 11 9L # A-4 10 8R # A-5 9 8L # # # #------------------------------------------------------------ # # # TRNS10 Right Chip A Port 0 BI Ch 14 J24 Rw 8 Slot 14 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 10 R Chip A U31 Port 0 NET 'Chip_A_TRD0_0_DIR' U31-201 TRNS10-R1 NET 'Chip_A_TRD0_0_CMP' U31-202 TRNS10-R3 NET 'Chip_A_TRD1_0_DIR' U31-205 TRNS10-R6 NET 'Chip_A_TRD1_0_CMP' U31-204 TRNS10-R4 NET 'Chip_A_TRD2_0_DIR' U31-207 TRNS10-R24 NET 'Chip_A_TRD2_0_CMP' U31-208 TRNS10-R22 NET 'Chip_A_TRD3_0_DIR' U31-211 TRNS10-R19 NET 'Chip_A_TRD3_0_CMP' U31-210 TRNS10-R21 # # Secondary Nets Trans 10 R Base IF Ch 14 J24 Row 8 NET 'BI_DA14_DIR' TRNS10-R7 J24-A8 NET 'BI_DA14_CMP' TRNS10-R9 J24-B8 NET 'BI_DB14_DIR' TRNS10-R12 J24-C8 NET 'BI_DB14_CMP' TRNS10-R10 J24-D8 NET 'BI_DC14_DIR' TRNS10-R18 J24-E8 NET 'BI_DC14_CMP' TRNS10-R16 J24-F8 NET 'BI_DD14_DIR' TRNS10-R13 J24-G8 NET 'BI_DD14_CMP' TRNS10-R15 J24-H8 # #------------------------------------------------------------ # # # TRNS10 Left Chip A Port 1 BI Ch 13 J24 Rw 7 Slot 13 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 10 L Chip A U31 Port 1 NET 'Chip_A_TRD0_1_DIR' U31-223 TRNS10-L1 NET 'Chip_A_TRD0_1_CMP' U31-222 TRNS10-L3 NET 'Chip_A_TRD1_1_DIR' U31-219 TRNS10-L6 NET 'Chip_A_TRD1_1_CMP' U31-220 TRNS10-L4 NET 'Chip_A_TRD2_1_DIR' U31-217 TRNS10-L24 NET 'Chip_A_TRD2_1_CMP' U31-216 TRNS10-L22 NET 'Chip_A_TRD3_1_DIR' U31-213 TRNS10-L19 NET 'Chip_A_TRD3_1_CMP' U31-214 TRNS10-L21 # # Secondary Nets Trans 10 L Base Channel 13 J24 Row 7 NET 'BI_DA13_DIR' TRNS10-L7 J24-A7 NET 'BI_DA13_CMP' TRNS10-L9 J24-B7 NET 'BI_DB13_DIR' TRNS10-L12 J24-C7 NET 'BI_DB13_CMP' TRNS10-L10 J24-D7 NET 'BI_DC13_DIR' TRNS10-L18 J24-E7 NET 'BI_DC13_CMP' TRNS10-L16 J24-F7 NET 'BI_DD13_DIR' TRNS10-L13 J24-G7 NET 'BI_DD13_CMP' TRNS10-L15 J24-H7 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS9 Right Chip A Port 2 BI Ch 12 J24 Rw 6 Slot 12 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 9 R Chip A U31 Port 2 NET 'Chip_A_TRD0_2_DIR' U31-230 TRNS9-R1 NET 'Chip_A_TRD0_2_CMP' U31-231 TRNS9-R3 NET 'Chip_A_TRD1_2_DIR' U31-234 TRNS9-R6 NET 'Chip_A_TRD1_2_CMP' U31-233 TRNS9-R4 NET 'Chip_A_TRD2_2_DIR' U31-236 TRNS9-R24 NET 'Chip_A_TRD2_2_CMP' U31-237 TRNS9-R22 NET 'Chip_A_TRD3_2_DIR' U31-240 TRNS9-R19 NET 'Chip_A_TRD3_2_CMP' U31-239 TRNS9-R21 # # Secondary Nets Trans 9 R Base Channel 12 J24 Row 6 NET 'BI_DA12_DIR' TRNS9-R7 J24-A6 NET 'BI_DA12_CMP' TRNS9-R9 J24-B6 NET 'BI_DB12_DIR' TRNS9-R12 J24-C6 NET 'BI_DB12_CMP' TRNS9-R10 J24-D6 NET 'BI_DC12_DIR' TRNS9-R18 J24-E6 NET 'BI_DC12_CMP' TRNS9-R16 J24-F6 NET 'BI_DD12_DIR' TRNS9-R13 J24-G6 NET 'BI_DD12_CMP' TRNS9-R15 J24-H6 # #------------------------------------------------------------ # # # TRNS9 Left Chip A Port 3 BI Ch 11 J24 Rw 5 Slot 11 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 9 L Chip A U31 Port 3 NET 'Chip_A_TRD0_3_DIR' U31-252 TRNS9-L1 NET 'Chip_A_TRD0_3_CMP' U31-251 TRNS9-L3 NET 'Chip_A_TRD1_3_DIR' U31-248 TRNS9-L6 NET 'Chip_A_TRD1_3_CMP' U31-249 TRNS9-L4 NET 'Chip_A_TRD2_3_DIR' U31-246 TRNS9-L24 NET 'Chip_A_TRD2_3_CMP' U31-245 TRNS9-L22 NET 'Chip_A_TRD3_3_DIR' U31-242 TRNS9-L19 NET 'Chip_A_TRD3_3_CMP' U31-243 TRNS9-L21 # # Secondary Nets Trans 9 L Base Channel 11 J24 Row 5 NET 'BI_DA11_DIR' TRNS9-L7 J24-A5 NET 'BI_DA11_CMP' TRNS9-L9 J24-B5 NET 'BI_DB11_DIR' TRNS9-L12 J24-C5 NET 'BI_DB11_CMP' TRNS9-L10 J24-D5 NET 'BI_DC11_DIR' TRNS9-L18 J24-E5 NET 'BI_DC11_CMP' TRNS9-L16 J24-F5 NET 'BI_DD11_DIR' TRNS9-L13 J24-G5 NET 'BI_DD11_CMP' TRNS9-L15 J24-H5 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS8 Right Chip A Port 4 BI Ch 10 J24 Rw 4 Slot 10 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 8 R Chip A U31 Port 4 NET 'Chip_A_TRD0_4_DIR' U31-72 TRNS8-R1 NET 'Chip_A_TRD0_4_CMP' U31-73 TRNS8-R3 NET 'Chip_A_TRD1_4_DIR' U31-76 TRNS8-R6 NET 'Chip_A_TRD1_4_CMP' U31-75 TRNS8-R4 NET 'Chip_A_TRD2_4_DIR' U31-78 TRNS8-R24 NET 'Chip_A_TRD2_4_CMP' U31-79 TRNS8-R22 NET 'Chip_A_TRD3_4_DIR' U31-82 TRNS8-R19 NET 'Chip_A_TRD3_4_CMP' U31-81 TRNS8-R21 # # Secondary Nets Trans 8 R Base Channel 10 J24 Row 4 NET 'BI_DA10_DIR' TRNS8-R7 J24-A4 NET 'BI_DA10_CMP' TRNS8-R9 J24-B4 NET 'BI_DB10_DIR' TRNS8-R12 J24-C4 NET 'BI_DB10_CMP' TRNS8-R10 J24-D4 NET 'BI_DC10_DIR' TRNS8-R18 J24-E4 NET 'BI_DC10_CMP' TRNS8-R16 J24-F4 NET 'BI_DD10_DIR' TRNS8-R13 J24-G4 NET 'BI_DD10_CMP' TRNS8-R15 J24-H4 # #------------------------------------------------------------ # # # TRNS8 Left Chip A Port 5 BI Ch 9 J24 Rw 3 Slot 9 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 8 L Chip A U31 Port 5 NET 'Chip_A_TRD0_5_DIR' U31-94 TRNS8-L1 NET 'Chip_A_TRD0_5_CMP' U31-93 TRNS8-L3 NET 'Chip_A_TRD1_5_DIR' U31-90 TRNS8-L6 NET 'Chip_A_TRD1_5_CMP' U31-91 TRNS8-L4 NET 'Chip_A_TRD2_5_DIR' U31-88 TRNS8-L24 NET 'Chip_A_TRD2_5_CMP' U31-87 TRNS8-L22 NET 'Chip_A_TRD3_5_DIR' U31-84 TRNS8-L19 NET 'Chip_A_TRD3_5_CMP' U31-85 TRNS8-L21 # # Secondary Nets Trans 8 L Base Channel 9 J24 Row 3 NET 'BI_DA9_DIR' TRNS8-L7 J24-A3 NET 'BI_DA9_CMP' TRNS8-L9 J24-B3 NET 'BI_DB9_DIR' TRNS8-L12 J24-C3 NET 'BI_DB9_CMP' TRNS8-L10 J24-D3 NET 'BI_DC9_DIR' TRNS8-L18 J24-E3 NET 'BI_DC9_CMP' TRNS8-L16 J24-F3 NET 'BI_DD9_DIR' TRNS8-L13 J24-G3 NET 'BI_DD9_CMP' TRNS8-L15 J24-H3 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS7 Right Chip C Port 0 BI Ch 8 J24 Rw 2 Slot 8 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 7 R Chip C U33 Port 0 NET 'Chip_C_TRD0_0_DIR' U33-201 TRNS7-R1 NET 'Chip_C_TRD0_0_CMP' U33-202 TRNS7-R3 NET 'Chip_C_TRD1_0_DIR' U33-205 TRNS7-R6 NET 'Chip_C_TRD1_0_CMP' U33-204 TRNS7-R4 NET 'Chip_C_TRD2_0_DIR' U33-207 TRNS7-R24 NET 'Chip_C_TRD2_0_CMP' U33-208 TRNS7-R22 NET 'Chip_C_TRD3_0_DIR' U33-211 TRNS7-R19 NET 'Chip_C_TRD3_0_CMP' U33-210 TRNS7-R21 # # Secondary Nets Trans 7 R Base Channel 8 J24 Row 2 NET 'BI_DA8_DIR' TRNS7-R7 J24-A2 NET 'BI_DA8_CMP' TRNS7-R9 J24-B2 NET 'BI_DB8_DIR' TRNS7-R12 J24-C2 NET 'BI_DB8_CMP' TRNS7-R10 J24-D2 NET 'BI_DC8_DIR' TRNS7-R18 J24-E2 NET 'BI_DC8_CMP' TRNS7-R16 J24-F2 NET 'BI_DD8_DIR' TRNS7-R13 J24-G2 NET 'BI_DD8_CMP' TRNS7-R15 J24-H2 # #------------------------------------------------------------ # # # TRNS7 Left Chip C Port 1 BI Ch 7 J24 Rw 1 Slot 7 FEX # # FLIPS: primary L4,L6 and secondary L10,L12 flipped # primary L19,L21 and secondary L13,L15 flipped # # # Primary Nets Trans 7 L Chip C U33 Port 1 NET 'Chip_C_TRD0_1_DIR' U33-223 TRNS7-L1 NET 'Chip_C_TRD0_1_CMP' U33-222 TRNS7-L3 NET 'Chip_C_TRD1_1_DIR' U33-219 TRNS7-L6 NET 'Chip_C_TRD1_1_CMP' U33-220 TRNS7-L4 NET 'Chip_C_TRD2_1_DIR' U33-217 TRNS7-L24 NET 'Chip_C_TRD2_1_CMP' U33-216 TRNS7-L22 NET 'Chip_C_TRD3_1_DIR' U33-213 TRNS7-L19 NET 'Chip_C_TRD3_1_CMP' U33-214 TRNS7-L21 # # Secondary Nets Trans 7 L Base Channel 7 J24 Row 1 NET 'BI_DA7_DIR' TRNS7-L7 J24-A1 NET 'BI_DA7_CMP' TRNS7-L9 J24-B1 NET 'BI_DB7_DIR' TRNS7-L12 J24-C1 NET 'BI_DB7_CMP' TRNS7-L10 J24-D1 NET 'BI_DC7_DIR' TRNS7-L18 J24-E1 NET 'BI_DC7_CMP' TRNS7-L16 J24-F1 NET 'BI_DD7_DIR' TRNS7-L13 J24-G1 NET 'BI_DD7_CMP' TRNS7-L15 J24-H1 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS6 Right Chip C Port 2 BI Ch 6 J23 Rw 10 Slot 6 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 6 R Chip C U33 Port 2 NET 'Chip_C_TRD0_2_DIR' U33-230 TRNS6-R1 NET 'Chip_C_TRD0_2_CMP' U33-231 TRNS6-R3 NET 'Chip_C_TRD1_2_DIR' U33-234 TRNS6-R6 NET 'Chip_C_TRD1_2_CMP' U33-233 TRNS6-R4 NET 'Chip_C_TRD2_2_DIR' U33-236 TRNS6-R24 NET 'Chip_C_TRD2_2_CMP' U33-237 TRNS6-R22 NET 'Chip_C_TRD3_2_DIR' U33-240 TRNS6-R19 NET 'Chip_C_TRD3_2_CMP' U33-239 TRNS6-R21 # # Secondary Nets Trans 6 R Base Channel 6 J23 Row 10 NET 'BI_DA6_DIR' TRNS6-R7 J23-A10 NET 'BI_DA6_CMP' TRNS6-R9 J23-B10 NET 'BI_DB6_DIR' TRNS6-R12 J23-C10 NET 'BI_DB6_CMP' TRNS6-R10 J23-D10 NET 'BI_DC6_DIR' TRNS6-R18 J23-E10 NET 'BI_DC6_CMP' TRNS6-R16 J23-F10 NET 'BI_DD6_DIR' TRNS6-R13 J23-G10 NET 'BI_DD6_CMP' TRNS6-R15 J23-H10 # #------------------------------------------------------------ # # # TRNS6 Left Chip C Port 3 BI Ch 5 J23 Rw 9 Slot 5 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 6 L Chip C U33 Port 3 NET 'Chip_C_TRD0_3_DIR' U33-252 TRNS6-L1 NET 'Chip_C_TRD0_3_CMP' U33-251 TRNS6-L3 NET 'Chip_C_TRD1_3_DIR' U33-248 TRNS6-L6 NET 'Chip_C_TRD1_3_CMP' U33-249 TRNS6-L4 NET 'Chip_C_TRD2_3_DIR' U33-246 TRNS6-L24 NET 'Chip_C_TRD2_3_CMP' U33-245 TRNS6-L22 NET 'Chip_C_TRD3_3_DIR' U33-242 TRNS6-L19 NET 'Chip_C_TRD3_3_CMP' U33-243 TRNS6-L21 # # Secondary Nets Trans 6 L Base Channel 5 J23 Row 9 NET 'BI_DA5_DIR' TRNS6-L7 J23-A9 NET 'BI_DA5_CMP' TRNS6-L9 J23-B9 NET 'BI_DB5_DIR' TRNS6-L12 J23-C9 NET 'BI_DB5_CMP' TRNS6-L10 J23-D9 NET 'BI_DC5_DIR' TRNS6-L18 J23-E9 NET 'BI_DC5_CMP' TRNS6-L16 J23-F9 NET 'BI_DD5_DIR' TRNS6-L13 J23-G9 NET 'BI_DD5_CMP' TRNS6-L15 J23-H9 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS5 Right Chip C Port 4 BI Ch 4 J23 Rw 8 Slot 4 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 5 R Chip C U33 Port 4 NET 'Chip_C_TRD0_4_DIR' U33-72 TRNS5-R1 NET 'Chip_C_TRD0_4_CMP' U33-73 TRNS5-R3 NET 'Chip_C_TRD1_4_DIR' U33-76 TRNS5-R6 NET 'Chip_C_TRD1_4_CMP' U33-75 TRNS5-R4 NET 'Chip_C_TRD2_4_DIR' U33-78 TRNS5-R24 NET 'Chip_C_TRD2_4_CMP' U33-79 TRNS5-R22 NET 'Chip_C_TRD3_4_DIR' U33-82 TRNS5-R19 NET 'Chip_C_TRD3_4_CMP' U33-81 TRNS5-R21 # # Secondary Nets Trans 5 R Base Channel 4 J23 Row 8 NET 'BI_DA4_DIR' TRNS5-R7 J23-A8 NET 'BI_DA4_CMP' TRNS5-R9 J23-B8 NET 'BI_DB4_DIR' TRNS5-R12 J23-C8 NET 'BI_DB4_CMP' TRNS5-R10 J23-D8 NET 'BI_DC4_DIR' TRNS5-R18 J23-E8 NET 'BI_DC4_CMP' TRNS5-R16 J23-F8 NET 'BI_DD4_DIR' TRNS5-R13 J23-G8 NET 'BI_DD4_CMP' TRNS5-R15 J23-H8 # #------------------------------------------------------------ # # # TRNS5 Left Chip C Port 5 BI Ch 3 J23 Rw 7 Slot 3 FEX # # FLIPS: primary R4,R6 and secondary R10,R12 flipped # primary R19,R21 and secondary R13,R15 flipped # # # Primary Nets Trans 5 L Chip C U33 Port 5 NET 'Chip_C_TRD0_5_DIR' U33-94 TRNS5-L1 NET 'Chip_C_TRD0_5_CMP' U33-93 TRNS5-L3 NET 'Chip_C_TRD1_5_DIR' U33-90 TRNS5-L6 NET 'Chip_C_TRD1_5_CMP' U33-91 TRNS5-L4 NET 'Chip_C_TRD2_5_DIR' U33-88 TRNS5-L24 NET 'Chip_C_TRD2_5_CMP' U33-87 TRNS5-L22 NET 'Chip_C_TRD3_5_DIR' U33-84 TRNS5-L19 NET 'Chip_C_TRD3_5_CMP' U33-85 TRNS5-L21 # # Secondary Nets Trans 5 L Base Channel 3 J23 Row 7 NET 'BI_DA3_DIR' TRNS5-L7 J23-A7 NET 'BI_DA3_CMP' TRNS5-L9 J23-B7 NET 'BI_DB3_DIR' TRNS5-L12 J23-C7 NET 'BI_DB3_CMP' TRNS5-L10 J23-D7 NET 'BI_DC3_DIR' TRNS5-L18 J23-E7 NET 'BI_DC3_CMP' TRNS5-L16 J23-F7 NET 'BI_DD3_DIR' TRNS5-L13 J23-G7 NET 'BI_DD3_CMP' TRNS5-L15 J23-H7 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # # TRNS4 Right Chip B Port 5 Update Channel J20 Rw 3&4 # # This Hub's Switch Chip B Port 5 to Other Hub's FPGA # # # Primary Nets Trans 4 R Chip B U32 Port 5 NET 'Chip_B_TRD0_5_DIR' U32-94 TRNS4-R1 NET 'Chip_B_TRD0_5_CMP' U32-93 TRNS4-R3 NET 'Chip_B_TRD1_5_DIR' U32-90 TRNS4-R4 NET 'Chip_B_TRD1_5_CMP' U32-91 TRNS4-R6 NET 'Chip_B_TRD2_5_DIR' U32-88 TRNS4-R24 NET 'Chip_B_TRD2_5_CMP' U32-87 TRNS4-R22 NET 'Chip_B_TRD3_5_DIR' U32-84 TRNS4-R21 NET 'Chip_B_TRD3_5_CMP' U32-85 TRNS4-R19 # # Secondary Nets Trans 4 R Update Channel J20 Row 3&4 NET 'UP_Tx0_A_Dir' TRNS4-R7 J20-A4 NET 'UP_Tx0_A_Cmp' TRNS4-R9 J20-B4 NET 'UP_Tx1_B_Dir' TRNS4-R10 J20-E4 NET 'UP_Tx1_B_Cmp' TRNS4-R12 J20-F4 NET 'UP_Tx2_C_Dir' TRNS4-R18 J20-A3 NET 'UP_Tx2_C_Cmp' TRNS4-R16 J20-B3 NET 'UP_Tx3_D_Dir' TRNS4-R15 J20-E3 NET 'UP_Tx3_D_Cmp' TRNS4-R13 J20-F3 # #------------------------------------------------------------ # # # TRNS4 Left This Hub's FPGA Phys Chip U21 Update Channel J20 Rw 3&4 # # This Hub's FPGA Phys U21 to Other Hub's Switch Chip B Port 5 # # # Primary Nets Trans 4 L This Hub's FPGA Phys U21 NET 'Phys_U21_TxRx_A_Dir' TRNS4-L1 NET 'Phys_U21_TxRx_A_CMP' TRNS4-L3 NET 'Phys_U21_TxRx_B_Dir' TRNS4-L4 NET 'Phys_U21_TxRx_B_CMP' TRNS4-L6 NET 'Phys_U21_TxRx_C_Dir' TRNS4-L24 NET 'Phys_U21_TxRx_C_CMP' TRNS4-L22 NET 'Phys_U21_TxRx_D_Dir' TRNS4-L21 NET 'Phys_U21_TxRx_D_CMP' TRNS4-L19 # # Secondary Nets Trans 4 L Update Channel J20 Row 3&4 NET 'UP_Rx0_A_Dir' TRNS4-L7 J20-C4 NET 'UP_Rx0_A_Cmp' TRNS4-L9 J20-D4 NET 'UP_Rx1_B_Dir' TRNS4-L10 J20-G4 NET 'UP_Rx1_B_Cmp' TRNS4-L12 J20-H4 NET 'UP_Rx2_C_Dir' TRNS4-L18 J20-C3 NET 'UP_Rx2_C_Cmp' TRNS4-L16 J20-D3 NET 'UP_Rx3_D_Dir' TRNS4-L15 J20-G3 NET 'UP_Rx3_D_Cmp' TRNS4-L13 J20-H3 # #------------------------------------------------------------ # # #------------------------------------------------------------ #------------------------------------------------------------ #------------------------------------------------------------ # # # Now start a different section of the Nets File # where we connect the various RC Components to # the Ethernet Magnetics. # # This section is separate because even if you need # to swap things around in the above section to # facilitate routing - you do not need to change # these RC component connections. # # These RC component connections have net names # that isolate them from needed to be changed when # swaps are made above for routing. # # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS4 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 4 Right and Left # NET 'TRNS4_R_A_0_PRI_CT' TRNS4-R2 C1431-1 NET 'TRNS4_R_B_1_PRI_CT' TRNS4-R5 C1434-1 NET 'TRNS4_R_C_2_PRI_CT' TRNS4-R23 C1432-1 NET 'TRNS4_R_D_3_PRI_CT' TRNS4-R20 C1433-1 NET 'GROUND' C1431-2 C1432-2 C1433-2 C1434-2 NET 'TRNS4_L_A_0_PRI_CT' TRNS4-L2 C1437-1 NET 'TRNS4_L_B_1_PRI_CT' TRNS4-L5 C1438-1 NET 'TRNS4_L_C_2_PRI_CT' TRNS4-L23 C1436-1 NET 'TRNS4_L_D_3_PRI_CT' TRNS4-L20 C1439-1 NET 'GROUND' C1436-2 C1437-2 C1438-2 C1439-2 # # Secondary Center Tap Nets Trans 4 Right and Left # NET 'TRNS4_R_A_0_SEC_CT' TRNS4-R8 R1432-2 NET 'TRNS4_R_B_1_SEC_CT' TRNS4-R11 R1434-2 NET 'TRNS4_R_C_2_SEC_CT' TRNS4-R17 R1431-2 NET 'TRNS4_R_D_3_SEC_CT' TRNS4-R14 R1433-2 NET 'TRNS4_R_SEC_CT_TIE' R1431-1 R1432-1 R1433-1 R1434-1 NET 'TRNS4_R_SEC_CT_TIE' C1435-2 NET 'GROUND' C1435-1 NET 'TRNS4_L_A_0_SEC_CT' TRNS4-L8 R1437-2 NET 'TRNS4_L_B_1_SEC_CT' TRNS4-L11 R1438-2 NET 'TRNS4_L_C_2_SEC_CT' TRNS4-L17 R1436-2 NET 'TRNS4_L_D_3_SEC_CT' TRNS4-L14 R1439-2 NET 'TRNS4_L_SEC_CT_TIE' R1436-1 R1437-1 R1438-1 R1439-1 NET 'TRNS4_L_SEC_CT_TIE' C1440-2 NET 'GROUND' C1440-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS5 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 5 Right and Left # NET 'TRNS5_R_A_0_PRI_CT' TRNS5-R2 C1441-1 NET 'TRNS5_R_B_1_PRI_CT' TRNS5-R5 C1444-1 NET 'TRNS5_R_C_2_PRI_CT' TRNS5-R23 C1442-1 NET 'TRNS5_R_D_3_PRI_CT' TRNS5-R20 C1443-1 NET 'GROUND' C1441-2 C1442-2 C1443-2 C1444-2 NET 'TRNS5_L_A_0_PRI_CT' TRNS5-L2 C1447-1 NET 'TRNS5_L_B_1_PRI_CT' TRNS5-L5 C1448-1 NET 'TRNS5_L_C_2_PRI_CT' TRNS5-L23 C1446-1 NET 'TRNS5_L_D_3_PRI_CT' TRNS5-L20 C1449-1 NET 'GROUND' C1446-2 C1447-2 C1448-2 C1449-2 # # Secondary Center Tap Nets Trans 5 Right and Left # NET 'TRNS5_R_A_0_SEC_CT' TRNS5-R8 R1442-2 NET 'TRNS5_R_B_1_SEC_CT' TRNS5-R11 R1444-2 NET 'TRNS5_R_C_2_SEC_CT' TRNS5-R17 R1441-2 NET 'TRNS5_R_D_3_SEC_CT' TRNS5-R14 R1443-2 NET 'TRNS5_R_SEC_CT_TIE' R1441-1 R1442-1 R1443-1 R1444-1 NET 'TRNS5_R_SEC_CT_TIE' C1445-2 NET 'GROUND' C1445-1 NET 'TRNS5_L_A_0_SEC_CT' TRNS5-L8 R1447-2 NET 'TRNS5_L_B_1_SEC_CT' TRNS5-L11 R1448-2 NET 'TRNS5_L_C_2_SEC_CT' TRNS5-L17 R1446-2 NET 'TRNS5_L_D_3_SEC_CT' TRNS5-L14 R1449-2 NET 'TRNS5_L_SEC_CT_TIE' R1446-1 R1447-1 R1448-1 R1449-1 NET 'TRNS5_L_SEC_CT_TIE' C1450-2 NET 'GROUND' C1450-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS6 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 6 Right and Left # NET 'TRNS6_R_A_0_PRI_CT' TRNS6-R2 C1451-1 NET 'TRNS6_R_B_1_PRI_CT' TRNS6-R5 C1454-1 NET 'TRNS6_R_C_2_PRI_CT' TRNS6-R23 C1452-1 NET 'TRNS6_R_D_3_PRI_CT' TRNS6-R20 C1453-1 NET 'GROUND' C1451-2 C1452-2 C1453-2 C1454-2 NET 'TRNS6_L_A_0_PRI_CT' TRNS6-L2 C1457-1 NET 'TRNS6_L_B_1_PRI_CT' TRNS6-L5 C1458-1 NET 'TRNS6_L_C_2_PRI_CT' TRNS6-L23 C1456-1 NET 'TRNS6_L_D_3_PRI_CT' TRNS6-L20 C1459-1 NET 'GROUND' C1456-2 C1457-2 C1458-2 C1459-2 # # Secondary Center Tap Nets Trans 6 Right and Left # NET 'TRNS6_R_A_0_SEC_CT' TRNS6-R8 R1452-2 NET 'TRNS6_R_B_1_SEC_CT' TRNS6-R11 R1454-2 NET 'TRNS6_R_C_2_SEC_CT' TRNS6-R17 R1451-2 NET 'TRNS6_R_D_3_SEC_CT' TRNS6-R14 R1453-2 NET 'TRNS6_R_SEC_CT_TIE' R1451-1 R1452-1 R1453-1 R1454-1 NET 'TRNS6_R_SEC_CT_TIE' C1455-2 NET 'GROUND' C1455-1 NET 'TRNS6_L_A_0_SEC_CT' TRNS6-L8 R1457-2 NET 'TRNS6_L_B_1_SEC_CT' TRNS6-L11 R1458-2 NET 'TRNS6_L_C_2_SEC_CT' TRNS6-L17 R1456-2 NET 'TRNS6_L_D_3_SEC_CT' TRNS6-L14 R1459-2 NET 'TRNS6_L_SEC_CT_TIE' R1456-1 R1457-1 R1458-1 R1459-1 NET 'TRNS6_L_SEC_CT_TIE' C1460-2 NET 'GROUND' C1460-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS7 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 7 Right and Left # NET 'TRNS7_R_A_0_PRI_CT' TRNS7-R2 C1461-1 NET 'TRNS7_R_B_1_PRI_CT' TRNS7-R5 C1464-1 NET 'TRNS7_R_C_2_PRI_CT' TRNS7-R23 C1462-1 NET 'TRNS7_R_D_3_PRI_CT' TRNS7-R20 C1463-1 NET 'GROUND' C1461-2 C1462-2 C1463-2 C1464-2 NET 'TRNS7_L_A_0_PRI_CT' TRNS7-L2 C1467-1 NET 'TRNS7_L_B_1_PRI_CT' TRNS7-L5 C1468-1 NET 'TRNS7_L_C_2_PRI_CT' TRNS7-L23 C1466-1 NET 'TRNS7_L_D_3_PRI_CT' TRNS7-L20 C1469-1 NET 'GROUND' C1466-2 C1467-2 C1468-2 C1469-2 # # Secondary Center Tap Nets Trans 7 Right and Left # NET 'TRNS7_R_A_0_SEC_CT' TRNS7-R8 R1462-2 NET 'TRNS7_R_B_1_SEC_CT' TRNS7-R11 R1464-2 NET 'TRNS7_R_C_2_SEC_CT' TRNS7-R17 R1461-2 NET 'TRNS7_R_D_3_SEC_CT' TRNS7-R14 R1463-2 NET 'TRNS7_R_SEC_CT_TIE' R1461-1 R1462-1 R1463-1 R1464-1 NET 'TRNS7_R_SEC_CT_TIE' C1465-2 NET 'GROUND' C1465-1 NET 'TRNS7_L_A_0_SEC_CT' TRNS7-L8 R1467-2 NET 'TRNS7_L_B_1_SEC_CT' TRNS7-L11 R1468-2 NET 'TRNS7_L_C_2_SEC_CT' TRNS7-L17 R1466-2 NET 'TRNS7_L_D_3_SEC_CT' TRNS7-L14 R1469-2 NET 'TRNS7_L_SEC_CT_TIE' R1466-1 R1467-1 R1468-1 R1469-1 NET 'TRNS7_L_SEC_CT_TIE' C1470-2 NET 'GROUND' C1470-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS8 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 8 Right and Left # NET 'TRNS8_R_A_0_PRI_CT' TRNS8-R2 C1471-1 NET 'TRNS8_R_B_1_PRI_CT' TRNS8-R5 C1474-1 NET 'TRNS8_R_C_2_PRI_CT' TRNS8-R23 C1472-1 NET 'TRNS8_R_D_3_PRI_CT' TRNS8-R20 C1473-1 NET 'GROUND' C1471-2 C1472-2 C1473-2 C1474-2 NET 'TRNS8_L_A_0_PRI_CT' TRNS8-L2 C1477-1 NET 'TRNS8_L_B_1_PRI_CT' TRNS8-L5 C1478-1 NET 'TRNS8_L_C_2_PRI_CT' TRNS8-L23 C1476-1 NET 'TRNS8_L_D_3_PRI_CT' TRNS8-L20 C1479-1 NET 'GROUND' C1476-2 C1477-2 C1478-2 C1479-2 # # Secondary Center Tap Nets Trans 8 Right and Left # NET 'TRNS8_R_A_0_SEC_CT' TRNS8-R8 R1472-2 NET 'TRNS8_R_B_1_SEC_CT' TRNS8-R11 R1474-2 NET 'TRNS8_R_C_2_SEC_CT' TRNS8-R17 R1471-2 NET 'TRNS8_R_D_3_SEC_CT' TRNS8-R14 R1473-2 NET 'TRNS8_R_SEC_CT_TIE' R1471-1 R1472-1 R1473-1 R1474-1 NET 'TRNS8_R_SEC_CT_TIE' C1475-2 NET 'GROUND' C1475-1 NET 'TRNS8_L_A_0_SEC_CT' TRNS8-L8 R1477-2 NET 'TRNS8_L_B_1_SEC_CT' TRNS8-L11 R1478-2 NET 'TRNS8_L_C_2_SEC_CT' TRNS8-L17 R1476-2 NET 'TRNS8_L_D_3_SEC_CT' TRNS8-L14 R1479-2 NET 'TRNS8_L_SEC_CT_TIE' R1476-1 R1477-1 R1478-1 R1479-1 NET 'TRNS8_L_SEC_CT_TIE' C1480-2 NET 'GROUND' C1480-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS9 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 9 Right and Left # NET 'TRNS9_R_A_0_PRI_CT' TRNS9-R2 C1481-1 NET 'TRNS9_R_B_1_PRI_CT' TRNS9-R5 C1484-1 NET 'TRNS9_R_C_2_PRI_CT' TRNS9-R23 C1482-1 NET 'TRNS9_R_D_3_PRI_CT' TRNS9-R20 C1483-1 NET 'GROUND' C1481-2 C1482-2 C1483-2 C1484-2 NET 'TRNS9_L_A_0_PRI_CT' TRNS9-L2 C1487-1 NET 'TRNS9_L_B_1_PRI_CT' TRNS9-L5 C1488-1 NET 'TRNS9_L_C_2_PRI_CT' TRNS9-L23 C1486-1 NET 'TRNS9_L_D_3_PRI_CT' TRNS9-L20 C1489-1 NET 'GROUND' C1486-2 C1487-2 C1488-2 C1489-2 # # Secondary Center Tap Nets Trans 9 Right and Left # NET 'TRNS9_R_A_0_SEC_CT' TRNS9-R8 R1482-2 NET 'TRNS9_R_B_1_SEC_CT' TRNS9-R11 R1484-2 NET 'TRNS9_R_C_2_SEC_CT' TRNS9-R17 R1481-2 NET 'TRNS9_R_D_3_SEC_CT' TRNS9-R14 R1483-2 NET 'TRNS9_R_SEC_CT_TIE' R1481-1 R1482-1 R1483-1 R1484-1 NET 'TRNS9_R_SEC_CT_TIE' C1485-2 NET 'GROUND' C1485-1 NET 'TRNS9_L_A_0_SEC_CT' TRNS9-L8 R1487-2 NET 'TRNS9_L_B_1_SEC_CT' TRNS9-L11 R1488-2 NET 'TRNS9_L_C_2_SEC_CT' TRNS9-L17 R1486-2 NET 'TRNS9_L_D_3_SEC_CT' TRNS9-L14 R1489-2 NET 'TRNS9_L_SEC_CT_TIE' R1486-1 R1487-1 R1488-1 R1489-1 NET 'TRNS9_L_SEC_CT_TIE' C1490-2 NET 'GROUND' C1490-1 # #------------------------------------------------------------ #------------------------------------------------------------ # # TRNS10 Magnetics RC Component Connections # # Primary Center Tap Nets Trans 10 Right and Left # NET 'TRNS10_R_A_0_PRI_CT' TRNS10-R2 C1491-1 NET 'TRNS10_R_B_1_PRI_CT' TRNS10-R5 C1494-1 NET 'TRNS10_R_C_2_PRI_CT' TRNS10-R23 C1492-1 NET 'TRNS10_R_D_3_PRI_CT' TRNS10-R20 C1493-1 NET 'GROUND' C1491-2 C1492-2 C1493-2 C1494-2 NET 'TRNS10_L_A_0_PRI_CT' TRNS10-L2 C1497-1 NET 'TRNS10_L_B_1_PRI_CT' TRNS10-L5 C1498-1 NET 'TRNS10_L_C_2_PRI_CT' TRNS10-L23 C1496-1 NET 'TRNS10_L_D_3_PRI_CT' TRNS10-L20 C1499-1 NET 'GROUND' C1496-2 C1497-2 C1498-2 C1499-2 # # Secondary Center Tap Nets Trans 10 Right and Left # NET 'TRNS10_R_A_0_SEC_CT' TRNS10-R8 R1492-2 NET 'TRNS10_R_B_1_SEC_CT' TRNS10-R11 R1494-2 NET 'TRNS10_R_C_2_SEC_CT' TRNS10-R17 R1491-2 NET 'TRNS10_R_D_3_SEC_CT' TRNS10-R14 R1493-2 NET 'TRNS10_R_SEC_CT_TIE' R1491-1 R1492-1 R1493-1 R1494-1 NET 'TRNS10_R_SEC_CT_TIE' C1495-2 NET 'GROUND' C1495-1 NET 'TRNS10_L_A_0_SEC_CT' TRNS10-L8 R1497-2 NET 'TRNS10_L_B_1_SEC_CT' TRNS10-L11 R1498-2 NET 'TRNS10_L_C_2_SEC_CT' TRNS10-L17 R1496-2 NET 'TRNS10_L_D_3_SEC_CT' TRNS10-L14 R1499-2 NET 'TRNS10_L_SEC_CT_TIE' R1496-1 R1497-1 R1498-1 R1499-1 NET 'TRNS10_L_SEC_CT_TIE' C1500-2 NET 'GROUND' C1500-1 # #------------------------------------------------------------ # # Switch Chips to RJ2 Front Panel RJ-45 Nets # ------------------------------------------------ # # # Original Rev. 28-Mar-2015 # Current Rev. 4-Apr-2016 # # # This Net List File contain the connections from Switch # Chips A and B to the front panel RJ-45 connector RJ2. # # RJ2 Lower or Left Switch Chip "A" Port 6 # Upper or Right Switch Chip "C" Port 6 # # # TRNS2 Left RJ2 Lower Switch Chip "A" Port 6 # Right RJ2 Upper Switch Chip "C" Port 6 # # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Swch Pri Sec ADFplus # ATCA Chip Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # To Facilitate routing one may: # # - Swap transformers within a given side of a module. # For example R1, R3, R7, R9 could be # swapped with R4, R6, R10, R12. # # - It is probably best not to wire things up so that # for a given ethernet link some of its transformers # are in the R side of the module and some of its # transformers are in the L side of the module. # # - Swap the polarity of a given transformer. For # example one may swap R1 with R3 while also # swapping R7 with R9. # # # To facilitate understanding how the magnetics for a # given Ethernet link are wired up I'm putting the nets # for the Primary and Seconday sides of a given link # next to each other in this file. # # Note that the RC components attached to the magnetics # have net names that are independed of the Etherent link # that they service. These Center Tap (CT) nets are # listed at the end of this file. These magnetics RC # nets do not have to be disturbed if the Primary and # Seconday nets are swapped for routing. # # # #------------------------------------------------------------ # # # TRNS2 Right RJ2 Upper/Right Switch Chip "C" Port 6 # # # Primary Nets Trans 2 R Chip C U33 Port 6 NET 'Chip_C_TRD0_6_DIR' U33-101 TRNS2-R1 NET 'Chip_C_TRD0_6_CMP' U33-102 TRNS2-R3 NET 'Chip_C_TRD1_6_DIR' U33-105 TRNS2-R4 NET 'Chip_C_TRD1_6_CMP' U33-104 TRNS2-R6 NET 'Chip_C_TRD2_6_DIR' U33-107 TRNS2-R24 NET 'Chip_C_TRD2_6_CMP' U33-108 TRNS2-R22 NET 'Chip_C_TRD3_6_DIR' U33-111 TRNS2-R21 NET 'Chip_C_TRD3_6_CMP' U33-110 TRNS2-R19 # # Secondary Nets Trans 2 R Front Panel RJ2 Right-Upper NET 'RJ2_U_A_0_DIR' TRNS2-R7 RJ2-U1 NET 'RJ2_U_A_0_CMP' TRNS2-R9 RJ2-U2 NET 'RJ2_U_B_1_DIR' TRNS2-R10 RJ2-U3 NET 'RJ2_U_B_1_CMP' TRNS2-R12 RJ2-U6 NET 'RJ2_U_C_2_DIR' TRNS2-R18 RJ2-U4 NET 'RJ2_U_C_2_CMP' TRNS2-R16 RJ2-U5 NET 'RJ2_U_D_3_DIR' TRNS2-R15 RJ2-U7 NET 'RJ2_U_D_3_CMP' TRNS2-R13 RJ2-U8 # #------------------------------------------------------------ # # # TRNS2 Left RJ2 Lower/Left Switch Chip "A" Port 6 # # # Primary Nets Trans 2 L Chip A U31 Port 6 NET 'Chip_A_TRD0_6_DIR' U31-101 TRNS2-L1 NET 'Chip_A_TRD0_6_CMP' U31-102 TRNS2-L3 NET 'Chip_A_TRD1_6_DIR' U31-105 TRNS2-L4 NET 'Chip_A_TRD1_6_CMP' U31-104 TRNS2-L6 NET 'Chip_A_TRD2_6_DIR' U31-107 TRNS2-L24 NET 'Chip_A_TRD2_6_CMP' U31-108 TRNS2-L22 NET 'Chip_A_TRD3_6_DIR' U31-111 TRNS2-L21 NET 'Chip_A_TRD3_6_CMP' U31-110 TRNS2-L19 # # Secondary Nets Trans 2 L Front Panel RJ2 Left-Lower NET 'RJ2_L_A_0_DIR' TRNS2-L7 RJ2-L1 NET 'RJ2_L_A_0_CMP' TRNS2-L9 RJ2-L2 NET 'RJ2_L_B_1_DIR' TRNS2-L10 RJ2-L3 NET 'RJ2_L_B_1_CMP' TRNS2-L12 RJ2-L6 NET 'RJ2_L_C_2_DIR' TRNS2-L18 RJ2-L4 NET 'RJ2_L_C_2_CMP' TRNS2-L16 RJ2-L5 NET 'RJ2_L_D_3_DIR' TRNS2-L15 RJ2-L7 NET 'RJ2_L_D_3_CMP' TRNS2-L13 RJ2-L8 # #------------------------------------------------------------ # # # Primary Center Tap Nets Trans 2 R and L # NET 'TRNS2_R_A_0_PRI_CT' TRNS2-R2 C1411-2 NET 'TRNS2_R_B_1_PRI_CT' TRNS2-R5 C1414-2 NET 'TRNS2_R_C_2_PRI_CT' TRNS2-R23 C1412-2 NET 'TRNS2_R_D_3_PRI_CT' TRNS2-R20 C1413-2 NET 'GROUND' C1411-1 C1412-1 C1413-1 C1414-1 NET 'TRNS2_L_A_0_PRI_CT' TRNS2-L2 C1417-2 NET 'TRNS2_L_B_1_PRI_CT' TRNS2-L5 C1418-2 NET 'TRNS2_L_C_2_PRI_CT' TRNS2-L23 C1416-2 NET 'TRNS2_L_D_3_PRI_CT' TRNS2-L20 C1419-2 NET 'GROUND' C1416-1 C1417-1 C1418-1 C1419-1 # # Secondary Center Tap Nets Trans 2 R and L # NET 'TRNS2_R_A_0_SEC_CT' TRNS2-R8 R1412-1 NET 'TRNS2_R_B_1_SEC_CT' TRNS2-R11 R1414-1 NET 'TRNS2_R_C_2_SEC_CT' TRNS2-R17 R1411-1 NET 'TRNS2_R_D_3_SEC_CT' TRNS2-R14 R1413-1 NET 'TRNS2_L_SEC_CT_TIE' R1411-2 R1412-2 R1413-2 R1414-2 NET 'TRNS2_L_SEC_CT_TIE' C1415-1 NET 'GROUND' C1415-2 NET 'TRNS2_L_A_0_SEC_CT' TRNS2-L8 R1417-1 NET 'TRNS2_L_B_1_SEC_CT' TRNS2-L11 R1418-1 NET 'TRNS2_L_C_2_SEC_CT' TRNS2-L17 R1416-1 NET 'TRNS2_L_D_3_SEC_CT' TRNS2-L14 R1419-1 NET 'TRNS2_R_SEC_CT_TIE' R1416-2 R1417-2 R1418-2 R1419-2 NET 'TRNS2_R_SEC_CT_TIE' C1420-1 NET 'GROUND' C1420-2 NET 'SHELF_GND' RJ2-M1 RJ2-M2 RJ2-M3 RJ2-M4 RJ2-GC1 # # Switch Chips to RJ3 Front Panel RJ-45 Nets # ------------------------------------------------ # # # Original Rev. 28-Mar-2015 # Current Rev. 4-Apr-2016 # # # This Net List File contain the connections from Switch # Chips B to the front panel RJ-45 condo connector RJ3. # # RJ3 Lower or Left Switch Chip "B" Port 6 # Upper or Right Switch Chip "B" Port 7 # # # TRNS3 Left RJ3 Lower Switch Chip "B" Port 6 # Right RJ3 Upper Switch Chip "B" Port 7 # # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Swch Pri Sec ADFplus # ATCA Chip Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # To Facilitate routing one may: # # - Swap transformers within a given side of a module. # For example R1, R3, R7, R9 could be # swapped with R4, R6, R10, R12. # # - It is probably best not to wire things up so that # for a given ethernet link some of its transformers # are in the R side of the module and some of its # transformers are in the L side of the module. # # - Swap the polarity of a given transformer. For # example one may swap R1 with R3 while also # swapping R7 with R9. # # # To facilitate understanding how the magnetics for a # given Ethernet link are wired up I'm putting the nets # for the Primary and Seconday sides of a given link # next to each other in this file. # # Note that the RC components attached to the magnetics # have net names that are independed of the Etherent link # that they service. These Center Tap (CT) nets are # listed at the end of this file. These magnetics RC # nets do not have to be disturbed if the Primary and # Seconday nets are swapped for routing. # # # #------------------------------------------------------------ # # # TRNS3 Right RJ3 Upper/Right Switch Chip "B" Port 7 # # # Primary Nets Trans 3 R Chip B U32 Port 7 NET 'Chip_B_TRD0_7_DIR' U32-123 TRNS3-R1 NET 'Chip_B_TRD0_7_CMP' U32-122 TRNS3-R3 NET 'Chip_B_TRD1_7_DIR' U32-119 TRNS3-R4 NET 'Chip_B_TRD1_7_CMP' U32-120 TRNS3-R6 NET 'Chip_B_TRD2_7_DIR' U32-117 TRNS3-R24 NET 'Chip_B_TRD2_7_CMP' U32-116 TRNS3-R22 NET 'Chip_B_TRD3_7_DIR' U32-113 TRNS3-R21 NET 'Chip_B_TRD3_7_CMP' U32-114 TRNS3-R19 # # Secondary Nets Trans 3 R Front Panel RJ3 Right-Upper NET 'RJ3_U_A_0_DIR' TRNS3-R7 RJ3-U1 NET 'RJ3_U_A_0_CMP' TRNS3-R9 RJ3-U2 NET 'RJ3_U_B_1_DIR' TRNS3-R10 RJ3-U3 NET 'RJ3_U_B_1_CMP' TRNS3-R12 RJ3-U6 NET 'RJ3_U_C_2_DIR' TRNS3-R18 RJ3-U4 NET 'RJ3_U_C_2_CMP' TRNS3-R16 RJ3-U5 NET 'RJ3_U_D_3_DIR' TRNS3-R15 RJ3-U7 NET 'RJ3_U_D_3_CMP' TRNS3-R13 RJ3-U8 # #------------------------------------------------------------ # # # TRNS3 Left RJ3 Lower/Left Switch Chip "B" Port 6 # # # Primary Nets Trans 3 L Chip B U32 Port 6 NET 'Chip_B_TRD0_6_DIR' U32-101 TRNS3-L1 NET 'Chip_B_TRD0_6_CMP' U32-102 TRNS3-L3 NET 'Chip_B_TRD1_6_DIR' U32-105 TRNS3-L4 NET 'Chip_B_TRD1_6_CMP' U32-104 TRNS3-L6 NET 'Chip_B_TRD2_6_DIR' U32-107 TRNS3-L24 NET 'Chip_B_TRD2_6_CMP' U32-108 TRNS3-L22 NET 'Chip_B_TRD3_6_DIR' U32-111 TRNS3-L21 NET 'Chip_B_TRD3_6_CMP' U32-110 TRNS3-L19 # # Secondary Nets Trans 3 L Front Panel RJ3 Left-Lower NET 'RJ3_L_A_0_DIR' TRNS3-L7 RJ3-L1 NET 'RJ3_L_A_0_CMP' TRNS3-L9 RJ3-L2 NET 'RJ3_L_B_1_DIR' TRNS3-L10 RJ3-L3 NET 'RJ3_L_B_1_CMP' TRNS3-L12 RJ3-L6 NET 'RJ3_L_C_2_DIR' TRNS3-L18 RJ3-L4 NET 'RJ3_L_C_2_CMP' TRNS3-L16 RJ3-L5 NET 'RJ3_L_D_3_DIR' TRNS3-L15 RJ3-L7 NET 'RJ3_L_D_3_CMP' TRNS3-L13 RJ3-L8 # #------------------------------------------------------------ # # # Primary Center Tap Nets Trans 3 R and L # NET 'TRNS3_R_A_0_PRI_CT' TRNS3-R2 C1421-2 NET 'TRNS3_R_B_1_PRI_CT' TRNS3-R5 C1424-2 NET 'TRNS3_R_C_2_PRI_CT' TRNS3-R23 C1422-2 NET 'TRNS3_R_D_3_PRI_CT' TRNS3-R20 C1423-2 NET 'GROUND' C1421-1 C1422-1 C1423-1 C1424-1 NET 'TRNS3_L_A_0_PRI_CT' TRNS3-L2 C1427-2 NET 'TRNS3_L_B_1_PRI_CT' TRNS3-L5 C1428-2 NET 'TRNS3_L_C_2_PRI_CT' TRNS3-L23 C1426-2 NET 'TRNS3_L_D_3_PRI_CT' TRNS3-L20 C1429-2 NET 'GROUND' C1426-1 C1427-1 C1428-1 C1429-1 # # Secondary Center Tap Nets Trans 3 R and L # NET 'TRNS3_R_A_0_SEC_CT' TRNS3-R8 R1422-1 NET 'TRNS3_R_B_1_SEC_CT' TRNS3-R11 R1424-1 NET 'TRNS3_R_C_2_SEC_CT' TRNS3-R17 R1421-1 NET 'TRNS3_R_D_3_SEC_CT' TRNS3-R14 R1423-1 NET 'TRNS3_L_SEC_CT_TIE' R1421-2 R1422-2 R1423-2 R1424-2 NET 'TRNS3_L_SEC_CT_TIE' C1425-1 NET 'GROUND' C1425-2 NET 'TRNS3_L_A_0_SEC_CT' TRNS3-L8 R1427-1 NET 'TRNS3_L_B_1_SEC_CT' TRNS3-L11 R1428-1 NET 'TRNS3_L_C_2_SEC_CT' TRNS3-L17 R1426-1 NET 'TRNS3_L_D_3_SEC_CT' TRNS3-L14 R1429-1 NET 'TRNS3_R_SEC_CT_TIE' R1426-2 R1427-2 R1428-2 R1429-2 NET 'TRNS3_R_SEC_CT_TIE' C1430-1 NET 'GROUND' C1430-2 NET 'SHELF_GND' RJ3-M1 RJ3-M2 RJ3-M3 RJ3-M4 RJ3-GC1 # # Switch Chips - All Other Nets # ------------------------------- # # # Original Rev. 22-May-2015 # Current Rev. 5-Oct-2016 # # # # This file holds All Other Nets for the 3 Switch Chips. # # # List of Nets in this File: # # - RDAC Resistor Nets on A, B, C # - Jumpers on Switch Chip "A" # - Jumpers on Switch Chip "B" # - Jumpers on Switch Chip "C" # - IMP_VOL_REF on A, B, C # - RESET Input to Switch Chips A, B, C # - CLOCK Input to Switch Chips A, B, C # - EEPROM Connection to Switch Chips A, B, C # - Loop Detect Connections to Switch Chips A, B, C # - MDC/MDIO Connections to Switch Chips A, B, C # - Serial LED Clock and Data from Switch Chips A, B, c # # # RDAC Resistors Nets to Ground for Switch Chips A, B, and C # NET 'SW_A_GPHY1_RDAC' U31-228 R2001-1 NET 'SW_A_GPHY2_RDAC' U31-96 R2002-1 NET 'GROUND' R2001-2 NET 'GROUND' R2002-2 NET 'SW_B_GPHY1_RDAC' U32-228 R2101-1 NET 'SW_B_GPHY2_RDAC' U32-96 R2102-1 NET 'GROUND' R2101-2 NET 'GROUND' R2102-2 NET 'SW_C_GPHY1_RDAC' U33-228 R2201-1 NET 'SW_C_GPHY2_RDAC' U33-96 R2202-1 NET 'GROUND' R2201-2 NET 'GROUND' R2202-2 # # Jumpers for Switch Chip A # NET 'SW_A_HW_FWDG_EN' U31-9 R2003-2 NET 'BULK_3V3' R2003-1 NET 'SW_A_LED_MODE_0' U31-12 R2004-2 NET 'GROUND' R2004-1 NET 'SW_A_LED_MODE_1' U31-13 R2005-2 NET 'BULK_3V3' R2005-1 NET 'SW_A_CPU_EEPROM_SEL' U31-18 R2006-2 NET 'GROUND' R2006-1 NET 'SW_A_TRST' U31-36 R2007-2 NET 'GROUND' R2007-1 NET 'SW_A_LED_3_EN_GREEN' U31-172 R2008-2 NET 'BULK_3V3' R2008-1 NET 'SW_A_LED_11_EPROM_TYPE1' U31-182 R2009-2 NET 'BULK_3V3' R2009-1 NET 'SW_A_LED_14_LOOP_DET_ENB' U31-186 R2010-2 NET 'BULK_3V3' R2010-1 NET 'SW_A_LED_22_DIS_IMP' U31-196 R2011-2 NET 'BULK_3V3' R2011-1 NET 'SW_A_EN_EEE' U31-38 R2012-1 NET 'GROUND' R2012-2 # # Jumpers for Switch Chip B # NET 'SW_B_HW_FWDG_EN' U32-9 R2103-2 NET 'BULK_3V3' R2103-1 NET 'SW_B_LED_MODE_0' U32-12 R2104-2 NET 'GROUND' R2104-1 NET 'SW_B_LED_MODE_1' U32-13 R2105-2 NET 'BULK_3V3' R2105-1 NET 'SW_B_CPU_EEPROM_SEL' U32-18 R2106-2 NET 'GROUND' R2106-1 NET 'SW_B_TRST' U32-36 R2107-2 NET 'GROUND' R2107-1 NET 'SW_B_LED_3_EN_GREEN' U32-172 R2108-2 NET 'BULK_3V3' R2108-1 NET 'SW_B_LED_11_EPROM_TYPE1' U32-182 R2109-2 NET 'BULK_3V3' R2109-1 NET 'SW_B_LED_14_LOOP_DET_ENB' U32-186 R2110-2 NET 'BULK_3V3' R2110-1 NET 'SW_B_LED_22_DIS_IMP' U32-196 R2111-2 NET 'BULK_3V3' R2111-1 NET 'SW_B_EN_EEE' U32-38 R2112-1 NET 'GROUND' R2112-2 # # Jumpers for Switch Chip C # NET 'SW_C_HW_FWDG_EN' U33-9 R2203-2 NET 'BULK_3V3' R2203-1 NET 'SW_C_LED_MODE_0' U33-12 R2204-2 NET 'GROUND' R2204-1 NET 'SW_C_LED_MODE_1' U33-13 R2205-2 NET 'BULK_3V3' R2205-1 NET 'SW_C_CPU_EEPROM_SEL' U33-18 R2206-2 NET 'GROUND' R2206-1 NET 'SW_C_TRST' U33-36 R2207-2 NET 'GROUND' R2207-1 NET 'SW_C_LED_3_EN_GREEN' U33-172 R2208-2 NET 'BULK_3V3' R2208-1 NET 'SW_C_LED_11_EPROM_TYPE1' U33-182 R2209-2 NET 'BULK_3V3' R2209-1 NET 'SW_C_LED_14_LOOP_DET_ENB' U33-186 R2210-2 NET 'BULK_3V3' R2210-1 NET 'SW_C_LED_22_DIS_IMP' U33-196 R2211-2 NET 'BULK_3V3' R2211-1 NET 'SW_C_EN_EEE' U33-38 R2212-1 NET 'GROUND' R2212-2 # # Ground the IMP_VOL_REF pin 146 on each Switch # NET 'GROUND' U31-146 NET 'GROUND' U32-146 NET 'GROUND' U33-146 # # RESET Input to Switch Chips A, B, C # and Generation of Switch Reset Signal # NET 'SWITCH_CHIPS_RESET_B' U31-17 NET 'SWITCH_CHIPS_RESET_B' U32-17 NET 'SWITCH_CHIPS_RESET_B' U33-17 # # CLOCK Inputs to Switch Chips A, B, C # NET 'SW_A_CLOCK' U31-34 NET 'SW_B_CLOCK' U32-34 NET 'SW_C_CLOCK' U33-34 # # EEPROM Connection to Switch Chips A, B, C # and their EEPROM Circuits # NET 'SW_A_SLV_SEL' U31-160 R2015-1 NET 'SW_A_SCLK' U31-163 R2016-1 NET 'SW_A_MOSI' U31-164 R2017-1 NET 'SW_A_MISO' U31-161 R2018-1 NET 'SW_A_EEPROM_CS' U35-1 R2015-2 NET 'SW_A_EEPROM_SCLK' U35-2 R2016-2 NET 'SW_A_EEPROM_DI' U35-3 R2017-2 NET 'SW_A_EEPROM_DO' U35-4 R2018-2 NET 'BULK_3V3' U35-8 U35-6 C2091-1 NET 'GROUND' U35-5 C2091-2 NET 'No_Conn_SW_A_EEPROM_7' U35-7 NET 'SW_B_SLV_SEL' U32-160 R2115-1 NET 'SW_B_SCLK' U32-163 R2116-1 NET 'SW_B_MOSI' U32-164 R2117-1 NET 'SW_B_MISO' U32-161 R2118-1 NET 'SW_B_EEPROM_CS' U36-1 R2115-2 NET 'SW_B_EEPROM_SCLK' U36-2 R2116-2 NET 'SW_B_EEPROM_DI' U36-3 R2117-2 NET 'SW_B_EEPROM_DO' U36-4 R2118-2 NET 'BULK_3V3' U36-8 U36-6 C2191-1 NET 'GROUND' U36-5 C2191-2 NET 'No_Conn_SW_B_EEPROM_7' U36-7 NET 'SW_C_SLV_SEL' U33-160 R2215-1 NET 'SW_C_SCLK' U33-163 R2216-1 NET 'SW_C_MOSI' U33-164 R2217-1 NET 'SW_C_MISO' U33-161 R2218-1 NET 'SW_C_EEPROM_CS' U37-1 R2215-2 NET 'SW_C_EEPROM_SCLK' U37-2 R2216-2 NET 'SW_C_EEPROM_DI' U37-3 R2217-2 NET 'SW_C_EEPROM_DO' U37-4 R2218-2 NET 'BULK_3V3' U37-8 U37-6 C2291-1 NET 'GROUND' U37-5 C2291-2 NET 'No_Conn_SW_C_EEPROM_7' U37-7 # # MDC/MDIO Connections to Switch Chips A, B, C # # These Switch Chip pins are connected to the # Hub's UltraScale FPGA 3V3 I/O Banks 84 and 94. # NET 'SW_A_MDIO_BUS' U31-61 R2020-1 NET 'FPGA_SW_A_MDIO' R2020-2 U1-AW15 # IO_L2P_T0L_N2_94 NET 'SW_A_MDC_BUS' U31-62 R2021-1 NET 'FPGA_SW_A_MDC' R2021-2 U1-AW13 # IO_L12P_T1U_N10_GC_94 NET 'SW_B_MDIO_BUS' U32-61 R2120-1 NET 'FPGA_SW_B_MDIO' R2120-2 U1-AU16 # IO_L19N_T3L_N1_DBC_AD9N_84 NET 'SW_B_MDC_BUS' U32-62 R2121-1 NET 'FPGA_SW_B_MDC' R2121-2 U1-AT16 # IO_L19P_T3L_N0_DBC_AD9P_84 NET 'SW_C_MDIO_BUS' U33-61 R2220-1 NET 'FPGA_SW_C_MDIO' R2220-2 U1-AY14 # IO_L2N_T0L_N3_94 NET 'SW_C_MDC_BUS' U33-62 R2221-1 NET 'FPGA_SW_C_MDC' R2221-2 U1-AY13 # IO_T1U_N12_94 # # Loop-Detection Connections to Switch Chips A, B, C # # For now I'm connecting these Switch Chip pins to # pins in the Hub's UltraScale FPGA 3V3 I/O Bank #84. # NET 'SW_A_ATC_LOOP_DET' U31-59 R2022-1 NET 'FPGA_SW_A_ATC_LOOP_DET' R2022-2 U1-AV13 # IO_L11N_T1U_N9_GC_94 NET 'SW_A_LOOP_DETECTED' U31-58 R2023-1 NET 'FPGA_SW_A_LOOP_DETECTED' R2023-2 U1-AY15 # IO_L1P_T0L_N0_DBC_94 NET 'SW_B_ATC_LOOP_DET' U32-59 R2122-1 NET 'FPGA_SW_B_ATC_LOOP_DET' R2122-2 U1-AT14 # IO_L14N_T2L_N3_GC_84 NET 'SW_B_LOOP_DETECTED' U32-58 R2123-1 NET 'FPGA_SW_B_LOOP_DETECTED' R2123-2 U1-AU13 # IO_L13N_T2L_N1_GC_QBC_84 NET 'SW_C_ATC_LOOP_DET' U33-59 R2222-1 NET 'FPGA_SW_C_ATC_LOOP_DET' R2222-2 U1-AV15 # IO_L22N_T3U_N7_DBC_AD0N_84 NET 'SW_C_LOOP_DETECTED' U33-58 R2223-1 NET 'FPGA_SW_C_LOOP_DETECTED' R2223-2 U1-AV16 # IO_L22P_T3U_N6_DBC_AD0P_84 # # Serial LED Clock and Data from Switch Chips A, B, C # NET 'No_Conn_SW_A_LED_CLK' U31-167 NET 'No_Conn_SW_A_LED_DATA' U31-166 NET 'No_Conn_SW_B_LED_CLK' U32-167 NET 'No_Conn_SW_B_LED_DATA' U32-166 NET 'No_Conn_SW_C_LED_CLK' U33-167 NET 'No_Conn_SW_C_LED_DATA' U33-166 # # Switch Chips - No Connection Nets # ----------------------------------- # # # Original Rev. 22-May-2015 # Current Rev. 14-Jul-2016 # # # # This file holds all No-Connection Nets # for the 3 Switch Chips. # # The point is to assign a net to every pin on the # switch chip, even pins that are not connected to # anything, and in that way you can help find mistakes. # # List of Nets in this File: # # - No Connection Nets for Switch Chip "A" currently 77 # - No Connection Nets for Switch Chip "B" currently 97 # - No Connection Nets for Switch Chip "C" currently 77 # # Note that Switch Chip "B" has more un-connected pins # because it has 2 ports (0 and 1) that are not used. # # # No-Connection Nets on Switch Chip "A" # NET 'No_Conn_SW_A_CLK_FREQ0_GPIO0' U31-14 NET 'No_Conn_SW_A_CLK_FREQ1_GPIO1' U31-15 NET 'No_Conn_SW_A_EN_8051_TxRx' U31-47 NET 'No_Conn_SW_A_EN_CLK25_OUT_CLK25_OUT' U31-26 NET 'No_Conn_SW_A_EN_CLK50_OUT_CLK50_OUT' U31-21 NET 'No_Conn_SW_A_FCSB' U31-65 NET 'No_Conn_SW_A_FSCLK' U31-66 NET 'No_Conn_SW_A_FSI' U31-67 NET 'No_Conn_SW_A_FSO' U31-64 NET 'No_Conn_SW_A_GPIO2' U31-10 NET 'No_Conn_SW_A_IMP_COL' U31-159 NET 'No_Conn_SW_A_IMP_CRS' U31-143 NET 'No_Conn_SW_A_IMP_DUPLEX' U31-52 NET 'No_Conn_SW_A_IMP_GTXCLK' U31-132 NET 'No_Conn_SW_A_IMP_LINK' U31-54 NET 'No_Conn_SW_A_IMP_MODE0_GPIO5' U31-7 NET 'No_Conn_SW_A_IMP_MODE1_GPIO6' U31-8 NET 'No_Conn_SW_A_IMP_PAUSECAP_RX' U31-55 NET 'No_Conn_SW_A_IMP_PAUSECAP_TX' U31-56 NET 'No_Conn_SW_A_IMP_RXCLK' U31-144 NET 'No_Conn_SW_A_IMP_RXD0' U31-150 NET 'No_Conn_SW_A_IMP_RXD1' U31-151 NET 'No_Conn_SW_A_IMP_RXD2' U31-152 NET 'No_Conn_SW_A_IMP_RXD3' U31-154 NET 'No_Conn_SW_A_IMP_RXD4' U31-155 NET 'No_Conn_SW_A_IMP_RXD5' U31-156 NET 'No_Conn_SW_A_IMP_RXD6' U31-157 NET 'No_Conn_SW_A_IMP_RXD7' U31-158 NET 'No_Conn_SW_A_IMP_RXDV' U31-149 NET 'No_Conn_SW_A_IMP_RXER' U31-147 NET 'No_Conn_SW_A_IMP_SPEED0' U31-51 NET 'No_Conn_SW_A_IMP_SPEED1' U31-50 NET 'No_Conn_SW_A_IMP_TXCLK' U31-141 NET 'No_Conn_SW_A_IMP_TXD0' U31-137 NET 'No_Conn_SW_A_IMP_TXD1' U31-136 NET 'No_Conn_SW_A_IMP_TXD2' U31-134 NET 'No_Conn_SW_A_IMP_TXD3' U31-131 NET 'No_Conn_SW_A_IMP_TXD4' U31-130 NET 'No_Conn_SW_A_IMP_TXD5' U31-128 NET 'No_Conn_SW_A_IMP_TXD6' U31-127 NET 'No_Conn_SW_A_IMP_TXD7' U31-126 NET 'No_Conn_SW_A_IMP_TXEN' U31-139 NET 'No_Conn_SW_A_IMP_TXER' U31-140 NET 'No_Conn_SW_A_IMP_VOL_SEL0' U31-49 NET 'No_Conn_SW_A_IMP_VOL_SEL1' U31-48 NET 'No_Conn_SW_A_INTR_B' U31-60 NET 'No_Conn_SW_A_LEDP2' U31-171 NET 'No_Conn_SW_A_LEDP6' U31-176 NET 'No_Conn_SW_A_LEDP7' U31-177 NET 'No_Conn_SW_A_LEDP10_EPROM_TYPE0' U31-181 NET 'No_Conn_SW_A_LEDP15_LOOP_IMP_SEL' U31-188 NET 'No_Conn_SW_A_LEDP18_BC_SUPP_EN' U31-191 NET 'No_Conn_SW_A_LEDP19' U31-192 NET 'No_Conn_SW_A_LEDP23_IMP_DUMB_FWDG_EN' U31-197 NET 'No_Conn_SW_A_LEDP26_ENFDXFLOW' U31-254 NET 'No_Conn_SW_A_LEDP27_ENHDXFLOW' U31-255 NET 'No_Conn_SW_A_LEDP30_IMP_TXC_DELAY' U31-2 NET 'No_Conn_SW_A_LEDP31_IMP_RXC_DELAY' U31-4 NET 'No_Conn_SW_A_NC_5' U31-5 NET 'No_Conn_SW_A_NC_6' U31-6 NET 'No_Conn_SW_A_NC_20' U31-20 NET 'No_Conn_SW_A_NC_28' U31-28 NET 'No_Conn_SW_A_NC_37' U31-37 NET 'No_Conn_SW_A_NC_39' U31-39 NET 'No_Conn_SW_A_NC_41' U31-41 NET 'No_Conn_SW_A_NC_42' U31-42 NET 'No_Conn_SW_A_NC_45' U31-45 NET 'No_Conn_SW_A_NC_46' U31-46 NET 'No_Conn_SW_A_NC_69' U31-69 NET 'No_Conn_SW_A_NC_70' U31-70 NET 'No_Conn_SW_A_NC_99' U31-99 NET 'No_Conn_SW_A_NC_225' U31-225 NET 'No_Conn_SW_A_TCK' U31-24 NET 'No_Conn_SW_A_TDI' U31-23 NET 'No_Conn_SW_A_TDO' U31-22 NET 'No_Conn_SW_A_TMS' U31-25 NET 'No_Conn_SW_A_XTALO' U31-33 # # No-Connection Nets on Switch Chip "B" # NET 'No_Conn_SW_B_CLK_FREQ0_GPIO0' U32-14 NET 'No_Conn_SW_B_CLK_FREQ1_GPIO1' U32-15 NET 'No_Conn_SW_B_EN_8051_TxRx' U32-47 NET 'No_Conn_SW_B_EN_CLK25_OUT_CLK25_OUT' U32-26 NET 'No_Conn_SW_B_EN_CLK50_OUT_CLK50_OUT' U32-21 NET 'No_Conn_SW_B_FCSB' U32-65 NET 'No_Conn_SW_B_FSCLK' U32-66 NET 'No_Conn_SW_B_FSI' U32-67 NET 'No_Conn_SW_B_FSO' U32-64 NET 'No_Conn_SW_B_GPIO2' U32-10 NET 'No_Conn_SW_B_IMP_COL' U32-159 NET 'No_Conn_SW_B_IMP_CRS' U32-143 NET 'No_Conn_SW_B_IMP_DUPLEX' U32-52 NET 'No_Conn_SW_B_IMP_GTXCLK' U32-132 NET 'No_Conn_SW_B_IMP_LINK' U32-54 NET 'No_Conn_SW_B_IMP_MODE0_GPIO5' U32-7 NET 'No_Conn_SW_B_IMP_MODE1_GPIO6' U32-8 NET 'No_Conn_SW_B_IMP_PAUSECAP_RX' U32-55 NET 'No_Conn_SW_B_IMP_PAUSECAP_TX' U32-56 NET 'No_Conn_SW_B_IMP_RXCLK' U32-144 NET 'No_Conn_SW_B_IMP_RXD0' U32-150 NET 'No_Conn_SW_B_IMP_RXD1' U32-151 NET 'No_Conn_SW_B_IMP_RXD2' U32-152 NET 'No_Conn_SW_B_IMP_RXD3' U32-154 NET 'No_Conn_SW_B_IMP_RXD4' U32-155 NET 'No_Conn_SW_B_IMP_RXD5' U32-156 NET 'No_Conn_SW_B_IMP_RXD6' U32-157 NET 'No_Conn_SW_B_IMP_RXD7' U32-158 NET 'No_Conn_SW_B_IMP_RXDV' U32-149 NET 'No_Conn_SW_B_IMP_RXER' U32-147 NET 'No_Conn_SW_B_IMP_SPEED0' U32-51 NET 'No_Conn_SW_B_IMP_SPEED1' U32-50 NET 'No_Conn_SW_B_IMP_TXCLK' U32-141 NET 'No_Conn_SW_B_IMP_TXD0' U32-137 NET 'No_Conn_SW_B_IMP_TXD1' U32-136 NET 'No_Conn_SW_B_IMP_TXD2' U32-134 NET 'No_Conn_SW_B_IMP_TXD3' U32-131 NET 'No_Conn_SW_B_IMP_TXD4' U32-130 NET 'No_Conn_SW_B_IMP_TXD5' U32-128 NET 'No_Conn_SW_B_IMP_TXD6' U32-127 NET 'No_Conn_SW_B_IMP_TXD7' U32-126 NET 'No_Conn_SW_B_IMP_TXEN' U32-139 NET 'No_Conn_SW_B_IMP_TXER' U32-140 NET 'No_Conn_SW_B_IMP_VOL_SEL0' U32-49 NET 'No_Conn_SW_B_IMP_VOL_SEL1' U32-48 NET 'No_Conn_SW_B_INTR_B' U32-60 NET 'No_Conn_SW_B_LEDP2' U32-171 NET 'No_Conn_SW_B_LEDP6' U32-176 NET 'No_Conn_SW_B_LEDP7' U32-177 NET 'No_Conn_SW_B_LEDP10_EPROM_TYPE0' U32-181 NET 'No_Conn_SW_B_LEDP15_LOOP_IMP_SEL' U32-188 NET 'No_Conn_SW_B_LEDP18_BC_SUPP_EN' U32-191 NET 'No_Conn_SW_B_LEDP19' U32-192 NET 'No_Conn_SW_B_LEDP23_IMP_DUMB_FWDG_EN' U32-197 NET 'No_Conn_SW_B_LEDP26_ENFDXFLOW' U32-254 NET 'No_Conn_SW_B_LEDP27_ENHDXFLOW' U32-255 NET 'No_Conn_SW_B_LEDP30_IMP_TXC_DELAY' U32-2 NET 'No_Conn_SW_B_LEDP31_IMP_RXC_DELAY' U32-4 NET 'No_Conn_SW_B_NC_5' U32-5 NET 'No_Conn_SW_B_NC_6' U32-6 NET 'No_Conn_SW_B_NC_20' U32-20 NET 'No_Conn_SW_B_NC_28' U32-28 NET 'No_Conn_SW_B_NC_37' U32-37 NET 'No_Conn_SW_B_NC_39' U32-39 NET 'No_Conn_SW_B_NC_41' U32-41 NET 'No_Conn_SW_B_NC_42' U32-42 NET 'No_Conn_SW_B_NC_45' U32-45 NET 'No_Conn_SW_B_NC_46' U32-46 NET 'No_Conn_SW_B_NC_69' U32-69 NET 'No_Conn_SW_B_NC_70' U32-70 NET 'No_Conn_SW_B_NC_99' U32-99 NET 'No_Conn_SW_B_NC_225' U32-225 NET 'No_Conn_SW_B_TCK' U32-24 NET 'No_Conn_SW_B_TDI' U32-23 NET 'No_Conn_SW_B_TDO' U32-22 NET 'No_Conn_SW_B_TMS' U32-25 NET 'No_Conn_SW_B_XTALO' U32-33 # # On Switch Chip "B" Ethernet Ports 0 and 1 # and their LEDs are not used. # NET 'No_Conn_SW_B_TRD_Dir_0_Port_0' U32-201 NET 'No_Conn_SW_B_TRD_Cmp_0_Port_0' U32-202 NET 'No_Conn_SW_B_TRD_Dir_1_Port_0' U32-205 NET 'No_Conn_SW_B_TRD_Cmp_1_Port_0' U32-204 NET 'No_Conn_SW_B_TRD_Dir_2_Port_0' U32-207 NET 'No_Conn_SW_B_TRD_Cmp_2_Port_0' U32-208 NET 'No_Conn_SW_B_TRD_Dir_3_Port_0' U32-211 NET 'No_Conn_SW_B_TRD_Cmp_3_Port_0' U32-210 NET 'No_Conn_SW_B_Port_0_LEDP28' U32-256 NET 'No_Conn_SW_B_Port_0_LEDP29' U32-1 NET 'No_Conn_SW_B_TRD_Dir_0_Port_1' U32-223 NET 'No_Conn_SW_B_TRD_Cmp_0_Port_1' U32-222 NET 'No_Conn_SW_B_TRD_Dir_1_Port_1' U32-219 NET 'No_Conn_SW_B_TRD_Cmp_1_Port_1' U32-220 NET 'No_Conn_SW_B_TRD_Dir_2_Port_1' U32-217 NET 'No_Conn_SW_B_TRD_Cmp_2_Port_1' U32-216 NET 'No_Conn_SW_B_TRD_Dir_3_Port_1' U32-213 NET 'No_Conn_SW_B_TRD_Cmp_3_Port_1' U32-214 NET 'No_Conn_SW_B_Port_1_LEDP24' U32-198 NET 'No_Conn_SW_B_Port_1_LEDP25' U32-199 # # No-Connection Nets on Switch Chip "C" # NET 'No_Conn_SW_C_CLK_FREQ0_GPIO0' U33-14 NET 'No_Conn_SW_C_CLK_FREQ1_GPIO1' U33-15 NET 'No_Conn_SW_C_EN_8051_TxRx' U33-47 NET 'No_Conn_SW_C_EN_CLK25_OUT_CLK25_OUT' U33-26 NET 'No_Conn_SW_C_EN_CLK50_OUT_CLK50_OUT' U33-21 NET 'No_Conn_SW_C_FCSB' U33-65 NET 'No_Conn_SW_C_FSCLK' U33-66 NET 'No_Conn_SW_C_FSI' U33-67 NET 'No_Conn_SW_C_FSO' U33-64 NET 'No_Conn_SW_C_GPIO2' U33-10 NET 'No_Conn_SW_C_IMP_COL' U33-159 NET 'No_Conn_SW_C_IMP_CRS' U33-143 NET 'No_Conn_SW_C_IMP_DUPLEX' U33-52 NET 'No_Conn_SW_C_IMP_GTXCLK' U33-132 NET 'No_Conn_SW_C_IMP_LINK' U33-54 NET 'No_Conn_SW_C_IMP_MODE0_GPIO5' U33-7 NET 'No_Conn_SW_C_IMP_MODE1_GPIO6' U33-8 NET 'No_Conn_SW_C_IMP_PAUSECAP_RX' U33-55 NET 'No_Conn_SW_C_IMP_PAUSECAP_TX' U33-56 NET 'No_Conn_SW_C_IMP_RXCLK' U33-144 NET 'No_Conn_SW_C_IMP_RXD0' U33-150 NET 'No_Conn_SW_C_IMP_RXD1' U33-151 NET 'No_Conn_SW_C_IMP_RXD2' U33-152 NET 'No_Conn_SW_C_IMP_RXD3' U33-154 NET 'No_Conn_SW_C_IMP_RXD4' U33-155 NET 'No_Conn_SW_C_IMP_RXD5' U33-156 NET 'No_Conn_SW_C_IMP_RXD6' U33-157 NET 'No_Conn_SW_C_IMP_RXD7' U33-158 NET 'No_Conn_SW_C_IMP_RXDV' U33-149 NET 'No_Conn_SW_C_IMP_RXER' U33-147 NET 'No_Conn_SW_C_IMP_SPEED0' U33-51 NET 'No_Conn_SW_C_IMP_SPEED1' U33-50 NET 'No_Conn_SW_C_IMP_TXCLK' U33-141 NET 'No_Conn_SW_C_IMP_TXD0' U33-137 NET 'No_Conn_SW_C_IMP_TXD1' U33-136 NET 'No_Conn_SW_C_IMP_TXD2' U33-134 NET 'No_Conn_SW_C_IMP_TXD3' U33-131 NET 'No_Conn_SW_C_IMP_TXD4' U33-130 NET 'No_Conn_SW_C_IMP_TXD5' U33-128 NET 'No_Conn_SW_C_IMP_TXD6' U33-127 NET 'No_Conn_SW_C_IMP_TXD7' U33-126 NET 'No_Conn_SW_C_IMP_TXEN' U33-139 NET 'No_Conn_SW_C_IMP_TXER' U33-140 NET 'No_Conn_SW_C_IMP_VOL_SEL0' U33-49 NET 'No_Conn_SW_C_IMP_VOL_SEL1' U33-48 NET 'No_Conn_SW_C_INTR_B' U33-60 NET 'No_Conn_SW_C_LEDP2' U33-171 NET 'No_Conn_SW_C_LEDP6' U33-176 NET 'No_Conn_SW_C_LEDP7' U33-177 NET 'No_Conn_SW_C_LEDP10_EPROM_TYPE0' U33-181 NET 'No_Conn_SW_C_LEDP15_LOOP_IMP_SEL' U33-188 NET 'No_Conn_SW_C_LEDP18_BC_SUPP_EN' U33-191 NET 'No_Conn_SW_C_LEDP19' U33-192 NET 'No_Conn_SW_C_LEDP23_IMP_DUMB_FWDG_EN' U33-197 NET 'No_Conn_SW_C_LEDP26_ENFDXFLOW' U33-254 NET 'No_Conn_SW_C_LEDP27_ENHDXFLOW' U33-255 NET 'No_Conn_SW_C_LEDP30_IMP_TXC_DELAY' U33-2 NET 'No_Conn_SW_C_LEDP31_IMP_RXC_DELAY' U33-4 NET 'No_Conn_SW_C_NC_5' U33-5 NET 'No_Conn_SW_C_NC_6' U33-6 NET 'No_Conn_SW_C_NC_20' U33-20 NET 'No_Conn_SW_C_NC_28' U33-28 NET 'No_Conn_SW_C_NC_37' U33-37 NET 'No_Conn_SW_C_NC_39' U33-39 NET 'No_Conn_SW_C_NC_41' U33-41 NET 'No_Conn_SW_C_NC_42' U33-42 NET 'No_Conn_SW_C_NC_45' U33-45 NET 'No_Conn_SW_C_NC_46' U33-46 NET 'No_Conn_SW_C_NC_69' U33-69 NET 'No_Conn_SW_C_NC_70' U33-70 NET 'No_Conn_SW_C_NC_99' U33-99 NET 'No_Conn_SW_C_NC_225' U33-225 NET 'No_Conn_SW_C_TCK' U33-24 NET 'No_Conn_SW_C_TDI' U33-23 NET 'No_Conn_SW_C_TDO' U33-22 NET 'No_Conn_SW_C_TMS' U33-25 NET 'No_Conn_SW_C_XTALO' U33-33 # # RJ1 on Front Panel and TRNS1 Magnetics # # Key In Net List file for the Hub Module # ---------------------------------------------- # # # # Original Rev. 17-Apr-2015 # Most Recent Rev. 31-Aug-2016 # # # This file is the Nets to the Front Panel RJ1 # condo RJ-45 connector and the associated TRNS1 # dual etherent magnetics module. # # # RJ1 Lower or Left This Hub's ROD # Upper or Right This Hub's IPMC # # # NOTE: # # At one time, at Ed's request, all 4 of the Ethernet # pairs from the ROD were inverted on the Hub between # the MagArray connector and going into the Ethernet # Magnetics for the ROD. At some point this request # was removed and the ROD's Ethernet circuits are now # routed "straight through" without inversion on the # Hub. This matches the ROD 1-Jul-2016 and the Host # version 2 schematics. The net names used on the # Hub for these Ethernet circuits match the net nemes # used in the ROD schematics. # # # #------------------------------------------------------------ # # # TRNS1 Right RJ1 Upper Hub's IPMC 10/100 Base-T # ------ # # Primary Nets Trans 1 R IPMC Ethernet from Connector IPMC NET 'IPMC_Eth_Gb_A_DIR' IPMC-171 TRNS1-R1 NET 'IPMC_Eth_Gb_A_CMP' IPMC-172 TRNS1-R3 NET 'IPMC_Eth_Gb_B_DIR' IPMC-174 TRNS1-R4 NET 'IPMC_Eth_Gb_B_CMP' IPMC-175 TRNS1-R6 NET 'IPMC_Eth_Gb_C_DIR' IPMC-177 TRNS1-R24 NET 'IPMC_Eth_Gb_C_CMP' IPMC-178 TRNS1-R22 NET 'IPMC_Eth_Gb_D_DIR' IPMC-180 TRNS1-R21 NET 'IPMC_Eth_Gb_D_CMP' IPMC-181 TRNS1-R19 # # Secondary Nets Trans 1 R Front Panel RJ1 Right-Upper NET 'RJ1_U_A_0_DIR' TRNS1-R7 RJ1-U1 NET 'RJ1_U_A_0_CMP' TRNS1-R9 RJ1-U2 NET 'RJ1_U_B_1_DIR' TRNS1-R10 RJ1-U3 NET 'RJ1_U_B_1_CMP' TRNS1-R12 RJ1-U6 NET 'RJ1_U_C_2_DIR' TRNS1-R18 RJ1-U4 NET 'RJ1_U_C_2_CMP' TRNS1-R16 RJ1-U5 NET 'RJ1_U_D_3_DIR' TRNS1-R15 RJ1-U7 NET 'RJ1_U_D_3_CMP' TRNS1-R13 RJ1-U8 # #------------------------------------------------------------ # # # TRNS1 Left RJ1 Lower Hub's ROD 10/100/1000 Base_T # ----- # # Primary Nets Trans 1 L ROD Ethernet from Meg Array S1 NET 'ROD_TxRxA_P' Meg_S1-B29 TRNS1-L1 NET 'ROD_TxRxA_N' Meg_S1-C29 TRNS1-L3 NET 'ROD_TxRxB_P' Meg_S1-B31 TRNS1-L4 NET 'ROD_TxRxB_N' Meg_S1-C31 TRNS1-L6 NET 'ROD_TxRxC_P' Meg_S1-B33 TRNS1-L24 NET 'ROD_TxRxC_N' Meg_S1-C33 TRNS1-L22 NET 'ROD_TxRxD_P' Meg_S1-B35 TRNS1-L21 NET 'ROD_TxRxD_N' Meg_S1-C35 TRNS1-L19 # # Secondary Nets Trans 1 L Front Panel RJ1 Left-Lower NET 'RJ1_L_A_0_DIR' TRNS1-L7 RJ1-L1 NET 'RJ1_L_A_0_CMP' TRNS1-L9 RJ1-L2 NET 'RJ1_L_B_1_DIR' TRNS1-L10 RJ1-L3 NET 'RJ1_L_B_1_CMP' TRNS1-L12 RJ1-L6 NET 'RJ1_L_C_2_DIR' TRNS1-L18 RJ1-L4 NET 'RJ1_L_C_2_CMP' TRNS1-L16 RJ1-L5 NET 'RJ1_L_D_3_DIR' TRNS1-L15 RJ1-L7 NET 'RJ1_L_D_3_CMP' TRNS1-L13 RJ1-L8 # #------------------------------------------------------------ # # # Primary Center Tap Nets Trans 1 R and L # NET 'TRNS1_R_A_0_PRI_CT' TRNS1-R2 C1401-2 NET 'TRNS1_R_B_1_PRI_CT' TRNS1-R5 C1404-2 NET 'TRNS1_R_C_2_PRI_CT' TRNS1-R23 C1402-2 NET 'TRNS1_R_D_3_PRI_CT' TRNS1-R20 C1403-2 NET 'GROUND' C1401-1 C1402-1 C1403-1 C1404-1 NET 'TRNS1_L_A_0_PRI_CT' TRNS1-L2 C1407-2 NET 'TRNS1_L_B_1_PRI_CT' TRNS1-L5 C1408-2 NET 'TRNS1_L_C_2_PRI_CT' TRNS1-L23 C1406-2 NET 'TRNS1_L_D_3_PRI_CT' TRNS1-L20 C1409-2 NET 'GROUND' C1406-1 C1407-1 C1408-1 C1409-1 # # Jumpers to connect the Primay Center Taps of the # IPMC A/Tx B/Rx Etherent circuit magnetics to # the BULK_3V3 rail. These center tap to 3V3 connections # are needed because the IPMC uses an old "current mode" # Phys chip a National/TI DP83848. # # These two jumpers to connect the center taps to 3V3 # are Zero_Ohm 0603 packages. # # These 3V3 center tap connections are only needed on the # IPMC A/Tx B/Rx circuits because all of the other # Ethernet circuits on the Hub Module use "voltage mode" # Phys chips. # NET 'TRNS1_R_A_0_PRI_CT' R1405-1 NET 'TRNS1_R_B_1_PRI_CT' R1410-1 NET 'BULK_3V3' R1405-2 R1410-2 # # Secondary Center Tap Nets Trans 1 R and L # NET 'TRNS1_R_A_0_SEC_CT' TRNS1-R8 R1402-1 NET 'TRNS1_R_B_1_SEC_CT' TRNS1-R11 R1404-1 NET 'TRNS1_R_C_2_SEC_CT' TRNS1-R17 R1401-1 NET 'TRNS1_R_D_3_SEC_CT' TRNS1-R14 R1403-1 NET 'TRNS1_L_SEC_CT_TIE' R1401-2 R1402-2 R1403-2 R1404-2 NET 'TRNS1_L_SEC_CT_TIE' C1405-1 NET 'GROUND' C1405-2 NET 'TRNS1_L_A_0_SEC_CT' TRNS1-L8 R1407-1 NET 'TRNS1_L_B_1_SEC_CT' TRNS1-L11 R1408-1 NET 'TRNS1_L_C_2_SEC_CT' TRNS1-L17 R1406-1 NET 'TRNS1_L_D_3_SEC_CT' TRNS1-L14 R1409-1 NET 'TRNS1_R_SEC_CT_TIE' R1406-2 R1407-2 R1408-2 R1409-2 NET 'TRNS1_R_SEC_CT_TIE' C1410-1 NET 'GROUND' C1410-2 NET 'SHELF_GND' RJ1-M1 RJ1-M2 RJ1-M3 RJ1-M4 RJ1-GC1 # # Switch Chip to Switch Chip Nets # -------------------------------------- # # # Original Rev. 22-Apr-2015 # Current Rev. 8-Mar-2016 # # # This Net List File contain the connections between: # # Switch Chip B <--> Switch Chip A # Switch Chip B <--> Switch Chip C # Switch Chip B <--> This Hub's FPGA Phys U22. # # # Chip "A" U31 # # Port 7 to Switch Chip "B" Capacitor Coupled # # # Chip "B" U32 is the "center" Switch Chip: # # Port 4 to This Hub's FPGA Phys U22 Capacitor Coupled # Port 2 to Switch Chip "A" Capacitor Coupled # Port 3 to Switch Chip "C" Capacitor Coupled # # # Chip "C" U33 # # Port 7 to Switch Chip "B" Capacitor Coupled # # # #------------------------------------------------------------ # # Link: Chip B Port 2 <--> Chip A Port 7 # #------------------------------------------------------------ # # Switch Chip "B" U32 Port 2 # NET 'Chip_B_TRD0_2_DIR' U32-230 C2309-1 NET 'Chip_B_TRD0_2_CMP' U32-231 C2310-1 NET 'Chip_B_TRD1_2_DIR' U32-234 C2311-1 NET 'Chip_B_TRD1_2_CMP' U32-233 C2312-1 NET 'Chip_B_TRD2_2_DIR' U32-236 C2313-1 NET 'Chip_B_TRD2_2_CMP' U32-237 C2314-1 NET 'Chip_B_TRD3_2_DIR' U32-240 C2315-1 NET 'Chip_B_TRD3_2_CMP' U32-239 C2316-1 # #------------------------------------------------------------ # # Switch Chip "A" U31 Port 7 # NET 'Chip_A_TRD0_7_DIR' U31-123 C2309-2 NET 'Chip_A_TRD0_7_CMP' U31-122 C2310-2 NET 'Chip_A_TRD1_7_DIR' U31-119 C2311-2 NET 'Chip_A_TRD1_7_CMP' U31-120 C2312-2 NET 'Chip_A_TRD2_7_DIR' U31-117 C2313-2 NET 'Chip_A_TRD2_7_CMP' U31-116 C2314-2 NET 'Chip_A_TRD3_7_DIR' U31-113 C2315-2 NET 'Chip_A_TRD3_7_CMP' U31-114 C2316-2 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # Link: Chip B Port 3 <--> Chip C Port 7 # #------------------------------------------------------------ # # Switch Chip "B" U32 Port 3 # NET 'Chip_B_TRD0_3_DIR' U32-252 C2301-1 NET 'Chip_B_TRD0_3_CMP' U32-251 C2302-1 NET 'Chip_B_TRD1_3_DIR' U32-248 C2303-1 NET 'Chip_B_TRD1_3_CMP' U32-249 C2304-1 NET 'Chip_B_TRD2_3_DIR' U32-246 C2305-1 NET 'Chip_B_TRD2_3_CMP' U32-245 C2306-1 NET 'Chip_B_TRD3_3_DIR' U32-242 C2307-1 NET 'Chip_B_TRD3_3_CMP' U32-243 C2308-1 # #------------------------------------------------------------ # # Switch Chip "C" U33 Port 7 # NET 'Chip_C_TRD0_7_DIR' U33-123 C2301-2 NET 'Chip_C_TRD0_7_CMP' U33-122 C2302-2 NET 'Chip_C_TRD1_7_DIR' U33-119 C2303-2 NET 'Chip_C_TRD1_7_CMP' U33-120 C2304-2 NET 'Chip_C_TRD2_7_DIR' U33-117 C2305-2 NET 'Chip_C_TRD2_7_CMP' U33-116 C2306-2 NET 'Chip_C_TRD3_7_DIR' U33-113 C2307-2 NET 'Chip_C_TRD3_7_CMP' U33-114 C2308-2 # #------------------------------------------------------------ # # #------------------------------------------------------------ # # Link: Chip B Port 4 <--> This Hub's FPGA Phys U22 # #------------------------------------------------------------ # # Switch Chip "B" U32 Port 4 connection to couping caps # NET 'Chip_B_TRD0_4_DIR' U32-72 C2317-1 NET 'Chip_B_TRD0_4_CMP' U32-73 C2318-1 NET 'Chip_B_TRD1_4_DIR' U32-76 C2319-1 NET 'Chip_B_TRD1_4_CMP' U32-75 C2320-1 NET 'Chip_B_TRD2_4_DIR' U32-78 C2321-1 NET 'Chip_B_TRD2_4_CMP' U32-79 C2322-1 NET 'Chip_B_TRD3_4_DIR' U32-82 C2323-1 NET 'Chip_B_TRD3_4_CMP' U32-81 C2324-1 # #------------------------------------------------------------ # # This Hub's FPGA Phys Chip U22 connection to coupling caps # NET 'Phys_U22_TXRX_A_DIR' C2317-2 NET 'Phys_U22_TXRX_A_CMP' C2318-2 NET 'Phys_U22_TXRX_B_DIR' C2319-2 NET 'Phys_U22_TXRX_B_CMP' C2320-2 NET 'Phys_U22_TXRX_C_DIR' C2321-2 NET 'Phys_U22_TXRX_C_CMP' C2322-2 NET 'Phys_U22_TXRX_D_DIR' C2323-2 NET 'Phys_U22_TXRX_D_CMP' C2324-2 # #------------------------------------------------------------ # # # LED Connection Nets # # Key In Net List file for the Hub Module # ------------------------------------------------- # # # Original Rev. 24-Apr-2015 # Most Recent Rev. 15-Aug-2016 # # # This file holds the Nets involved with the # front panel LEDs # # # # The following set of nets connect the 40 LEDs # at the top of the front panel that show the status # of various Ethernet links. # # The Anodes of these 40 LEDs are now connected directly # to the BULK_3V3 supply. The cathodes of these LEDs are # connected through a series resistor to the source of # the signal that is displayed by a given LED. # # # Connect the LED Anodes to BULK_3V3 # NET 'BULK_3V3' LE5-2 # LED_5 Anode NET 'BULK_3V3' LE6-2 # LED_6 Anode NET 'BULK_3V3' LE7-2 # LED_7 Anode NET 'BULK_3V3' LE8-2 # LED_8 Anode NET 'BULK_3V3' LE9-2 # LED__9 Anode NET 'BULK_3V3' LE10-2 # LED_10 Anode NET 'BULK_3V3' LE11-2 # LED_11 Anode NET 'BULK_3V3' LE12-2 # LED_12 Anode NET 'BULK_3V3' LE13-2 # LED_13 Anode NET 'BULK_3V3' LE14-2 # LED_14 Anode NET 'BULK_3V3' LE15-2 # LED_15 Anode NET 'BULK_3V3' LE16-2 # LED_16 Anode NET 'BULK_3V3' LE17-2 # LED_17 Anode NET 'BULK_3V3' LE18-2 # LED_18 Anode NET 'BULK_3V3' LE19-2 # LED_19 Anode NET 'BULK_3V3' LE20-2 # LED_20 Anode NET 'BULK_3V3' LE21-2 # LED_21 Anode NET 'BULK_3V3' LE22-2 # LED_22 Anode NET 'BULK_3V3' LE23-2 # LED_23 Anode NET 'BULK_3V3' LE24-2 # LED_24 Anode NET 'BULK_3V3' LE25-2 # LED_25 Anode NET 'BULK_3V3' LE26-2 # LED_25 Anode NET 'BULK_3V3' LE27-2 # LED_27 Anode NET 'BULK_3V3' LE28-2 # LED_28 Anode NET 'BULK_3V3' LE29-2 # LED_29 Anode NET 'BULK_3V3' LE30-2 # LED_30 Anode NET 'BULK_3V3' LE31-2 # LED_31 Anode NET 'BULK_3V3' LE32-2 # LED_32 Anode NET 'BULK_3V3' LE33-2 # LED_33 Anode NET 'BULK_3V3' LE34-2 # LED_34 Anode NET 'BULK_3V3' LE35-2 # LED_35 Anode NET 'BULK_3V3' LE36-2 # LED_36 Anode NET 'BULK_3V3' LE37-2 # LED_37 Anode NET 'BULK_3V3' LE38-2 # LED_38 Anode NET 'BULK_3V3' LE39-2 # LED_39 Anode NET 'BULK_3V3' LE40-2 # LED_40 Anode NET 'BULK_3V3' LE41-2 # LED_41 Anode NET 'BULK_3V3' LE42-2 # LED_42 Anode NET 'BULK_3V3' LE43-2 # LED_43 Anode NET 'BULK_3V3' LE44-2 # LED_44 Anode # # Connect the LED Cathodes to their Series Resistor # NET 'LED_5_Cathode' LE5-1 R205-1 NET 'LED_6_Cathode' LE6-1 R206-1 NET 'LED_7_Cathode' LE7-1 R207-1 NET 'LED_8_Cathode' LE8-1 R208-1 NET 'LED_9_Cathode' LE9-1 R209-1 NET 'LED_10_Cathode' LE10-1 R210-1 NET 'LED_11_Cathode' LE11-1 R211-1 NET 'LED_12_Cathode' LE12-1 R212-1 NET 'LED_13_Cathode' LE13-1 R213-1 NET 'LED_14_Cathode' LE14-1 R214-1 NET 'LED_15_Cathode' LE15-1 R215-1 NET 'LED_16_Cathode' LE16-1 R216-1 NET 'LED_17_Cathode' LE17-1 R217-1 NET 'LED_18_Cathode' LE18-1 R218-1 NET 'LED_19_Cathode' LE19-1 R219-1 NET 'LED_20_Cathode' LE20-1 R220-1 NET 'LED_21_Cathode' LE21-1 R221-1 NET 'LED_22_Cathode' LE22-1 R222-1 NET 'LED_23_Cathode' LE23-1 R223-1 NET 'LED_24_Cathode' LE24-1 R224-1 NET 'LED_25_Cathode' LE25-1 R225-1 NET 'LED_26_Cathode' LE26-1 R226-1 NET 'LED_27_Cathode' LE27-1 R227-1 NET 'LED_28_Cathode' LE28-1 R228-1 NET 'LED_29_Cathode' LE29-1 R229-1 NET 'LED_30_Cathode' LE30-1 R230-1 NET 'LED_31_Cathode' LE31-1 R231-1 NET 'LED_32_Cathode' LE32-1 R232-1 NET 'LED_33_Cathode' LE33-1 R233-1 NET 'LED_34_Cathode' LE34-1 R234-1 NET 'LED_35_Cathode' LE35-1 R235-1 NET 'LED_36_Cathode' LE36-1 R236-1 NET 'LED_37_Cathode' LE37-1 R237-1 NET 'LED_38_Cathode' LE38-1 R238-1 NET 'LED_39_Cathode' LE39-1 R239-1 NET 'LED_40_Cathode' LE40-1 R240-1 NET 'LED_41_Cathode' LE41-1 R241-1 NET 'LED_42_Cathode' LE42-1 R242-1 NET 'LED_43_Cathode' LE43-1 R243-1 NET 'LED_44_Cathode' LE44-1 R244-1 # # Connect the LED Series Resistor to the # source of the signal that illuminates the LED # NET 'LED_5_Cath_Res' R205-2 U32-178 # Swch Chip B Port 5 NET 'LED_6_Cath_Res' R206-2 U32-179 NET 'LED_7_Cath_Res' R207-2 U33-178 # Swch Chip C Port 5 NET 'LED_8_Cath_Res' R208-2 U33-179 NET 'LED_9_Cath_Res' R209-2 U33-184 # Swch Chip C Port 4 NET 'LED_10_Cath_Res' R210-2 U33-185 NET 'LED_11_Cath_Res' R211-2 U33-189 # Swch Chip C Port 3 NET 'LED_12_Cath_Res' R212-2 U33-190 NET 'LED_13_Cath_Res' R213-2 U33-194 # Swch Chip C Port 2 NET 'LED_14_Cath_Res' R214-2 U33-195 NET 'LED_15_Cath_Res' R215-2 U33-198 # Swch Chip C Port 1 NET 'LED_16_Cath_Res' R216-2 U33-199 NET 'LED_17_Cath_Res' R217-2 U33-256 # Swch Chip C Port 0 NET 'LED_18_Cath_Res' R218-2 U33-1 NET 'LED_19_Cath_Res' R219-2 U31-178 # Swch Chip A Port 5 NET 'LED_20_Cath_Res' R220-2 U31-179 NET 'LED_21_Cath_Res' R221-2 U31-184 # Swch Chip A Port 4 NET 'LED_22_Cath_Res' R222-2 U31-185 NET 'LED_23_Cath_Res' R223-2 U31-189 # Swch Chip A Port 3 NET 'LED_24_Cath_Res' R224-2 U31-190 NET 'LED_25_Cath_Res' R225-2 U31-194 # Swch Chip A Port 2 NET 'LED_26_Cath_Res' R226-2 U31-195 NET 'LED_27_Cath_Res' R227-2 U31-198 # Swch Chip A Port 1 NET 'LED_28_Cath_Res' R228-2 U31-199 NET 'LED_29_Cath_Res' R229-2 U31-256 # Swch Chip A Port 0 NET 'LED_30_Cath_Res' R230-2 U31-1 NET 'LED_31_Cath_Res' R231-2 U32-184 # Swch Chip B Port 4 NET 'LED_32_Cath_Res' R232-2 U32-185 NET 'LED_33_Cath_Res' R233-2 U32-194 # Swch Chip B Port 2 NET 'LED_34_Cath_Res' R234-2 U32-195 NET 'LED_35_Cath_Res' R235-2 U32-189 # Swch Chip B Port 3 NET 'LED_36_Cath_Res' R236-2 U32-190 NET 'LED_37_Cath_Res' R237-2 U31-168 # Swch Chip A Port 7 NET 'LED_38_Cath_Res' R238-2 U31-170 NET 'LED_39_Cath_Res' R239-2 U33-168 # Swch Chip C Port 7 NET 'LED_40_Cath_Res' R240-2 U33-170 NET 'LED_41_Cath_Res' R241-2 # Phys Chip U22 NET 'LED_42_Cath_Res' R242-2 # led_lemo_translator_driver_nets U553-18 & 19 NET 'LED_43_Cath_Res' R243-2 # Phys Chip U21 NET 'LED_44_Cath_Res' R244-2 # led_lemo_translator_driver_nets U553-20 & 21 # # Now show the connections for the 4 ATCA LEDs # that are driven by the IPMC mezzanine. # # I think that the IPMC (stupidly) drives its # outputs voltage Hi to turn ON an LED. I don't # know this for certain because the IPMC manual # never bothers to tell you one way of the other. # # I will tie the Cathodes of these 4 LEDs to # ground and run their Anodes through series # resistors to the appropriate IMPC connector pins. # NET 'GROUND' LE1-1 LE2-1 LE3-1 LE4-1 # ATCA LED1 Red NET 'LED1_Anode' LE1-2 R201-2 NET 'ATCA_LED_1' R201-1 IPMC-104 # ATCA LED2 Green NET 'LED2_Anode' LE2-2 R202-2 NET 'ATCA_LED_2' R202-1 IPMC-105 # ATCA LED3 Yellow NET 'LED3_Anode' LE3-2 R203-2 NET 'ATCA_LED_3' R203-1 IPMC-106 # ATCA BLUE LED NET 'LED4_Anode' LE4-2 R204-2 NET 'ATCA_LED_4' R204-1 IPMC-103 # # Now show the connections for the: # # 5 ROD LEDs LE45, LE46, LE47, LE48, LE49 # # 3 Hub LEDs LE50, LE51, LE52 # # The Anodes on most of these 8 LEDs are now connected # directly to the BULK_3V3 supply. # # The Anodes on the two Blue LEDs, LE48 and LE49 are # connected directly to the CNST_5V0 supply. # # The cathodes of these LEDs are connected through a # series resistor to the source of the signal that is # displayed by a given LED. # # The drivers for these 8 LEDs are described in # the nets file: led_lemo_translator_driver_nets # # The 5 Front Panel ROD LEDs: NET 'BULK_3V3' LE45-2 # LED_45 Anode NET 'BULK_3V3' LE46-2 # LED_46 Anode NET 'BULK_3V3' LE47-2 # LED_47 Anode NET 'CNST_5V0' LE48-2 # LED_48 Anode NET 'CNST_5V0' LE49-2 # LED_49 Anode NET 'LED_45_Cathode' LE45-1 R245-1 NET 'LED_46_Cathode' LE46-1 R246-1 NET 'LED_47_Cathode' LE47-1 R247-1 NET 'LED_48_Cathode' LE48-1 R248-1 NET 'LED_49_Cathode' LE49-1 R249-1 NET 'LED_45_Cath_Res' R245-2 # Driven by U551-17 from S1-B3 NET 'LED_46_Cath_Res' R246-2 # Driven by U551-20 from S1-C1 NET 'LED_47_Cath_Res' R247-2 # Driven by U551-18 from S1-C2 NET 'LED_48_Cath_Res' R248-2 # Driven by U552-2 from S1-C3 NET 'LED_49_Cath_Res' R249-2 # Driven by U552-4 from S1-C4 # The 3 Front Panel Hub LEDs: NET 'BULK_3V3' LE50-2 # LED_50 Anode NET 'BULK_3V3' LE51-2 # LED_51 Anode NET 'BULK_3V3' LE52-2 # LED_52 Anode NET 'LED_50_Cathode' LE50-1 R250-1 NET 'LED_51_Cathode' LE51-1 R251-1 NET 'LED_52_Cathode' LE52-1 R252-1 NET 'LED_50_Cath_Res' R250-2 # Driven by U553-17 NET 'LED_51_Cath_Res' R251-2 # Driven by U553-16 NET 'LED_52_Cath_Res' R252-2 # Driven by U553-15 # # Now show the connections for the 2 "Rationality LEDs" # # - One of these LEDs (LE53) shows whether or not # the Isolated +12V supply is running. # # - The other LED (LE54) shows whether or not all of # the power buses on the Hub Module are operating within # tolerance. # # The cathode of the Iso +12V LED is connected to ground. # The anode of this LED is connected through a series # resistor to the Iso_12V bus. This is LED53. # # The anode of the All Power OK LED is tied through # a series resistor to the BULK_3V3 bus. The cathode # of this LED is tied to the source of the All Power # Is OK signal. This is LED54 # NET 'LED_53_Anode' LE53-2 R253-2 NET 'ISO_12V' R253-1 NET 'GROUND' LE53-1 NET 'LED_54_Anode' LE54-2 R254-2 NET 'BULK_3V3' R254-1 NET 'LED_54_Cathode' LE54-1 # # Now for the 12 LEDs in the 3 Condo RJ-45 Connectors. # # Each jack in each condo connector has 2 LEDs. # # Using the TE Conn definition of the RJ-45 LEDs: # # LED2 & LED3 are Upper or Right jack # LED1 & LED4 are Lower or Left jack # # The Anodes of these LEDs are connected directly # to the BULK_3V3 rail. This is not the way that # I like it but there is no room to do it correctly, # i.e. put the series resistor in the Anode circuit. # # The Cathodes of these LEDs are connected through # a series resistor to the low active source of a # given signal. # # Carefuly note the LED pin number vs LED location # on the Condo RJ-45 connectors. # # # RJ1-LED2 LED_55 RJ1 Upper or Right # RJ1-LED3 LED_56 # # RJ1-LED1 LED_57 RJ1 Lower or Left # RJ1-LED4 LED_58 # # # RJ2-LED2 LED_59 RJ2 Upper or Right # RJ2-LED3 LED_60 # # RJ2-LED1 LED_61 RJ2 Lower or Left # RJ2-LED4 LED_62 # # # RJ3-LED2 LED_63 RJ3 Upper or Right # RJ3-LED3 LED_64 # # RJ3-LED1 LED_65 RJ3 Lower or Left # RJ3-LED4 LED_66 # # # Connect the Anodes of these 12 Condo RJ45 # LEDs to BULK_3V3 # # RJ1 Upper or Right NET 'BULK_3V3' RJ1-LED2AND # LED_55_Anode NET 'BULK_3V3' RJ1-LED3AND # LED_56_Anode # RJ1 Lower or Left NET 'BULK_3V3' RJ1-LED1AND # LED_57_Anode NET 'BULK_3V3' RJ1-LED4AND # LED_58_Anode # RJ2 Upper or Right NET 'BULK_3V3' RJ2-LED2AND # LED_59 Anode NET 'BULK_3V3' RJ2-LED3AND # LED_60 Anode # RJ2 Lower or Left NET 'BULK_3V3' RJ2-LED1AND # LED_61 Anode NET 'BULK_3V3' RJ2-LED4AND # LED_62 Anode # RJ3 Upper or Right NET 'BULK_3V3' RJ3-LED2AND # LED_63 Anode NET 'BULK_3V3' RJ3-LED3AND # LED_64 Anode # RJ3 Lower or Left NET 'BULK_3V3' RJ3-LED1AND # LED_65 Anode NET 'BULK_3V3' RJ3-LED4AND # LED_66 Anode # # Connect the LED Cathodes to their Series Resistor # NET 'LED_55_Cathode' RJ1-LED2CTH R255-1 NET 'LED_56_Cathode' RJ1-LED3CTH R256-1 NET 'LED_57_Cathode' RJ1-LED1CTH R257-1 NET 'LED_58_Cathode' RJ1-LED4CTH R258-1 NET 'LED_59_Cathode' RJ2-LED2CTH R259-1 NET 'LED_60_Cathode' RJ2-LED3CTH R260-1 NET 'LED_61_Cathode' RJ2-LED1CTH R261-1 NET 'LED_62_Cathode' RJ2-LED4CTH R262-1 NET 'LED_63_Cathode' RJ3-LED2CTH R263-1 NET 'LED_64_Cathode' RJ3-LED3CTH R264-1 NET 'LED_65_Cathode' RJ3-LED1CTH R265-1 NET 'LED_66_Cathode' RJ3-LED4CTH R266-1 # # Connect the LED Series Resistor to the # source of the signal that illuminates the LED # NET 'No_Conn_LED_55_Cath_Res' R255-2 # No Connection to IPMC NET 'No_Conn_LED_56_Cath_Res' R256-2 # No Connection to IPMC NET 'LED_57_Cath_Res' R257-2 # ROD via led_lemo_translator_driver_nets NET 'LED_58_Cath_Res' R258-2 # ROD via led_lemo_translator_driver_nets NET 'LED_59_Cath_Res' R259-2 U33-174 # Swch Chip C Port 6 NET 'LED_60_Cath_Res' R260-2 U33-175 NET 'LED_61_Cath_Res' R261-2 U31-174 # Swch Chip A Port 6 NET 'LED_62_Cath_Res' R262-2 U31-175 NET 'LED_63_Cath_Res' R263-2 U32-168 # Swch Chip B Port 7 NET 'LED_64_Cath_Res' R264-2 U32-170 NET 'LED_65_Cath_Res' R265-2 U32-174 # Swch Chip B Port 6 NET 'LED_66_Cath_Res' R266-2 U32-175 # # # LED and LEMO Translator and Driver Nets # # Key In Net List file for the Hub Module # ------------------------------------------------- # # # Original Rev. 25-Sep-2015 # Most Recent Rev. 5-Dec-2016 # # # This file holds the nets for the Translators and Drivers # for the LEDs and the LEMO Connector that are controlled # by both the ROD and by the Hub. # # # ROD - Front panel signal table: # # MegArray Old-Old Old New LED # S1 Pin# Name Name Current Name Color # -------- ------- ------ ---------------- ------ # # B1 FP1 LED-0 Phy_LED2_B Green # B2 FP3 LED-Y Phy_LED1_B Yellow # B3 FP5 LED-B Prog_Done_LED_B Green # B4 FP7 LEMO-0 LEMO -- # # C1 FP2 LED-1 Pwr_Good_LED_B Green # C2 FP4 LED-R SMB_Alert_LED_B RED # C3 FP6 LED-G GP_LED_B Blue # C4 FP8 LEMO-1 Run_LED_B Blue # # # # ROD Front-Panel LEDs & Lemo # # # Nets from the S1 MegArray Connector # to the 1V8 Inputs on the Translator # NET 'ROD_FP_MegArray_B1' Meg_S1-B1 U551-3 NET 'ROD_FP_MegArray_C1' Meg_S1-C1 U551-4 NET 'ROD_FP_MegArray_B2' Meg_S1-B2 U551-5 NET 'ROD_FP_MegArray_C2' Meg_S1-C2 U551-6 NET 'ROD_FP_MegArray_B3' Meg_S1-B3 U551-7 NET 'ROD_FP_MegArray_C3' Meg_S1-C3 U551-8 NET 'ROD_FP_MegArray_B4' Meg_S1-B4 U551-9 NET 'ROD_FP_MegArray_C4' Meg_S1-C4 U551-10 # # ROD Front-Panel LEDs & Lemo # # ROD Front Panel Connections from the ROD Translator # to the LED or LEMO through a Driver or Direct # # B1 FP1 LED-0 Phy_LED2_B Green # LED_57 RJ1-LED1 RJ1 Lower or Left Lnk Grn MegArray S1 B1 # led_connection_nets:NET 'LED_57_Cath_Res' R257-2 NET 'LED_57_Cath_Res' U551-21 # ROD_FP_B1_LED # B2 FP3 LED-Y Phy_LED1_B Yellow # LED_58 RJ1-LED4 RJ1 Lower or Left Act Yel MegArray S1 B2 # led_connection_nets:NET 'LED_58_Cath_Res' R258-2 NET 'LED_58_Cath_Res' U551-19 # ROD_FP_B2_LED # B3 FP5 LED-B Prog_Done_LED_B Green # LED_45 Prog_Done_LED_B Green MegArray S1 B3 # led_connection_nets:NET 'LED_45_Cath_Res' R245-2 NET 'LED_45_Cath_Res' U551-17 # ROD_FP_B3_LED # C1 FP2 LED-1 Pwr_Good_LED_B Green # LED_46 Pwr_Good_LED_B Green MegArray S1 C1 # led_connection_nets:NET 'LED_46_Cath_Res' R246-2 NET 'LED_46_Cath_Res' U551-20 # ROD_FP_C1_LED # C2 FP4 LED-R SMB_Alert_LED_B RED # LED_47 SMB_Alert_LED_B RED MegArray S1 C2 # led_connection_nets:NET 'LED_47_Cath_Res' R247-2 NET 'LED_47_Cath_Res' U551-18 # ROD_FP_C2_LED # C3 FP6 LED-G GP_LED_B Blue # LED_48 GP_LED_B Blue MegArray S1 C3 # led_connection_nets:NET 'LED_48_Cath_Res' R248-2 NET 'ROD_FP_MegArray_C3_Drv_In' U551-16 U552-1 NET 'LED_48_Cath_Res' U552-2 # ROD_FP_C3_LED # C4 FP8 LEMO-1 Run_LED_B Blue # LED_49 Run_LED_B Blue MegArray S1 C4 # led_connection_nets:NET 'LED_49_Cath_Res' R249-2 NET 'ROD_FP_MegArray_C4_Drv_In' U551-14 U552-3 NET 'LED_49_Cath_Res' U552-4 # ROD_FP_C4_LED # B4 FP7 LEMO-0 LEMO -- NET 'ROD_FP_MegArray_B4_Drv_In' U551-15 U552-5 U552-13 U552-11 U552-9 NET 'LEMO_Center' Wterm61-1 U552-6 U552-12 U552-10 U552-8 # ROD_FP_B4_LEMO NET 'GROUND' Wterm62-1 NET 'LEMO_Center' R2901-1 NET 'BULK_3V3' R2901-2 # # Hub Front-Panel LEDs # # Hub Front Panel Connections through the Hub Translator # to the Hub Front-Panel LEDs # # # Hub Phys Chip U21 & U22 Front-Panel LEDs # # # LED Ref # Desgntr Display Source -Pin # ------- --------------------- -------------------------- # # LE41 Hub FPGA to Sw Link Grn Phys U22 LED2-15 # LE42 Hub FPGA to Sw Active Yel Phys U22 LED1-17 # # LE43 Hub FPGA to BI Ch 2 Link Grn Phys U21 LED2-15 # LE44 Hub FPGA to BI Ch 2 Active Yel Phys U21 LED1-17 # NET 'PHYS_U22_LED1__PHYAD0' U553-5 NET 'LED_42_Cath_Res' U553-19 NET 'PHYS_U22_LED2__PHYAD1' U553-6 NET 'LED_41_Cath_Res' U553-18 NET 'PHYS_U21_LED1__PHYAD0' U553-3 NET 'LED_44_Cath_Res' U553-21 NET 'PHYS_U21_LED2__PHYAD1' U553-4 NET 'LED_43_Cath_Res' U553-20 # # Hub FPGA Driven LEDs # # The Hub Module's FPGA directly controls 3 Front Panel # LEDs using 3 of its Select I/O lines. # # LED Ref # Desgntr Display Source -Pin # ------- --------------------- -------------------------- # # LE50 Hub FPGA LED Grn Hub FPGA Select I/O ?? # LE51 Hub FPGA LED Yel Hub FPGA Select I/O ?? # LE52 Hub FPGA LED Red Hub FPGA Select I/O ?? # # For now I will connect these LED circuits for Bank 67 # a 1V8 HP Bank on the ultrascale FPGA. # NET 'HUB_FPGA_LED50_DRV' U553-7 U1-BF29 # IO_L22N_T3U_N7_DBC_AD0N_68 NET 'HUB_FPGA_LED51_DRV' U553-8 U1-BF30 # IO_L24P_T3U_N10_68 NET 'HUB_FPGA_LED52_DRV' U553-9 U1-BF31 # IO_L24N_T3U_N11_68 NET 'LED_50_Cath_Res' U553-17 NET 'LED_51_Cath_Res' U553-16 NET 'LED_52_Cath_Res' U553-15 # # There is currently one Un-Used Section in # the U553 Translator/Driver # Ground its input and No_Conn net its output. # NET 'GROUND' U553-10 NET 'No_Conn_U553_Pin_14' U553-14 # # Power Supply and ByPass Capacitor connections to these # Translators and Drivers & Connect their DIR and OE_B pins. # # The setup of the U551 and U553 Translators is the following: # # "A" side has 1.8 Volt Vcc # "B" side had 3.3 Volt Vcc # # The Direction is from "A" to "B" # which requires the DIR pin to be HI. # # Outputs are always Enabled # which requires the OE_B pin to be LOW. # # # Translator U551 VCC_A pin #1 1V8 # Translator U551 VCC_B pins #23, #24 3V3 # NET 'BULK_1V8' U551-1 NET 'BULK_3V3' U551-23 U551-24 NET 'GROUND' U551-11 U551-12 U551-13 NET 'BULK_1V8' C2902-1 NET 'BULK_3V3' C2901-2 NET 'GROUND' C2901-1 C2902-2 # # Translator U551 DIR pin #2 HI "A" --> "B" # Translator U551 OE_B pin #22 LOW Enabled # NET 'BULK_1V8' U551-2 NET 'GROUND' U551-22 # # Open-Drain Hex Buffer U552 is powered from Vcc of 3V3. # NET 'BULK_3V3' U552-14 C2903-1 NET 'GROUND' U552-7 C2903-2 # # Translator U553 VCC_A pin #1 1V8 # Translator U553 VCC_B pins #23, #24 3V3 # NET 'BULK_1V8' U553-1 NET 'BULK_3V3' U553-23 U553-24 NET 'GROUND' U553-11 U553-12 U553-13 NET 'BULK_1V8' C2905-1 NET 'BULK_3V3' C2904-2 NET 'GROUND' C2904-1 C2905-2 # # Translator U553 DIR pin #2 HI "A" --> "B" # Translator U553 OE_B pin #22 LOW Enabled # NET 'BULK_1V8' U553-2 NET 'GROUND' U553-22 # # This is a Hub-Module Key In Net List file # # All Other MGT Nets # ----------------------------------------------- # # # Original Rev. 3-May-2015 # Most Recent Rev. 3-Jan-2017 # # # This file holds all of the sundry MGT nets. # The MGT nets presented here are: # # 1 GTY input for the Other Hub's TCC + Readout Control # Combined Data # # 1 GTH input for This Hub's ROD Readout Control Data # # # 4 GTH>Y inputs from the Receiver MiniPOD (its first 4 channels) # # 8 GTH outputs to the Transmitter MiniPOD # # # 2 GTH outputs to send This Hub's readout data # to the ROD on This Hub # # 2 GTY outputs to send This Hub's readout data # to the Other Hub # # 34 Differential Via Pair connections to the DVP # components around the FPGA that handle the # FEX MGT Receiver Input Data # # # Note that all 80 of the MGT input are connected and most # are used during the normal operation of the Hub Module. # A total of 6 MGT inputs are defined in this nets file. # 74 MGT inputs are defined in other nets files. # # # 12 MGT outputs are defined in this nets file. # # 14 MGT outputs for Combined Data signals are # defined in another nets file. # # Note that there are 54 MGT outputs that are not # connected on the Hub Module. # # # Note the other nets files that describe the MGT # connections to the Hub's FPGA are: # # mgt_fanout_to_hub_fpga_nets in the /Net_Lists/Build_MGT_Readout_Nets/ # # combined_data_distribution_nets # # # # GTY Input of the Other Hub's TTC + Readout Control # Combined Data # # This data from the Other Hub arrives on # Fabric Interface Rx1 Channel 1 # J23 Row 4 G & H # # and goes into GTY Input Rx1 Bank 124 # NET 'Combined_Data_from_OTHER_Hub_Dir' J23-G4 U1-AP44 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Rx1 Bank 124 NET 'Combined_Data_from_OTHER_Hub_Cmp' J23-H4 U1-AP43 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- # # MGT Input of This Hub's ROD Readout Control Data # # This data from This Hub's ROD arrives on # MegArray Connector 2, RRC pins, H39 & J39 # # and goes into GTH Input Rx3 Bank 224 # # The ROD does provide the DC Blocking Caps for this link. # NET 'This_RODs_Readout_Ctrl_to_GTH_Input_Dir' Meg_S2-H39 U1-AM3 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx3 Bank 224 NET 'This_RODs_Readout_Ctrl_to_GTH_Input_Cmp' Meg_S2-J39 U1-AM4 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- # # MGT Inputs from the Receiver MiniPOD for 4 fibers # # This optical data arrives to Receiver MiniPOD 2 # on Fibers: 2, 4, 6, 8 # # and goes into GTH Input Rx0 Rx1 Rx2 of Bank 224 # and GTY Input Rx0 of Bank 124 # # DC Blocking Caps are required: C2301 through C2308 # # Note that 3 of these 4 circuits include Differential Pair # Via components at the breakout from the FPGA. # These are DPV101, DPV135, and DPV136. # # Note that all 4 circuit include a Differential Pair Via # component at the connection to the MiniPOD adjacent # to the DC Blocking Capacitors. These are DPVs 137:140. # NET 'Rec_MP_Fiber_8_Data_Dir' Rec_MP2-A8 C2401-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 8 NET 'Rec_MP_Fiber_8_Data_Cmp' Rec_MP2-B8 C2402-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_8_to_FPGA_Dir' C2401-2 U1-AR45 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Rx0 Bank 124 NET 'Rec_MP_Fiber_8_to_FPGA_Cmp' C2402-2 U1-AR46 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_8_to_FPGA_Dir' DPV101-3 DPV140-2 NET 'Rec_MP_Fiber_8_to_FPGA_Cmp' DPV101-2 DPV140-3 NET 'GROUND' DPV101-1 DPV140-1 NET 'GROUND' DPV141-1 NET 'Rec_MP_Fiber_6_Data_Dir' Rec_MP2-A6 C2404-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 6 NET 'Rec_MP_Fiber_6_Data_Cmp' Rec_MP2-B6 C2403-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_6_to_FPGA_Dir' C2404-2 U1-AR2 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx0 Bank 224 NET 'Rec_MP_Fiber_6_to_FPGA_Cmp' C2403-2 U1-AR1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_6_to_FPGA_Dir' DPV135-3 DPV139-3 NET 'Rec_MP_Fiber_6_to_FPGA_Cmp' DPV135-2 DPV139-2 NET 'GROUND' DPV135-1 DPV139-1 NET 'Rec_MP_Fiber_4_Data_Dir' Rec_MP2-A4 C2405-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 4 NET 'Rec_MP_Fiber_4_Data_Cmp' Rec_MP2-B4 C2406-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_4_to_FPGA_Dir' C2405-2 U1-AP4 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx1 Bank 224 NET 'Rec_MP_Fiber_4_to_FPGA_Cmp' C2406-2 U1-AP3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_4_to_FPGA_Dir' DPV138-3 NET 'Rec_MP_Fiber_4_to_FPGA_Cmp' DPV138-2 NET 'GROUND' DPV138-1 NET 'Rec_MP_Fiber_2_Data_Dir' Rec_MP2-A2 C2407-1 (NET_TYPE, 'DIFF_PAIR_HS') # Rec MiniPOD Fiber 2 NET 'Rec_MP_Fiber_2_Data_Cmp' Rec_MP2-B2 C2408-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_2_to_FPGA_Dir' C2407-2 U1-AN2 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Rx2 Bank 224 NET 'Rec_MP_Fiber_2_to_FPGA_Cmp' C2408-2 U1-AN1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Rec_MP_Fiber_2_to_FPGA_Dir' DPV136-3 DPV137-3 NET 'Rec_MP_Fiber_2_to_FPGA_Cmp' DPV136-2 DPV137-2 NET 'GROUND' DPV136-1 DPV137-1 # # Mgt Outputs to the MiniPOD Transmitter 8 of 12 fibers # # This data is send out from MiniPOD Transmitter on # # Fibers: 0, 1, 2, 4, 6, 8, 10, 11 are currently driven # # Fibers: 3, 5, 7, 9 are not currently driven # # This data comes from MGT Outputs Tx0 & Tx2 # from Banks: 224 225 226 227 # NET 'MiniPOD_Trans_Fiber_0_Data_Dir' Trn_MP1-D1 U1-AA6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 227 NET 'MiniPOD_Trans_Fiber_0_Data_Cmp' Trn_MP1-D2 U1-AA7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_1_Data_Dir' Trn_MP1-F1 U1-AC6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 227 NET 'MiniPOD_Trans_Fiber_1_Data_Cmp' Trn_MP1-F2 U1-AC7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_2_Data_Dir' Trn_MP1-B2 U1-AE6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 226 NET 'MiniPOD_Trans_Fiber_2_Data_Cmp' Trn_MP1-A2 U1-AE7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_4_Data_Dir' Trn_MP1-B4 U1-AG6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 226 NET 'MiniPOD_Trans_Fiber_4_Data_Cmp' Trn_MP1-A4 U1-AG7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_6_Data_Dir' Trn_MP1-B6 U1-AJ6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 225 NET 'MiniPOD_Trans_Fiber_6_Data_Cmp' Trn_MP1-A6 U1-AJ7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_8_Data_Dir' Trn_MP1-B8 U1-AL6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 225 NET 'MiniPOD_Trans_Fiber_8_Data_Cmp' Trn_MP1-A8 U1-AL7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_10_Data_Dir' Trn_MP1-D8 U1-AN6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx2 Bank 224 NET 'MiniPOD_Trans_Fiber_10_Data_Cmp' Trn_MP1-D9 U1-AN7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'MiniPOD_Trans_Fiber_11_Data_Dir' Trn_MP1-F8 U1-AR6 (NET_TYPE, 'DIFF_PAIR_HS') # Tx0 Bank 224 NET 'MiniPOD_Trans_Fiber_11_Data_Cmp' Trn_MP1-F9 U1-AR7 (NET_TYPE, 'DIFF_PAIR_HS') # -- FLIPPED -- NET 'NO_CONN_MiniPOD_Trans_Fiber_3_Data_Dir' Trn_MP1-H2 NET 'NO_CONN_MiniPOD_Trans_Fiber_3_Data_Cmp' Trn_MP1-J2 NET 'NO_CONN_MiniPOD_Trans_Fiber_5_Data_Dir' Trn_MP1-H4 NET 'NO_CONN_MiniPOD_Trans_Fiber_5_Data_Cmp' Trn_MP1-J4 NET 'NO_CONN_MiniPOD_Trans_Fiber_7_Data_Dir' Trn_MP1-H6 NET 'NO_CONN_MiniPOD_Trans_Fiber_7_Data_Cmp' Trn_MP1-J6 NET 'NO_CONN_MiniPOD_Trans_Fiber_9_Data_Dir' Trn_MP1-H8 NET 'NO_CONN_MiniPOD_Trans_Fiber_9_Data_Cmp' Trn_MP1-J8 # # MGT Outputs of the Readout Data from This Hub's FPGA # # There are 2 paths for This Hub's FPGA Readout Data: # # - to the ROD on This Hub # # - to the Other Hub where it goes through # the 2x fanout and then to the Other Hub's ROD # and to the Other Hub's FPGA # # # This Hub's Readout Data comes out of its FPGA from: # # - GTH Transmitter Tx0 of Bank 229 and Tx2 of Bank 228 # from which it goes to the ROD on This Hub # # - GTY Transmitters Tx2 and Tx0 of Bank 127 # from wich it goes to the Other Hub # # # This Hub's Readout Data: # # - Tx0 of Bank 229 is Aurora Lane 0 to MegArray 2 B2,C2 to ROD # - Tx2 of Bank 228 is Aurora Lane 1 to MegArray 2 H6,J6 to ROD # # - Tx2 of Bank 127 is Aurora Lane 0 to Backplane J23 A3,B3 to Other Hub # - Tx0 of Bank 127 is Aurora Lane 1 to Backplane J23 E3,F3 to Other Hub # # # All 4 of these links need DC Blocking Caps. The standard # is to have DC Blocking Caps on the source end of all GTH links. # # # This Hub's Readout to the ROD on This Hub # NET 'This_Hubs_RO_0_to_Cap_Its_ROD_Dir' U1-R7 C2503-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Tx0 Bank 229 NET 'This_Hubs_RO_0_to_Cap_Its_ROD_Cmp' U1-R6 C2504-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Its_ROD_Dir' C2503-2 Meg_S2-B2 (NET_TYPE, 'DIFF_PAIR_HS') # and into This ROD NET 'This_Hubs_RO_0_Cap_to_Its_ROD_Cmp' C2504-2 Meg_S2-C2 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_1_to_Cap_Its_ROD_Dir' U1-U7 C2505-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTH Tx2 Bank 228 NET 'This_Hubs_RO_1_to_Cap_Its_ROD_Cmp' U1-U6 C2506-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 NET 'This_Hubs_RO_1_Cap_to_Its_ROD_Dir' C2505-2 Meg_S2-H6 (NET_TYPE, 'DIFF_PAIR_HS') # and into This ROD NET 'This_Hubs_RO_1_Cap_to_Its_ROD_Cmp' C2506-2 Meg_S2-J6 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 # # This Hub's Readout to the ROD on the Other Hub # # Note that these two connections involve both AC Coupling # Capacitors and Differential Pair Vias on their runs # from the FPGA to the Backplane Connectors. # NET 'This_Hubs_RO_0_to_Cap_Other_ROD_Dir' U1-AA40 C2507-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Tx2 Bank 127 NET 'This_Hubs_RO_0_to_Cap_Other_ROD_Cmp' U1-AA41 C2508-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Dir' C2507-2 J23-A3 (NET_TYPE, 'DIFF_PAIR_HS') # RO to Other Hub NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Cmp' C2508-2 J23-B3 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 0 NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Dir' DPV702-3 # Diff Pair Via NET 'This_Hubs_RO_0_Cap_to_Other_ROD_Cmp' DPV702-2 # in run from caps NET 'GROUND' DPV702-1 # to Backplane NET 'This_Hubs_RO_1_to_Cap_Other_ROD_Dir' U1-AC41 C2509-1 (NET_TYPE, 'DIFF_PAIR_HS') # GTY Tx0 Bank 127 NET 'This_Hubs_RO_1_to_Cap_Other_ROD_Cmp' U1-AC40 C2510-1 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 # -- FLIPPED -- NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Dir' C2509-2 J23-E3 (NET_TYPE, 'DIFF_PAIR_HS') # RO to Other Hub NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Cmp' C2510-2 J23-F3 (NET_TYPE, 'DIFF_PAIR_HS') # Aurora Lane 1 NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Dir' DPV703-2 # Diff Pair Via NET 'This_Hubs_RO_1_Cap_to_Other_ROD_Cmp' DPV703-3 # in run from caps NET 'GROUND' DPV703-1 # to Backplane # # Finally the Differential Via Pairs that are # around the Hub's FPGA. # # These are for FEX Data MGT Receiver Inputs # NET 'MGT_FO_CH_8_OUT_HUB_CMP' DPV102-2 NET 'MGT_FO_CH_8_OUT_HUB_DIR' DPV102-3 NET 'GROUND' DPV102-1 NET 'MGT_FO_CH_6_OUT_HUB_CMP' DPV103-2 NET 'MGT_FO_CH_6_OUT_HUB_DIR' DPV103-3 NET 'GROUND' DPV103-1 NET 'MGT_FO_CH_4_OUT_HUB_CMP' DPV104-2 NET 'MGT_FO_CH_4_OUT_HUB_DIR' DPV104-3 NET 'GROUND' DPV104-1 NET 'MGT_FO_CH_2_OUT_HUB_CMP' DPV105-2 NET 'MGT_FO_CH_2_OUT_HUB_DIR' DPV105-3 NET 'GROUND' DPV105-1 NET 'MGT_FO_CH_16_OUT_HUB_CMP' DPV106-2 NET 'MGT_FO_CH_16_OUT_HUB_DIR' DPV106-3 NET 'GROUND' DPV106-1 NET 'MGT_FO_CH_14_OUT_HUB_CMP' DPV107-2 NET 'MGT_FO_CH_14_OUT_HUB_DIR' DPV107-3 NET 'GROUND' DPV107-1 NET 'MGT_FO_CH_12_OUT_HUB_CMP' DPV108-2 NET 'MGT_FO_CH_12_OUT_HUB_DIR' DPV108-3 NET 'GROUND' DPV108-1 NET 'MGT_FO_CH_10_OUT_HUB_CMP' DPV109-2 NET 'MGT_FO_CH_10_OUT_HUB_DIR' DPV109-3 NET 'GROUND' DPV109-1 NET 'MGT_FO_CH_24_OUT_HUB_CMP' DPV110-2 NET 'MGT_FO_CH_24_OUT_HUB_DIR' DPV110-3 NET 'GROUND' DPV110-1 NET 'MGT_FO_CH_22_OUT_HUB_CMP' DPV111-2 NET 'MGT_FO_CH_22_OUT_HUB_DIR' DPV111-3 NET 'GROUND' DPV111-1 NET 'MGT_FO_CH_20_OUT_HUB_CMP' DPV112-2 NET 'MGT_FO_CH_20_OUT_HUB_DIR' DPV112-3 NET 'GROUND' DPV112-1 NET 'MGT_FO_CH_18_OUT_HUB_CMP' DPV113-2 NET 'MGT_FO_CH_18_OUT_HUB_DIR' DPV113-3 NET 'GROUND' DPV113-1 NET 'MGT_FO_CH_32_OUT_HUB_CMP' DPV114-2 NET 'MGT_FO_CH_32_OUT_HUB_DIR' DPV114-3 NET 'GROUND' DPV114-1 NET 'MGT_FO_CH_30_OUT_HUB_CMP' DPV115-2 NET 'MGT_FO_CH_30_OUT_HUB_DIR' DPV115-3 NET 'GROUND' DPV115-1 NET 'MGT_FO_CH_28_OUT_HUB_CMP' DPV116-2 NET 'MGT_FO_CH_28_OUT_HUB_DIR' DPV116-3 NET 'GROUND' DPV116-1 NET 'MGT_FO_CH_26_OUT_HUB_CMP' DPV117-2 NET 'MGT_FO_CH_26_OUT_HUB_DIR' DPV117-3 NET 'GROUND' DPV117-1 NET 'MGT_FO_CH_65_OUT_HUB_CMP' DPV118-2 NET 'MGT_FO_CH_65_OUT_HUB_DIR' DPV118-3 NET 'GROUND' DPV118-1 NET 'MGT_FO_CH_67_OUT_HUB_CMP' DPV119-2 NET 'MGT_FO_CH_67_OUT_HUB_DIR' DPV119-3 NET 'GROUND' DPV119-1 NET 'MGT_FO_CH_69_OUT_HUB_CMP' DPV120-2 NET 'MGT_FO_CH_69_OUT_HUB_DIR' DPV120-3 NET 'GROUND' DPV120-1 NET 'MGT_FO_CH_71_OUT_HUB_CMP' DPV121-2 NET 'MGT_FO_CH_71_OUT_HUB_DIR' DPV121-3 NET 'GROUND' DPV121-1 NET 'MGT_FO_CH_73_OUT_HUB_CMP' DPV122-2 NET 'MGT_FO_CH_73_OUT_HUB_DIR' DPV122-3 NET 'GROUND' DPV122-1 NET 'MGT_FO_CH_57_OUT_HUB_CMP' DPV123-2 NET 'MGT_FO_CH_57_OUT_HUB_DIR' DPV123-3 NET 'GROUND' DPV123-1 NET 'MGT_FO_CH_59_OUT_HUB_CMP' DPV124-2 NET 'MGT_FO_CH_59_OUT_HUB_DIR' DPV124-3 NET 'GROUND' DPV124-1 NET 'MGT_FO_CH_61_OUT_HUB_CMP' DPV125-2 NET 'MGT_FO_CH_61_OUT_HUB_DIR' DPV125-3 NET 'GROUND' DPV125-1 NET 'MGT_FO_CH_63_OUT_HUB_CMP' DPV126-2 NET 'MGT_FO_CH_63_OUT_HUB_DIR' DPV126-3 NET 'GROUND' DPV126-1 NET 'MGT_FO_CH_49_OUT_HUB_CMP' DPV127-2 NET 'MGT_FO_CH_49_OUT_HUB_DIR' DPV127-3 NET 'GROUND' DPV127-1 NET 'MGT_FO_CH_51_OUT_HUB_CMP' DPV128-2 NET 'MGT_FO_CH_51_OUT_HUB_DIR' DPV128-3 NET 'GROUND' DPV128-1 NET 'MGT_FO_CH_53_OUT_HUB_CMP' DPV129-2 NET 'MGT_FO_CH_53_OUT_HUB_DIR' DPV129-3 NET 'GROUND' DPV129-1 NET 'MGT_FO_CH_55_OUT_HUB_CMP' DPV130-2 NET 'MGT_FO_CH_55_OUT_HUB_DIR' DPV130-3 NET 'GROUND' DPV130-1 NET 'MGT_FO_CH_41_OUT_HUB_CMP' DPV131-2 NET 'MGT_FO_CH_41_OUT_HUB_DIR' DPV131-3 NET 'GROUND' DPV131-1 NET 'MGT_FO_CH_43_OUT_HUB_CMP' DPV132-2 NET 'MGT_FO_CH_43_OUT_HUB_DIR' DPV132-3 NET 'GROUND' DPV132-1 NET 'MGT_FO_CH_48_OUT_HUB_CMP' DPV133-2 NET 'MGT_FO_CH_48_OUT_HUB_DIR' DPV133-3 NET 'GROUND' DPV133-1 NET 'MGT_FO_CH_37_OUT_HUB_CMP' DPV134-2 NET 'MGT_FO_CH_37_OUT_HUB_DIR' DPV134-3 NET 'GROUND' DPV134-1 # # MiniPOD - Power and Ground Nets # ---------------------------------- # # Hub-Module Key In Nets File # # # Original Rev. 26-May-2015 # Current Rev. 29-Sep-2016 # # # # This file holds all of the Power and Ground Nets # for the 2 MiniPOD devices on the Hub Module. # # Recall that the MiniPODs use both 3V3 and 2V5 power. # Both of these supplies must be filtered before they # are used to power the MiniPODs. # # The Hub Module has one Transmitter MiniPOD and one # Receiver MiniPOD. # # Transmitter MiniPOD Trn_MP1 # Receiver MiniPOD Rec_MP2 # # # # Ground Connections to the 2 MiniPod Sockets # # # List the Ground connections to: Trn_MP1 # NET 'GROUND' Trn_MP1-A1 Trn_MP1-A3 Trn_MP1-A5 Trn_MP1-A7 Trn_MP1-A9 NET 'GROUND' Trn_MP1-B1 Trn_MP1-B3 Trn_MP1-B5 Trn_MP1-B7 Trn_MP1-B9 NET 'GROUND' Trn_MP1-C1 Trn_MP1-C2 Trn_MP1-C8 Trn_MP1-C9 NET 'GROUND' Trn_MP1-D3 Trn_MP1-D7 NET 'GROUND' Trn_MP1-E1 Trn_MP1-E2 Trn_MP1-E8 Trn_MP1-E9 NET 'GROUND' Trn_MP1-F3 Trn_MP1-F7 NET 'GROUND' Trn_MP1-G1 Trn_MP1-G2 Trn_MP1-G8 Trn_MP1-G9 NET 'GROUND' Trn_MP1-H1 Trn_MP1-H3 Trn_MP1-H5 Trn_MP1-H7 Trn_MP1-H9 NET 'GROUND' Trn_MP1-J1 Trn_MP1-J3 Trn_MP1-J5 Trn_MP1-J7 Trn_MP1-J9 # # List the Ground connections to: Rec_MP2 # NET 'GROUND' Rec_MP2-A1 Rec_MP2-A3 Rec_MP2-A5 Rec_MP2-A7 Rec_MP2-A9 NET 'GROUND' Rec_MP2-B1 Rec_MP2-B3 Rec_MP2-B5 Rec_MP2-B7 Rec_MP2-B9 NET 'GROUND' Rec_MP2-C1 Rec_MP2-C2 Rec_MP2-C8 Rec_MP2-C9 NET 'GROUND' Rec_MP2-D3 Rec_MP2-D7 NET 'GROUND' Rec_MP2-E1 Rec_MP2-E2 Rec_MP2-E8 Rec_MP2-E9 NET 'GROUND' Rec_MP2-F3 Rec_MP2-F7 NET 'GROUND' Rec_MP2-G1 Rec_MP2-G2 Rec_MP2-G8 Rec_MP2-G9 NET 'GROUND' Rec_MP2-H1 Rec_MP2-H3 Rec_MP2-H5 Rec_MP2-H7 Rec_MP2-H9 NET 'GROUND' Rec_MP2-J1 Rec_MP2-J3 Rec_MP2-J5 Rec_MP2-J7 Rec_MP2-J9 # # Power Connections to the 2 MiniPod Sockets # # Power Connections to: Trn_MP1 # --------- # # List the 2.5 Volt power connections to Trn_MP1 NET 'BULK_2V5' L2411-1 C2411-1 C2412-2 C2413-1 NET 'GROUND' C2411-2 C2412-1 C2413-2 NET 'MP1_2V5' L2411-2 C2414-2 C2415-1 C2416-1 NET 'GROUND' C2414-1 C2415-2 R2411-1 NET 'MP1_2V5_FLT_RES' C2416-2 R2411-2 NET 'MP1_2V5' Trn_MP1-F4 Trn_MP1-G4 Trn_MP1-G5 Trn_MP1-G6 # # List the 3.3 Volt power connections to Trn_MP1 NET 'BULK_3V3' L2421-1 C2421-1 C2422-2 C2423-1 NET 'GROUND' C2421-2 C2422-1 C2423-2 NET 'MP1_3V3' L2421-2 C2424-2 C2425-1 C2426-1 NET 'GROUND' C2424-1 C2425-2 R2421-1 NET 'MP1_3V3_FLT_RES' C2426-2 R2421-2 NET 'MP1_3V3' Trn_MP1-C4 Trn_MP1-C5 Trn_MP1-C6 # Power Connections to: Rec_MP2 # ------- # # List the 2.5 Volt power connections to Rec_MP2 NET 'BULK_2V5' L2431-1 C2431-1 C2432-2 C2433-1 NET 'GROUND' C2431-2 C2432-1 C2433-2 NET 'MP2_2V5' L2431-2 C2434-2 C2435-1 C2436-1 NET 'GROUND' C2434-1 C2435-2 R2431-1 NET 'MP2_2V5_FLT_RES' C2436-2 R2431-2 NET 'MP2_2V5' Rec_MP2-F4 Rec_MP2-G4 Rec_MP2-G5 Rec_MP2-G6 # # List the 3.3 Volt power connections to Rec_MP2 NET 'BULK_3V3' L2441-1 C2441-1 C2442-2 C2443-1 NET 'GROUND' C2441-2 C2442-1 C2443-2 NET 'MP2_3V3' L2441-2 C2444-2 C2445-1 C2446-1 NET 'GROUND' C2444-1 C2445-2 R2441-1 NET 'MP2_3V3_FLT_RES' C2446-2 R2441-2 NET 'MP2_3V3' Rec_MP2-C4 Rec_MP2-C5 Rec_MP2-C6 # # Control Connections to the 2 MiniPod Sockets # to/from the Hub's UltraScale FPGA 3V3 I/O Bank # and the MiniPOD serial bus address control pins. # # # Control Connections to: Trn_MP1 # --------- NET 'Trans_MiniPOD_SDA' Trn_MP1-D4 U1-AP15 # IO_L23N_T3U_N9_84 NET 'Trans_MiniPOD_SDA' R2425-1 NET 'Trans_MiniPOD_SCL' Trn_MP1-E6 U1-AN15 # IO_L23P_T3U_N8_84 NET 'Trans_MiniPOD_SCL' R2426-1 NET 'Trans_MiniPOD_INTR_B' Trn_MP1-D6 U1-AN16 # IO_L21P_T3L_N4_AD8P_84 NET 'Trans_MiniPOD_INTR_B' R2427-1 NET 'Trans_MiniPOD_RESET_B' Trn_MP1-E4 U1-AP13 # IO_L18P_T2U_N10_AD2P_84 NET 'Trans_MiniPOD_RESET_B' R2428-1 # Connect the 4 Pull-Up resistors to Bulk_3V3 NET 'BULK_3V3' R2425-2 R2426-2 R2427-2 R2428-2 # Ground all of the Trans MiniPOD Serial Bus Address pins NET 'GROUND' Trn_MP1-C3 NET 'GROUND' Trn_MP1-E3 NET 'GROUND' Trn_MP1-G3 # # Control Connections to: Recvr_MP2 # --------- NET 'Recvr_MiniPOD_SDA' Rec_MP2-D4 U1-AR13 # IO_L18N_T2U_N11_AD2N_84 NET 'Recvr_MiniPOD_SDA' R2445-1 NET 'Recvr_MiniPOD_SCL' Rec_MP2-E6 U1-AR12 # IO_L15P_T2L_N4_AD11P_84 NET 'Recvr_MiniPOD_SCL' R2446-1 NET 'Recvr_MiniPOD_INTR_B' Rec_MP2-D6 U1-AR15 # IO_L16P_T2U_N6_QBC_AD3P_84 NET 'Recvr_MiniPOD_INTR_B' R2447-1 NET 'Recvr_MiniPOD_RESET_B' Rec_MP2-E4 U1-AR14 # IO_L16N_T2U_N7_QBC_AD3N_84 NET 'Recvr_MiniPOD_RESET_B' R2448-1 # Connect the 4 Pull-Up resistors to Bulk_3V3 NET 'BULK_3V3' R2445-2 R2446-2 R2447-2 R2448-2 # Ground all of the Recvr MiniPOD Serial Bus Address pins NET 'GROUND' Rec_MP2-C3 NET 'GROUND' Rec_MP2-E3 NET 'GROUND' Rec_MP2-G3 # # Finally Ground the Mounting Screw "pins" # on all 2 MiniPOD components. Recall that # the mounting screws are terminal pins on # the MiniPOD component. NET 'GROUND' Trn_MP1-SCRW1 Trn_MP1-SCRW2 NET 'GROUND' Rec_MP2-SCRW1 Rec_MP2-SCRW2 # # Include in this file the Un-Used # Receiver MiniPOD Output Pins # 8 of the 12 Receiver MiniPOD Channels are Un-Used. # # Only Receivers: 2, 4, 6, 8 are used # NET 'No_Conn_MP2_D0_Dir_D1' Rec_MP2-D1 NET 'No_Conn_MP2_D0_Cmp_D2' Rec_MP2-D2 NET 'No_Conn_MP2_D1_Dir_F1' Rec_MP2-F1 NET 'No_Conn_MP2_D1_Cmp_F2' Rec_MP2-F2 NET 'No_Conn_MP2_D3_Dir_J2' Rec_MP2-J2 NET 'No_Conn_MP2_D3_Cmp_H2' Rec_MP2-H2 NET 'No_Conn_MP2_D5_Dir_J4' Rec_MP2-J4 NET 'No_Conn_MP2_D5_Cmp_H4' Rec_MP2-H4 NET 'No_Conn_MP2_D7_Dir_J6' Rec_MP2-J6 NET 'No_Conn_MP2_D7_Cmp_H6' Rec_MP2-H6 NET 'No_Conn_MP2_D9_Dir_J8' Rec_MP2-J8 NET 'No_Conn_MP2_D9_Cmp_H8' Rec_MP2-H8 NET 'No_Conn_MP2_D10_Dir_D9' Rec_MP2-D9 NET 'No_Conn_MP2_D10_Cmp_D8' Rec_MP2-D8 NET 'No_Conn_MP2_D11_Dir_F9' Rec_MP2-F9 NET 'No_Conn_MP2_D11_Cmp_F8' Rec_MP2-F8 # # Also include in this file the Do Not Connect # pins on the two MiniPOD Components. # NET 'No_Conn_MP1_NC_C7' Trn_MP1-C7 NET 'No_Conn_MP1_NC_D5' Trn_MP1-D5 NET 'No_Conn_MP1_NC_E5' Trn_MP1-E5 NET 'No_Conn_MP1_NC_E7' Trn_MP1-E7 NET 'No_Conn_MP1_NC_F5' Trn_MP1-F5 NET 'No_Conn_MP1_NC_F6' Trn_MP1-F6 NET 'No_Conn_MP1_NC_G7' Trn_MP1-G7 NET 'No_Conn_MP2_NC_C7' Rec_MP2-C7 NET 'No_Conn_MP2_NC_D5' Rec_MP2-D5 NET 'No_Conn_MP2_NC_E5' Rec_MP2-E5 NET 'No_Conn_MP2_NC_E7' Rec_MP2-E7 NET 'No_Conn_MP2_NC_F5' Rec_MP2-F5 NET 'No_Conn_MP2_NC_F6' Rec_MP2-F6 NET 'No_Conn_MP2_NC_G7' Rec_MP2-G7 # # FPGA Power and Ground Nets # ----------------------------- # # Original Rev. 27-Mar-2015 # Current Rev. 23-Apr-2016 # # # This file holds all of the Power and Ground connections # to the Hub's XCVU125-FLVC2104 FPGA. # # The Power and Ground connections held in this nets file # are the following: # # Ground 765 pins Ground # # VCCINT 105 pins Feed from the FPGA_CORE supply # # VCCINT_IO 9 pins Feed from the FPGA_CORE supply # # VCCBRAM 8 pins Feed from the FPGA_CORE supply # # # VCCAUX 11 pins Feed from the BULK_1V8 supply. # # VCCAUX_IO 13 pins Feed from the BULK_1V8 supply. # # # VCCO 56 pins Banks: 0, 65, 66, 67, 68, 70, 71, 72 BULK_1V8 supply. # # Banks: 84, 94 BULK_3V3 supply. # # # MGT_AVCC 46 pins Feed from the MGT_AVCC supply. # # MGT_AVTT 90 pins Feed from the MGT_AVTT supply. # # MGT_AVAUX 12 pins Feed from the MGT_AVAUX supply. # # # Total of 1115 pins connected to U1 in this file. # # # FPGA U1 Ground net 765 Ground pins # NET 'GROUND' U1-A3 NET 'GROUND' U1-A5 NET 'GROUND' U1-A12 NET 'GROUND' U1-A13 NET 'GROUND' U1-A14 NET 'GROUND' U1-A17 NET 'GROUND' U1-A22 NET 'GROUND' U1-A30 NET 'GROUND' U1-A33 NET 'GROUND' U1-A34 NET 'GROUND' U1-A35 NET 'GROUND' U1-A42 NET 'GROUND' U1-A44 NET 'GROUND' U1-B2 NET 'GROUND' U1-B5 NET 'GROUND' U1-B6 NET 'GROUND' U1-B10 NET 'GROUND' U1-B12 NET 'GROUND' U1-B15 NET 'GROUND' U1-B16 NET 'GROUND' U1-B17 NET 'GROUND' U1-B19 NET 'GROUND' U1-B29 NET 'GROUND' U1-B30 NET 'GROUND' U1-B31 NET 'GROUND' U1-B32 NET 'GROUND' U1-B35 NET 'GROUND' U1-B37 NET 'GROUND' U1-B41 NET 'GROUND' U1-B42 NET 'GROUND' U1-B45 NET 'GROUND' U1-C3 NET 'GROUND' U1-C4 NET 'GROUND' U1-C5 NET 'GROUND' U1-C8 NET 'GROUND' U1-C12 NET 'GROUND' U1-C13 NET 'GROUND' U1-C14 NET 'GROUND' U1-C17 NET 'GROUND' U1-C26 NET 'GROUND' U1-C30 NET 'GROUND' U1-C33 NET 'GROUND' U1-C34 NET 'GROUND' U1-C35 NET 'GROUND' U1-C39 NET 'GROUND' U1-C42 NET 'GROUND' U1-C43 NET 'GROUND' U1-C44 NET 'GROUND' U1-D1 NET 'GROUND' U1-D2 NET 'GROUND' U1-D5 NET 'GROUND' U1-D11 NET 'GROUND' U1-D12 NET 'GROUND' U1-D15 NET 'GROUND' U1-D16 NET 'GROUND' U1-D17 NET 'GROUND' U1-D23 NET 'GROUND' U1-D30 NET 'GROUND' U1-D31 NET 'GROUND' U1-D32 NET 'GROUND' U1-D35 NET 'GROUND' U1-D36 NET 'GROUND' U1-D42 NET 'GROUND' U1-D45 NET 'GROUND' U1-D46 NET 'GROUND' U1-E3 NET 'GROUND' U1-E4 NET 'GROUND' U1-E5 NET 'GROUND' U1-E9 NET 'GROUND' U1-E12 NET 'GROUND' U1-E13 NET 'GROUND' U1-E14 NET 'GROUND' U1-E17 NET 'GROUND' U1-E20 NET 'GROUND' U1-E30 NET 'GROUND' U1-E33 NET 'GROUND' U1-E34 NET 'GROUND' U1-E35 NET 'GROUND' U1-E38 NET 'GROUND' U1-E42 NET 'GROUND' U1-E43 NET 'GROUND' U1-E44 NET 'GROUND' U1-F1 NET 'GROUND' U1-F2 NET 'GROUND' U1-F5 NET 'GROUND' U1-F6 NET 'GROUND' U1-F10 NET 'GROUND' U1-F14 NET 'GROUND' U1-F15 NET 'GROUND' U1-F16 NET 'GROUND' U1-F17 NET 'GROUND' U1-F27 NET 'GROUND' U1-F30 NET 'GROUND' U1-F31 NET 'GROUND' U1-F32 NET 'GROUND' U1-F33 NET 'GROUND' U1-F37 NET 'GROUND' U1-F41 NET 'GROUND' U1-F42 NET 'GROUND' U1-F45 NET 'GROUND' U1-F46 NET 'GROUND' U1-G3 NET 'GROUND' U1-G4 NET 'GROUND' U1-G5 NET 'GROUND' U1-G8 NET 'GROUND' U1-G12 NET 'GROUND' U1-G14 NET 'GROUND' U1-G17 NET 'GROUND' U1-G24 NET 'GROUND' U1-G30 NET 'GROUND' U1-G33 NET 'GROUND' U1-G35 NET 'GROUND' U1-G39 NET 'GROUND' U1-G42 NET 'GROUND' U1-G43 NET 'GROUND' U1-G44 NET 'GROUND' U1-H1 NET 'GROUND' U1-H2 NET 'GROUND' U1-H5 NET 'GROUND' U1-H7 NET 'GROUND' U1-H11 NET 'GROUND' U1-H14 NET 'GROUND' U1-H15 NET 'GROUND' U1-H16 NET 'GROUND' U1-H17 NET 'GROUND' U1-H21 NET 'GROUND' U1-H30 NET 'GROUND' U1-H31 NET 'GROUND' U1-H32 NET 'GROUND' U1-H33 NET 'GROUND' U1-H36 NET 'GROUND' U1-H40 NET 'GROUND' U1-H42 NET 'GROUND' U1-H45 NET 'GROUND' U1-H46 NET 'GROUND' U1-J3 NET 'GROUND' U1-J4 NET 'GROUND' U1-J5 NET 'GROUND' U1-J9 NET 'GROUND' U1-J13 NET 'GROUND' U1-J14 NET 'GROUND' U1-J18 NET 'GROUND' U1-J28 NET 'GROUND' U1-J33 NET 'GROUND' U1-J34 NET 'GROUND' U1-J38 NET 'GROUND' U1-J42 NET 'GROUND' U1-J43 NET 'GROUND' U1-J44 NET 'GROUND' U1-K1 NET 'GROUND' U1-K2 NET 'GROUND' U1-K5 NET 'GROUND' U1-K6 NET 'GROUND' U1-K10 NET 'GROUND' U1-K15 NET 'GROUND' U1-K25 NET 'GROUND' U1-K33 NET 'GROUND' U1-K37 NET 'GROUND' U1-K41 NET 'GROUND' U1-K42 NET 'GROUND' U1-K45 NET 'GROUND' U1-K46 NET 'GROUND' U1-L3 NET 'GROUND' U1-L4 NET 'GROUND' U1-L5 NET 'GROUND' U1-L8 NET 'GROUND' U1-L12 NET 'GROUND' U1-L14 NET 'GROUND' U1-L22 NET 'GROUND' U1-L32 NET 'GROUND' U1-L33 NET 'GROUND' U1-L35 NET 'GROUND' U1-L39 NET 'GROUND' U1-L42 NET 'GROUND' U1-L43 NET 'GROUND' U1-L44 NET 'GROUND' U1-M1 NET 'GROUND' U1-M2 NET 'GROUND' U1-M5 NET 'GROUND' U1-M7 NET 'GROUND' U1-M11 NET 'GROUND' U1-M19 NET 'GROUND' U1-M29 NET 'GROUND' U1-M33 NET 'GROUND' U1-M36 NET 'GROUND' U1-M40 NET 'GROUND' U1-M42 NET 'GROUND' U1-M45 NET 'GROUND' U1-M46 NET 'GROUND' U1-N3 NET 'GROUND' U1-N4 NET 'GROUND' U1-N5 NET 'GROUND' U1-N9 NET 'GROUND' U1-N13 NET 'GROUND' U1-N14 NET 'GROUND' U1-N16 NET 'GROUND' U1-N26 NET 'GROUND' U1-N33 NET 'GROUND' U1-N34 NET 'GROUND' U1-N38 NET 'GROUND' U1-N42 NET 'GROUND' U1-N43 NET 'GROUND' U1-N44 NET 'GROUND' U1-P1 NET 'GROUND' U1-P2 NET 'GROUND' U1-P5 NET 'GROUND' U1-P6 NET 'GROUND' U1-P10 NET 'GROUND' U1-P23 NET 'GROUND' U1-P29 NET 'GROUND' U1-P31 NET 'GROUND' U1-P33 NET 'GROUND' U1-P37 NET 'GROUND' U1-P41 NET 'GROUND' U1-P42 NET 'GROUND' U1-P45 NET 'GROUND' U1-P46 NET 'GROUND' U1-R3 NET 'GROUND' U1-R4 NET 'GROUND' U1-R5 NET 'GROUND' U1-R8 NET 'GROUND' U1-R12 NET 'GROUND' U1-R14 NET 'GROUND' U1-R16 NET 'GROUND' U1-R18 NET 'GROUND' U1-R20 NET 'GROUND' U1-R22 NET 'GROUND' U1-R24 NET 'GROUND' U1-R26 NET 'GROUND' U1-R28 NET 'GROUND' U1-R30 NET 'GROUND' U1-R32 NET 'GROUND' U1-R33 NET 'GROUND' U1-R35 NET 'GROUND' U1-R39 NET 'GROUND' U1-R42 NET 'GROUND' U1-R43 NET 'GROUND' U1-R44 NET 'GROUND' U1-T1 NET 'GROUND' U1-T2 NET 'GROUND' U1-T5 NET 'GROUND' U1-T7 NET 'GROUND' U1-T11 NET 'GROUND' U1-T15 NET 'GROUND' U1-T17 NET 'GROUND' U1-T19 NET 'GROUND' U1-T21 NET 'GROUND' U1-T23 NET 'GROUND' U1-T25 NET 'GROUND' U1-T27 NET 'GROUND' U1-T29 NET 'GROUND' U1-T31 NET 'GROUND' U1-T33 NET 'GROUND' U1-T36 NET 'GROUND' U1-T40 NET 'GROUND' U1-T42 NET 'GROUND' U1-T45 NET 'GROUND' U1-T46 NET 'GROUND' U1-U3 NET 'GROUND' U1-U4 NET 'GROUND' U1-U5 NET 'GROUND' U1-U9 NET 'GROUND' U1-U13 NET 'GROUND' U1-U14 NET 'GROUND' U1-U16 NET 'GROUND' U1-U18 NET 'GROUND' U1-U20 NET 'GROUND' U1-U22 NET 'GROUND' U1-U24 NET 'GROUND' U1-U26 NET 'GROUND' U1-U28 NET 'GROUND' U1-U30 NET 'GROUND' U1-U32 NET 'GROUND' U1-U33 NET 'GROUND' U1-U34 NET 'GROUND' U1-U38 NET 'GROUND' U1-U42 NET 'GROUND' U1-U43 NET 'GROUND' U1-U44 NET 'GROUND' U1-V1 NET 'GROUND' U1-V2 NET 'GROUND' U1-V5 NET 'GROUND' U1-V6 NET 'GROUND' U1-V10 NET 'GROUND' U1-V15 NET 'GROUND' U1-V17 NET 'GROUND' U1-V19 NET 'GROUND' U1-V21 NET 'GROUND' U1-V23 NET 'GROUND' U1-V25 NET 'GROUND' U1-V27 NET 'GROUND' U1-V29 NET 'GROUND' U1-V31 NET 'GROUND' U1-V33 NET 'GROUND' U1-V37 NET 'GROUND' U1-V41 NET 'GROUND' U1-V42 NET 'GROUND' U1-V45 NET 'GROUND' U1-V46 NET 'GROUND' U1-W3 NET 'GROUND' U1-W4 NET 'GROUND' U1-W5 NET 'GROUND' U1-W8 NET 'GROUND' U1-W12 NET 'GROUND' U1-W14 NET 'GROUND' U1-W16 NET 'GROUND' U1-W18 NET 'GROUND' U1-W20 NET 'GROUND' U1-W22 NET 'GROUND' U1-W24 NET 'GROUND' U1-W26 NET 'GROUND' U1-W28 NET 'GROUND' U1-W30 NET 'GROUND' U1-W32 NET 'GROUND' U1-W33 NET 'GROUND' U1-W35 NET 'GROUND' U1-W39 NET 'GROUND' U1-W42 NET 'GROUND' U1-W43 NET 'GROUND' U1-W44 NET 'GROUND' U1-Y1 NET 'GROUND' U1-Y2 NET 'GROUND' U1-Y5 NET 'GROUND' U1-Y7 NET 'GROUND' U1-Y11 NET 'GROUND' U1-Y15 NET 'GROUND' U1-Y17 NET 'GROUND' U1-Y19 NET 'GROUND' U1-Y21 NET 'GROUND' U1-Y23 NET 'GROUND' U1-Y25 NET 'GROUND' U1-Y27 NET 'GROUND' U1-Y29 NET 'GROUND' U1-Y31 NET 'GROUND' U1-Y33 NET 'GROUND' U1-Y36 NET 'GROUND' U1-Y40 NET 'GROUND' U1-Y42 NET 'GROUND' U1-Y45 NET 'GROUND' U1-Y46 NET 'GROUND' U1-AA3 NET 'GROUND' U1-AA4 NET 'GROUND' U1-AA5 NET 'GROUND' U1-AA9 NET 'GROUND' U1-AA13 NET 'GROUND' U1-AA14 NET 'GROUND' U1-AA15 NET 'GROUND' U1-AA16 NET 'GROUND' U1-AA18 NET 'GROUND' U1-AA20 NET 'GROUND' U1-AA22 NET 'GROUND' U1-AA24 NET 'GROUND' U1-AA26 NET 'GROUND' U1-AA28 NET 'GROUND' U1-AA30 NET 'GROUND' U1-AA32 NET 'GROUND' U1-AA33 NET 'GROUND' U1-AA34 NET 'GROUND' U1-AA38 NET 'GROUND' U1-AA42 NET 'GROUND' U1-AA43 NET 'GROUND' U1-AA44 NET 'GROUND' U1-AB1 NET 'GROUND' U1-AB2 NET 'GROUND' U1-AB5 NET 'GROUND' U1-AB6 NET 'GROUND' U1-AB10 NET 'GROUND' U1-AB17 NET 'GROUND' U1-AB21 NET 'GROUND' U1-AB23 NET 'GROUND' U1-AB25 NET 'GROUND' U1-AB27 NET 'GROUND' U1-AB29 NET 'GROUND' U1-AB31 NET 'GROUND' U1-AB33 NET 'GROUND' U1-AB37 NET 'GROUND' U1-AB41 NET 'GROUND' U1-AB42 NET 'GROUND' U1-AB45 NET 'GROUND' U1-AB46 NET 'GROUND' U1-AC3 NET 'GROUND' U1-AC4 NET 'GROUND' U1-AC5 NET 'GROUND' U1-AC8 NET 'GROUND' U1-AC12 NET 'GROUND' U1-AC16 NET 'GROUND' U1-AC18 NET 'GROUND' U1-AC22 NET 'GROUND' U1-AC24 NET 'GROUND' U1-AC26 NET 'GROUND' U1-AC28 NET 'GROUND' U1-AC30 NET 'GROUND' U1-AC32 NET 'GROUND' U1-AC33 NET 'GROUND' U1-AC35 NET 'GROUND' U1-AC39 NET 'GROUND' U1-AC42 NET 'GROUND' U1-AC43 NET 'GROUND' U1-AC44 NET 'GROUND' U1-AD1 NET 'GROUND' U1-AD2 NET 'GROUND' U1-AD5 NET 'GROUND' U1-AD7 NET 'GROUND' U1-AD11 NET 'GROUND' U1-AD14 NET 'GROUND' U1-AD17 NET 'GROUND' U1-AD21 NET 'GROUND' U1-AD23 NET 'GROUND' U1-AD25 NET 'GROUND' U1-AD27 NET 'GROUND' U1-AD29 NET 'GROUND' U1-AD31 NET 'GROUND' U1-AD33 NET 'GROUND' U1-AD36 NET 'GROUND' U1-AD40 NET 'GROUND' U1-AD42 NET 'GROUND' U1-AD45 NET 'GROUND' U1-AD46 NET 'GROUND' U1-AE3 NET 'GROUND' U1-AE4 NET 'GROUND' U1-AE5 NET 'GROUND' U1-AE9 NET 'GROUND' U1-AE13 NET 'GROUND' U1-AE16 NET 'GROUND' U1-AE18 NET 'GROUND' U1-AE22 NET 'GROUND' U1-AE24 NET 'GROUND' U1-AE26 NET 'GROUND' U1-AE28 NET 'GROUND' U1-AE30 NET 'GROUND' U1-AE32 NET 'GROUND' U1-AE33 NET 'GROUND' U1-AE34 NET 'GROUND' U1-AE38 NET 'GROUND' U1-AE42 NET 'GROUND' U1-AE43 NET 'GROUND' U1-AE44 NET 'GROUND' U1-AF1 NET 'GROUND' U1-AF2 NET 'GROUND' U1-AF5 NET 'GROUND' U1-AF6 NET 'GROUND' U1-AF10 NET 'GROUND' U1-AF17 NET 'GROUND' U1-AF19 NET 'GROUND' U1-AF21 NET 'GROUND' U1-AF23 NET 'GROUND' U1-AF25 NET 'GROUND' U1-AF27 NET 'GROUND' U1-AF29 NET 'GROUND' U1-AF31 NET 'GROUND' U1-AF33 NET 'GROUND' U1-AF37 NET 'GROUND' U1-AF41 NET 'GROUND' U1-AF42 NET 'GROUND' U1-AF45 NET 'GROUND' U1-AF46 NET 'GROUND' U1-AG3 NET 'GROUND' U1-AG4 NET 'GROUND' U1-AG5 NET 'GROUND' U1-AG8 NET 'GROUND' U1-AG12 NET 'GROUND' U1-AG14 NET 'GROUND' U1-AG15 NET 'GROUND' U1-AG16 NET 'GROUND' U1-AG18 NET 'GROUND' U1-AG20 NET 'GROUND' U1-AG22 NET 'GROUND' U1-AG24 NET 'GROUND' U1-AG26 NET 'GROUND' U1-AG28 NET 'GROUND' U1-AG30 NET 'GROUND' U1-AG32 NET 'GROUND' U1-AG33 NET 'GROUND' U1-AG35 NET 'GROUND' U1-AG39 NET 'GROUND' U1-AG42 NET 'GROUND' U1-AG43 NET 'GROUND' U1-AG44 NET 'GROUND' U1-AH1 NET 'GROUND' U1-AH2 NET 'GROUND' U1-AH5 NET 'GROUND' U1-AH11 NET 'GROUND' U1-AH15 NET 'GROUND' U1-AH17 NET 'GROUND' U1-AH19 NET 'GROUND' U1-AH21 NET 'GROUND' U1-AH23 NET 'GROUND' U1-AH25 NET 'GROUND' U1-AH27 NET 'GROUND' U1-AH29 NET 'GROUND' U1-AH31 NET 'GROUND' U1-AH33 NET 'GROUND' U1-AH36 NET 'GROUND' U1-AH42 NET 'GROUND' U1-AH45 NET 'GROUND' U1-AH46 NET 'GROUND' U1-AJ3 NET 'GROUND' U1-AJ4 NET 'GROUND' U1-AJ5 NET 'GROUND' U1-AJ9 NET 'GROUND' U1-AJ13 NET 'GROUND' U1-AJ14 NET 'GROUND' U1-AJ16 NET 'GROUND' U1-AJ18 NET 'GROUND' U1-AJ20 NET 'GROUND' U1-AJ22 NET 'GROUND' U1-AJ24 NET 'GROUND' U1-AJ26 NET 'GROUND' U1-AJ28 NET 'GROUND' U1-AJ30 NET 'GROUND' U1-AJ32 NET 'GROUND' U1-AJ33 NET 'GROUND' U1-AJ34 NET 'GROUND' U1-AJ38 NET 'GROUND' U1-AJ42 NET 'GROUND' U1-AJ43 NET 'GROUND' U1-AJ44 NET 'GROUND' U1-AK1 NET 'GROUND' U1-AK2 NET 'GROUND' U1-AK5 NET 'GROUND' U1-AK6 NET 'GROUND' U1-AK10 NET 'GROUND' U1-AK15 NET 'GROUND' U1-AK17 NET 'GROUND' U1-AK19 NET 'GROUND' U1-AK21 NET 'GROUND' U1-AK23 NET 'GROUND' U1-AK25 NET 'GROUND' U1-AK27 NET 'GROUND' U1-AK29 NET 'GROUND' U1-AK31 NET 'GROUND' U1-AK33 NET 'GROUND' U1-AK37 NET 'GROUND' U1-AK41 NET 'GROUND' U1-AK42 NET 'GROUND' U1-AK45 NET 'GROUND' U1-AK46 NET 'GROUND' U1-AL3 NET 'GROUND' U1-AL4 NET 'GROUND' U1-AL5 NET 'GROUND' U1-AL8 NET 'GROUND' U1-AL12 NET 'GROUND' U1-AL14 NET 'GROUND' U1-AL16 NET 'GROUND' U1-AL18 NET 'GROUND' U1-AL20 NET 'GROUND' U1-AL22 NET 'GROUND' U1-AL24 NET 'GROUND' U1-AL26 NET 'GROUND' U1-AL28 NET 'GROUND' U1-AL30 NET 'GROUND' U1-AL32 NET 'GROUND' U1-AL33 NET 'GROUND' U1-AL35 NET 'GROUND' U1-AL39 NET 'GROUND' U1-AL42 NET 'GROUND' U1-AL43 NET 'GROUND' U1-AL44 NET 'GROUND' U1-AM1 NET 'GROUND' U1-AM2 NET 'GROUND' U1-AM5 NET 'GROUND' U1-AM7 NET 'GROUND' U1-AM11 NET 'GROUND' U1-AM15 NET 'GROUND' U1-AM25 NET 'GROUND' U1-AM33 NET 'GROUND' U1-AM36 NET 'GROUND' U1-AM40 NET 'GROUND' U1-AM42 NET 'GROUND' U1-AM45 NET 'GROUND' U1-AM46 NET 'GROUND' U1-AN3 NET 'GROUND' U1-AN4 NET 'GROUND' U1-AN5 NET 'GROUND' U1-AN9 NET 'GROUND' U1-AN12 NET 'GROUND' U1-AN14 NET 'GROUND' U1-AN22 NET 'GROUND' U1-AN33 NET 'GROUND' U1-AN34 NET 'GROUND' U1-AN35 NET 'GROUND' U1-AN38 NET 'GROUND' U1-AN42 NET 'GROUND' U1-AN43 NET 'GROUND' U1-AN44 NET 'GROUND' U1-AP1 NET 'GROUND' U1-AP2 NET 'GROUND' U1-AP5 NET 'GROUND' U1-AP6 NET 'GROUND' U1-AP10 NET 'GROUND' U1-AP11 NET 'GROUND' U1-AP12 NET 'GROUND' U1-AP19 NET 'GROUND' U1-AP29 NET 'GROUND' U1-AP35 NET 'GROUND' U1-AP36 NET 'GROUND' U1-AP37 NET 'GROUND' U1-AP41 NET 'GROUND' U1-AP42 NET 'GROUND' U1-AP45 NET 'GROUND' U1-AP46 NET 'GROUND' U1-AR3 NET 'GROUND' U1-AR4 NET 'GROUND' U1-AR5 NET 'GROUND' U1-AR8 NET 'GROUND' U1-AR10 NET 'GROUND' U1-AR16 NET 'GROUND' U1-AR26 NET 'GROUND' U1-AR37 NET 'GROUND' U1-AR39 NET 'GROUND' U1-AR42 NET 'GROUND' U1-AR43 NET 'GROUND' U1-AR44 NET 'GROUND' U1-AT1 NET 'GROUND' U1-AT2 NET 'GROUND' U1-AT5 NET 'GROUND' U1-AT7 NET 'GROUND' U1-AT10 NET 'GROUND' U1-AT13 NET 'GROUND' U1-AT23 NET 'GROUND' U1-AT33 NET 'GROUND' U1-AT37 NET 'GROUND' U1-AT40 NET 'GROUND' U1-AT42 NET 'GROUND' U1-AT45 NET 'GROUND' U1-AT46 NET 'GROUND' U1-AU3 NET 'GROUND' U1-AU4 NET 'GROUND' U1-AU5 NET 'GROUND' U1-AU9 NET 'GROUND' U1-AU10 NET 'GROUND' U1-AU20 NET 'GROUND' U1-AU30 NET 'GROUND' U1-AU37 NET 'GROUND' U1-AU38 NET 'GROUND' U1-AU42 NET 'GROUND' U1-AU43 NET 'GROUND' U1-AU44 NET 'GROUND' U1-AV1 NET 'GROUND' U1-AV2 NET 'GROUND' U1-AV5 NET 'GROUND' U1-AV6 NET 'GROUND' U1-AV10 NET 'GROUND' U1-AV17 NET 'GROUND' U1-AV27 NET 'GROUND' U1-AV37 NET 'GROUND' U1-AV41 NET 'GROUND' U1-AV42 NET 'GROUND' U1-AV45 NET 'GROUND' U1-AV46 NET 'GROUND' U1-AW3 NET 'GROUND' U1-AW4 NET 'GROUND' U1-AW5 NET 'GROUND' U1-AW8 NET 'GROUND' U1-AW10 NET 'GROUND' U1-AW14 NET 'GROUND' U1-AW24 NET 'GROUND' U1-AW34 NET 'GROUND' U1-AW37 NET 'GROUND' U1-AW39 NET 'GROUND' U1-AW42 NET 'GROUND' U1-AW43 NET 'GROUND' U1-AW44 NET 'GROUND' U1-AY1 NET 'GROUND' U1-AY2 NET 'GROUND' U1-AY5 NET 'GROUND' U1-AY7 NET 'GROUND' U1-AY10 NET 'GROUND' U1-AY11 NET 'GROUND' U1-AY21 NET 'GROUND' U1-AY31 NET 'GROUND' U1-AY37 NET 'GROUND' U1-AY40 NET 'GROUND' U1-AY42 NET 'GROUND' U1-AY45 NET 'GROUND' U1-AY46 NET 'GROUND' U1-BA3 NET 'GROUND' U1-BA4 NET 'GROUND' U1-BA5 NET 'GROUND' U1-BA9 NET 'GROUND' U1-BA10 NET 'GROUND' U1-BA18 NET 'GROUND' U1-BA28 NET 'GROUND' U1-BA37 NET 'GROUND' U1-BA38 NET 'GROUND' U1-BA42 NET 'GROUND' U1-BA43 NET 'GROUND' U1-BA44 NET 'GROUND' U1-BB1 NET 'GROUND' U1-BB2 NET 'GROUND' U1-BB5 NET 'GROUND' U1-BB6 NET 'GROUND' U1-BB10 NET 'GROUND' U1-BB25 NET 'GROUND' U1-BB35 NET 'GROUND' U1-BB37 NET 'GROUND' U1-BB41 NET 'GROUND' U1-BB42 NET 'GROUND' U1-BB45 NET 'GROUND' U1-BB46 NET 'GROUND' U1-BC3 NET 'GROUND' U1-BC4 NET 'GROUND' U1-BC5 NET 'GROUND' U1-BC8 NET 'GROUND' U1-BC10 NET 'GROUND' U1-BC11 NET 'GROUND' U1-BC12 NET 'GROUND' U1-BC13 NET 'GROUND' U1-BC14 NET 'GROUND' U1-BC15 NET 'GROUND' U1-BC22 NET 'GROUND' U1-BC32 NET 'GROUND' U1-BC33 NET 'GROUND' U1-BC34 NET 'GROUND' U1-BC35 NET 'GROUND' U1-BC36 NET 'GROUND' U1-BC37 NET 'GROUND' U1-BC39 NET 'GROUND' U1-BC42 NET 'GROUND' U1-BC43 NET 'GROUND' U1-BC44 NET 'GROUND' U1-BD1 NET 'GROUND' U1-BD2 NET 'GROUND' U1-BD5 NET 'GROUND' U1-BD7 NET 'GROUND' U1-BD12 NET 'GROUND' U1-BD15 NET 'GROUND' U1-BD19 NET 'GROUND' U1-BD29 NET 'GROUND' U1-BD32 NET 'GROUND' U1-BD35 NET 'GROUND' U1-BD40 NET 'GROUND' U1-BD42 NET 'GROUND' U1-BD45 NET 'GROUND' U1-BD46 NET 'GROUND' U1-BE2 NET 'GROUND' U1-BE3 NET 'GROUND' U1-BE4 NET 'GROUND' U1-BE5 NET 'GROUND' U1-BE9 NET 'GROUND' U1-BE12 NET 'GROUND' U1-BE13 NET 'GROUND' U1-BE14 NET 'GROUND' U1-BE15 NET 'GROUND' U1-BE26 NET 'GROUND' U1-BE32 NET 'GROUND' U1-BE33 NET 'GROUND' U1-BE34 NET 'GROUND' U1-BE35 NET 'GROUND' U1-BE38 NET 'GROUND' U1-BE42 NET 'GROUND' U1-BE43 NET 'GROUND' U1-BE44 NET 'GROUND' U1-BE45 NET 'GROUND' U1-BF5 NET 'GROUND' U1-BF6 NET 'GROUND' U1-BF11 NET 'GROUND' U1-BF12 NET 'GROUND' U1-BF15 NET 'GROUND' U1-BF23 NET 'GROUND' U1-BF32 NET 'GROUND' U1-BF35 NET 'GROUND' U1-BF36 NET 'GROUND' U1-BF41 NET 'GROUND' U1-BF42 # # FPGA U1 VCCINT net 105 VCCINT pins # # Feed from the FPGA_CORE supply. # NET 'FPGA_CORE' U1-P26 NET 'FPGA_CORE' U1-P28 NET 'FPGA_CORE' U1-R15 NET 'FPGA_CORE' U1-R17 NET 'FPGA_CORE' U1-R19 NET 'FPGA_CORE' U1-R21 NET 'FPGA_CORE' U1-R23 NET 'FPGA_CORE' U1-R25 NET 'FPGA_CORE' U1-R27 NET 'FPGA_CORE' U1-R29 NET 'FPGA_CORE' U1-T16 NET 'FPGA_CORE' U1-T18 NET 'FPGA_CORE' U1-T20 NET 'FPGA_CORE' U1-T22 NET 'FPGA_CORE' U1-T24 NET 'FPGA_CORE' U1-T26 NET 'FPGA_CORE' U1-T28 NET 'FPGA_CORE' U1-U15 NET 'FPGA_CORE' U1-U17 NET 'FPGA_CORE' U1-U19 NET 'FPGA_CORE' U1-U21 NET 'FPGA_CORE' U1-U23 NET 'FPGA_CORE' U1-U25 NET 'FPGA_CORE' U1-U27 NET 'FPGA_CORE' U1-U29 NET 'FPGA_CORE' U1-V18 NET 'FPGA_CORE' U1-V20 NET 'FPGA_CORE' U1-V22 NET 'FPGA_CORE' U1-V24 NET 'FPGA_CORE' U1-V26 NET 'FPGA_CORE' U1-V28 NET 'FPGA_CORE' U1-W19 NET 'FPGA_CORE' U1-W21 NET 'FPGA_CORE' U1-W23 NET 'FPGA_CORE' U1-W25 NET 'FPGA_CORE' U1-W27 NET 'FPGA_CORE' U1-W29 NET 'FPGA_CORE' U1-Y18 NET 'FPGA_CORE' U1-Y20 NET 'FPGA_CORE' U1-Y22 NET 'FPGA_CORE' U1-Y24 NET 'FPGA_CORE' U1-Y26 NET 'FPGA_CORE' U1-Y28 NET 'FPGA_CORE' U1-AA19 NET 'FPGA_CORE' U1-AA21 NET 'FPGA_CORE' U1-AA23 NET 'FPGA_CORE' U1-AA25 NET 'FPGA_CORE' U1-AA27 NET 'FPGA_CORE' U1-AB18 NET 'FPGA_CORE' U1-AB22 NET 'FPGA_CORE' U1-AB24 NET 'FPGA_CORE' U1-AB26 NET 'FPGA_CORE' U1-AB28 NET 'FPGA_CORE' U1-AC21 NET 'FPGA_CORE' U1-AC23 NET 'FPGA_CORE' U1-AC25 NET 'FPGA_CORE' U1-AC27 NET 'FPGA_CORE' U1-AD18 NET 'FPGA_CORE' U1-AD22 NET 'FPGA_CORE' U1-AD24 NET 'FPGA_CORE' U1-AD26 NET 'FPGA_CORE' U1-AD28 NET 'FPGA_CORE' U1-AE21 NET 'FPGA_CORE' U1-AE23 NET 'FPGA_CORE' U1-AE25 NET 'FPGA_CORE' U1-AE27 NET 'FPGA_CORE' U1-AF18 NET 'FPGA_CORE' U1-AF20 NET 'FPGA_CORE' U1-AF22 NET 'FPGA_CORE' U1-AF24 NET 'FPGA_CORE' U1-AF26 NET 'FPGA_CORE' U1-AF28 NET 'FPGA_CORE' U1-AG19 NET 'FPGA_CORE' U1-AG21 NET 'FPGA_CORE' U1-AG23 NET 'FPGA_CORE' U1-AG25 NET 'FPGA_CORE' U1-AG27 NET 'FPGA_CORE' U1-AH16 NET 'FPGA_CORE' U1-AH18 NET 'FPGA_CORE' U1-AH20 NET 'FPGA_CORE' U1-AH22 NET 'FPGA_CORE' U1-AH24 NET 'FPGA_CORE' U1-AH26 NET 'FPGA_CORE' U1-AH28 NET 'FPGA_CORE' U1-AJ15 NET 'FPGA_CORE' U1-AJ17 NET 'FPGA_CORE' U1-AJ19 NET 'FPGA_CORE' U1-AJ21 NET 'FPGA_CORE' U1-AJ23 NET 'FPGA_CORE' U1-AJ25 NET 'FPGA_CORE' U1-AJ27 NET 'FPGA_CORE' U1-AK16 NET 'FPGA_CORE' U1-AK18 NET 'FPGA_CORE' U1-AK20 NET 'FPGA_CORE' U1-AK22 NET 'FPGA_CORE' U1-AK24 NET 'FPGA_CORE' U1-AK26 NET 'FPGA_CORE' U1-AK28 NET 'FPGA_CORE' U1-AL15 NET 'FPGA_CORE' U1-AL17 NET 'FPGA_CORE' U1-AL19 NET 'FPGA_CORE' U1-AL21 NET 'FPGA_CORE' U1-AL23 NET 'FPGA_CORE' U1-AL25 NET 'FPGA_CORE' U1-AL27 # # FPGA U1 VCCINT_IO net 9 VCCINT_IO pins # # Feed from the FPGA_CORE supply. # NET 'FPGA_CORE' U1-P30 NET 'FPGA_CORE' U1-T30 NET 'FPGA_CORE' U1-V30 NET 'FPGA_CORE' U1-AA29 NET 'FPGA_CORE' U1-AC29 NET 'FPGA_CORE' U1-AE29 NET 'FPGA_CORE' U1-AG29 NET 'FPGA_CORE' U1-AJ29 NET 'FPGA_CORE' U1-AL29 # # FPGA U1 VCCBRAM net 8 VCCBRAM pins # # Feed from the FPGA_CORE supply. # NET 'FPGA_CORE' U1-V16 NET 'FPGA_CORE' U1-W15 NET 'FPGA_CORE' U1-W17 NET 'FPGA_CORE' U1-Y16 NET 'FPGA_CORE' U1-AA17 NET 'FPGA_CORE' U1-AC17 NET 'FPGA_CORE' U1-AE17 NET 'FPGA_CORE' U1-AG17 # # FPGA U1 VCCAUX net 11 VCCAUX pins # # Feed from the BULK_1V8 supply. # NET 'BULK_1V8' U1-P32 NET 'BULK_1V8' U1-T32 NET 'BULK_1V8' U1-V32 NET 'BULK_1V8' U1-Y32 NET 'BULK_1V8' U1-AB32 NET 'BULK_1V8' U1-AC31 NET 'BULK_1V8' U1-AD32 NET 'BULK_1V8' U1-AE31 NET 'BULK_1V8' U1-AF32 NET 'BULK_1V8' U1-AH32 NET 'BULK_1V8' U1-AK32 # # FPGA U1 VCCAUX_IO net 13 VCCAUX_IO pins # # Feed from the BULK_1V8 supply. # NET 'BULK_1V8' U1-R31 NET 'BULK_1V8' U1-U31 NET 'BULK_1V8' U1-W31 NET 'BULK_1V8' U1-Y30 NET 'BULK_1V8' U1-AA31 NET 'BULK_1V8' U1-AB30 NET 'BULK_1V8' U1-AD30 NET 'BULK_1V8' U1-AF30 NET 'BULK_1V8' U1-AG31 NET 'BULK_1V8' U1-AH30 NET 'BULK_1V8' U1-AJ31 NET 'BULK_1V8' U1-AK30 NET 'BULK_1V8' U1-AL31 # # FPGA U1 VCCO nets 56 VCCO pins # # Banks: 0, 65, 66, 67, 68, 70, 71, 72 are feed from the BULK_1V8 supply. # # Banks: 84, 94 are feed from the BULK_3V3 supply. # # VCCO Bank #0 NET 'BULK_1V8' U1-AC15 NET 'BULK_1V8' U1-AE15 # VCCO Bank #65 NET 'BULK_1V8' U1-AM20 NET 'BULK_1V8' U1-AR21 NET 'BULK_1V8' U1-AT18 NET 'BULK_1V8' U1-AW19 NET 'BULK_1V8' U1-BB20 NET 'BULK_1V8' U1-BF18 # VCCO Bank #66 NET 'BULK_1V8' U1-AN27 NET 'BULK_1V8' U1-AP24 NET 'BULK_1V8' U1-AU25 NET 'BULK_1V8' U1-AV22 NET 'BULK_1V8' U1-BA23 NET 'BULK_1V8' U1-BD24 NET 'BULK_1V8' U1-BE21 # VCCO Bank #67 NET 'BULK_1V8' U1-AM30 NET 'BULK_1V8' U1-AR31 NET 'BULK_1V8' U1-AT28 NET 'BULK_1V8' U1-AW29 NET 'BULK_1V8' U1-AY26 NET 'BULK_1V8' U1-BC27 NET 'BULK_1V8' U1-BF28 # VCCO Bank #68 NET 'BULK_1V8' U1-AP34 NET 'BULK_1V8' U1-AU35 NET 'BULK_1V8' U1-AV32 NET 'BULK_1V8' U1-AY36 NET 'BULK_1V8' U1-BA33 NET 'BULK_1V8' U1-BB30 NET 'BULK_1V8' U1-BE31 # VCCO Bank #70 NET 'BULK_1V8' U1-A27 NET 'BULK_1V8' U1-D28 NET 'BULK_1V8' U1-G29 NET 'BULK_1V8' U1-H26 NET 'BULK_1V8' U1-K30 NET 'BULK_1V8' U1-L27 NET 'BULK_1V8' U1-N31 # VCCO Bank #71 NET 'BULK_1V8' U1-B24 NET 'BULK_1V8' U1-E25 NET 'BULK_1V8' U1-F22 NET 'BULK_1V8' U1-J23 NET 'BULK_1V8' U1-M24 NET 'BULK_1V8' U1-N21 # VCCO Bank #72 NET 'BULK_1V8' U1-C21 NET 'BULK_1V8' U1-D18 NET 'BULK_1V8' U1-G19 NET 'BULK_1V8' U1-K20 NET 'BULK_1V8' U1-L17 NET 'BULK_1V8' U1-P18 # VCCO Bank #84 NET 'BULK_3V3' U1-AN17 NET 'BULK_3V3' U1-AP14 NET 'BULK_3V3' U1-AR11 NET 'BULK_3V3' U1-AU15 # VCCO Bank #94 NET 'BULK_3V3' U1-AV12 NET 'BULK_3V3' U1-AY16 NET 'BULK_3V3' U1-BA13 NET 'BULK_3V3' U1-BC17 # # FPGA U1 MGT_AVCC net 46 MGT_AVCC pins # # Feed from the MGT_AVCC supply. # # MGT_AVCC Power Group LC NET 'MGT_AVCC' U1-U35 NET 'MGT_AVCC' U1-V36 NET 'MGT_AVCC' U1-W34 NET 'MGT_AVCC' U1-W38 NET 'MGT_AVCC' U1-AA35 NET 'MGT_AVCC' U1-AC34 NET 'MGT_AVCC' U1-AD37 NET 'MGT_AVCC' U1-AE35 NET 'MGT_AVCC' U1-AF36 # MGT_AVCC Power Group LN NET 'MGT_AVCC' U1-F36 NET 'MGT_AVCC' U1-G34 NET 'MGT_AVCC' U1-H37 NET 'MGT_AVCC' U1-K36 NET 'MGT_AVCC' U1-M37 NET 'MGT_AVCC' U1-N35 NET 'MGT_AVCC' U1-P36 NET 'MGT_AVCC' U1-R34 NET 'MGT_AVCC' U1-T37 # MGT_AVCC Power Group LS NET 'MGT_AVCC' U1-AG34 NET 'MGT_AVCC' U1-AH37 NET 'MGT_AVCC' U1-AJ35 NET 'MGT_AVCC' U1-AL34 NET 'MGT_AVCC' U1-AL38 # MGT_AVCC Power Group RC NET 'MGT_AVCC' U1-U12 NET 'MGT_AVCC' U1-V11 NET 'MGT_AVCC' U1-W9 NET 'MGT_AVCC' U1-W13 NET 'MGT_AVCC' U1-AA12 NET 'MGT_AVCC' U1-AC13 NET 'MGT_AVCC' U1-AD10 NET 'MGT_AVCC' U1-AE12 NET 'MGT_AVCC' U1-AF11 # MGT_AVCC Power Group RN NET 'MGT_AVCC' U1-F11 NET 'MGT_AVCC' U1-G13 NET 'MGT_AVCC' U1-H10 NET 'MGT_AVCC' U1-K11 NET 'MGT_AVCC' U1-M10 NET 'MGT_AVCC' U1-N12 NET 'MGT_AVCC' U1-P11 NET 'MGT_AVCC' U1-R13 NET 'MGT_AVCC' U1-T10 # MGT_AVCC Power Group RS NET 'MGT_AVCC' U1-AG13 NET 'MGT_AVCC' U1-AH10 NET 'MGT_AVCC' U1-AJ12 NET 'MGT_AVCC' U1-AL9 NET 'MGT_AVCC' U1-AL13 # # FPGA U1 MGT_AVTT net 90 MGT_AVTT pins # # Feed from the MGT_AVTT supply. # # MGT_AVTT Power Group LC NET 'MGT_AVTT' U1-U39 NET 'MGT_AVTT' U1-V40 NET 'MGT_AVTT' U1-Y41 NET 'MGT_AVTT' U1-AA39 NET 'MGT_AVTT' U1-AB40 NET 'MGT_AVTT' U1-AC38 NET 'MGT_AVTT' U1-AD41 NET 'MGT_AVTT' U1-AE39 NET 'MGT_AVTT' U1-AF40 NET 'MGT_AVTT' U1-AG38 NET 'MGT_AVTT' U1-AJ39 NET 'MGT_AVTT' U1-AK40 NET 'MGT_AVTT' U1-AM41 NET 'MGT_AVTT' U1-AN39 NET 'MGT_AVTT' U1-AP40 NET 'MGT_AVTT' U1-AR38 NET 'MGT_AVTT' U1-AT41 # MGT_AVTT Power Group LN NET 'MGT_AVTT' U1-A43 NET 'MGT_AVTT' U1-B36 NET 'MGT_AVTT' U1-B40 NET 'MGT_AVTT' U1-C38 NET 'MGT_AVTT' U1-D37 NET 'MGT_AVTT' U1-E39 NET 'MGT_AVTT' U1-F40 NET 'MGT_AVTT' U1-G38 NET 'MGT_AVTT' U1-H41 NET 'MGT_AVTT' U1-J39 NET 'MGT_AVTT' U1-K40 NET 'MGT_AVTT' U1-L38 NET 'MGT_AVTT' U1-M41 NET 'MGT_AVTT' U1-N39 NET 'MGT_AVTT' U1-P40 NET 'MGT_AVTT' U1-R38 NET 'MGT_AVTT' U1-T41 # MGT_AVTT Power Group LS NET 'MGT_AVTT' U1-AU39 NET 'MGT_AVTT' U1-AV40 NET 'MGT_AVTT' U1-AW38 NET 'MGT_AVTT' U1-AY41 NET 'MGT_AVTT' U1-BA39 NET 'MGT_AVTT' U1-BB40 NET 'MGT_AVTT' U1-BC38 NET 'MGT_AVTT' U1-BD41 NET 'MGT_AVTT' U1-BE39 NET 'MGT_AVTT' U1-BF37 NET 'MGT_AVTT' U1-BF40 # MGT_AVTT Power Group RC NET 'MGT_AVTT' U1-U8 NET 'MGT_AVTT' U1-V7 NET 'MGT_AVTT' U1-Y6 NET 'MGT_AVTT' U1-AA8 NET 'MGT_AVTT' U1-AB7 NET 'MGT_AVTT' U1-AC9 NET 'MGT_AVTT' U1-AD6 NET 'MGT_AVTT' U1-AE8 NET 'MGT_AVTT' U1-AF7 NET 'MGT_AVTT' U1-AG9 NET 'MGT_AVTT' U1-AJ8 NET 'MGT_AVTT' U1-AK7 NET 'MGT_AVTT' U1-AM6 NET 'MGT_AVTT' U1-AN8 NET 'MGT_AVTT' U1-AP7 NET 'MGT_AVTT' U1-AR9 NET 'MGT_AVTT' U1-AT6 # MGT_AVTT Power Group RN NET 'MGT_AVTT' U1-A4 NET 'MGT_AVTT' U1-B7 NET 'MGT_AVTT' U1-B11 NET 'MGT_AVTT' U1-C9 NET 'MGT_AVTT' U1-D10 NET 'MGT_AVTT' U1-E8 NET 'MGT_AVTT' U1-F7 NET 'MGT_AVTT' U1-G9 NET 'MGT_AVTT' U1-H6 NET 'MGT_AVTT' U1-J8 NET 'MGT_AVTT' U1-K7 NET 'MGT_AVTT' U1-L9 NET 'MGT_AVTT' U1-M6 NET 'MGT_AVTT' U1-N8 NET 'MGT_AVTT' U1-P7 NET 'MGT_AVTT' U1-R9 NET 'MGT_AVTT' U1-T6 # MGT_AVTT Power Group RS NET 'MGT_AVTT' U1-AU8 NET 'MGT_AVTT' U1-AV7 NET 'MGT_AVTT' U1-AW9 NET 'MGT_AVTT' U1-AY6 NET 'MGT_AVTT' U1-BA8 NET 'MGT_AVTT' U1-BB7 NET 'MGT_AVTT' U1-BC9 NET 'MGT_AVTT' U1-BD6 NET 'MGT_AVTT' U1-BE8 NET 'MGT_AVTT' U1-BF7 NET 'MGT_AVTT' U1-BF10 # # FPGA U1 MGT_AVAUX net 12 MGT_AVAUX pins # # Feed from the MGT_AVAUX supply. # # MGT_AVAUX Group LC NET 'MGT_AVAUX' U1-Y37 NET 'MGT_AVAUX' U1-AB36 # MGT_AVAUX Group LN NET 'MGT_AVAUX' U1-J35 NET 'MGT_AVAUX' U1-L34 # MGT_AVAUX Group LS NET 'MGT_AVAUX' U1-AK36 NET 'MGT_AVAUX' U1-AM37 # MGT_AVAUX Group RC NET 'MGT_AVAUX' U1-Y10 NET 'MGT_AVAUX' U1-AB11 # MGT_AVAUX Group RN NET 'MGT_AVAUX' U1-J12 NET 'MGT_AVAUX' U1-L13 # MGT_AVAUX Group RS NET 'MGT_AVAUX' U1-AK11 NET 'MGT_AVAUX' U1-AM10 # # Ultra FPGA Bypass Capacitor Nets # ------------------------------------ # # Initial Rev. 27-Mar-2015 # Current Rev. 5-Nov-2016 # # This file holds all of the Power and Ground connections # to the ByPass Capacitors on the Hub's Virtex-7 FPGA. # # # FPGA_CORE Bus # VCCINT & VCCBRAM 8x 470 uFd 2.5V case V 9 mOhm C10 : C17 # 1.000 V Supply 11x 10 uFd 10V 0805 X7R C19 : C29 # 3760 uFd total Tant 10x 2.2 uFd 10 V 0603 X7R C30 : C39 # 132 uFd total Ceramic # NET 'FPGA_CORE' C10-1 C11-1 C12-1 C13-1 C14-1 NET 'GROUND' C10-2 C11-2 C12-2 C13-2 C14-2 NET 'FPGA_CORE' C15-1 C16-1 C17-1 NET 'GROUND' C15-2 C16-2 C17-2 NET 'FPGA_CORE' C19-1 C20-1 C21-1 C22-1 C23-1 NET 'GROUND' C19-2 C20-2 C21-2 C22-2 C23-2 NET 'FPGA_CORE' C24-1 C25-1 C26-1 C27-1 C28-1 C29-1 NET 'GROUND' C24-2 C25-2 C26-2 C27-2 C28-2 C29-2 NET 'FPGA_CORE' C30-1 C31-1 C32-1 C33-1 C34-1 NET 'GROUND' C30-2 C31-2 C32-2 C33-2 C34-2 NET 'FPGA_CORE' C35-1 C36-1 C37-1 C38-1 C39-1 NET 'GROUND' C35-2 C36-2 C37-2 C38-2 C39-2 # # BULK_1V8 Bus 2x 470 uFd 2.5V case V 9 mOhm C50, C51 # VCCAUX, VCCAUX_IO, 10x 10 uFd 10V 0805 X7R C60 : C69 # VCCO Bank 0 10x 2.2 uFd 10 V 0603 X7R C70 : C79 # VCCO per Bank, 12 Banks # 940 uFd total Tant # 122 uFd total Ceramic # NET 'BULK_1V8' C50-1 C51-1 NET 'GROUND' C50-2 C51-2 NET 'BULK_1V8' C60-1 C61-1 C62-1 C63-1 C64-1 NET 'GROUND' C60-2 C61-2 C62-2 C63-2 C64-2 NET 'BULK_1V8' C65-1 C66-1 C67-1 C68-1 C69-1 NET 'GROUND' C65-2 C66-2 C67-2 C68-2 C69-2 NET 'BULK_1V8' C70-1 C71-1 C72-1 C73-1 C74-1 NET 'GROUND' C70-2 C71-2 C72-2 C73-2 C74-2 NET 'BULK_1V8' C75-1 C76-1 C77-1 C78-1 C79-1 NET 'GROUND' C75-2 C76-2 C77-2 C78-2 C79-2 # # MGT_AVCC Bus 2x 470 uFd 2.5V case V 9 mOhm C90, C91 # 1.000 V 7x 10 uFd 10V 0805 X7R C100 : C106 # 940 uFd total Tant 7x 2.2 uFd 10 V 0603 X7R C110 : C116 # 85 uFd total Ceramic # NET 'MGT_AVCC' C90-1 C91-1 NET 'GROUND' C90-2 C91-2 NET 'MGT_AVCC' C100-1 C101-1 C102-1 C103-1 C104-1 C105-1 C106-1 NET 'GROUND' C100-2 C101-2 C102-2 C103-2 C104-2 C105-2 C106-2 NET 'MGT_AVCC' C110-1 C111-1 C112-1 C113-1 C114-1 C115-1 C116-1 NET 'GROUND' C110-2 C111-2 C112-2 C113-2 C114-2 C115-2 C116-2 # # MGT_AVTT Bus 2x 470 uFd 2.5V case V 9 mOhm C120, C121 # 1.200 V 7x 10 uFd 10V 0805 X7R C130 : C136 # 940 uFd total Tant 7x 2.2 uFd 10 V 0603 X7R C140 : C146 # 85 uFd total Ceramic # NET 'MGT_AVTT' C120-1 C121-1 NET 'GROUND' C120-2 C121-2 NET 'MGT_AVTT' C130-1 C131-1 C132-1 C133-1 C134-1 C135-1 C136-1 NET 'GROUND' C130-2 C131-2 C132-2 C133-2 C134-2 C135-2 C136-2 NET 'MGT_AVTT' C140-1 C141-1 C142-1 C143-1 C144-1 C145-1 C146-1 NET 'GROUND' C140-2 C141-2 C142-2 C143-2 C144-2 C145-2 C146-2 # # MGT_AVAUX Bus 2x 470 uFd 2.5V case V 9 mOhm C150, C151 # 1.200 V 6x 10 uFd 10V 0805 X7R C160 : C165 # 940 uFd total Tant 6x 2.2 uFd 10 V 0603 X7R C170 : C175 # 73 uFd total Ceramic # NET 'MGT_AVAUX' C150-1 C151-1 NET 'GROUND' C150-2 C151-2 NET 'MGT_AVAUX' C160-1 C161-1 C162-1 C163-1 C164-1 C165-1 NET 'GROUND' C160-2 C161-2 C162-2 C163-2 C164-2 C165-2 NET 'MGT_AVAUX' C170-1 C171-1 C172-1 C173-1 C174-1 C175-1 NET 'GROUND' C170-2 C171-2 C172-2 C173-2 C174-2 C175-2 # # BULK_3V3 Bus - DCDC-8 5x 10 uFd 10V 0805 X7R C180 : C184 # VCCO per Bank 2x 2.2 uFd 10 V 0603 X7R C185 : C186 # total of 2 Banks # 54 uFd total Ceramic # NET 'BULK_3V3' C180-1 C181-1 C182-1 C183-1 C184-1 NET 'GROUND' C180-2 C181-2 C182-2 C183-2 C184-2 NET 'BULK_3V3' C185-1 C186-1 NET 'GROUND' C185-2 C186-2 # # -------------------------------------------------------------- # -------------------------------------------------------------- # # # ByPass Capacitors Under the FPGA # # # -------------------------------------------------------------- # -------------------------------------------------------------- # # # FPGA_CORE Bypass Caps Under the FPGA NET 'FPGA_CORE' C191-1 C192-1 C193-1 C194-1 C195-1 NET 'GROUND' C191-2 C192-2 C193-2 C194-2 C195-2 NET 'FPGA_CORE' C196-1 C197-1 C198-1 C199-1 C200-1 NET 'GROUND' C196-2 C197-2 C198-2 C199-2 C200-2 NET 'FPGA_CORE' C201-1 C202-1 NET 'GROUND' C201-2 C202-2 # # BULK_1V8 Bypass Caps Under the FPGA NET 'BULK_1V8' C211-1 C212-1 C213-1 C214-1 C215-1 NET 'GROUND' C211-2 C212-2 C213-2 C214-2 C215-2 NET 'BULK_1V8' C216-1 C217-1 C218-1 C219-1 NET 'GROUND' C216-2 C217-2 C218-2 C219-2 NET 'BULK_1V8' C245-1 C246-1 C247-1 C248-1 C249-1 NET 'GROUND' C245-2 C246-2 C247-2 C248-2 C249-2 # # MGT_AVCC Bypass Caps Under the FPGA NET 'MGT_AVCC' C221-1 C222-1 C223-1 C224-1 C225-1 NET 'GROUND' C221-2 C222-2 C223-2 C224-2 C225-2 NET 'MGT_AVCC' C226-1 C227-1 C228-1 C229-1 C230-1 NET 'GROUND' C226-2 C227-2 C228-2 C229-2 C230-2 NET 'MGT_AVCC' C231-1 C232-1 C233-1 C234-1 C235-1 NET 'GROUND' C231-2 C232-2 C233-2 C234-2 C235-2 NET 'MGT_AVCC' C236-1 C237-1 C238-1 NET 'GROUND' C236-2 C237-2 C238-2 # # MGT_AVTT Bypass Caps Under the FPGA NET 'MGT_AVTT' C311-1 C312-1 C313-1 C314-1 C315-1 NET 'GROUND' C311-2 C312-2 C313-2 C314-2 C315-2 NET 'MGT_AVTT' C316-1 C317-1 C318-1 C319-1 C320-1 NET 'GROUND' C316-2 C317-2 C318-2 C319-2 C320-2 NET 'MGT_AVTT' C321-1 C322-1 C323-1 C324-1 C325-1 NET 'GROUND' C321-2 C322-2 C323-2 C324-2 C325-2 NET 'MGT_AVTT' C326-1 C327-1 C328-1 NET 'GROUND' C326-2 C327-2 C328-2 # # MGT_AVAUX Bypass Caps Under the FPGA NET 'MGT_AVAUX' C331-1 C332-1 C333-1 C334-1 C335-1 NET 'GROUND' C331-2 C332-2 C333-2 C334-2 C335-2 NET 'MGT_AVAUX' C336-1 C337-1 C338-1 C339-1 C340-1 NET 'GROUND' C336-2 C337-2 C338-2 C339-2 C340-2 # # BULK_3V3 Bypass Caps Under the FPGA NET 'BULK_3V3' C241-1 C242-1 NET 'GROUND' C241-2 C242-2 # # FPGA Un-Connected Pins Net List # ----------------------------------- # # Hub-Module Key In Nets File # # # Original Rev. 3-Sep-2015 # Current Rev. 28-Dec-2016 # # # # This file holds almost all of the UnConnected pins # on the U1 FPGA part XCVU125 - FLVC2104. # # A few UnConnected U1 pins are listed in the net list # file where their piers that are used in the Hub # Module design are described. Some of these net list # files are noted below. # # # UnConnected pins in Select I/O Bank 65. # # 1V8 HP I/O Bank # # Most of the pins in Bank 65 are used in # the BMI Configuration scheme for the FPGA # on the Hub Module. The few unconnected pins # in Bank 65 are listed in the net list file: # # bank_0_and_bank_65_config_mem_nets # # # UnConnected pins in Select I/O Bank 66. # # 1V8 HP I/O Bank # # As of 28-Nov-2016 no pins have been used in BAnk 66. # # Access to Bank 66 is almost impossible because of the # large number of Configuration signals that run into # the inner rings of Bank 65. # NET 'No_Conn_FPGA_BE24' U1-BE24 # IO_L24P_T3U_N10_66 NET 'No_Conn_FPGA_BF24' U1-BF24 # IO_L24N_T3U_N11_66 NET 'No_Conn_FPGA_BD21' U1-BD21 # IO_T3U_N12_66 NET 'No_Conn_FPGA_BD23' U1-BD23 # IO_L23P_T3U_N8_66 NET 'No_Conn_FPGA_BE23' U1-BE23 # IO_L23N_T3U_N9_66 NET 'No_Conn_FPGA_BF21' U1-BF21 # IO_L22P_T3U_N6_DBC_AD0P_66 NET 'No_Conn_FPGA_BF22' U1-BF22 # IO_L22N_T3U_N7_DBC_AD0N_66 NET 'No_Conn_FPGA_BB24' U1-BB24 # IO_L21P_T3L_N4_AD8P_66 NET 'No_Conn_FPGA_BC24' U1-BC24 # IO_L21N_T3L_N5_AD8N_66 NET 'No_Conn_FPGA_BD22' U1-BD22 # IO_L20P_T3L_N2_AD1P_66 NET 'No_Conn_FPGA_BE22' U1-BE22 # IO_L20N_T3L_N3_AD1N_66 NET 'No_Conn_FPGA_BB23' U1-BB23 # IO_L19P_T3L_N0_DBC_AD9P_66 NET 'No_Conn_FPGA_BC23' U1-BC23 # IO_L19N_T3L_N1_DBC_AD9N_66 NET 'No_Conn_FPGA_AY25' U1-AY25 # IO_L18P_T2U_N10_AD2P_66 NET 'No_Conn_FPGA_BA25' U1-BA25 # IO_L18N_T2U_N11_AD2N_66 NET 'No_Conn_FPGA_BA22' U1-BA22 # IO_L17P_T2U_N8_AD10P_66 NET 'No_Conn_FPGA_BB22' U1-BB22 # IO_L17N_T2U_N9_AD10N_66 NET 'No_Conn_FPGA_AY24' U1-AY24 # IO_L16P_T2U_N6_QBC_AD3P_66 NET 'No_Conn_FPGA_BA24' U1-BA24 # IO_L16N_T2U_N7_QBC_AD3N_66 NET 'No_Conn_FPGA_AY22' U1-AY22 # IO_L15P_T2L_N4_AD11P_66 NET 'No_Conn_FPGA_AY23' U1-AY23 # IO_L15N_T2L_N5_AD11N_66 NET 'No_Conn_FPGA_AW22' U1-AW22 # IO_L14P_T2L_N2_GC_66 NET 'No_Conn_FPGA_AW23' U1-AW23 # IO_L14N_T2L_N3_GC_66 NET 'No_Conn_FPGA_AW25' U1-AW25 # IO_T2U_N12_66 NET 'No_Conn_FPGA_AV23' U1-AV23 # IO_L13P_T2L_N0_GC_QBC_66 NET 'No_Conn_FPGA_AV24' U1-AV24 # IO_L13N_T2L_N1_GC_QBC_66 NET 'No_Conn_FPGA_AT24' U1-AT24 # IO_L12P_T1U_N10_GC_66 NET 'No_Conn_FPGA_AT25' U1-AT25 # IO_L12N_T1U_N11_GC_66 NET 'No_Conn_FPGA_AV25' U1-AV25 # IO_T1U_N12_66 NET 'No_Conn_FPGA_AU23' U1-AU23 # IO_L11P_T1U_N8_GC_66 NET 'No_Conn_FPGA_AU24' U1-AU24 # IO_L11N_T1U_N9_GC_66 NET 'No_Conn_FPGA_AT26' U1-AT26 # IO_L10P_T1U_N6_QBC_AD4P_66 NET 'No_Conn_FPGA_AU26' U1-AU26 # IO_L10N_T1U_N7_QBC_AD4N_66 NET 'No_Conn_FPGA_AT22' U1-AT22 # IO_L9P_T1L_N4_AD12P_66 NET 'No_Conn_FPGA_AU22' U1-AU22 # IO_L9N_T1L_N5_AD12N_66 NET 'No_Conn_FPGA_AR24' U1-AR24 # IO_L8P_T1L_N2_AD5P_66 NET 'No_Conn_FPGA_AR25' U1-AR25 # IO_L8N_T1L_N3_AD5N_66 NET 'No_Conn_FPGA_AR22' U1-AR22 # IO_L7P_T1L_N0_QBC_AD13P_66 NET 'No_Conn_FPGA_AR23' U1-AR23 # IO_L7N_T1L_N1_QBC_AD13N_66 NET 'No_Conn_FPGA_AP26' U1-AP26 # IO_L6P_T0U_N10_AD6P_66 NET 'No_Conn_FPGA_AP27' U1-AP27 # IO_L6N_T0U_N11_AD6N_66 NET 'No_Conn_FPGA_AM24' U1-AM24 # IO_L5P_T0U_N8_AD14P_66 NET 'No_Conn_FPGA_AN24' U1-AN24 # IO_L5N_T0U_N9_AD14N_66 NET 'No_Conn_FPGA_AN25' U1-AN25 # IO_L4P_T0U_N6_DBC_AD7P_66 NET 'No_Conn_FPGA_AP25' U1-AP25 # IO_L4N_T0U_N7_DBC_AD7N_66 NET 'No_Conn_FPGA_AP22' U1-AP22 # IO_L3P_T0L_N4_AD15P_66 NET 'No_Conn_FPGA_AP23' U1-AP23 # IO_L3N_T0L_N5_AD15N_66 NET 'No_Conn_FPGA_AM26' U1-AM26 # IO_L2P_T0L_N2_66 NET 'No_Conn_FPGA_AN26' U1-AN26 # IO_L2N_T0L_N3_66 NET 'No_Conn_FPGA_AM23' U1-AM23 # IO_L1P_T0L_N0_DBC_66 NET 'No_Conn_FPGA_AN23' U1-AN23 # IO_L1N_T0L_N1_DBC_66 # # UnConnected pins in Select I/O Bank 67. # # 1V8 HP I/O Bank # NET 'No_Conn_FPGA_BC28' U1-BC28 # IO_L24P_T3U_N10_67 NET 'No_Conn_FPGA_BD28' U1-BD28 # IO_L24N_T3U_N11_67 NET 'No_Conn_FPGA_BD27' U1-BD27 # IO_T3U_N12_67 NET 'No_Conn_FPGA_BC26' U1-BC26 # IO_L21P_T3L_N4_AD8P_67 NET 'No_Conn_FPGA_BD26' U1-BD26 # IO_L21N_T3L_N5_AD8N_67 NET 'No_Conn_FPGA_BC25' U1-BC25 # IO_L19P_T3L_N0_DBC_AD9P_67 NET 'No_Conn_FPGA_BD25' U1-BD25 # IO_L19N_T3L_N1_DBC_AD9N_67 NET 'No_Conn_FPGA_BA26' U1-BA26 # IO_L17P_T2U_N8_AD10P_67 NET 'No_Conn_FPGA_BB26' U1-BB26 # IO_L17N_T2U_N9_AD10N_67 NET 'No_Conn_FPGA_BA27' U1-BA27 # IO_L16P_T2U_N6_QBC_AD3P_67 NET 'No_Conn_FPGA_BB27' U1-BB27 # IO_L16N_T2U_N7_QBC_AD3N_67 NET 'No_Conn_FPGA_AY29' U1-AY29 # IO_L15P_T2L_N4_AD11P_67 NET 'No_Conn_FPGA_AY30' U1-AY30 # IO_L15N_T2L_N5_AD11N_67 NET 'No_Conn_FPGA_AW30' U1-AW30 # IO_T1U_N12_67 NET 'No_Conn_FPGA_AN30' U1-AN30 # IO_L6P_T0U_N10_AD6P_67 NET 'No_Conn_FPGA_AP30' U1-AP30 # IO_L6N_T0U_N11_AD6N_67 NET 'No_Conn_FPGA_AR27' U1-AR27 # IO_L5P_T0U_N8_AD14P_67 NET 'No_Conn_FPGA_AR28' U1-AR28 # IO_L5N_T0U_N9_AD14N_67 NET 'No_Conn_FPGA_AR29' U1-AR29 # IO_L4P_T0U_N6_DBC_AD7P_67 NET 'No_Conn_FPGA_AR30' U1-AR30 # IO_L4N_T0U_N7_DBC_AD7N_67 NET 'No_Conn_FPGA_AM29' U1-AM29 # IO_L3P_T0L_N4_AD15P_67 NET 'No_Conn_FPGA_AN29' U1-AN29 # IO_L3N_T0L_N5_AD15N_67 NET 'No_Conn_FPGA_AM31' U1-AM31 # IO_L2P_T0L_N2_67 NET 'No_Conn_FPGA_AN31' U1-AN31 # IO_L2N_T0L_N3_67 NET 'No_Conn_FPGA_AN28' U1-AN28 # IO_L1P_T0L_N0_DBC_67 NET 'No_Conn_FPGA_AP28' U1-AP28 # IO_L1N_T0L_N1_DBC_67 # # UnConnected pins in Select I/O Bank 68. # # 1V8 HP I/O Bank # NET 'No_Conn_FPGA_BD31' U1-BD31 # IO_L23N_T3U_N9_68 NET 'No_Conn_FPGA_BD30' U1-BD30 # IO_L20P_T3L_N2_AD1P_68 NET 'No_Conn_FPGA_BC29' U1-BC29 # IO_L19P_T3L_N0_DBC_AD9P_68 NET 'No_Conn_FPGA_BA32' U1-BA32 # IO_L15N_T2L_N5_AD11N_68 NET 'No_Conn_FPGA_AU31' U1-AU31 # IO_L8P_T1L_N2_AD5P_68 NET 'No_Conn_FPGA_AP33' U1-AP33 # IO_L5P_T0U_N8_AD14P_68 NET 'No_Conn_FPGA_AR33' U1-AR33 # IO_L5N_T0U_N9_AD14N_68 NET 'No_Conn_FPGA_AR32' U1-AR32 # IO_L3P_T0L_N4_AD15P_68 NET 'No_Conn_FPGA_AT32' U1-AT32 # IO_L3N_T0L_N5_AD15N_68 NET 'No_Conn_FPGA_AR34' U1-AR34 # IO_L2P_T0L_N2_68 NET 'No_Conn_FPGA_AN32' U1-AN32 # IO_L1P_T0L_N0_DBC_68 NET 'No_Conn_FPGA_AP32' U1-AP32 # IO_L1N_T0L_N1_DBC_68 # # UnConnected pins in Select I/O Bank 84. # # 3V3 HR I/O Bank # NET 'No_Conn_FPGA_AT17' U1-AT17 # IO_L20P_T3L_N2_AD1P_84 NET 'No_Conn_FPGA_AU17' U1-AU17 # IO_L20N_T3L_N3_AD1N_84 NET 'No_Conn_FPGA_AU14' U1-AU14 # IO_L13P_T2L_N0_GC_QBC_84 # # UnConnected pins in Select I/O Bank 94. # # 3V3 HR I/O Bank # NET 'No_Conn_FPGA_AV14' U1-AV14 # IO_L11P_T1U_N8_GC_94 NET 'No_Conn_FPGA_AY17' U1-AY17 # IO_L6P_T0U_N10_AD6P_94 NET 'No_Conn_FPGA_BA17' U1-BA17 # IO_L6N_T0U_N11_AD6N_94 NET 'No_Conn_FPGA_BB17' U1-BB17 # IO_L4P_T0U_N6_DBC_AD7P_94 NET 'No_Conn_FPGA_BC16' U1-BC16 # IO_T0U_N12_94 # # UnConnected pins in Select I/O Bank 70. # # 1V8 HP I/O Bank # # As of 28-Nov_2016 only 3 pins in Bank 70 are in use. # # These are pins: B26, A26, B27. # # These pins are low current static outputs # NET 'No_Conn_FPGA_E26' U1-E26 # IO_T3U_N12_70 NET 'No_Conn_FPGA_D29' U1-D29 # IO_L23P_T3U_N8_70 NET 'No_Conn_FPGA_C29' U1-C29 # IO_L23N_T3U_N9_70 NET 'No_Conn_FPGA_B28' U1-B28 # IO_L22N_T3U_N7_DBC_AD0N_70 NET 'No_Conn_FPGA_C27' U1-C27 # IO_L21P_T3L_N4_AD8P_70 NET 'No_Conn_FPGA_C28' U1-C28 # IO_L21N_T3L_N5_AD8N_70 NET 'No_Conn_FPGA_A28' U1-A28 # IO_L20P_T3L_N2_AD1P_70 NET 'No_Conn_FPGA_A29' U1-A29 # IO_L20N_T3L_N3_AD1N_70 NET 'No_Conn_FPGA_D26' U1-D26 # IO_L19P_T3L_N0_DBC_AD9P_70 NET 'No_Conn_FPGA_D27' U1-D27 # IO_L19N_T3L_N1_DBC_AD9N_70 NET 'No_Conn_FPGA_E27' U1-E27 # IO_L18P_T2U_N10_AD2P_70 NET 'No_Conn_FPGA_E28' U1-E28 # IO_L18N_T2U_N11_AD2N_70 NET 'No_Conn_FPGA_F29' U1-F29 # IO_L17P_T2U_N8_AD10P_70 NET 'No_Conn_FPGA_E29' U1-E29 # IO_L17N_T2U_N9_AD10N_70 NET 'No_Conn_FPGA_G26' U1-G26 # IO_L16P_T2U_N6_QBC_AD3P_70 NET 'No_Conn_FPGA_F26' U1-F26 # IO_L16N_T2U_N7_QBC_AD3N_70 NET 'No_Conn_FPGA_G28' U1-G28 # IO_L15P_T2L_N4_AD11P_70 NET 'No_Conn_FPGA_F28' U1-F28 # IO_L15N_T2L_N5_AD11N_70 NET 'No_Conn_FPGA_J27' U1-J27 # IO_L14P_T2L_N2_GC_70 NET 'No_Conn_FPGA_H27' U1-H27 # IO_L14N_T2L_N3_GC_70 NET 'No_Conn_FPGA_G27' U1-G27 # IO_T2U_N12_70 NET 'No_Conn_FPGA_H28' U1-H28 # IO_L13P_T2L_N0_GC_QBC_70 NET 'No_Conn_FPGA_H29' U1-H29 # IO_L13N_T2L_N1_GC_QBC_70 NET 'No_Conn_FPGA_K29' U1-K29 # IO_L12P_T1U_N10_GC_70 NET 'No_Conn_FPGA_J29' U1-J29 # IO_L12N_T1U_N11_GC_70 NET 'No_Conn_FPGA_L26' U1-L26 # IO_T1U_N12_70 NET 'No_Conn_FPGA_K27' U1-K27 # IO_L11P_T1U_N8_GC_70 NET 'No_Conn_FPGA_K28' U1-K28 # IO_L11N_T1U_N9_GC_70 NET 'No_Conn_FPGA_K26' U1-K26 # IO_L10P_T1U_N6_QBC_AD4P_70 NET 'No_Conn_FPGA_J26' U1-J26 # IO_L10N_T1U_N7_QBC_AD4N_70 NET 'No_Conn_FPGA_L28' U1-L28 # IO_L9P_T1L_N4_AD12P_70 NET 'No_Conn_FPGA_L29' U1-L29 # IO_L9N_T1L_N5_AD12N_70 NET 'No_Conn_FPGA_N27' U1-N27 # IO_L8P_T1L_N2_AD5P_70 NET 'No_Conn_FPGA_M27' U1-M27 # IO_L8N_T1L_N3_AD5N_70 NET 'No_Conn_FPGA_N28' U1-N28 # IO_L7P_T1L_N0_QBC_AD13P_70 NET 'No_Conn_FPGA_M28' U1-M28 # IO_L7N_T1L_N1_QBC_AD13N_70 NET 'No_Conn_FPGA_M30' U1-M30 # IO_L6P_T0U_N10_AD6P_70 NET 'No_Conn_FPGA_L30' U1-L30 # IO_L6N_T0U_N11_AD6N_70 NET 'No_Conn_FPGA_K31' U1-K31 # IO_L5P_T0U_N8_AD14P_70 NET 'No_Conn_FPGA_J31' U1-J31 # IO_L5N_T0U_N9_AD14N_70 NET 'No_Conn_FPGA_N29' U1-N29 # IO_L4P_T0U_N6_DBC_AD7P_70 NET 'No_Conn_FPGA_N30' U1-N30 # IO_L4N_T0U_N7_DBC_AD7N_70 NET 'No_Conn_FPGA_K32' U1-K32 # IO_L3P_T0L_N4_AD15P_70 NET 'No_Conn_FPGA_J32' U1-J32 # IO_L3N_T0L_N5_AD15N_70 NET 'No_Conn_FPGA_N32' U1-N32 # IO_L2P_T0L_N2_70 NET 'No_Conn_FPGA_M32' U1-M32 # IO_L2N_T0L_N3_70 NET 'No_Conn_FPGA_J30' U1-J30 # IO_T0U_N12_VRP_70 NET 'No_Conn_FPGA_M31' U1-M31 # IO_L1P_T0L_N0_DBC_70 NET 'No_Conn_FPGA_L31' U1-L31 # IO_L1N_T0L_N1_DBC_70 NET 'No_Conn_FPGA_P27' U1-P27 # VREF_70 # # UnConnected pins in Select I/O Bank 71. # # 1V8 HP I/O Bank # NET 'No_Conn_FPGA_G21' U1-G21 # IO_L18P_T2U_N10_AD2P_71 NET 'No_Conn_FPGA_F21' U1-F21 # IO_L18N_T2U_N11_AD2N_71 NET 'No_Conn_FPGA_F24' U1-F24 # IO_L17P_T2U_N8_AD10P_71 NET 'No_Conn_FPGA_F23' U1-F23 # IO_L16P_T2U_N6_QBC_AD3P_71 NET 'No_Conn_FPGA_G25' U1-G25 # IO_L15P_T2L_N4_AD11P_71 NET 'No_Conn_FPGA_F25' U1-F25 # IO_L15N_T2L_N5_AD11N_71 NET 'No_Conn_FPGA_H22' U1-H22 # IO_L13P_T2L_N0_GC_QBC_71 NET 'No_Conn_FPGA_G22' U1-G22 # IO_L13N_T2L_N1_GC_QBC_71 NET 'No_Conn_FPGA_L25' U1-L25 # IO_T1U_N12_71 NET 'No_Conn_FPGA_K21' U1-K21 # IO_L10P_T1U_N6_QBC_AD4P_71 NET 'No_Conn_FPGA_J21' U1-J21 # IO_L10N_T1U_N7_QBC_AD4N_71 NET 'No_Conn_FPGA_J25' U1-J25 # IO_L9P_T1L_N4_AD12P_71 NET 'No_Conn_FPGA_H25' U1-H25 # IO_L9N_T1L_N5_AD12N_71 NET 'No_Conn_FPGA_L23' U1-L23 # IO_L8P_T1L_N2_AD5P_71 NET 'No_Conn_FPGA_K23' U1-K23 # IO_L8N_T1L_N3_AD5N_71 NET 'No_Conn_FPGA_L24' U1-L24 # IO_L7P_T1L_N0_QBC_AD13P_71 NET 'No_Conn_FPGA_K24' U1-K24 # IO_L7N_T1L_N1_QBC_AD13N_71 NET 'No_Conn_FPGA_M21' U1-M21 # IO_L6P_T0U_N10_AD6P_71 NET 'No_Conn_FPGA_L21' U1-L21 # IO_L6N_T0U_N11_AD6N_71 NET 'No_Conn_FPGA_P25' U1-P25 # IO_L5P_T0U_N8_AD14P_71 NET 'No_Conn_FPGA_N25' U1-N25 # IO_L5N_T0U_N9_AD14N_71 NET 'No_Conn_FPGA_N22' U1-N22 # IO_L4P_T0U_N6_DBC_AD7P_71 NET 'No_Conn_FPGA_M22' U1-M22 # IO_L4N_T0U_N7_DBC_AD7N_71 NET 'No_Conn_FPGA_M26' U1-M26 # IO_L3P_T0L_N4_AD15P_71 NET 'No_Conn_FPGA_M25' U1-M25 # IO_L3N_T0L_N5_AD15N_71 NET 'No_Conn_FPGA_P24' U1-P24 # IO_L2P_T0L_N2_71 NET 'No_Conn_FPGA_N24' U1-N24 # IO_L2N_T0L_N3_71 NET 'No_Conn_FPGA_N23' U1-N23 # IO_L1P_T0L_N0_DBC_71 NET 'No_Conn_FPGA_M23' U1-M23 # IO_L1N_T0L_N1_DBC_71 NET 'No_Conn_FPGA_B23' U1-B23 # IO_L22N_T3U_N7_DBC_AD0N_71 NET 'No_Conn_FPGA_C23' U1-C23 # IO_L22P_T3U_N6_DBC_AD0P_71 NET 'No_Conn_FPGA_C22' U1-C22 # IO_L24P_T3U_N10_71 NET 'No_Conn_FPGA_D22' U1-D22 # IO_T3U_N12_71 NET 'No_Conn_FPGA_E24' U1-E24 # IO_L17N_T2U_N9_AD10N_71 NET 'No_Conn_FPGA_D25' U1-D25 # IO_L21P_T3L_N4_AD8P_71 NET 'No_Conn_FPGA_E23' U1-E23 # IO_L16N_T2U_N7_QBC_AD3N_71 NET 'No_Conn_FPGA_D24' U1-D24 # IO_L19P_T3L_N0_DBC_AD9P_71 NET 'No_Conn_FPGA_E22' U1-E22 # IO_T2U_N12_71 # # # UnConnected pins in Select I/O Bank 72. # # 1V8 HP I/O Bank # # As of 28-Nov_2016 only 6 pins in Bank 72 are in use. # # These are pins: A18, A20, A19, A21, D20, C20. # # These pins are low current static outputs # NET 'No_Conn_FPGA_B18' U1-B18 # IO_L24P_T3U_N10_72 NET 'No_Conn_FPGA_D21' U1-D21 # IO_T3U_N12_72 NET 'No_Conn_FPGA_C19' U1-C19 # IO_L22P_T3U_N6_DBC_AD0P_72 NET 'No_Conn_FPGA_C18' U1-C18 # IO_L22N_T3U_N7_DBC_AD0N_72 NET 'No_Conn_FPGA_B21' U1-B21 # IO_L21P_T3L_N4_AD8P_72 NET 'No_Conn_FPGA_D19' U1-D19 # IO_L20N_T3L_N3_AD1N_72 NET 'No_Conn_FPGA_B20' U1-B20 # IO_L19N_T3L_N1_DBC_AD9N_72 NET 'No_Conn_FPGA_E19' U1-E19 # IO_L18P_T2U_N10_AD2P_72 NET 'No_Conn_FPGA_E18' U1-E18 # IO_L18N_T2U_N11_AD2N_72 NET 'No_Conn_FPGA_G20' U1-G20 # IO_L17P_T2U_N8_AD10P_72 NET 'No_Conn_FPGA_F20' U1-F20 # IO_L17N_T2U_N9_AD10N_72 NET 'No_Conn_FPGA_H18' U1-H18 # IO_L16P_T2U_N6_QBC_AD3P_72 NET 'No_Conn_FPGA_G18' U1-G18 # IO_L16N_T2U_N7_QBC_AD3N_72 NET 'No_Conn_FPGA_F19' U1-F19 # IO_L15P_T2L_N4_AD11P_72 NET 'No_Conn_FPGA_F18' U1-F18 # IO_L15N_T2L_N5_AD11N_72 NET 'No_Conn_FPGA_H20' U1-H20 # IO_L14P_T2L_N2_GC_72 NET 'No_Conn_FPGA_H19' U1-H19 # IO_L14N_T2L_N3_GC_72 NET 'No_Conn_FPGA_E21' U1-E21 # IO_T2U_N12_72 NET 'No_Conn_FPGA_J20' U1-J20 # IO_L13P_T2L_N0_GC_QBC_72 NET 'No_Conn_FPGA_J19' U1-J19 # IO_L13N_T2L_N1_GC_QBC_72 NET 'No_Conn_FPGA_K19' U1-K19 # IO_L12P_T1U_N10_GC_72 NET 'No_Conn_FPGA_K18' U1-K18 # IO_L12N_T1U_N11_GC_72 NET 'No_Conn_FPGA_J15' U1-J15 # IO_T1U_N12_72 NET 'No_Conn_FPGA_L19' U1-L19 # IO_L11P_T1U_N8_GC_72 NET 'No_Conn_FPGA_L18' U1-L18 # IO_L11N_T1U_N9_GC_72 NET 'No_Conn_FPGA_K16' U1-K16 # IO_L10P_T1U_N6_QBC_AD4P_72 NET 'No_Conn_FPGA_J16' U1-J16 # IO_L10N_T1U_N7_QBC_AD4N_72 NET 'No_Conn_FPGA_M20' U1-M20 # IO_L9P_T1L_N4_AD12P_72 NET 'No_Conn_FPGA_L20' U1-L20 # IO_L9N_T1L_N5_AD12N_72 NET 'No_Conn_FPGA_L16' U1-L16 # IO_L8P_T1L_N2_AD5P_72 NET 'No_Conn_FPGA_L15' U1-L15 # IO_L8N_T1L_N3_AD5N_72 NET 'No_Conn_FPGA_K17' U1-K17 # IO_L7P_T1L_N0_QBC_AD13P_72 NET 'No_Conn_FPGA_J17' U1-J17 # IO_L7N_T1L_N1_QBC_AD13N_72 NET 'No_Conn_FPGA_P17' U1-P17 # IO_L6P_T0U_N10_AD6P_72 NET 'No_Conn_FPGA_P16' U1-P16 # IO_L6N_T0U_N11_AD6N_72 NET 'No_Conn_FPGA_P20' U1-P20 # IO_L5P_T0U_N8_AD14P_72 NET 'No_Conn_FPGA_N20' U1-N20 # IO_L5N_T0U_N9_AD14N_72 NET 'No_Conn_FPGA_M16' U1-M16 # IO_L4P_T0U_N6_DBC_AD7P_72 NET 'No_Conn_FPGA_M15' U1-M15 # IO_L4N_T0U_N7_DBC_AD7N_72 NET 'No_Conn_FPGA_P19' U1-P19 # IO_L3P_T0L_N4_AD15P_72 NET 'No_Conn_FPGA_N19' U1-N19 # IO_L3N_T0L_N5_AD15N_72 NET 'No_Conn_FPGA_N17' U1-N17 # IO_L2P_T0L_N2_72 NET 'No_Conn_FPGA_M17' U1-M17 # IO_L2N_T0L_N3_72 NET 'No_Conn_FPGA_N15' U1-N15 # IO_T0U_N12_VRP_72 NET 'No_Conn_FPGA_N18' U1-N18 # IO_L1P_T0L_N0_DBC_72 NET 'No_Conn_FPGA_M18' U1-M18 # IO_L1N_T0L_N1_DBC_72 NET 'No_Conn_FPGA_P15' U1-P15 # VREF_72 # # Pins in GTY Bank 124 that are not connected. # NET 'No_Conn_FPGA_AM38' U1-AM38 # MGTYTXP3_124 GTY 0 NET 'No_Conn_FPGA_AM39' U1-AM39 # MGTYTXN3_124 GTY 0 NET 'No_Conn_FPGA_AN40' U1-AN40 # MGTYTXP2_124 GTY 0 NET 'No_Conn_FPGA_AN41' U1-AN41 # MGTYTXN2_124 GTY 0 NET 'No_Conn_FPGA_AP38' U1-AP38 # MGTYTXP1_124 GTY 0 NET 'No_Conn_FPGA_AP39' U1-AP39 # MGTYTXN1_124 GTY 0 NET 'No_Conn_FPGA_AR40' U1-AR40 # MGTYTXP0_124 GTY 0 NET 'No_Conn_FPGA_AR41' U1-AR41 # MGTYTXN0_124 GTY 0 # # Pins in GTY Bank 125 that are not connected. # NET 'No_Conn_FPGA_AH38' U1-AH38 # MGTYTXP3_125 GTY 0 NET 'No_Conn_FPGA_AH39' U1-AH39 # MGTYTXN3_125 GTY 0 NET 'No_Conn_FPGA_AJ40' U1-AJ40 # MGTYTXP2_125 GTY 0 NET 'No_Conn_FPGA_AJ41' U1-AJ41 # MGTYTXN2_125 GTY 0 NET 'No_Conn_FPGA_AK38' U1-AK38 # MGTYTXP1_125 GTY 0 NET 'No_Conn_FPGA_AK39' U1-AK39 # MGTYTXN1_125 GTY 0 NET 'No_Conn_FPGA_AL40' U1-AL40 # MGTYTXP0_125 GTY 0 NET 'No_Conn_FPGA_AL41' U1-AL41 # MGTYTXN0_125 GTY 0 # # Pins in GTY Bank 126 that are not connected. # NET 'No_Conn_FPGA_AD38' U1-AD38 # MGTYTXP3_126 GTY 0 NET 'No_Conn_FPGA_AD39' U1-AD39 # MGTYTXN3_126 GTY 0 NET 'No_Conn_FPGA_AE40' U1-AE40 # MGTYTXP2_126 GTY 0 NET 'No_Conn_FPGA_AE41' U1-AE41 # MGTYTXN2_126 GTY 0 NET 'No_Conn_FPGA_AF38' U1-AF38 # MGTYTXP1_126 GTY 0 NET 'No_Conn_FPGA_AF39' U1-AF39 # MGTYTXN1_126 GTY 0 NET 'No_Conn_FPGA_AG40' U1-AG40 # MGTYTXP0_126 GTY 0 NET 'No_Conn_FPGA_AG41' U1-AG41 # MGTYTXN0_126 GTY 0 # # Pins in GTY Bank 127 that are not connected. # NET 'No_Conn_FPGA_Y38' U1-Y38 # MGTYTXP3_127 GTY 0 NET 'No_Conn_FPGA_Y39' U1-Y39 # MGTYTXN3_127 GTY 0 NET 'No_Conn_FPGA_AB38' U1-AB38 # MGTYTXP1_127 GTY 0 NET 'No_Conn_FPGA_AB39' U1-AB39 # MGTYTXN1_127 GTY 0 # # Pins in GTY Bank 128 that are not connected. # NET 'No_Conn_FPGA_T38' U1-T38 # MGTYTXP3_128 GTY 0 NET 'No_Conn_FPGA_T39' U1-T39 # MGTYTXN3_128 GTY 0 NET 'No_Conn_FPGA_U40' U1-U40 # MGTYTXP2_128 GTY 0 NET 'No_Conn_FPGA_U41' U1-U41 # MGTYTXN2_128 GTY 0 NET 'No_Conn_FPGA_V38' U1-V38 # MGTYTXP1_128 GTY 0 NET 'No_Conn_FPGA_V39' U1-V39 # MGTYTXN1_128 GTY 0 NET 'No_Conn_FPGA_W40' U1-W40 # MGTYTXP0_128 GTY 0 NET 'No_Conn_FPGA_W41' U1-W41 # MGTYTXN0_128 GTY 0 # # Pins in GTY Bank 129 that are not connected. # NET 'No_Conn_FPGA_M38' U1-M38 # MGTYTXP3_129 GTY 1 NET 'No_Conn_FPGA_M39' U1-M39 # MGTYTXN3_129 GTY 1 NET 'No_Conn_FPGA_P38' U1-P38 # MGTYTXP1_129 GTY 1 NET 'No_Conn_FPGA_P39' U1-P39 # MGTYTXN1_129 GTY 1 # # Pins in GTY Bank 130 that are not connected. # NET 'No_Conn_FPGA_H38' U1-H38 # MGTYTXP3_130 GTY 1 NET 'No_Conn_FPGA_H39' U1-H39 # MGTYTXN3_130 GTY 1 NET 'No_Conn_FPGA_K38' U1-K38 # MGTYTXP1_130 GTY 1 NET 'No_Conn_FPGA_K39' U1-K39 # MGTYTXN1_130 GTY 1 # # Pins in GTY Bank 131 that are not connected. # NET 'No_Conn_FPGA_F34' U1-F34 # MGTYTXP3_131 GTY 1 NET 'No_Conn_FPGA_F35' U1-F35 # MGTYTXN3_131 GTY 1 NET 'No_Conn_FPGA_G36' U1-G36 # MGTYTXP2_131 GTY 1 NET 'No_Conn_FPGA_G37' U1-G37 # MGTYTXN2_131 GTY 1 NET 'No_Conn_FPGA_F38' U1-F38 # MGTYTXP1_131 GTY 1 NET 'No_Conn_FPGA_F39' U1-F39 # MGTYTXN1_131 GTY 1 NET 'No_Conn_FPGA_G40' U1-G40 # MGTYTXP0_131 GTY 1 NET 'No_Conn_FPGA_G41' U1-G41 # MGTYTXN0_131 GTY 1 # # Pins in GTY Bank 132 that are not connected. # NET 'No_Conn_FPGA_C40' U1-C40 # MGTYTXP2_132 GTY 1 NET 'No_Conn_FPGA_C41' U1-C41 # MGTYTXN2_132 GTY 1 NET 'No_Conn_FPGA_E36' U1-E36 # MGTYTXP1_132 GTY 1 NET 'No_Conn_FPGA_E37' U1-E37 # MGTYTXN1_132 GTY 1 NET 'No_Conn_FPGA_E40' U1-E40 # MGTYTXP0_132 GTY 1 NET 'No_Conn_FPGA_E41' U1-E41 # MGTYTXN0_132 GTY 1 # # Pins in GTY Bank 133 that are not connected. # NET 'No_Conn_FPGA_C36' U1-C36 # MGTYTXP1_133 GTY 1 NET 'No_Conn_FPGA_C37' U1-C37 # MGTYTXN1_133 GTY 1 NET 'No_Conn_FPGA_D38' U1-D38 # MGTYTXP0_133 GTY 1 NET 'No_Conn_FPGA_D39' U1-D39 # MGTYTXN0_133 GTY 1 # # Pins in GTH Bank 224 that are not connected. # NET 'No_Conn_FPGA_AM9' U1-AM9 # MGTHTXP3_224 GTH 0 NET 'No_Conn_FPGA_AM8' U1-AM8 # MGTHTXN3_224 GTH 0 NET 'No_Conn_FPGA_AP9' U1-AP9 # MGTHTXP1_224 GTH 0 NET 'No_Conn_FPGA_AP8' U1-AP8 # MGTHTXN1_224 GTH 0 # # Pins in GTH Bank 225 that are not connected. # NET 'No_Conn_FPGA_AH9' U1-AH9 # MGTHTXP3_225 GTH 0 NET 'No_Conn_FPGA_AH8' U1-AH8 # MGTHTXN3_225 GTH 0 NET 'No_Conn_FPGA_AK9' U1-AK9 # MGTHTXP1_225 GTH 0 NET 'No_Conn_FPGA_AK8' U1-AK8 # MGTHTXN1_225 GTH 0 # # Pins in GTH Bank 226 that are not connected. # NET 'No_Conn_FPGA_AD9' U1-AD9 # MGTHTXP3_226 GTH 0 NET 'No_Conn_FPGA_AD8' U1-AD8 # MGTHTXN3_226 GTH 0 NET 'No_Conn_FPGA_AF9' U1-AF9 # MGTHTXP1_226 GTH 0 NET 'No_Conn_FPGA_AF8' U1-AF8 # MGTHTXN1_226 GTH 0 # # Pins in GTH Bank 227 that are not connected. # NET 'No_Conn_FPGA_Y9' U1-Y9 # MGTHTXP3_227 GTH 0 NET 'No_Conn_FPGA_Y8' U1-Y8 # MGTHTXN3_227 GTH 0 NET 'No_Conn_FPGA_AB9' U1-AB9 # MGTHTXP1_227 GTH 0 NET 'No_Conn_FPGA_AB8' U1-AB8 # MGTHTXN1_227 GTH 0 # # Pins in GTH Bank 228 that are not connected. # NET 'No_Conn_FPGA_T9' U1-T9 # MGTHTXP3_228 GTH 0 NET 'No_Conn_FPGA_T8' U1-T8 # MGTHTXN3_228 GTH 0 NET 'No_Conn_FPGA_V9' U1-V9 # MGTHTXP1_228 GTH 0 NET 'No_Conn_FPGA_V8' U1-V8 # MGTHTXN1_228 GTH 0 # # Pins in GTH Bank 229 that are not connected. # NET 'No_Conn_FPGA_M9' U1-M9 # MGTHTXP3_229 GTH 1 NET 'No_Conn_FPGA_M8' U1-M8 # MGTHTXN3_229 GTH 1 NET 'No_Conn_FPGA_P9' U1-P9 # MGTHTXP1_229 GTH 1 NET 'No_Conn_FPGA_P8' U1-P8 # MGTHTXN1_229 GTH 1 # # Pins in GTH Bank 230 that are not connected. # NET 'No_Conn_FPGA_H9' U1-H9 # MGTHTXP3_230 GTH 1 NET 'No_Conn_FPGA_H8' U1-H8 # MGTHTXN3_230 GTH 1 NET 'No_Conn_FPGA_K9' U1-K9 # MGTHTXP1_230 GTH 1 NET 'No_Conn_FPGA_K8' U1-K8 # MGTHTXN1_230 GTH 1 # # Pins in GTH Bank 231 that are not connected. # NET 'No_Conn_FPGA_F13' U1-F13 # MGTHTXP3_231 GTH 1 NET 'No_Conn_FPGA_F12' U1-F12 # MGTHTXN3_231 GTH 1 NET 'No_Conn_FPGA_G11' U1-G11 # MGTHTXP2_231 GTH 1 NET 'No_Conn_FPGA_G10' U1-G10 # MGTHTXN2_231 GTH 1 NET 'No_Conn_FPGA_F9' U1-F9 # MGTHTXP1_231 GTH 1 NET 'No_Conn_FPGA_F8' U1-F8 # MGTHTXN1_231 GTH 1 NET 'No_Conn_FPGA_G7' U1-G7 # MGTHTXP0_231 GTH 1 NET 'No_Conn_FPGA_G6' U1-G6 # MGTHTXN0_231 GTH 1 # # Pins in GTH Bank 232 that are not connected. # NET 'No_Conn_FPGA_C7' U1-C7 # MGTHTXP2_232 GTH 1 NET 'No_Conn_FPGA_C6' U1-C6 # MGTHTXN2_232 GTH 1 NET 'No_Conn_FPGA_E11' U1-E11 # MGTHTXP1_232 GTH 1 NET 'No_Conn_FPGA_E10' U1-E10 # MGTHTXN1_232 GTH 1 NET 'No_Conn_FPGA_E7' U1-E7 # MGTHTXP0_232 GTH 1 NET 'No_Conn_FPGA_E6' U1-E6 # MGTHTXN0_232 GTH 1 # # Pins in GTH Bank 233 that are not connected. # NET 'No_Conn_FPGA_C11' U1-C11 # MGTHTXP1_233 GTH 1 NET 'No_Conn_FPGA_C10' U1-C10 # MGTHTXN1_233 GTH 1 NET 'No_Conn_FPGA_D9' U1-D9 # MGTHTXP0_233 GTH 1 NET 'No_Conn_FPGA_D8' U1-D8 # MGTHTXN0_233 GTH 1 # # MGT Transceiver Reference Clock pins that are not connected. # NET 'No_Conn_FPGA_AF34' U1-AF34 # MGTREFCLK1P_124 GTY 0 NET 'No_Conn_FPGA_AF35' U1-AF35 # MGTREFCLK1N_124 GTY 0 NET 'No_Conn_FPGA_AG36' U1-AG36 # MGTREFCLK0P_124 GTY 0 NET 'No_Conn_FPGA_AG37' U1-AG37 # MGTREFCLK0N_124 GTY 0 NET 'No_Conn_FPGA_AD34' U1-AD34 # MGTREFCLK1P_125 GTY 0 NET 'No_Conn_FPGA_AD35' U1-AD35 # MGTREFCLK1N_125 GTY 0 NET 'No_Conn_FPGA_AB34' U1-AB34 # MGTREFCLK1P_126 GTY 0 NET 'No_Conn_FPGA_AB35' U1-AB35 # MGTREFCLK1N_126 GTY 0 NET 'No_Conn_FPGA_AC36' U1-AC36 # MGTREFCLK0P_126 GTY 0 NET 'No_Conn_FPGA_AC37' U1-AC37 # MGTREFCLK0N_126 GTY 0 NET 'No_Conn_FPGA_AA36' U1-AA36 # MGTREFCLK0P_127 GTY 0 NET 'No_Conn_FPGA_AA37' U1-AA37 # MGTREFCLK0N_127 GTY 0 NET 'No_Conn_FPGA_V34' U1-V34 # MGTREFCLK1P_128 GTY 0 NET 'No_Conn_FPGA_V35' U1-V35 # MGTREFCLK1N_128 GTY 0 NET 'No_Conn_FPGA_W36' U1-W36 # MGTREFCLK0P_128 GTY 0 NET 'No_Conn_FPGA_W37' U1-W37 # MGTREFCLK0N_128 GTY 0 NET 'No_Conn_FPGA_T34' U1-T34 # MGTREFCLK1P_129 GTY 1 NET 'No_Conn_FPGA_T35' U1-T35 # MGTREFCLK1N_129 GTY 1 NET 'No_Conn_FPGA_U36' U1-U36 # MGTREFCLK0P_129 GTY 1 NET 'No_Conn_FPGA_U37' U1-U37 # MGTREFCLK0N_129 GTY 1 NET 'No_Conn_FPGA_P34' U1-P34 # MGTREFCLK1P_130 GTY 1 NET 'No_Conn_FPGA_P35' U1-P35 # MGTREFCLK1N_130 GTY 1 NET 'No_Conn_FPGA_M34' U1-M34 # MGTREFCLK1P_131 GTY 1 NET 'No_Conn_FPGA_M35' U1-M35 # MGTREFCLK1N_131 GTY 1 NET 'No_Conn_FPGA_N36' U1-N36 # MGTREFCLK0P_131 GTY 1 NET 'No_Conn_FPGA_N37' U1-N37 # MGTREFCLK0N_131 GTY 1 NET 'No_Conn_FPGA_L36' U1-L36 # MGTREFCLK0P_132 GTY 1 NET 'No_Conn_FPGA_L37' U1-L37 # MGTREFCLK0N_132 GTY 1 NET 'No_Conn_FPGA_H34' U1-H34 # MGTREFCLK1P_133 GTY 1 NET 'No_Conn_FPGA_H35' U1-H35 # MGTREFCLK1N_133 GTY 1 NET 'No_Conn_FPGA_J36' U1-J36 # MGTREFCLK0P_133 GTY 1 NET 'No_Conn_FPGA_J37' U1-J37 # MGTREFCLK0N_133 GTY 1 NET 'No_Conn_FPGA_AF13' U1-AF13 # MGTREFCLK1P_224 GTH 0 NET 'No_Conn_FPGA_AF12' U1-AF12 # MGTREFCLK1N_224 GTH 0 NET 'No_Conn_FPGA_AG11' U1-AG11 # MGTREFCLK0P_224 GTH 0 NET 'No_Conn_FPGA_AG10' U1-AG10 # MGTREFCLK0N_224 GTH 0 NET 'No_Conn_FPGA_AD13' U1-AD13 # MGTREFCLK1P_225 GTH 0 NET 'No_Conn_FPGA_AD12' U1-AD12 # MGTREFCLK1N_225 GTH 0 NET 'No_Conn_FPGA_AB13' U1-AB13 # MGTREFCLK1P_226 GTH 0 NET 'No_Conn_FPGA_AB12' U1-AB12 # MGTREFCLK1N_226 GTH 0 NET 'No_Conn_FPGA_AC11' U1-AC11 # MGTREFCLK0P_226 GTH 0 NET 'No_Conn_FPGA_AC10' U1-AC10 # MGTREFCLK0N_226 GTH 0 NET 'No_Conn_FPGA_AA11' U1-AA11 # MGTREFCLK0P_227 GTH 0 NET 'No_Conn_FPGA_AA10' U1-AA10 # MGTREFCLK0N_227 GTH 0 NET 'No_Conn_FPGA_V13' U1-V13 # MGTREFCLK1P_228 GTH 0 NET 'No_Conn_FPGA_V12' U1-V12 # MGTREFCLK1N_228 GTH 0 NET 'No_Conn_FPGA_W11' U1-W11 # MGTREFCLK0P_228 GTH 0 NET 'No_Conn_FPGA_W10' U1-W10 # MGTREFCLK0N_228 GTH 0 NET 'No_Conn_FPGA_T13' U1-T13 # MGTREFCLK1P_229 GTH 1 NET 'No_Conn_FPGA_T12' U1-T12 # MGTREFCLK1N_229 GTH 1 NET 'No_Conn_FPGA_U11' U1-U11 # MGTREFCLK0P_229 GTH 1 NET 'No_Conn_FPGA_U10' U1-U10 # MGTREFCLK0N_229 GTH 1 NET 'No_Conn_FPGA_P13' U1-P13 # MGTREFCLK1P_230 GTH 1 NET 'No_Conn_FPGA_P12' U1-P12 # MGTREFCLK1N_230 GTH 1 NET 'No_Conn_FPGA_M13' U1-M13 # MGTREFCLK1P_231 GTH 1 NET 'No_Conn_FPGA_M12' U1-M12 # MGTREFCLK1N_231 GTH 1 NET 'No_Conn_FPGA_N11' U1-N11 # MGTREFCLK0P_231 GTH 1 NET 'No_Conn_FPGA_N10' U1-N10 # MGTREFCLK0N_231 GTH 1 NET 'No_Conn_FPGA_L11' U1-L11 # MGTREFCLK0P_232 GTH 1 NET 'No_Conn_FPGA_L10' U1-L10 # MGTREFCLK0N_232 GTH 1 NET 'No_Conn_FPGA_H13' U1-H13 # MGTREFCLK1P_233 GTH 1 NET 'No_Conn_FPGA_H12' U1-H12 # MGTREFCLK1N_233 GTH 1 NET 'No_Conn_FPGA_J11' U1-J11 # MGTREFCLK0P_233 GTH 1 NET 'No_Conn_FPGA_J10' U1-J10 # MGTREFCLK0N_233 GTH 1 # # Pins in that really are just not connected to anything # on the XCVU125 in the FLVC2104 package. 128 of them. # NET 'No_Conn_FPGA_A8' U1-A8 NET 'No_Conn_FPGA_A9' U1-A9 NET 'No_Conn_FPGA_A38' U1-A38 NET 'No_Conn_FPGA_A39' U1-A39 NET 'No_Conn_FPGA_BD39' U1-BD39 NET 'No_Conn_FPGA_BD38' U1-BD38 NET 'No_Conn_FPGA_BD43' U1-BD43 NET 'No_Conn_FPGA_BD44' U1-BD44 NET 'No_Conn_FPGA_AM35' U1-AM35 NET 'No_Conn_FPGA_AM34' U1-AM34 NET 'No_Conn_FPGA_BE41' U1-BE41 NET 'No_Conn_FPGA_BE40' U1-BE40 NET 'No_Conn_FPGA_BF43' U1-BF43 NET 'No_Conn_FPGA_BF44' U1-BF44 NET 'No_Conn_FPGA_BD36' U1-BD36 NET 'No_Conn_FPGA_BD37' U1-BD37 NET 'No_Conn_FPGA_BE37' U1-BE37 NET 'No_Conn_FPGA_BE36' U1-BE36 NET 'No_Conn_FPGA_BD33' U1-BD33 NET 'No_Conn_FPGA_BD34' U1-BD34 NET 'No_Conn_FPGA_AN37' U1-AN37 NET 'No_Conn_FPGA_AN36' U1-AN36 NET 'No_Conn_FPGA_BF39' U1-BF39 NET 'No_Conn_FPGA_BF38' U1-BF38 NET 'No_Conn_FPGA_BF33' U1-BF33 NET 'No_Conn_FPGA_BF34' U1-BF34 NET 'No_Conn_FPGA_AY39' U1-AY39 NET 'No_Conn_FPGA_AY38' U1-AY38 NET 'No_Conn_FPGA_AY43' U1-AY43 NET 'No_Conn_FPGA_AY44' U1-AY44 NET 'No_Conn_FPGA_AK35' U1-AK35 NET 'No_Conn_FPGA_AK34' U1-AK34 NET 'No_Conn_FPGA_BA41' U1-BA41 NET 'No_Conn_FPGA_BA40' U1-BA40 NET 'No_Conn_FPGA_BA45' U1-BA45 NET 'No_Conn_FPGA_BA46' U1-BA46 NET 'No_Conn_FPGA_BB39' U1-BB39 NET 'No_Conn_FPGA_BB38' U1-BB38 NET 'No_Conn_FPGA_BB43' U1-BB43 NET 'No_Conn_FPGA_BB44' U1-BB44 NET 'No_Conn_FPGA_AL37' U1-AL37 NET 'No_Conn_FPGA_AL36' U1-AL36 NET 'No_Conn_FPGA_BC41' U1-BC41 NET 'No_Conn_FPGA_BC40' U1-BC40 NET 'No_Conn_FPGA_BC45' U1-BC45 NET 'No_Conn_FPGA_BC46' U1-BC46 NET 'No_Conn_FPGA_AT39' U1-AT39 NET 'No_Conn_FPGA_AT38' U1-AT38 NET 'No_Conn_FPGA_AT43' U1-AT43 NET 'No_Conn_FPGA_AT44' U1-AT44 NET 'No_Conn_FPGA_AH35' U1-AH35 NET 'No_Conn_FPGA_AH34' U1-AH34 NET 'No_Conn_FPGA_AU41' U1-AU41 NET 'No_Conn_FPGA_AU40' U1-AU40 NET 'No_Conn_FPGA_AU45' U1-AU45 NET 'No_Conn_FPGA_AU46' U1-AU46 NET 'No_Conn_FPGA_AV39' U1-AV39 NET 'No_Conn_FPGA_AV38' U1-AV38 NET 'No_Conn_FPGA_AV43' U1-AV43 NET 'No_Conn_FPGA_AV44' U1-AV44 NET 'No_Conn_FPGA_AJ37' U1-AJ37 NET 'No_Conn_FPGA_AJ36' U1-AJ36 NET 'No_Conn_FPGA_AW41' U1-AW41 NET 'No_Conn_FPGA_AW40' U1-AW40 NET 'No_Conn_FPGA_AW45' U1-AW45 NET 'No_Conn_FPGA_AW46' U1-AW46 NET 'No_Conn_FPGA_BD9' U1-BD9 NET 'No_Conn_FPGA_BD4' U1-BD4 NET 'No_Conn_FPGA_BD3' U1-BD3 NET 'No_Conn_FPGA_BD8' U1-BD8 NET 'No_Conn_FPGA_AM13' U1-AM13 NET 'No_Conn_FPGA_AM12' U1-AM12 NET 'No_Conn_FPGA_BE7' U1-BE7 NET 'No_Conn_FPGA_BF4' U1-BF4 NET 'No_Conn_FPGA_BF3' U1-BF3 NET 'No_Conn_FPGA_BE6' U1-BE6 NET 'No_Conn_FPGA_BE11' U1-BE11 NET 'No_Conn_FPGA_BD14' U1-BD14 NET 'No_Conn_FPGA_BD13' U1-BD13 NET 'No_Conn_FPGA_BE10' U1-BE10 NET 'No_Conn_FPGA_AN11' U1-AN11 NET 'No_Conn_FPGA_AN10' U1-AN10 NET 'No_Conn_FPGA_BF9' U1-BF9 NET 'No_Conn_FPGA_BF14' U1-BF14 NET 'No_Conn_FPGA_BF13' U1-BF13 NET 'No_Conn_FPGA_BF8' U1-BF8 NET 'No_Conn_FPGA_AY9' U1-AY9 NET 'No_Conn_FPGA_AY4' U1-AY4 NET 'No_Conn_FPGA_AY3' U1-AY3 NET 'No_Conn_FPGA_AY8' U1-AY8 NET 'No_Conn_FPGA_AK13' U1-AK13 NET 'No_Conn_FPGA_AK12' U1-AK12 NET 'No_Conn_FPGA_BA7' U1-BA7 NET 'No_Conn_FPGA_BA2' U1-BA2 NET 'No_Conn_FPGA_BA1' U1-BA1 NET 'No_Conn_FPGA_BA6' U1-BA6 NET 'No_Conn_FPGA_BD10' U1-BD10 NET 'No_Conn_FPGA_BD11' U1-BD11 NET 'No_Conn_FPGA_BB9' U1-BB9 NET 'No_Conn_FPGA_BB4' U1-BB4 NET 'No_Conn_FPGA_BB3' U1-BB3 NET 'No_Conn_FPGA_BB8' U1-BB8 NET 'No_Conn_FPGA_AL11' U1-AL11 NET 'No_Conn_FPGA_AL10' U1-AL10 NET 'No_Conn_FPGA_BC7' U1-BC7 NET 'No_Conn_FPGA_BC2' U1-BC2 NET 'No_Conn_FPGA_BC1' U1-BC1 NET 'No_Conn_FPGA_BC6' U1-BC6 NET 'No_Conn_FPGA_AT9' U1-AT9 NET 'No_Conn_FPGA_AT4' U1-AT4 NET 'No_Conn_FPGA_AT3' U1-AT3 NET 'No_Conn_FPGA_AT8' U1-AT8 NET 'No_Conn_FPGA_AH13' U1-AH13 NET 'No_Conn_FPGA_AH12' U1-AH12 NET 'No_Conn_FPGA_AU7' U1-AU7 NET 'No_Conn_FPGA_AU2' U1-AU2 NET 'No_Conn_FPGA_AU1' U1-AU1 NET 'No_Conn_FPGA_AU6' U1-AU6 NET 'No_Conn_FPGA_AV9' U1-AV9 NET 'No_Conn_FPGA_AV4' U1-AV4 NET 'No_Conn_FPGA_AV3' U1-AV3 NET 'No_Conn_FPGA_AV8' U1-AV8 NET 'No_Conn_FPGA_AJ11' U1-AJ11 NET 'No_Conn_FPGA_AJ10' U1-AJ10 NET 'No_Conn_FPGA_AW7' U1-AW7 NET 'No_Conn_FPGA_AW2' U1-AW2 NET 'No_Conn_FPGA_AW1' U1-AW1 NET 'No_Conn_FPGA_AW6' U1-AW6 # # Ultra FPGA to U21 U22 Phys Chips Nets # ------------------------------------------ # # Initial Rev. 17-Sept-2015 # Current Rev. 22-Dec-2016 # # # This file holds all of the connections between the Hub's # FPGA and the U21 U22 Phys Chips. # # The 16 connections per Phys chip are: # # - RGMII data and clock Phys Chip --> FPGA 6 lines # # - RGMII data and clock FPGA --> Phys Chip 6 lines # # - MDC MDIO Management FPGA <--> Phys Chip 2 lines # # - Miscellaneous 2 lines # 125 MHz Clk Phys Chip --> FPGA # Interrupt Phys Chip --> FPGA # # # # *** Connection to/from the U21 Phys Chip *** # *** *** # *** with Select I/O Bank 68 *** # # # # RGMII Bus connections to U21 Phys Chip # NET 'Phys_U21_RXD0__MODE0' U1-BC31 # Output from FPGA IO_L23P_T3U_N8_68 NET 'Phys_U21_RXD1__MODE1' U1-AY32 # Input to FPGA IO_L15P_T2L_N4_AD11P_68 NET 'Phys_U21_RXD2__MODE2' U1-BB33 # Input to FPGA IO_L17N_T2U_N9_AD10N_68 NET 'Phys_U21_RXD3__MODE3' U1-AY33 # Input to FPGA IO_L14N_T2L_N3_GC_68 NET 'Phys_U21_RX_DV__CLK125_EN' U1-BB31 # Input to FPGA IO_L21N_T3L_N5_AD8N_68 NET 'Phys_U21_RX_CLK__PHYAD2' U1-AV33 # Input to FPGA IO_L11P_T1U_N8_GC_68 NET 'Phys_U21_TXD0' U1-BA36 # Output from FPGA IO_L18P_T2U_N10_AD2P_68 NET 'Phys_U21_TXD1' U1-AY35 # Output from FPGA IO_L13N_T2L_N1_GC_QBC_68 NET 'Phys_U21_TXD2' U1-BB36 # Output from FPGA IO_L18N_T2U_N11_AD2N_68 NET 'Phys_U21_TXD3' U1-BA35 # Output from FPGA IO_T2U_N12_68 NET 'Phys_U21_TX_EN' U1-BB34 # Output from FPGA IO_L16N_T2U_N7_QBC_AD3N_68 NET 'Phys_U21_GTX_CLK' U1-BA34 # Output from FPGA IO_L16P_T2U_N6_QBC_AD3P_68 # # Management Bus connections to U21 Phys Chip # NET 'Phys_U21_MDC' U1-BB32 # Input to FPGA IO_L17P_T2U_N8_AD10P_68 NET 'Phys_U21_MDIO' U1-BA30 # FPGA Input/Output IO_T3U_N12_68 # # Miscellaneous connections to U21 Phys Chip # NET 'Phys_U21_CLK125__LED_MODE' U1-AU33 # Input to FPGA IO_L12P_T1U_N10_GC_68 NET 'Phys_U21_INT_B' U1-BC30 # Input to FPGA IO_L19N_T3L_N1_DBC_AD9N_68 # # # *** Connection to/from the U22 Phys Chip *** # *** *** # *** with Select I/O Bank 68 *** # # # # RGMII Bus connections to U22 Phys Chip # NET 'Phys_U22_RXD0__MODE0' U1-AV35 # Input to FPGA IO_L9P_T1L_N4_AD12P_68 NET 'Phys_U22_RXD1__MODE1' U1-AV36 # Input to FPGA IO_L10P_T1U_N6_QBC_AD4P_68 NET 'Phys_U22_RXD2__MODE2' U1-AV34 # Input to FPGA IO_L11N_T1U_N9_GC_68 NET 'Phys_U22_RXD3__MODE3' U1-AU32 # Input to FPGA IO_L8N_T1L_N3_AD5N_68 NET 'Phys_U22_RX_DV__CLK125_EN' U1-AW32 # Input to FPGA IO_T1U_N12_68 NET 'Phys_U22_RX_CLK__PHYAD2' U1-AW33 # Input to FPGA IO_L14P_T2L_N2_GC_68 NET 'Phys_U22_TXD0' U1-AR36 # Output from FPGA IO_L6P_T0U_N10_AD6P_68 NET 'Phys_U22_TXD1' U1-AT36 # Output from FPGA IO_L6N_T0U_N11_AD6N_68 NET 'Phys_U22_TXD2' U1-AR35 # Output from FPGA IO_L4P_T0U_N6_DBC_AD7P_68 NET 'Phys_U22_TXD3' U1-AT35 # Output from FPGA IO_L4N_T0U_N7_DBC_AD7N_68 NET 'Phys_U22_TX_EN' U1-AU34 # Output from FPGA IO_L12N_T1U_N11_GC_68 NET 'Phys_U22_GTX_CLK' U1-AT34 # Output from FPGA IO_L2N_T0L_N3_68 # # Management Bus connections to U22 Phys Chip # NET 'Phys_U22_MDC' U1-AW36 # Input to FPGA IO_L10N_T1U_N7_QBC_AD4N_68 NET 'Phys_U22_MDIO' U1-AW35 # FPGA Input/Output IO_L9N_T1L_N5_AD12N_68 # # Miscellaneous connections to U22 Phys Chip # NET 'Phys_U22_CLK125__LED_MODE' U1-AY34 # Input to FPGA IO_L13P_T2L_N0_GC_QBC_68 NET 'Phys_U22_INT_B' U1-BA31 # Input to FPGA IO_L21P_T3L_N4_AD8P_68 # # Ethernet Phys Chip U21 & U22 Power and Ground Nets # ------------------------------------------------------ # # # Original Rev. 10-Sept-2015 # Current Rev. 21-Apr-2016 # # # This file holds all of the Power and Ground connections to the # Hub's Ethernet Phys Chips, U21 & U22, Micrel KSZ9031RNX. # # # The Power and Ground connections held in this nets file # for each of the KSZ9031RNX Physc Chips are the following: # # # Grounds 5x pins: 29, and Exposed Thermal Pad pins 49, 50, 51, 52 # # # AVDDH pins: 1, 12 from BULK_3V3 # # AVDDL pins: 4, 9 from SWCH_1V2 # # AVDD_PLL pins: 44 from SWCH_1V2 # # DVDDH pins: 16, 34, 40 from BULK_1V8 # # DVDDL pins: 14, 18, 23, 26, 30, 39 from SWCH_1V2 # # # # ***** U21 Phys Chip Power and Ground Connections ***** # # # U21 Supplies that come from the SWCH_1V2 bus # NET 'SWCH_1V2' C1901-1 C1902-1 C1903-1 NET 'GROUND' C1901-2 C1902-2 C1903-2 NET 'SWCH_1V2' L1901-1 L1902-1 L1903-1 NET 'Phys_U21_AVDDL' L1901-2 C1906-1 C1911-1 C1912-1 NET 'GROUND' C1906-2 C1911-2 C1912-2 NET 'Phys_U21_AVDDL' U21-4 U21-9 NET 'Phys_U21_AVDD_PLL' L1902-2 C1907-1 C1913-1 U21-44 NET 'GROUND' C1907-2 C1913-2 NET 'Phys_U21_DVDDL' L1903-2 C1908-1 C1914-1 C1915-1 NET 'GROUND' C1908-2 C1914-2 C1915-2 NET 'Phys_U21_DVDDL' C1916-1 C1917-1 C1918-1 C1919-1 NET 'GROUND' C1916-2 C1917-2 C1918-2 C1919-2 NET 'Phys_U21_DVDDL' U21-14 U21-18 U21-23 NET 'Phys_U21_DVDDL' U21-26 U21-30 U21-39 # # U21 Supply that come from the BULK_1V8 bus # NET 'BULK_1V8' C1904-1 NET 'GROUND' C1904-2 NET 'BULK_1V8' L1904-1 NET 'Phys_U21_DVDDH' L1904-2 C1909-1 C1920-1 C1921-1 C1922-1 NET 'GROUND' C1909-2 C1920-2 C1921-2 C1922-2 NET 'Phys_U21_DVDDH' U21-16 U21-34 U21-40 # # U21 Supply that come from the BULK_3V3 bus # NET 'BULK_3V3' C1905-1 NET 'GROUND' C1905-2 NET 'BULK_3V3' L1905-1 NET 'Phys_U21_AVDDH' L1905-2 C1910-1 C1923-1 C1924-1 NET 'GROUND' C1910-2 C1923-2 C1924-2 NET 'Phys_U21_AVDDH' U21-1 U21-12 # # U21 GROUND Connections # NET 'GROUND' U21-29 U21-49 U21-50 U21-51 U21-52 # # ***** U22 Phys Chip Power and Ground Connections ***** # # # U22 Supplies that come from the SWCH_1V2 bus # NET 'SWCH_1V2' C1951-1 C1952-1 C1953-1 NET 'GROUND' C1951-2 C1952-2 C1953-2 NET 'SWCH_1V2' L1951-1 L1952-1 L1953-1 NET 'Phys_U22_AVDDL' L1951-2 C1956-1 C1961-1 C1962-1 NET 'GROUND' C1956-2 C1961-2 C1962-2 NET 'Phys_U22_AVDDL' U22-4 U22-9 NET 'Phys_U22_AVDD_PLL' L1952-2 C1957-1 C1963-1 U22-44 NET 'GROUND' C1957-2 C1963-2 NET 'Phys_U22_DVDDL' L1953-2 C1958-1 C1964-1 C1965-1 NET 'GROUND' C1958-2 C1964-2 C1965-2 NET 'Phys_U22_DVDDL' C1966-1 C1967-1 C1968-1 C1969-1 NET 'GROUND' C1966-2 C1967-2 C1968-2 C1969-2 NET 'Phys_U22_DVDDL' U22-14 U22-18 U22-23 NET 'Phys_U22_DVDDL' U22-26 U22-30 U22-39 # # U22 Supply that come from the BULK_1V8 bus # NET 'BULK_1V8' C1954-1 NET 'GROUND' C1954-2 NET 'BULK_1V8' L1954-1 NET 'Phys_U22_DVDDH' L1954-2 C1959-1 C1970-1 C1971-1 C1972-1 NET 'GROUND' C1959-2 C1970-2 C1971-2 C1972-2 NET 'Phys_U22_DVDDH' U22-16 U22-34 U22-40 # # U22 Supply that come from the BULK_3V3 bus # NET 'BULK_3V3' C1955-1 NET 'GROUND' C1955-2 NET 'BULK_3V3' L1955-1 NET 'Phys_U22_AVDDH' L1955-2 C1960-1 C1973-1 C1974-1 NET 'GROUND' C1960-2 C1973-2 C1974-2 NET 'Phys_U22_AVDDH' U22-1 U22-12 # # U22 GROUND Connections # NET 'GROUND' U22-29 U22-49 U22-50 U22-51 U22-52 # # Ethernet Phys Chip U21 Signal Nets # ------------------------------------------ # # # Original Rev. 11-Sept-2015 # Current Rev. 31-May-2015 # # # This file holds all of the signal nets for the U21 Phys Chip. # # These are the nets for the U21 Micrel KSZ9031RNX # Phys Chip which carries Ethernet from This Hub's FPGA # to the ADF Backplane Connectors and then over the # ATCA UpDate Channel to the Other Hub's Ethernet Switch. # # # This FPGA --> U21 Phys --> TRANS 4 Magnets --> J20 Backplane Connector # # # *** U21 Phys Chip Nets to its TRANS4 Magnetics *** # # These nets are held in the netsfile: switch_chips_to_adf_conn_nets # # # *** U21 Phys Chip Nets to its Front Panel LEDs *** # # These nets are held in the netsfile: led_connection_nets # # # Connect the 12.1k Ohm ISET Resistor R1915 # NET 'Phys_U21_ISET' U21-48 R1915-1 NET 'GROUND' R1915-2 # # Jumper aka Strapping Resistors for the 4 MODE lines # # - pin 32 MODE0 and pin 31 MODE1 have pull-up and pull-down # - pin 28 MODE2 and pin 27 MODE3 have pull-up only # # - These are all high-speed RGMII receiver data lines # so layout matters, no stubs # NET 'Phys_U21_RXD3__MODE3' U21-27 R1907-1 NET 'Phys_U21_DVDDH' R1907-2 NET 'Phys_U21_RXD2__MODE2' U21-28 R1908-1 NET 'Phys_U21_DVDDH' R1908-2 NET 'Phys_U21_RXD1__MODE1' U21-31 R1909-1 R1910-1 NET 'Phys_U21_DVDDH' R1909-2 NET 'GROUND' R1910-2 NET 'Phys_U21_RXD0__MODE0' U21-32 R1911-1 R1912-1 NET 'Phys_U21_DVDDH' R1911-2 NET 'GROUND' R1912-2 # # Jumper aka Strapping Resistors for the LED MODE # This is pull-up only # NET 'Phys_U21_CLK125__LED_MODE' U21-41 R1914-1 NET 'Phys_U21_DVDDH' R1914-2 # # Jumper aka Strapping Resistors for the CLK125 ENABLE # This is pull-up only # NET 'Phys_U21_RX_DV__CLK125_EN' U21-33 R1913-1 NET 'Phys_U21_DVDDH' R1913-2 # # Jumper aka Strapping Resistors for the 3 PHYAD lines # # - pin 17 PHYAD0 pin 15 PHYAD1 pin 35 PHYAD2 # all have pull-up and pull-down resistors # # - Pin 35 RX_CLK__PHYAD2 is a high-speed RGMII receiver # clock line so layout matters, no stubs # # - The PHYAD is the address for management operations # over the MDC MDIO bus lines. # # - Note that the Jumpers for PHYAD0 and PHYAD1 are located # up by the LED translator/driver U553 and the Pull-Up jumpers # for these lines uses a filtered 1V8 supply instead of the # U21 DVDDH bus. # NET 'Phys_U21_LED1__PHYAD0' U21-17 R1901-1 R1902-1 NET 'RC_FLTR_1V8' R1901-2 NET 'GROUND' R1902-2 NET 'Phys_U21_LED2__PHYAD1' U21-15 R1903-1 R1904-1 NET 'RC_FLTR_1V8' R1903-2 NET 'GROUND' R1904-2 NET 'Phys_U21_RX_CLK__PHYAD2' U21-35 R1905-1 R1906-1 NET 'Phys_U21_DVDDH' R1905-2 NET 'GROUND' R1906-2 # # No Connection Pin - the Hub Module does not use these pins # NET 'NO_CONN_Phys_U21_NC_PIN_13' U21-13 NET 'NO_CONN_Phys_U21_LDO_PIN_43' U21-43 NET 'NO_CONN_Phys_U21_X0_PIN_45' U21-45 NET 'NO_CONN_Phys_U21_NC_PIN_47' U21-47 # # Define the Phys U21 RGMII Bus Lines: # # Note that the pins for the following RGMII Bus Lines # have already been defined in the jumper strapping # section above: # # RXD0__MODE0, RXD1__MODE1, RXD2__MODE2, RXD3__MODE3, # RX_CLK__PHYAD2 # # NET 'Phys_U21_TXD0' U21-19 NET 'Phys_U21_TXD1' U21-20 NET 'Phys_U21_TXD2' U21-21 NET 'Phys_U21_TXD3' U21-22 NET 'Phys_U21_GTX_CLK' U21-24 NET 'Phys_U21_TX_EN' U21-25 # # Define the 25.000 MHz Clock Input pin X1: # # Note that pin X0 was defined in the No Connect section # NET 'Phys_U21_X1' U21-46 # # Define the Phys U21 Management Bus MDC and MDIO lines: # # Recall that MDIO needs a pull-up resistor. # NET 'Phys_U21_MDC' U21-36 NET 'Phys_U21_MDIO' U21-37 R1917-1 NET 'Phys_U21_DVDDH' R1917-2 # # Define the Phys U21 RESET and Interrupt lines: # NET 'Phys_Chips_RESET_B' U21-42 NET 'Phys_U21_INT_B' U21-38 # # Define the 4 Pairs of BASE-T signals to/from Phys U21 # # Note from U21 these BASE_T pairs connect to # Magnetics TRANS4 and then to the Backplane # NET 'Phys_U21_TXRX_A_DIR' U21-2 NET 'Phys_U21_TXRX_A_CMP' U21-3 NET 'Phys_U21_TXRX_B_DIR' U21-5 NET 'Phys_U21_TXRX_B_CMP' U21-6 NET 'Phys_U21_TXRX_C_DIR' U21-7 NET 'Phys_U21_TXRX_C_CMP' U21-8 NET 'Phys_U21_TXRX_D_DIR' U21-10 NET 'Phys_U21_TXRX_D_CMP' U21-11 # # For routing reasons the resistor/jumpers for the # LED1_PHYAD0 and LED1_PHYAD0 lines are located up # by the U553 translator/driver for these LEDs. # Instead of trying to route the U21 and U22 DVDDH # power buses up to these jumpers I'm just going # to use an RC Filter R1991 / C1991 to make a clean # 1V8 supply for the 4 possible Pull-Up jumpers in # this group: R1901 and R1903 for U21 and R1951 and # R1953 for U22. The following is just the nets for # this little 1V8 RC filter 100 Ohm and 1 uFd. # NET 'BULK_1V8' R1991-2 NET 'RC_FLTR_1V8' R1991-1 C1991-1 NET 'GROUND' C1991-2 # # Ethernet Phys Chip U22 Signal Nets # ------------------------------------------ # # # Original Rev. 11-Sept-2015 # Current Rev. 31-May-2015 # # # This file holds all of the signal nets for the U22 Phys Chip. # # These are the nets for the U22 Micrel KSZ9031RNX # Phys Chip which carries Ethernet from This Hub's FPGA # to Switch B on This Hub. # # # This FPGA --> U22 Phys --> Cap Coupling --> Switch B on This Hub # # # *** U22 Phys Chip Nets to its Capacitor Coupling to Switch B *** # # These nets are held in the netsfile: switch_chip_to_cap_coupled_nets # # # *** U22 Phys Chip Nets to its Front Panel LEDs *** # # These nets are held in the netsfile: led_connection_nets # # # Connect the 12.1k Ohm ISET Resistor R1965 # NET 'Phys_U22_ISET' U22-48 R1965-1 NET 'GROUND' R1965-2 # # Jumper aka Strapping Resistors for the 4 MODE lines # # - pin 32 MODE0 and pin 31 MODE1 have pull-up and pull-down # - pin 28 MODE2 and pin 27 MODE3 have pull-up only # # - These are all high-speed RGMII receiver data lines # so layout matters, no stubs # NET 'Phys_U22_RXD3__MODE3' U22-27 R1957-1 NET 'Phys_U22_DVDDH' R1957-2 NET 'Phys_U22_RXD2__MODE2' U22-28 R1958-1 NET 'Phys_U22_DVDDH' R1958-2 NET 'Phys_U22_RXD1__MODE1' U22-31 R1959-1 R1960-1 NET 'Phys_U22_DVDDH' R1959-2 NET 'GROUND' R1960-2 NET 'Phys_U22_RXD0__MODE0' U22-32 R1961-1 R1962-1 NET 'Phys_U22_DVDDH' R1961-2 NET 'GROUND' R1962-2 # # Jumper aka Strapping Resistors for the LED MODE # This is pull-up only # NET 'Phys_U22_CLK125__LED_MODE' U22-41 R1964-1 NET 'Phys_U22_DVDDH' R1964-2 # # Jumper aka Strapping Resistors for the CLK125 ENABLE # This is pull-up only # NET 'Phys_U22_RX_DV__CLK125_EN' U22-33 R1963-1 NET 'Phys_U22_DVDDH' R1963-2 # # Jumper aka Strapping Resistors for the 3 PHYAD lines # # - pin 17 PHYAD0 pin 15 PHYAD1 pin 35 PHYAD2 # all have pull-up and pull-down resistors # # - Pin 35 RX_CLK__PHYAD2 is a high-speed RGMII receiver # clock line so layout matters, no stubs # # - The PHYAD is the address for management operations # over the MDC MDIO bus lines. # # - Note that the Jumpers for PHYAD0 and PHYAD1 are located # up by the LED translator/driver U553 and the Pull-Up jumpers # for these lines uses a filtered 1V8 supply instead of the # U22 DVDDH bus. # NET 'Phys_U22_LED1__PHYAD0' U22-17 R1951-1 R1952-1 NET 'RC_FLTR_1V8' R1951-2 NET 'GROUND' R1952-2 NET 'Phys_U22_LED2__PHYAD1' U22-15 R1953-1 R1954-1 NET 'RC_FLTR_1V8' R1953-2 NET 'GROUND' R1954-2 NET 'Phys_U22_RX_CLK__PHYAD2' U22-35 R1955-1 R1956-1 NET 'Phys_U22_DVDDH' R1955-2 NET 'GROUND' R1956-2 # # No Connection Pin - the Hub Module does not use these pins # NET 'NO_CONN_Phys_U22_NC_PIN_13' U22-13 NET 'NO_CONN_Phys_U22_LDO_PIN_43' U22-43 NET 'NO_CONN_Phys_U22_X0_PIN_45' U22-45 NET 'NO_CONN_Phys_U22_NC_PIN_47' U22-47 # # Define the Phys U22 RGMII Bus Lines: # # Note that the pins for the following RGMII Bus Lines # have already been defined in the jumper strapping # section above: # # RXD0__MODE0, RXD1__MODE1, RXD2__MODE2, RXD3__MODE3, # RX_CLK__PHYAD2 # # NET 'Phys_U22_TXD0' U22-19 NET 'Phys_U22_TXD1' U22-20 NET 'Phys_U22_TXD2' U22-21 NET 'Phys_U22_TXD3' U22-22 NET 'Phys_U22_GTX_CLK' U22-24 NET 'Phys_U22_TX_EN' U22-25 # # Define the 25.000 MHz Clock Input pin X1: # # Note that pin X0 was defined in the No Connect section # NET 'Phys_U22_X1' U22-46 # # Define the Phys U22 Management Bus MDC and MDIO lines: # # Recall that MDIO needs a pull-up resistor. # NET 'Phys_U22_MDC' U22-36 NET 'Phys_U22_MDIO' U22-37 R1967-1 NET 'Phys_U22_DVDDH' R1967-2 # # Define the Phys U22 RESET and Interrupt lines: # NET 'Phys_Chips_RESET_B' U22-42 NET 'Phys_U22_INT_B' U22-38 # # Define the 4 Pairs of BASE-T signals to/from Phys U22 # # Note from U22 these BASE_T pairs connect to # coupling capacitors and then to Switch B. # NET 'Phys_U22_TXRX_A_DIR' U22-2 NET 'Phys_U22_TXRX_A_CMP' U22-3 NET 'Phys_U22_TXRX_B_DIR' U22-5 NET 'Phys_U22_TXRX_B_CMP' U22-6 NET 'Phys_U22_TXRX_C_DIR' U22-7 NET 'Phys_U22_TXRX_C_CMP' U22-8 NET 'Phys_U22_TXRX_D_DIR' U22-10 NET 'Phys_U22_TXRX_D_CMP' U22-11 # # # Bank 0 and Bank 65 Configuration Memory Nets # # This is the Key In Net List file for the Hub Module # ------------------------------------------------------ # # # Original Rev. 21-Sept-2015 # Most Recent Rev. 14-Dec-2015 # # # This file holds the Nets involved with Bank 0 of the # UltraScale FPGA and the associated Configuration # Flash Memory. # # Note: This file contains fixed pin connections to the # UltraScale FPGA. # # # Configuration Flash Memory # ---------------------------- # # This is a single 2 Gbit Micron MT28GU01GAAA1EGC-0SIT # device in a 64 pin 1mm BGA package that is mounted on # the top side of the PCB. # # # Power Ground and ByPass Caps for the Configuration Memory # NET 'BULK_1V8' U25-A4 U25-A6 U25-D5 NET 'BULK_1V8' U25-D6 U25-G4 U25-H3 NET 'GROUND' U25-B2 U25-H2 U25-H4 U25-H6 NET 'BULK_1V8' C1801-1 C1802-1 C1803-1 NET 'GROUND' C1801-2 C1802-2 C1803-2 NET 'BULK_1V8' C1804-1 C1805-1 C1806-1 C1807-1 NET 'GROUND' C1804-2 C1805-2 C1806-2 C1807-2 # # Data Lines between the Configuration Flash Memory and BANKS 0 & 65 # NET 'FLASH_D00' U25-F2 U1-AM14 # D00_MOSI_0 NET 'FLASH_D01' U25-E2 U1-AK14 # D01_DIN_0 NET 'FLASH_D02' U25-G3 U1-AF16 # D02_0 NET 'FLASH_D03' U25-E4 U1-AH14 # D03_0 NET 'FLASH_D04' U25-E5 U1-BE19 # IO_L22P_T3U_N6_DBC_AD0P_D04_65 NET 'FLASH_D05' U25-G5 U1-BF19 # IO_L22N_T3U_N7_DBC_AD0N_D05_65 NET 'FLASH_D06' U25-G6 U1-BD18 # IO_L21P_T3L_N4_AD8P_D06_65 NET 'FLASH_D07' U25-H7 U1-BE18 # IO_L21N_T3L_N5_AD8N_D07_65 NET 'FLASH_D08' U25-E1 U1-BE17 # IO_L20P_T3L_N2_AD1P_D08_65 NET 'FLASH_D09' U25-E3 U1-BF17 # IO_L20N_T3L_N3_AD1N_D09_65 NET 'FLASH_D10' U25-F3 U1-BD17 # IO_L19P_T3L_N0_DBC_AD9P_D10_65 NET 'FLASH_D11' U25-F4 U1-BD16 # IO_L19N_T3L_N1_DBC_AD9N_D11_65 NET 'FLASH_D12' U25-F5 U1-BC20 # IO_L18P_T2U_N10_AD2P_D12_65 NET 'FLASH_D13' U25-H5 U1-BC19 # IO_L18N_T2U_N11_AD2N_D13_65 NET 'FLASH_D14' U25-G7 U1-BA19 # IO_L17P_T2U_N8_AD10P_D14_65 NET 'FLASH_D15' U25-E7 U1-BB19 # IO_L17N_T2U_N9_AD10N_D15_65 # # Address Lines from BANK 65 to the Configuration Flash Memory # NET 'FLASH_A00' U25-A1 U1-BA21 # IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 NET 'FLASH_A01' U25-B1 U1-BB21 # IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 NET 'FLASH_A02' U25-C1 U1-BB18 # IO_L15P_T2L_N4_AD11P_A02_D18_65 NET 'FLASH_A03' U25-D1 U1-BC18 # IO_L15N_T2L_N5_AD11N_A03_D19_65 NET 'FLASH_A04' U25-D2 U1-AY20 # IO_L14P_T2L_N2_GC_A04_D20_65 NET 'FLASH_A05' U25-A2 U1-BA20 # IO_L14N_T2L_N3_GC_A05_D21_65 NET 'FLASH_A06' U25-C2 U1-AY19 # IO_L13P_T2L_N0_GC_QBC_A06_D22_65 NET 'FLASH_A07' U25-A3 U1-AY18 # IO_L13N_T2L_N1_GC_QBC_A07_D23_65 NET 'FLASH_A08' U25-B3 U1-AV20 # IO_L12P_T1U_N10_GC_A08_D24_65 NET 'FLASH_A09' U25-C3 U1-AW20 # IO_L12N_T1U_N11_GC_A09_D25_65 NET 'FLASH_A10' U25-D3 U1-AW18 # IO_L11P_T1U_N8_GC_A10_D26_65 NET 'FLASH_A11' U25-C4 U1-AW17 # IO_L11N_T1U_N9_GC_A11_D27_65 NET 'FLASH_A12' U25-A5 U1-AV21 # IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 NET 'FLASH_A13' U25-B5 U1-AW21 # IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 NET 'FLASH_A14' U25-C5 U1-AU18 # IO_L9P_T1L_N4_AD12P_A14_D30_65 NET 'FLASH_A15' U25-D7 U1-AV18 # IO_L9N_T1L_N5_AD12N_A15_D31_65 NET 'FLASH_A16' U25-D8 U1-AT21 # IO_L8P_T1L_N2_AD5P_A16_65 NET 'FLASH_A17' U25-A7 U1-AU21 # IO_L8N_T1L_N3_AD5N_A17_65 NET 'FLASH_A18' U25-B7 U1-AT19 # IO_L7P_T1L_N0_QBC_AD13P_A18_65 NET 'FLASH_A19' U25-C7 U1-AU19 # IO_L7N_T1L_N1_QBC_AD13N_A19_65 NET 'FLASH_A20' U25-C8 U1-AR20 # IO_L6P_T0U_N10_AD6P_A20_65 NET 'FLASH_A21' U25-A8 U1-AT20 # IO_L6N_T0U_N11_AD6N_A21_65 NET 'FLASH_A22' U25-G1 U1-AR19 # IO_L5P_T0U_N8_AD14P_A22_65 NET 'FLASH_A23' U25-H8 U1-AR18 # IO_L5N_T0U_N9_AD14N_A23_65 NET 'FLASH_A24' U25-B6 U1-AM21 # IO_L4P_T0U_N6_DBC_AD7P_A24_65 NET 'FLASH_A25' U25-B8 U1-AN21 # IO_L4N_T0U_N7_DBC_AD7N_A25_65 # # Control Signals between Configuration Flash Memory and BANKS 0 & 65 # # These signals include pull-up resistors as described in # the Xilinx Configuration User's Guide. # NET 'FLASH_RESET_B' U25-D4 U1-P14 R1802-1 # INIT_B_0 NET 'FLASH_CHIP_ENB_B' U25-B4 U1-AF14 R1804-1 # RDWR_FCS_B_0 NET 'FLASH_WRITE_ENB_B' U25-G8 U1-AP20 R1805-1 # IO_L2N_T0L_N3_FWE_FCS2_B_65 NET 'FLASH_OUTPUT_ENB_B' U25-F8 U1-AN20 R1806-1 # IO_L2P_T0L_N2_FOE_B_65 NET 'BULK_1V8' R1802-2 R1804-2 R1805-2 R1806-2 # Pull-Up Resistors to 1V8 # # Other Control Signals to the Configuration Flash Memory # NET 'FLASH_WRITE_PROTECT_B' U25-C6 R1807-1 # Flash Mem Write Protect Pin NET 'GROUND' U25-F6 # Flash Address Valid Bar NET 'GROUND' U25-E6 # Flash Clock for Sync Operation NET 'BULK_1V8' R1807-2 # Pull-Up Resistor to 1V8 # # ALL Other Bank 0 Configuration Signals Except for JTAG # ----------- # NET 'PROGRAM_B' U1-AE14 R1801-1 # PROGRAM_B_0 NET 'BULK_1V8' R1801-2 # Pull-Up Resistor to 1V8 NET 'FPGA_Config_DONE' U1-AC14 R1803-1 # DONE_0 NET 'BULK_1V8' R1803-2 # Pull-Up Resistor to 1V8 NET 'CONFIG_M0' R1811-1 R1812-1 U1-Y14 # M0_0 Configuration Mode NET 'CONFIG_M1' R1813-1 R1814-1 U1-V14 # M1_0 NET 'CONFIG_M2' R1815-1 R1816-1 U1-T14 # M2_0 NET 'BULK_1V8' R1811-2 R1813-2 R1815-2 # Pull-Up on Config Mode NET 'GROUND' R1812-2 R1814-2 R1816-2 # Pull-Down on Config Mode # We want 100 Ohm: 0,1,0 NET 'POR_OVERRIDE' U1-AB14 R1821-1 R1822-1 # POR_OVERRIDE Power On Reset Delay NET 'FPGA_CORE' R1821-2 # Shorter POR Delay Note: Zero Ohm NET 'GROUND' R1822-2 # Standard POR Delay to FPGA_CORE # We want Standard or to GND NET 'CFGBVS' U1-M14 R1823-1 R1824-1 # CFGBVS_0 Configuration Bank Voltage NET 'BULK_1V8' R1823-2 # Hi for 2V5 or 3V3 Note: Zero Ohm NET 'GROUND' R1824-2 # GND for VCCO_0 1V8 to VCCO_0 # We need GND. or to GND NET 'PUDC_B' U1-K14 R1825-1 R1826-1 # PUDC_B_0 Pull-Ups During Configuration NET 'BULK_1V8' R1825-2 # Hi --> Pull-Ups OFF Note: 100 Ohm NET 'GROUND' R1826-2 # GND -> Pull_Ups ON to VCCO_0 # We want weak pull-up or to GND # turned ON --> Gnd NET 'VBATT' U1-AN13 R1827-1 # VBATT Jumper to GND if not used NET 'GROUND' R1827-2 # GND We want VBATT Zero Ohm to GND NET 'NO_CONN_FPGA_BANK_0_CCLK' U1-AB16 # CCLK_0 We want No Connection # # No Connection pins on the Configuration Flash Memory # NET 'NO_CONN_FLASH_MEM_U25_F7' U25-F7 # WAIT NET 'NO_CONN_FLASH_MEM_U25_E8' U25-E8 # RFU NET 'NO_CONN_FLASH_MEM_U25_F1' U25-F1 # RFU NET 'NO_CONN_FLASH_MEM_U25_G2' U25-G2 # RFU NET 'NO_CONN_FLASH_MEM_U25_H1' U25-H1 # RFU # # No Connection pins on Bank 65 of the UltraScale FPGA # NET 'NO_CONN_FPGA_BANK_65_BE20' U1-BE20 # IO_L24P_T3U_N10_EMCCLK_65 NET 'NO_CONN_FPGA_BANK_65_BF20' U1-BF20 # IO_L24N_T3U_N11_DOUT_CSO_B_65 NET 'NO_CONN_FPGA_BANK_65_BD20' U1-BD20 # IO_T3U_N12_PERSTN0_65 NET 'NO_CONN_FPGA_BANK_65_BC21' U1-BC21 # IO_T2U_N12_CSI_ADV_B_65 NET 'NO_CONN_FPGA_BANK_65_AV19' U1-AV19 # IO_T1U_N12_PERSTN1_65 NET 'NO_CONN_FPGA_BANK_65_AM19' U1-AM19 # IO_L3P_T0L_N4_AD15P_A26_65 NET 'NO_CONN_FPGA_BANK_65_AN19' U1-AN19 # IO_L3N_T0L_N5_AD15N_A27_65 NET 'NO_CONN_FPGA_BANK_65_AN18' U1-AN18 # IO_L1P_T0L_N0_DBC_RS0_65 NET 'NO_CONN_FPGA_BANK_65_AP18' U1-AP18 # IO_L1N_T0L_N1_DBC_RS1_65 # # Note: There are 4 additional pins in Bank 65 but # they are not defined as No_Conn pins above. # # - 2 of these are pins: U1-AP21 # IO_T0U_N12_VRP_A28_65 # U1-AM18 # VREF_65 # # These pins are used for DCI calibration resistor and # the VREF pin is pulled down if it is not used as a # source of external reference to the differential # input buffer for single-ended signals. # # These two pins are defined in the nets file: # # ultra_dci_vref_mgt_calib_resistors_nets # # # # - 2 of these are pins: U1-BE16 # IO_L23P_T3U_N8_I2C_SCLK_65 # U1-BF16 # IO_L23N_T3U_N9_I2C_SDA_65 # # These pins are the I2C Bus port to the FPGA's SysMon. # These two pins are defined in the nets file: # # i2C_sensor_bus_nets # # # # This completes the definition of all pins # in Select I/O Bank 65. # # # Overall Hardware Address to Hub FPGA and to ROD Nets # # Key In Net List file for the Hub Module # --------------------------------------------------------- # # # # Original Rev. 29-Sep-2015 # Most Recent Rev. 13-Oct-2016 # # # This file holds the nets that make up the Overall # Hardware Address and route it to both the Hub's FPGA # and via the S2 MegArray Connector up to the ROD. # # The Overall Hardware Address is put together from two # parts: the Slot Backplane Hardware Address that also goes # to the IPMC and the Shelf Address that the IPMC obtains # from the Shelf Manager. # # # The Slot Backplane Hardware Address is provided by a set # of open or grounded pins in the Zone 1 connector. These # lines are pulled up to 3V3 by R1551 : R1558 and filtered # by C1551 : C1558. The resulting 8 signals run into the # IPMC as described in the nets file, # # ipmc_hw_adrs_handle_switch_ipmb_nets # # In this file these 8 signals will also provide the Slot # Backplane Hardware Address to a 3V3 HR Bank 94 in the # Hub FPGA through a 470 Ohm resistor array, R1571. # # NET 'HW_ADRS_0' R1571-16 NET 'HW_ADRS_1' R1571-15 NET 'HW_ADRS_2' R1571-14 NET 'HW_ADRS_3' R1571-13 NET 'HW_ADRS_4' R1571-12 NET 'HW_ADRS_5' R1571-11 NET 'HW_ADRS_6' R1571-10 NET 'HW_ADRS_7' R1571-9 NET 'ISO_SLOT_HW_ADRS_0' R1571-1 U1-AT12 # IO_L15N_T2L_N5_AD11N_84 NET 'ISO_SLOT_HW_ADRS_1' R1571-2 U1-AT11 # IO_T2U_N12_84 NET 'ISO_SLOT_HW_ADRS_2' R1571-3 U1-AU12 # IO_L17P_T2U_N8_AD10P_84 NET 'ISO_SLOT_HW_ADRS_3' R1571-4 U1-AU11 # IO_L17N_T2U_N9_AD10N_84 NET 'ISO_SLOT_HW_ADRS_4' R1571-5 U1-AV11 # IO_L7P_T1L_N0_QBC_AD13P_94 NET 'ISO_SLOT_HW_ADRS_5' R1571-6 U1-AW12 # IO_L12N_T1U_N11_GC_94 NET 'ISO_SLOT_HW_ADRS_6' R1571-7 U1-AW11 # IO_L7N_T1L_N1_QBC_AD13N_94 NET 'ISO_SLOT_HW_ADRS_7' R1571-8 U1-AY12 # IO_L9P_T1L_N4_AD12P_94 # # The next step in making the Overall Hardware Address # is to learn what Shelf this Hub is in. The IPMC learns # what Shelf it is in from the Shelf Manager. The IPMC # then sets this Shelf Address in 8 of its GPIO pins. # From these IPMC GPIO pins the Shelf Address is carried # to a 3V3 HR Bank 94 pins on the Hub's FPGA. # # Notes: One of these 8 signals from the IPMC to the # Hub's FPGA should indicate that it has been # successful in getting the Shelf Address from # the Shelf Manager, i.e. it indicates that the # state of the other 7 pins is valid. # # At this time I do not know which 8 pins on the # IPMC will be used for this function. So for # now I'm just going to pick the 8 GPIO pins that # are easy to route for this function. # NET 'SHELF_ADRS_0_TO_RES_NET' IPMC-197 R1572-1 # USR_2 INOUT IOIF User IO pin 2 NET 'SHELF_ADRS_1_TO_RES_NET' IPMC-198 R1572-2 # USR_3 INOUT IOIF User IO pin 3 NET 'SHELF_ADRS_2_TO_RES_NET' IPMC-200 R1572-3 # USR_6 INOUT IOIF User IO pin 6 NET 'SHELF_ADRS_3_TO_RES_NET' IPMC-201 R1572-4 # USR_7 INOUT IOIF User IO pin 7 NET 'SHELF_ADRS_4_TO_RES_NET' IPMC-203 R1572-5 # USR_10 INOUT IOIF User IO pin 10 NET 'SHELF_ADRS_5_TO_RES_NET' IPMC-204 R1572-6 # USR_11 INOUT IOIF User IO pin 11 NET 'SHELF_ADRS_6_TO_RES_NET' IPMC-206 R1572-7 # USR_14 INOUT IOIF User IO pin 14 NET 'SHELF_ADRS_7_TO_RES_NET' IPMC-207 R1572-8 # USR_15 INOUT IOIF User IO pin 15 NET 'SHELF_ADRS_0_TO_FPGA' R1572-16 U1-BB15 # IO_L3N_T0L_N5_AD15N_94 NET 'SHELF_ADRS_1_TO_FPGA' R1572-15 U1-BB14 # IO_L5N_T0U_N9_AD14N_94 NET 'SHELF_ADRS_2_TO_FPGA' R1572-14 U1-BA14 # IO_L5P_T0U_N8_AD14P_94 NET 'SHELF_ADRS_3_TO_FPGA' R1572-13 U1-BB13 # IO_L8P_T1L_N2_AD5P_94 NET 'SHELF_ADRS_4_TO_FPGA' R1572-12 U1-BB12 # IO_L8N_T1L_N3_AD5N_94 NET 'SHELF_ADRS_5_TO_FPGA' R1572-11 U1-BB11 # IO_L10N_T1U_N7_QBC_AD4N_94 NET 'SHELF_ADRS_6_TO_FPGA' R1572-10 U1-BA12 # IO_L9N_T1L_N5_AD12N_94 NET 'SHELF_ADRS_7_TO_FPGA' R1572-9 U1-BA11 # IO_L10P_T1U_N6_QBC_AD4P_94 # # Inside the Hub FPGA the Slot Backplane Hardware Address # Is combined with the Shelf Address to make up the # Overall Hardware Address. # # Then the Overall Hardware Address must be conveyed to # the ROD over 8 pins in the S2 Meg Array Connector. # # The Overall Hardware Address comes out of the Hub FPGA # on pins in the 1V8 HP Banks 67 and 68. # NET 'OVERALL_ADRS_0_TO_RES_NET' R1573-1 U1-BF25 # IO_L23N_T3U_N9_67 NET 'OVERALL_ADRS_1_TO_RES_NET' R1573-2 U1-BE25 # IO_L23P_T3U_N8_67 NET 'OVERALL_ADRS_2_TO_RES_NET' R1573-3 U1-BF26 # IO_L20P_T3L_N2_AD1P_67 NET 'OVERALL_ADRS_3_TO_RES_NET' R1573-4 U1-BE27 # IO_L22P_T3U_N6_DBC_AD0P_67 NET 'OVERALL_ADRS_4_TO_RES_NET' R1573-5 U1-BF27 # IO_L20N_T3L_N3_AD1N_67 NET 'OVERALL_ADRS_5_TO_RES_NET' R1573-6 U1-BE28 # IO_L22N_T3U_N7_DBC_AD0N_67 NET 'OVERALL_ADRS_6_TO_RES_NET' R1573-7 U1-BE29 # IO_L22P_T3U_N6_DBC_AD0P_68 NET 'OVERALL_ADRS_7_TO_RES_NET' R1573-8 U1-BE30 # IO_L20N_T3L_N3_AD1N_68 NET 'LOCATION_ADRS_1_TO_ROD' R1573-16 Meg_S2-H1 NET 'LOCATION_ADRS_2_TO_ROD' R1573-15 Meg_S2-J1 NET 'LOCATION_ADRS_3_TO_ROD' R1573-14 Meg_S2-H2 NET 'LOCATION_ADRS_4_TO_ROD' R1573-13 Meg_S2-J2 NET 'LOCATION_ADRS_5_TO_ROD' R1573-12 Meg_S2-H3 NET 'LOCATION_ADRS_6_TO_ROD' R1573-11 Meg_S2-J3 NET 'LOCATION_ADRS_7_TO_ROD' R1573-10 Meg_S2-H4 NET 'LOCATION_ADRS_8_TO_ROD' R1573-9 Meg_S2-J4 # # # ROD to/from Hub Spare Signal Nets # # Key In Net List file for the Hub Module # -------------------------------------------- # # # # Original Rev. 30-Sept-2015 # Most Recent Rev. 10-Nov-2016 # # # This file holds the nets for the 8 Spare Signals between # the ROD and the Hub. # # These 8 Spare Signals are Select I/O pins on both the ROD # FPGA and on the Hub FPGA. If needed they may be run as: # # - 8 single ended lines # # - 4 LVDS differential pair signals # # - 4 LVDS differential pairs carrying a serial protocol # # # Note that these 8 Spare Signals can send data in either # direction, ROD to Hub or Hub to ROD, whichever is needed. # # On the Hub FPGA these 8 Spare Signals connect to the 1V8 # HP Select I/O Bank 67. # # These 8 Spare Signals must not be confused with the # 4 spare Rod to Hub MGT links which are one way only. # # NET 'TBD_SPARE_LINK_0_DIR' Meg_S1-C22 U1-AV26 # IO_L7P_T1L_N0_QBC_AD13P_67 NET 'TBD_SPARE_LINK_0_CMP' Meg_S1-B22 U1-AW26 # IO_L7N_T1L_N1_QBC_AD13N_67 NET 'TBD_SPARE_LINK_1_DIR' Meg_S1-C20 U1-AT27 # IO_L8P_T1L_N2_AD5P_67 NET 'TBD_SPARE_LINK_1_CMP' Meg_S1-B20 U1-AU27 # IO_L8N_T1L_N3_AD5N_67 NET 'TBD_SPARE_LINK_2_DIR' Meg_S1-C18 U1-AY27 # IO_L13P_T2L_N0_GC_QBC_67 NET 'TBD_SPARE_LINK_2_CMP' Meg_S1-B18 U1-AY28 # IO_L13N_T2L_N1_GC_QBC_67 NET 'TBD_SPARE_LINK_3_DIR' Meg_S1-C16 U1-AT29 # IO_L9P_T1L_N4_AD12P_67 NET 'TBD_SPARE_LINK_3_CMP' Meg_S1-B16 U1-AU29 # IO_L9N_T1L_N5_AD12N_67 # # # Backplane No Connect Nets # # Key In Net List file for the Hub Module # -------------------------------------------- # # # # Original Rev. 30-Sept-2015 # Most Recent Rev. 19-Aug-2016 # # # This file holds the "single point nets" for the backplane # connector pins that have No Connection in the Hub Design. # # # Zone 1 Connector P10 with a total of 34 pins # # The Hub Module does not use the following Zone 1 P10 pins: # # - the JTAG connections pins 1:4 # # - the Metalic Test and Ring connections pins 17:24 # # Normally you would expect to see these 12 pins assigned # with "No_Conn" nets but for routing reasons these 12 # pins have been removed from the Geometry for the Zone 1 # connector so they will not appear in the net list at all. # # # Zone 2 Connector J24 with a total of 160 pins # # Base Interface Channels 15 and 16 are not used # because L1Calo uses 14 Slot Shelves. # This is Rows: 9, 10 of J24. # # But we are removing chicklets 9 and 10 # from the J24 connector so we do not # need No_COnn Nets for these 16 pins. # # # Zone 2 Connector J23 with a total of 160 pins # # Base Interface Channel 1 to the Shelf Manager # is not used, as per Dave. The Shelf Manager # will be connected to Ethernet via its front # panel connection. This is Row: 5 of J23. # # Base Interface Channel 2 to the Other Hub # is not used because for routing reasons we # will connect to the Other Hub via pins in # Rows 3 & 4 of J20 in its UpDate Channel area. # We do this to have 2 full criss-cross # Ethernet connections between Hubs. # This is Row: 6 of J23. NET 'No_Conn_J23_A5_BI_ShMCA_DIR' J23-A5 NET 'No_Conn_J23_B5_BI_ShMCA_CMP' J23-B5 NET 'No_Conn_J23_C5_BI_ShMCB_DIR' J23-C5 NET 'No_Conn_J23_D5_BI_ShMCB_CMP' J23-D5 NET 'No_Conn_J23_E5_BI_ShMCC_DIR' J23-E5 NET 'No_Conn_J23_F5_BI_ShMCC_CMP' J23-F5 NET 'No_Conn_J23_G5_BI_ShMCD_DIR' J23-G5 NET 'No_Conn_J23_H5_BI_ShMCD_CMP' J23-H5 NET 'No_Conn_J23_A6_BI_DA2_DIR' J23-A6 NET 'No_Conn_J23_B6_BI_DA2_CMP' J23-B6 NET 'No_Conn_J23_C6_BI_DB2_DIR' J23-C6 NET 'No_Conn_J23_D6_BI_DB2_CMP' J23-D6 NET 'No_Conn_J23_E6_BI_DC2_DIR' J23-E6 NET 'No_Conn_J23_F6_BI_DC2_CMP' J23-F6 NET 'No_Conn_J23_G6_BI_DD2_DIR' J23-G6 NET 'No_Conn_J23_H6_BI_DD2_CMP' J23-H6 # # Zone 2 Connector J20 with a total of 160 pins # # Fabric Interface Channels 14 and 15 are not used # because L1Calo uses 14 Slot Shelves # This is Rows: 8, 7, 6, 5 of J20. # # On J20 the Hub Module does not use: # # Clocks 1, 2, 3 A or B, or Update Channel 4. # These signals are in J20 Rows: 1, 2. # # But for routing reasons we are removing chicklets # 1 and 2 from the J20 connector so we do not need # No_COnn Nets for the 16 signal pins in Rows 1 and 2 # of this connector. # NET 'No_Conn_J20_A8_FI_Tx0_14_DIR' J20-A8 NET 'No_Conn_J20_B8_FI_Tx0_14_CMP' J20-B8 NET 'No_Conn_J20_C8_FI_Rx0_14_DIR' J20-C8 NET 'No_Conn_J20_D8_FI_Rx0_14_CMP' J20-D8 NET 'No_Conn_J20_E8_FI_Tx1_14_DIR' J20-E8 NET 'No_Conn_J20_F8_FI_Tx1_14_CMP' J20-F8 NET 'No_Conn_J20_G8_FI_Rx1_14_DIR' J20-G8 NET 'No_Conn_J20_H8_FI_Rx1_14_CMP' J20-H8 NET 'No_Conn_J20_A7_FI_Tx2_14_DIR' J20-A7 NET 'No_Conn_J20_B7_FI_Tx2_14_CMP' J20-B7 NET 'No_Conn_J20_C7_FI_Rx2_14_DIR' J20-C7 NET 'No_Conn_J20_D7_FI_Rx2_14_CMP' J20-D7 NET 'No_Conn_J20_E7_FI_Tx3_14_DIR' J20-E7 NET 'No_Conn_J20_F7_FI_Tx3_14_CMP' J20-F7 NET 'No_Conn_J20_G7_FI_Rx3_14_DIR' J20-G7 NET 'No_Conn_J20_H7_FI_Rx3_14_CMP' J20-H7 NET 'No_Conn_J20_A6_FI_Tx0_15_DIR' J20-A6 NET 'No_Conn_J20_B6_FI_Tx0_15_CMP' J20-B6 NET 'No_Conn_J20_C6_FI_Rx0_15_DIR' J20-C6 NET 'No_Conn_J20_D6_FI_Rx0_15_CMP' J20-D6 NET 'No_Conn_J20_E6_FI_Tx1_15_DIR' J20-E6 NET 'No_Conn_J20_F6_FI_Tx1_15_CMP' J20-F6 NET 'No_Conn_J20_G6_FI_Rx1_15_DIR' J20-G6 NET 'No_Conn_J20_H6_FI_Rx1_15_CMP' J20-H6 NET 'No_Conn_J20_A5_FI_Tx2_15_DIR' J20-A5 NET 'No_Conn_J20_B5_FI_Tx2_15_CMP' J20-B5 NET 'No_Conn_J20_C5_FI_Rx2_15_DIR' J20-C5 NET 'No_Conn_J20_D5_FI_Rx2_15_CMP' J20-D5 NET 'No_Conn_J20_E5_FI_Tx3_15_DIR' J20-E5 NET 'No_Conn_J20_F5_FI_Tx3_15_CMP' J20-F5 NET 'No_Conn_J20_G5_FI_Rx3_15_DIR' J20-G5 NET 'No_Conn_J20_H5_FI_Rx3_15_CMP' J20-H5 # # Hub Module - Key-In Nets File # # Power Supply - All Other NETs # # # # Original Rev. 2-Nov-2015 # Most Recent Rev. 28-Dec-2016 # # # This file holds All Other NETs for the # Hub Module Power Supply crcuits. These Include: # # - Header for Power Supply Monitoring # - Power Supply Statup Supervisor # - Power Supply "All Good" signal generator # - The "Always On" supply # - The Reference Supplies for the FPGA System Monitor # # # Because of the different types of components in this # file, it is divided into sections. # # # # System Monitor for the UltraScale Virtex FPGA # ----------------------------------------------- # # This includes the Reference supply and power filtering # for the System Monitor as well as the analog scaling # components for the monitored signals. # # The SysMon NETs use Reference Designators: 1851 through 1899. # # # SysMon Power/Ground Filtering and Reference Supply # NET 'BULK_1V8' L1851-1 C1851-2 NET 'GROUND' C1851-1 NET 'GROUND' L1852-1 NET 'SYSMON_GND' L1852-2 NET 'SYSMON_1V8' L1851-2 C1852-1 C1853-1 C1854-1 C1855-1 C1859-1 NET 'SYSMON_GND' C1852-2 C1853-2 C1854-2 C1855-2 C1859-2 NET 'SYSMON_1V8' U1851-1 NET 'SYSMON_GND' U1851-3 C1856-2 C1857-2 C1858-2 NET 'SYSMON_VREFP' U1851-2 C1856-1 C1857-1 C1858-1 # # Connections to the FPGA's SysMon Pins: # # - SysMon Power # - SysMon Reference Supply # - SysMon Main Input Voltage # - SysMon Temperature Diode # NET 'SYSMON_1V8' U1-AB20 NET 'SYSMON_GND' U1-AB19 U1-AC19 NET 'SYSMON_VREFP' U1-AD20 NET 'SysMon_Main_Input_VP' U1-AC20 NET 'SysMon_Main_Input_VN' U1-AD19 NET 'Temp_Diode_DXN' U1-AE19 NET 'Temp_Diode_DXP' U1-AE20 # # ================================================================= # # # Power Supply Controller # -------------------------- # # Controls the Startup and Shutdown # of the DCDC Converters on the Hub Module # # # Detect GOOD Iso_12V and then Delay for 500 msec. # NET 'ISO_12V' R2951-1 NET 'SENSE_12V' R2951-2 R2952-1 C2951-1 U2951-5 NET 'GROUND' R2952-2 C2951-2 NET 'CNST_5V0' U2951-6 C2955-1 C2959-1 NET 'GROUND' U2951-2 C2955-2 C2959-2 NET 'No_Conn_U2951_Pin_3' U2951-3 NET 'DEL_CAP_12V_DET' U2951-4 C2952-1 NET 'GROUND' C2952-2 NET 'GOOD_ISO_12V' U2951-1 R2953-1 NET 'CNST_5V0' R2953-2 # # Sequence the 3 Flags # NET 'GOOD_ISO_12V' U2952-3 NET 'CNST_5V0' U2952-1 C2956-1 NET 'GROUND' U2952-2 C2956-2 NET 'SEQUENCE_FLAG_1' U2952-6 R2954-1 NET 'SEQUENCE_FLAG_2' U2952-5 R2955-1 NET 'SEQUENCE_FLAG_3' U2952-4 R2956-1 NET 'CNST_5V0' R2954-2 R2955-2 R2956-2 # # Power and Ground to the NANDs and Inverters # NET 'CNST_5V0' U2953-14 C2957-1 U2954-14 C2958-1 NET 'GROUND' U2953-7 C2957-2 U2954-7 C2958-2 # # First Enable NAND # NET 'SEQUENCE_FLAG_1' U2953-1 NET 'GOOD_ISO_12V' U2953-2 NET 'HI_U2953_13' U2953-13 R2960-1 NET 'CNST_5V0' R2960-2 NET 'FIRST_ENABLE_NAND_OUT' U2953-12 # # First Enable Fanout Inverters # NET 'FIRST_ENABLE_NAND_OUT' U2954-1 NET 'BUFD_FIRST_ENABLE' U2954-2 U2954-3 U2954-5 U2954-9 NET 'FIRST_ENABLE_COPY_1' U2954-4 R2961-1 R2962-1 NET 'FIRST_ENABLE_COPY_2' U2954-6 R2963-1 R2965-1 NET 'FIRST_ENABLE_COPY_3' U2954-8 R2964-1 R2966-1 NET 'DCDC_1_OFF_ON' R2961-2 NET 'DCDC_2_OFF_ON' R2962-2 NET 'DCDC_3_OFF_ON' R2963-2 NET 'DCDC_6_OFF_ON' R2964-2 NET 'DCDC_7_OFF_ON' R2965-2 NET 'DCDC_8_OFF_ON' R2966-2 # # Second Enable NAND # NET 'SEQUENCE_FLAG_3' U2953-9 NET 'ENABLE_12V_2ND_BUF' U2953-10 NET 'GOOD_ISO_12V' U2953-11 NET 'SECOND_ENABLE_NAND_OUT' U2953-8 R2967-1 NET 'DCDC_5_OFF_ON' R2967-2 # # Sequence Ramp NAND # NET 'SEQUENCE_FLAG_2' U2953-3 NET 'GOOD_ISO_12V' U2953-4 NET 'ENABLE_12V_2ND_BUF' U2953-5 NET 'RAMP_ENABLE_NAND_OUT' U2953-6 R2957-1 # # Sequence Ramp Generator # NET 'RAMP_SWITCH_BASE' Q2951-2 R2957-2 NET 'GROUND' Q2951-1 NET 'RAMP_SWITCH_COLLECTOR' Q2951-3 R2959-1 NET 'ISO_12V' R2958-1 NET 'CONVERTER_RAMP' R2958-2 R2959-2 NET 'CONVERTER_RAMP' C2985-1 C2986-1 C2987-1 C2988-1 C2989-1 NET 'GROUND' C2985-2 C2986-2 C2987-2 C2988-2 C2989-2 # # Buffer the Hub_Power_Enable signal. # # - Note that this 3.3 Volt CMOS Logic signal normally comes # from the IPMC's Payload Power Enable pin and that it # drives an opto-coupler LED through R956 and drives this # U2954 input to the Hub's power supply control logic. # # - But that this signal can also come from an "always ON" # signal as a way to ignore the IPMC and have immediate # power up of the Hub Module. # # - Use JMP5 and JMP6 to select the desired mode of power up. # NET 'Hub_Power_Enable' U2954-13 NET 'ENABLE_12V_1ST_BUF' U2954-12 U2954-11 NET 'ENABLE_12V_2ND_BUF' U2954-10 # # ================================================================= # # # ALL Hub Power Good and Board Startup Reset # ---------------------------------------------- # # # This section of the net list really contains # two different: # # - Generate the Hub_Power_Good signal # # - from that generate the Board_Startup_Reset_B signal # # # To generate the Hub_Power_Good signal: # # - examine the Power Good signals from the # 7x DC/DC Converters and # # - examine the output of the MGT_AVAUX # and BULK_2V5 linear supplies and # # - include the Enable Iso_12V signal. # # # Connect Power, Ground, and ByPass Capacitors to the # 5 ICs in this functional section. # NET 'CNST_5V0' U2955-14 U2956-14 NET 'CNST_5V0' U2957-6 U2958-6 U2959-6 NET 'GROUND' U2955-7 U2956-7 NET 'GROUND' U2957-2 U2958-2 U2959-2 NET 'CNST_5V0' C2962-1 C2963-1 C2964-1 C2965-1 C2966-1 NET 'GROUND' C2962-2 C2963-2 C2964-2 C2965-2 C2966-2 # # Connect the DCDC Converter "Power_Good" signals to # the AND gates and connect the associated Pull-Up resistors # These Pull-Up resistors pull to CNST_5V0. # NET 'DCDC_1_POWER_GOOD' U2955-1 R2981-1 NET 'DCDC_2_POWER_GOOD' U2955-2 R2982-1 NET 'DCDC_3_POWER_GOOD' U2955-4 R2983-1 NET 'DCDC_5_POWER_GOOD' U2955-5 R2984-1 NET 'DCDC_6_POWER_GOOD' U2955-9 R2985-1 NET 'DCDC_7_POWER_GOOD' U2955-10 R2986-1 NET 'DCDC_8_POWER_GOOD' U2955-12 R2987-1 NET 'CNST_5V0' R2981-2 R2982-2 R2983-2 R2984-2 NET 'CNST_5V0' R2985-2 R2986-2 R2987-2 # # Include the Enable Iso_12V power supply signal # in the overall Hub Power Good generation. # # Note This 5 volt version of the Enable Isolated +12V # comes from U2954 in the Hub Power Supply Control circuit. # This forces the Board_Startup_Reset_B signal to be # asserted as soon the the Isolated +12V supply is # turned OFF. # NET 'ENABLE_12V_2ND_BUF' U2955-13 # # Connect the MGT_AVAUX power good threshold detector # and its associated components # NET 'MGT_AVAUX' R2971-1 NET 'PG_SENSE_MGT_AVAUX' R2971-2 R2972-2 U2957-5 NET 'GROUND' R2972-1 NET 'No_Conn_U2957_3_MR_B' U2957-3 NET 'No_Conn_U2957_4_TCap' U2957-4 NET 'MGT_AVAUX_GT_OK' U2957-1 R2975-1 U2956-10 NET 'CNST_5V0' R2975-2 # # Connect the BULK_2V5 power good threshold detector # and its associated components # NET 'BULK_2V5' R2973-1 NET 'PG_SENSE_BULK_2V5' R2973-2 R2974-2 U2958-5 NET 'GROUND' R2974-1 NET 'No_Conn_U2958_3_MR_B' U2958-3 NET 'No_Conn_U2958_4_TCap' U2958-4 NET 'BULK_2V5_GT_OK' U2958-1 R2976-1 U2956-9 NET 'CNST_5V0' R2976-2 # # Connect the various AND gates into the overall Hub Power Good # NET 'QUAD_ONE_PG_OK' U2955-6 U2956-13 NET 'QUAD_TWO_PG_OK' U2955-8 U2956-12 NET 'HUB_POWER_GOOD' U2956-8 # # Connect the HUB_POWER_GOOD signal to an FPGA Input. # # Note the 2.7k Ohm series resistor R2979 between the # 5.0V CMOS signal source and the 3.3V CMOS FPGA Input. # # The other connection to HUB_POWER_GOOD is shown below. # NET 'HUB_POWER_GOOD' R2979-1 NET 'ALL_HUB_POWER_GOOD_TO_FPGA' R2979-2 U1-AM16 # IO_T3U_N12_84 # # Ground the inputs on the unused section of U2956 # and assign a No_Conn net to the output of its # unused section. # # Assign No_Conn nets to the "no internal connection" # pins on both U2955 and U2956. # NET 'GROUND' U2956-1 U2956-2 U2956-4 U2956-5 NET 'No_Conn_U2956_Pin_6' U2956-6 NET 'No_Conn_U2955_Pin_3' U2955-3 NET 'No_Conn_U2955_Pin_11' U2955-11 NET 'No_Conn_U2956_Pin_3' U2956-3 NET 'No_Conn_U2956_Pin_11' U2956-11 # # Finally generate the Board_Startup_Reset_B signal # # Note that the MR_B pin on the TPS3808 that generates # the Board_Startup_Reset_B signal is not used. It # could be used as another input if needed. As on the # other TPS3808s the MR_B pins can be left open. # # Note that the Board_Startup_Reset_B signal is # pulled up to the Bulk_3V3 level. # NET 'HUB_POWER_GOOD' R2978-1 U2959-5 NET 'GROUND' R2978-2 NET 'BRD_STR_RESET_CAP' U2959-4 C2961-1 NET 'GROUND' C2961-2 NET 'No_Conn_U2959_Pin_3' U2959-3 NET 'BOARD_STARTUP_RESET_B' U2959-1 R2977-1 NET 'BULK_3V3' R2977-2 # # ================================================================= # # # Board Reset Distribution and part of ROD Power Control # ---------------------------------------------------------- # # # This section of the net list Distributes the # BOARD_STARTUP_RESET_B signal. # # The BOARD_STARTUP_RESET_B signal goes to: # # - The FPGA INIT pin and the Configuration # Flash Memory Reset pin. This prevents corruption # of the Flash Memory when the power supplies are # not all running and stable. # # - The 3 Switch chip Reset pins. As required, hold # the 3 Switch chips in reset until the power supplies # are all up and stable. # # - The reset pin on the 2 Phys chips.. As required, hold # the 2 Phys chips in reset until the power supplies are # all up and stable. # # - The BOARD_STARTUP_RESET_B signal goes into the AND # gate that makes up the Enable_ROD_Power signal. # The BOARD_STARTUP_RESET_B must NOT be asserted to # turn power ON on the ROD. # # # Connect Power, Ground, and ByPass Capacitors to the # 8x ICs in this functional section. Define the No_Conn # pin on the 5x NC7SV05 inverter chips. # NET 'BULK_3V3' U2960-5 U2961-5 U2962-5 NET 'BULK_3V3' U2963-5 U2964-5 U2965-5 NET 'BULK_3V3' U2966-5 U2967-5 NET 'GROUND' U2960-3 U2961-3 U2962-3 NET 'GROUND' U2963-3 U2964-3 U2965-3 NET 'GROUND' U2966-3 U2967-3 NET 'BULK_1V8' U2968-5 NET 'GROUND' U2968-3 NET 'No_Conn_U2960_pin_1' U2960-1 NET 'No_Conn_U2961_pin_1' U2961-1 NET 'No_Conn_U2962_pin_1' U2962-1 NET 'No_Conn_U2963_pin_1' U2963-1 NET 'No_Conn_U2964_pin_1' U2964-1 NET 'No_Conn_U2965_pin_1' U2965-1 NET 'BULK_3V3' C2971-1 C2972-1 C2973-1 NET 'BULK_3V3' C2974-1 C2975-1 C2976-1 C2980-1 NET 'GROUND' C2971-2 C2972-2 C2973-2 NET 'GROUND' C2974-2 C2975-2 C2976-2 C2980-2 NET 'BULK_1V8' C2977-1 C2978-1 C2979-1 NET 'GROUND' C2977-2 C2978-2 C2979-2 # # Connect the Board_Startup_Reset_B signal and # make the inverted version and distribute both. # NET 'BOARD_STARTUP_RESET_B' U2960-2 U2961-2 NET 'BOARD_STARTUP_RESET' U2960-4 NET 'BOARD_STARTUP_RESET' R2991-1 U2962-2 U2963-2 U2964-2 NET 'BULK_3V3' R2991-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # FPGA Init and Flash Memory Reset circuit. # # NOTE This is a 1V8 version of this signal. # # NOTE That the Pull-Up Resistor for this circuit # and the other connections to this circuit are in # the net file: bank_0_and_bank_65_config_mem_nets # NET 'FLASH_RESET_B' U2962-4 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # Reset pins on the 3x Switch Chips. # # Note This is a 3V3 version of this signal. # # Note The connection to the Switch Chips themselves # is made in the file: switch_chips_all_other_nets # NET 'SWITCH_CHIPS_RESET_B' U2963-4 R2992-1 NET 'BULK_3V3' R2992-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset_B signal to the # Reset pins on the 2x Phys Chips. # # Note This is a 1V8 version of this signal. # # Note The connection to the Phys Chips themselves # is made in the files: rgmii_phys_chip_u21_nets # rgmii_phys_chip_u22_nets # NET 'Phys_Chips_RESET_B' U2964-4 R2993-1 NET 'BULK_1V8' R2993-2 # # Connect the private Open-Drain copy of the # Board_Startup_Reset signal to the # LED_54 Cathode. This is the LED that Illuminates # when all of the Hub power supplies are up and stable # and the Board_Startup_Reset is over. # # This LED is usually called "All Hub Power Good". # # Note that this is an inverted copy of the normal # Board_Startup_Reset_B signal. # # Note that the connection to LED_54 is made # in the file: led_connection_nets # NET 'LED_54_Cathode' U2961-4 # # ================================================================= # # # ROD Power Control # --------------------- # # # This section of the net list file involves the generation # of the Enable ROD Power signal aka ROD Power Control #1. # # It also includes the other 3 ROD Powr Control sginals # numbers: 2,3,4. For now these 3 ROD Power Control # signals will just be connected to the Hub's Virtex FPGA. # # The Enable ROD Power signal is generated by ICs # U2965 through U2968. The power and ground and bypass # capacitor connections to these 4 chips were made in the # above section of this nets list file. # # All 4 of the ROD Power Control signals are defined as # 1V8 level CMOS signals. # # # Include the All Hub Power Good signal # NET 'BOARD_STARTUP_RESET_B' U2966-2 # # Include the ROD_Power_Enable and ROD_Power_Enable_B # logic signals from the Hub's FPGA. # # These two ROD_Power_Enable signals are 3V3 logic level # and must be connected to one of the 3V3 Select I/O Banks. # NET 'ROD_Power_Enable' U1-AR17 # IO_L24N_T3U_N11_84 NET 'ROD_Power_Enable_B' U1-AP17 # IO_L24P_T3U_N10_84 NET 'ROD_Power_Enable' U2966-1 NET 'ROD_Power_Enable_B' U2965-2 NET 'Flipped_ROD_Power_Enable_B' U2965-4 U2967-2 R2994-1 NET 'Bulk_3V3' R2994-2 # # Optionally include the 3V3 version of the # FPGA_Configuration_DONE signal. Including or # not including this signal is controlled by jumpers # JMP3 and JMP4. # # Start by converting the FPGA_Configuration_DONE # signal from 1V8 to 3V3. This logic level conversion # is done by U555. The other half of the U555 Translator # is used in the JTAG string as shown in Drawing 33 # and described in the file: jtag_and_associated_nets # # The FPGA_Configuration_DONE signal and its pull-up # are defined in the file: bank_0_and_bank_65_config_mem_nets # NET 'FPGA_Config_DONE' U555-7 NET 'FPGA_Config_DONE_3V3' U555-2 JMP3-1 NET 'Optional_DONE_RPC' JMP4-2 JMP3-2 U2967-1 NET 'BULK_3V3' JMP4-1 # # Now AND things together to make the overall # Enable ROD Power signal. # # Note that the Logic output from U2966 and from U2967 # is 3.3 Volt CMOS level. It is OK to connect these # directly to the 1V8 powered U2968 because this family # of Fairchild logic has 3.6 Volt I/O tolerance when # powered with Vcc from 0V9 to 3V6. # NET 'First_Part_ROD_Pow' U2966-4 U2968-2 NET 'Second_Part_ROD_Pow' U2967-4 U2968-1 NET 'Enable_ROD_Power' U2968-4 # # Define the Hub FPGA end of 3 of # the 4 Power_Control signals that # run to the ROD: PC2, PC3, PC4 # # These Power_Control signals to/from # the ROD are 1V8 logic level and must # run to a 1V8 bank. # NET 'ROD_Power_Control_2_FPGA' U1-AW28 # IO_L14N_T2L_N3_GC_67 NET 'ROD_Power_Control_3_FPGA' U1-AV30 # IO_L12N_T1U_N11_GC_67 NET 'ROD_Power_Control_4_FPGA' U1-AV29 # IO_L12P_T1U_N10_GC_67 # # Define the MegArray Connector - ROD end # of the 4 Power_Control signals that # run to the ROD: PC1, PC2, PC3, PC4 # NET 'Enable_ROD_Power' Meg_S2-H26 NET 'ROD_Power_Control_2_ROD' Meg_S2-J26 NET 'ROD_Power_Control_3_ROD' Meg_S2-H27 NET 'ROD_Power_Control_4_ROD' Meg_S2-J27 # # Connect the 3 ROD Power Control sginals: # PC2, PC3, PC4 Hub-FPGA to MegArray-ROD # with isolating resistors. # # At this time only PC2 is defined. Power Control #2 # is "ROD Power Good". When PC2 is Hi it indicates # that the ROD Power is Good. # # The Hub has a 10k Ohm pull-down R2998 on PC2 so # that when the ROD is not installed on the Hub, the # Hub will not have a floating input signal. # # Note that the PC2, ROD Power Good, is both an input # to the Hub's FPGA and it controls the JTAG Multiplexer # U556 that jumps the JTAG chain over the ROD when it is # not both installed and powered up. # NET 'ROD_Power_Control_2_FPGA' R2995-1 NET 'ROD_Power_Control_2_ROD' R2995-2 R2998-1 NET 'GROUND' R2998-2 NET 'ROD_Power_Control_3_FPGA' R2996-1 NET 'ROD_Power_Control_3_ROD' R2996-2 NET 'ROD_Power_Control_4_FPGA' R2997-1 NET 'ROD_Power_Control_4_ROD' R2997-2 # # Connect the ROD's SMBALERT_B signal through an # isolating resistor and then to a 1V8 Select I/O # pin in the Hub's FPGA. # # - This connection lets the Hub see the ROD's # SMBALERT_B status as requested by Ed. # # - Note that on the ROD, it pulls its SMBALERT_B # signal up to its 1V8 rail with a 1k Ohm resistor, # ROD reference designator R117. # # - Note that in the official ROD/Hub MegArray pinout, # Rev 1.4 6-May-2015, that the SMBALERT signal is # on pin S1-B27. I will make the Hub's connection # for this signal to this pin. I do not see this # connection in the Rev 1-July-2016 ROD schmatics # and I must ask Ed about this. # NET 'RODs_SMBALERT_B' Meg_S1-B27 NET 'RODs_SMBALERT_B' R2999-1 NET 'FPGA_RODs_SMBALERT_B' R2999-2 NET 'FPGA_RODs_SMBALERT_B' U1-BB28 # IO_T2U_N12_67 # # RC Filter and Safety Components Associated # with the J3 Power Supply Monitor Connector # ---------------------------------------------- # # These 11 RC filters are for the Power Supply Voltage # Monitor Test Points in the J3 Connector in the North # East corner of the Hub Module. The 100 Ohm Rs are # also a current limiter for safety. Reference # Designators in the range x2351 : x2369 may be used # for the J3 associated components. # # When using these Voltage Monitor Test Points note # that they have a series resistor connecting them # to the actual power supply rail. In all case but one # these are 100 Ohm series resistors. In the case of # the low current low noise SysMon Ref Supply this is # a 1k Ohm series resistor. # # The mapping of the Voltage Monitor pins on the J3 # connector is in the same basic order as the naming # of the DCDC_? Converters in the rest of the Hub # documentation. # # # J3 Voltage # Monitor Pin Hub Supply Monitored with this Pin # ----------- ------------------------------------ # # 1 DCDC_1 FPGA_Core 0.950 Volts # 3 DCDC_2 MGT_AVCC 1.000 # 5 DCDC_3 MGT_AVTT 1.200 # 7 DCDC_4 MGT_AVAUX 1.800 Linear # 9 DCDC_5 SWCH_1V2 1.200 # 11 DCDC_6 BULK_1V8 1.800 # 13 DCDC_7 FAN_1V8 1.800 # 15 DCDC_8 BULK_3V3 3.300 # 17 DCDC_9 BULK_2V5 2.500 Linear # 21 SysMon Reference 1.250 Linear # 25 Isolated +12V 12.000 ATCA Module # # Even Numbered Pins 2 through 26 are all Grounds. # # Note that I'm skipping monitor pins #19 and #23 # as I want to keep some isolation around the # SysMon Reference monitor pin (especially to # keep Iso_12V noise out of the SysMon Reference). # # # # Start by Grounding the low side of the 1 uFd 25V # ceramic filter capacitors. # NET 'GROUND' C2351-2 C2352-2 C2353-2 C2354-2 C2355-2 NET 'GROUND' C2356-2 C2357-2 C2358-2 C2359-2 C2360-2 NET 'GROUND' C2361-2 # # Now Ground the Even J3 Voltage Monitor Pins. # NET 'GROUND' J3-2 J3-4 J3-6 J3-8 J3-10 NET 'GROUND' J3-12 J3-14 J3-16 J3-18 J3-20 NET 'GROUND' J3-22 J3-24 J3-26 # # Now connect up each of the 10 RC filter circuits # and connect them to the power supply rail that # they monitor. # # DCDC_1 FPGA_Core 0.950 Volts NET 'DCDC_1_Monitor_Point' J3-1 R2351-2 C2351-1 NET 'FPGA_CORE' R2351-1 # DCDC_2 MGT_AVCC 1.000 Volts NET 'DCDC_2_Monitor_Point' J3-3 R2352-2 C2352-1 NET 'MGT_AVCC' R2352-1 # DCDC_3 MGT_AVTT 1.200 Volts NET 'DCDC_3_Monitor_Point' J3-5 R2353-2 C2353-1 NET 'MGT_AVTT' R2353-1 # DCDC_4 MGT_AVAUX 1.800 Volts Linear NET 'DCDC_4_Monitor_Point' J3-7 R2354-2 C2354-1 NET 'MGT_AVAUX' R2354-1 # DCDC_5 SWCH_1V2 1.200 Volts NET 'DCDC_5_Monitor_Point' J3-9 R2355-2 C2355-1 NET 'SWCH_1V2' R2355-1 # DCDC_6 BULK_1V8 1.800 Volts NET 'DCDC_6_Monitor_Point' J3-11 R2356-2 C2356-1 NET 'BULK_1V8' R2356-1 # DCDC_7 FAN_1V8 1.800 Volts NET 'DCDC_7_Monitor_Point' J3-13 R2357-2 C2357-1 NET 'FAN_1V8' R2357-1 # DCDC_8 BULK_3V3 3.300 Volts NET 'DCDC_8_Monitor_Point' J3-15 R2358-2 C2358-1 NET 'BULK_3V3' R2358-1 # DCDC_9 BULK_2V5 2.500 Volts Linear NET 'DCDC_9_Monitor_Point' J3-17 R2359-2 C2359-1 NET 'BULK_2V5' R2359-1 # SysMon Reference 1.250 Volts Linear NET 'DCDC_10_Monitor_Point' J3-21 R2360-2 C2360-1 NET 'SYSMON_VREFP' R2360-1 # Isolated +12 Volt 12.0 Volts ATCA Module NET 'ISO_12V_Monitor_Point' J3-25 R2361-2 C2361-1 NET 'ISO_12V' R2361-1 # # SMB_Alert_B Signal from the Hub's # 7 DCDC Converters to the Hub's FPGA # # The connection of the Hubs_SMB_Alert_B signal to # the SMB_Alert_B pin on each DCDC Converter is shown # in that converter's net list file. Shown here in # this file is just the Hubs_SMB_Alert_B connection # to its pull-up resistor and to a 3.3V I/O pin on # the Hub's FPGA. # NET 'Hubs_SMB_Alert_B' R2989-1 NET 'BULK_3V3' R2989-2 NET 'Hubs_SMB_Alert_B' U1-AP16 # IO_L21N_T3L_N5_AD8N_84 # # Sensor I2C Bus - Nets # --------------------------- # # # Original Rev. 14-Dec-2015 # Current Rev. 21-Oct-2016 # # # This file holds all of the nets for the Sensor I2C Bus # and its associated buffer/translators. # # # # Connect Power and Ground and ByPass Caps # to the I2C Buffer/Translators # # Note the different Bulk_3V3 and Ground connections: # U1501 buffers to a 3V3 I2C bus # U1502 and U1503 buffer to 1V8 I2C buses # NET 'Bulk_3V3' U1501-12 C1501-1 C1502-1 U1501-11 NET 'GROUND' U1501-6 C1501-2 C1502-2 NET 'Bulk_3V3' U1502-12 C1511-1 C1512-1 NET 'GROUND' U1502-6 C1511-2 C1512-2 U1502-11 NET 'Bulk_3V3' U1503-12 C1521-1 C1522-1 NET 'GROUND' U1503-6 C1521-2 C1522-2 U1503-11 # # Connect the Pull-Up Resistors to the various # control and monitor pins on the Buffer/Translator chips # NET 'I2C_Buf_1501_DISCEN' U1501-2 R1503-1 NET 'I2C_Buf_1501_ACC_B' U1501-5 R1504-1 NET 'I2C_Buf_1501_READY' U1501-7 R1505-1 NET 'I2C_Buf_1501_ENABLE' U1501-1 R1506-1 NET 'Bulk_3V3' R1503-2 R1504-2 R1505-2 R1506-2 NET 'I2C_Buf_1502_DISCEN' U1502-2 R1513-1 NET 'I2C_Buf_1502_ACC_B' U1502-5 R1514-1 NET 'I2C_Buf_1502_READY' U1502-7 R1515-1 NET 'I2C_Buf_1502_ENABLE' U1502-1 R1516-1 NET 'Bulk_3V3' R1513-2 R1514-2 R1515-2 R1516-2 NET 'I2C_Buf_1503_DISCEN' U1503-2 R1523-1 NET 'I2C_Buf_1503_ACC_B' U1503-5 R1524-1 NET 'I2C_Buf_1503_READY' U1503-7 R1525-1 NET 'I2C_Buf_1503_ENABLE' U1503-1 R1526-1 NET 'Bulk_3V3' R1523-2 R1524-2 R1525-2 R1526-2 # # Now connect the ENABLE pins on the 3 I2C Buffer/Translators # to Select I/O pins in a 3V3 Bank of the Hub Virtex FPGA. # NET 'I2C_Buf_1501_ENABLE' U1-BA16 # IO_L3P_T0L_N4_AD15P_94 NET 'I2C_Buf_1502_ENABLE' U1-BA15 # IO_L1N_T0L_N1_DBC_94 NET 'I2C_Buf_1503_ENABLE' U1-BB16 # IO_L4N_T0U_N7_DBC_AD7N_94 # # Now connect the Sensor I2C Bus from the IPMC # to the "in" side of the 3x I2C Buffer/Translators. NET 'IPMC_Sensor_I2C_Bus_SCL' IPMC-183 NET 'IPMC_Sensor_I2C_Bus_SCL' U1501-4 U1502-4 U1503-4 NET 'IPMC_Sensor_I2C_Bus_SDA' IPMC-184 NET 'IPMC_Sensor_I2C_Bus_SDA' U1501-9 U1502-9 U1503-9 # # Now connect the Sensor I2C Bus (that runs between the # IPMC and the "in" side of the 3x I2C Buffer/Translators) # to the J2 Front Panel connector pins 11 and 12. NET 'IPMC_Sensor_I2C_Bus_SCL' J2-11 NET 'IPMC_Sensor_I2C_Bus_SDA' J2-12 # # Now connect the I2C Buses on the "output" side of their # I2C Buffer/Translator chips. Connect their pull-up resistors. # # NOTE: The pull-up resistors for the I2C Bus that runs # to the Hub's 7x DCDC Converters pull up to 3V3. # # The pull-up resistors for the I2C Bus that runs # to the Hub FPGA SysMon port and Master port # pull up to 1V8. # # YES, there are two connections of the # Sensor I2C Bus to the Hub FPGA: # # - Connect to its defined SysMon I2C pins. # # - Connect to a second set of pins to provide # for an I2C Bus Master in the Hub FPGA, e.g. # to allow us to control the DC/DC Conveters. # # The pull-up resistors for the Sensor I2C Bus that # runs to the ROD mezzanine are on the ROD itself. # NET 'Hub_PMBus_SCL' U1501-3 R1501-1 NET 'Hub_PMBus_SDA' U1501-10 R1502-1 NET 'Bulk_3V3' R1501-2 R1502-2 NET 'Hub_I2C_to_FPGA_SCL' U1502-3 R1511-1 NET 'Hub_I2C_to_FPGA_SDA' U1502-10 R1512-1 NET 'Bulk_1V8' R1511-2 R1512-2 NET 'Hub_I2C_to_FPGA_SCL' U1-BE16 # IO_L23P_T3U_N8_I2C_SCLK_65 NET 'Hub_I2C_to_FPGA_SDA' U1-BF16 # IO_L23N_T3U_N9_I2C_SDA_65 NET 'Hub_I2C_to_FPGA_SCL' U1-BA29 # IO_L18P_T2U_N10_AD2P_67 NET 'Hub_I2C_to_FPGA_SDA' U1-BB29 # IO_L18N_T2U_N11_AD2N_67 NET 'Hub_I2C_to_ROD_SCL' U1503-3 Meg_S1-B26 NET 'Hub_I2C_to_ROD_SDA' U1503-10 Meg_S1-C26 # # Finally connect the ByPass Capacitors for # the 1V8 supply to the Pull-Up Resistors for # the U1502 Buffer/Translator for the I2C Bus # that runs to the Hub FPGA itself, i.e. to # this FPGA's SysMon I2C port and to this # FPGA's I2C Master port. # NET 'Bulk_1V8' C1513-1 C1514-1 NET 'GROUND' C1513-2 C1514-2 # # No Connect pins on the Buffer/Translator chips # NET 'No_Conn_U1501_Fault' U1501-8 NET 'No_Conn_U1502_Fault' U1502-8 NET 'No_Conn_U1503_Fault' U1503-8 # # Hub Module - Key-In Nets File # # JTAG String # -------------- # # # Original Rev. 20-Nov-2015 # Most Recent Rev. 9-Nov-2016 # # # This file holds all of the nets associated with the # Hub Module JTAG string. This includes the front # pannel J2 connections, level translator/buffers, # Hub FPGA and ROD JTAG circuits. # # Rcall the pinout of the JTAG section of the front # panel J2 connector: # # Pin Function # --- --------------- # # 2 3V3 JTAG Reference Power # 4 TMS # 6 TCK # 8 TDO # 10 TDI # # The 5 odd pins 1, 3, 5, 7, 9 are Ground # # # Connect the 3V3 JTAG Reference power and ground # to the front panel J2 connector. # NET 'BULK_3V3' F7-2 NET 'FUSED_JTAG_POWER' F7-1 J2-2 NET 'GROUND' J2-1 J2-3 J2-5 J2-7 J2-9 # # Connections from J2 to the Level Translator chips. # # Note that we are using the "B" side to "A" side direction. # # "B" data input to "A" data output. # # Thus both the Direction pin and the OE_B pin are tied Low. # # The input "B" side has 3V3 power. # The output "A" side has 1V8 power. # NET 'TMS_FROM_J2' J2-4 R581-1 U554-14 U554-16 NET 'TCK_FROM_J2' J2-6 R582-1 U554-15 U554-17 NET 'TDI_FROM_J2' J2-10 R583-1 U554-18 NET 'TDO_TO_J2' J2-8 R590-1 NET 'TDO_FROM_U555' R590-2 U555-3 NET 'BULK_3V3' R581-2 R582-2 R583-2 # # Connect the Power and Ground and DIR and OE_B # to the U554 Translator # # The input "B" side has 3V3 power. # The output "A" side has 1V8 power. # # U554 POWER AND GROUND NET 'BULK_1V8' U554-1 NET 'BULK_3V3' U554-23 U554-24 NET 'GROUND' U554-11 U554-12 U554-13 # U554 DIR and OE_B pins: NET 'GROUND' U554-2 U554-22 # # Connect the Power and Ground and DIR # to the U555 Translator # # The input "B" side has 1V8 power. # The output "A" side has 3V3 power. # NET 'BULK_1V8' U555-8 NET 'BULK_3V3' U555-1 NET 'GROUND' U555-4 # U555 DIR pin: NET 'GROUND' U555-5 # # ByPass Capacitors for U554 and U555 Translators # NET 'BULK_1V8' C2941-1 C2943-1 NET 'GROUND' C2941-2 C2943-2 NET 'BULK_3V3' C2942-1 C2944-1 NET 'GROUND' C2942-2 C2944-2 # # Define the Un-Used Inputs and Outputs # on the Translators U554. # # NOTE that the other section of the U555 # Translator is used to make a 3V3 version # of the FPGA Configuration DONE signal. # NET 'No_Conn_U554_Pin_3' U554-3 NET 'No_Conn_U554_Pin_4' U554-4 NET 'No_Conn_U554_Pin_5' U554-5 NET 'No_Conn_U554_Pin_19' U554-19 NET 'No_Conn_U554_Pin_20' U554-20 NET 'No_Conn_U554_Pin_21' U554-21 # # Now the TMS and TCK connections to the Hub's FPGA # NET 'TMS_HUB_PRE_SERIES' U554-10 R584-2 NET 'TMS_TO_HUB_FPGA' R584-1 U1-AB15 NET 'TCK_HUB_PRE_SERIES' U554-9 R585-2 NET 'TCK_TO_HUB_FPGA' R585-1 U1-AD16 # # Now the TMS and TCK connections to the ROD # NET 'TMS_ROD_PRE_SERIES' U554-8 R586-2 NET 'TMS_TO_ROD_FPGA' R586-1 Meg_S2-J24 NET 'TCK_ROD_PRE_SERIES' U554-7 R587-2 NET 'TCK_TO_ROD_FPGA' R587-1 Meg_S2-H24 # # Now the TDI to TDO circuit # # see also the AND Buffer for the TDI to the ROD # NET 'TDI_TO_SERIES_RES' U554-6 R588-2 NET 'TDI_SERIES_TO_HUB_FPGA' R588-1 U1-AF15 JMP2-2 NET 'TD_HUB_FPGA_TO_JMP1' U1-AD15 JMP1-2 NET 'TD_TO_MUX_AND_ROD_BUF' JMP2-1 JMP1-1 NET 'TD_TO_MUX_AND_ROD_BUF' U556-3 U557-1 U557-2 NET 'TD_FROM_ROD_TO_MUX' Meg_S2-J25 U556-1 NET 'TD_FROM_MUX_TO_SERIES' U556-4 R589-2 NET 'TDO_FROM_SERIES_TO_TRANS' U555-6 R589-1 # # Now the control line to the JTAG Multiplexer U556 # # When Power Control #2 aka ROD Power Good # signal is Hi then the JTAG multiplexer switches # to include the ROD in the JTAG string. # NET 'ROD_Power_Control_2_ROD' U556-6 # # Now the Multiplexer Power and Ground connections # NET 'BULK_1V8' U556-5 C2945-1 C2946-1 NET 'GROUND' U556-2 C2945-2 C2946-2 # # Now the AND Gate Buffer for the TDI to the ROD # and its Power and Ground connections # # The input to pins 1 and 2 of this buffer is given above. # NET 'TD_TO_ROD_BUFF_RES' U557-4 R593-1 NET 'TD_BUFF_RES_TO_ROD' R593-2 Meg_S2-H25 NET 'BULK_1V8' U557-5 C2947-1 NET 'GROUND' U557-3 C2947-2 # # Finally the ROD_Present_B circuit # # with its connection to the to the Hub's FPGA. # NET 'ROD_PRESENT_B' Meg_S1-C37 R591-1 R592-1 NET 'ROD_PRESENT_B_TO_FPGA' R592-2 NET 'BULK_1V8' R591-2 NET 'ROD_PRESENT_B_TO_FPGA' U1-AW27 # IO_L14P_T2L_N2_GC_67 # # Hub Module FPGA Resistors: # # DCI Calibration, VREF Pull-Down, # # and MGT Termination Calibration # ------------------------------------ # # # Original Rev. 11-Dec-2015 # Current Rev. 23-Dec-2015 # # # This file holds all of the nets for the various # calibration and pull-down resistors that are needed # the the Select I/O Banks and the MGT Transceivers. # # # ----------------------------------------------------------- # # Now include the Digitally Controlled Impedance DCI # calibration resistors. For each Select I/O Bank the # DCI calibration resistors is 240 Ohm from the VRP # pin to Ground. # # We have these for HP Banks: 65, 66, 67, 68 - R101:R104. # # We have one of these for HP Bank 71 - R105. # # We do not include them for the unused HP Banks: 70, 72. # # The DCI VRP pins do not exist for the HR Banks: 84, 94. # NET 'Bank_65_VRP_DCI' R101-1 U1-AP21 # IO_T0U_N12_VRP_A28_65 NET 'GROUND' R101-2 NET 'Bank_66_VRP_DCI' R102-1 U1-AM27 # IO_T0U_N12_VRP_66 NET 'GROUND' R102-2 NET 'Bank_67_VRP_DCI' R103-1 U1-AP31 # IO_T0U_N12_VRP_67 NET 'GROUND' R103-2 NET 'Bank_68_VRP_DCI' R104-1 U1-AU36 # IO_T0U_N12_VRP_68 NET 'GROUND' R104-2 NET 'Bank_71_VRP_DCI' R105-1 U1-P22 # IO_T0U_N12_VRP_71 NET 'GROUND' R105-2 # # ----------------------------------------------------------- # # Now include the pull-down resistors on the VREF pins # that are required for any Select I/O Bank that uses an # I/O standard that uses a differential input buffer and # uses an internal source of VREF (VREF_Internal or VREF_Scan). # These are 1k Ohm from the VREF pin to Ground. # # We have these for the HP Banks: 65, 66, 67, 68 - R106:R109. # # We have one of these for HP Bank 71 - R110. # # We do not have these for the unused HP Banks: 70, 71, 72. # # We have these for the HR Banks: 84, 94 - R111:R112. # NET 'Bank_65_VREF' R106-1 U1-AM18 # VREF_65 NET 'GROUND' R106-2 NET 'Bank_66_VREF' R107-1 U1-AM22 # VREF_66 NET 'GROUND' R107-2 NET 'Bank_67_VREF' R108-1 U1-AM28 # VREF_67 NET 'GROUND' R108-2 NET 'Bank_68_VREF' R109-1 U1-AM32 # VREF_68 NET 'GROUND' R109-2 NET 'Bank_71_VREF' R110-1 U1-P21 # VREF_71 NET 'GROUND' R110-2 NET 'Bank_84_VREF' R111-1 U1-AM17 # VREF_84 NET 'GROUND' R111-2 NET 'Bank_94_VREF' R112-1 U1-AW16 # VREF_94 NET 'GROUND' R112-2 # # ----------------------------------------------------------- # # Now includ the required MGT Termination Calibration Resistors # for the GTH and GTY transceivers. Thsese 100 Ohm resistors # from the MGTRREF pin to the MGTAVTTCAL pin and then to # the MGTAVTT pin. # # The traces from these resistors to the MGTRREF and # MGTAVTTCAL pins must be symmetric, matched in length # and under 0.5 Ohm. # # We need all 4 of these MGT Calibration Resistors # that are located near Quads: 125, 130, 226, 231. # NET 'MGT_AVTT' R113-1 U1-AH40 # MGTAVTTRCAL_LC NET 'QUAD_125_MGTRREF' R113-2 U1-AH41 # MGTRREF_LC NET 'MGT_AVTT' R114-1 U1-D40 # MGTAVTTRCAL_LN NET 'QUAD_130_MGTRREF' R114-2 U1-D41 # MGTRREF_LN NET 'MGT_AVTT' R115-1 U1-AH7 # MGTAVTTRCAL_RC NET 'QUAD_226_MGTRREF' R115-2 U1-AH6 # MGTRREF_RC NET 'MGT_AVTT' R116-1 U1-D7 # MGTAVTTRCAL_RN NET 'QUAD_231_MGTRREF' R116-2 U1-D6 # MGTRREF_RN # # Distributed ByPass Capacitor NETs # # Key In Nets File for the # HUB-0 ATLAS L1Calo Hub Module # ---=====----------------------------- # # Original Rev. 20-Jan-2016 # Most Recent Rev. 9-Nov-2016 # # # This file holds the nets for the "Distributed" bypass capacitors. # # These are the bypass capacitors that are placed # opportunistically during routing or that are placed # because during routing it looks like the circuit could # benefit from an additional bypass capacitor, e.g. for # symmetry of the layout. # # These bypass capacitors can be on any of the power nets. # # # # Neither the: SWCH_1V2 (DCDC5) or the # FAN_1V8 (DCDC7) or the # BULK_3V3 (DCDC8) # # converters have large Tantalum capacitors as part of # their Output Filters in their main comps and nets files. # # All of the other DCDC Converters pick up Output Filter # Tantalum Capacitors as part of their supply to the FPGA. # # So here are the nets for some large Tantalum capacitors # for each of these 3 supplies. # # # There are also some Distributed ByPass Capacitors for # the BULK_1V8 bus. These are needed because, although # there are two Tantalum caps on the BULK_1V8 located by # the FPGA, this is a long way from the BULK_1V8 converter # which is located up in the North-East corner. So I # have placed some Distributed bypass caps up by it, # including one Tantalum. BULK_1V8 is DCDC6. # # # # For the SWCH_1V2 converter. # NET 'SWCH_1V2' C251-1 C252-1 C267-1 NET 'GROUND' C251-2 C252-2 C267-2 NET 'SWCH_1V2' C269-1 C270-1 C271-1 NET 'GROUND' C269-2 C270-2 C271-2 # # For the FAN_1V8 converter. # NET 'FAN_1V8' C253-1 C254-1 C255-1 C256-1 NET 'GROUND' C253-2 C254-2 C255-2 C256-2 NET 'FAN_1V8' C259-1 C260-1 C261-1 C262-1 NET 'GROUND' C259-2 C260-2 C261-2 C262-2 NET 'FAN_1V8' C263-1 C264-1 C265-1 C266-1 NET 'GROUND' C263-2 C264-2 C265-2 C266-2 NET 'FAN_1V8' C277-1 C278-1 NET 'GROUND' C277-2 C278-2 # # For the BULK_3V3 converter. # NET 'BULK_3V3' C257-1 C258-1 C268-1 C279-1 NET 'GROUND' C257-2 C258-2 C268-2 C279-2 NET 'BULK_3V3' C272-1 C273-1 NET 'GROUND' C272-2 C273-2 # # For the BULK_1V8 converter. # NET 'BULK_1V8' C274-1 C275-1 C276-1 NET 'GROUND' C274-2 C275-2 C276-2 # # Sundry Hub-0 Nets # # Hub-0 Key-In Net List File # # # Original Rev. 16-May-2015 # Current Rev. 16-Jan-2017 # # # # # Currently this Sundry Net List file contains: # # - Ground the ROD's Mounting Screw Holes # # - Ground the Hub FPGA Heat Sink Mounting Screw Holes # # - Ground the Ground Rivets and the Scope Loops # # - Nets for the Front Panel Access Output Signals # # - Nets for the Spare LVDS Crystal Oscillator # # - Nets for the Isolation Shields: ATCA Module and ROD # # - Ground connections to some of the Spare Layout Pads # on the backside of the Hub PCB # # # # # Connect the 3 Mounting Screw Holes for the # ROD Standoffs to the Ground net. # NET 'GROUND' ROD_Mezzanine-1 ROD_Mezzanine-2 ROD_Mezzanine-3 # # Connect the 4 FPGA Heat-Sink Mounting Screw Holes # to the Ground net. # NET 'GROUND' HS1-1 HS1-2 HS1-3 HS1-4 # # Ground Rivets: # # by the High-Speed Signals and # around the perimeter of the card # NET 'GROUND' VR1-1 VR2-1 VR3-1 VR4-1 VR5-1 NET 'GROUND' VR6-1 VR7-1 VR8-1 VR9-1 VR10-1 NET 'GROUND' VR11-1 VR12-1 VR13-1 VR14-1 VR15-1 NET 'GROUND' VR16-1 VR17-1 VR18-1 VR19-1 VR20-1 NET 'GROUND' VR21-1 VR22-1 VR23-1 VR24-1 VR25-1 NET 'GROUND' VR26-1 VR27-1 VR28-1 VR29-1 VR30-1 NET 'GROUND' VR31-1 VR32-1 VR33-1 VR34-1 VR35-1 NET 'GROUND' VR36-1 VR37-1 VR38-1 VR39-1 VR40-1 # # Scope Probe Ground Loops: # NET 'GROUND' WTERM81-1 WTERM82-1 WTERM83-1 WTERM84-1 NET 'GROUND' WTERM85-1 WTERM86-1 WTERM87-1 WTERM88-1 # # Access Output Signals on Front Panel J2 Connector # # This is the 1V8 to 3V3 Translator Buffer U561 to make # the two Front-Panel Access Signals from the FPGA. # # The associated series terminator resistors R561, R562 # and bypass capacitors C2931, C2932 are included here. # # Translator U561 is setup with its Direction pin Low to # send data from its 1V8 side B to its 3V3 side A. NET 'ACCESS_SIGNAL_1_FROM_FPGA' U561-6 U1-AT30 # IO_L10P_T1U_N6_QBC_AD4P_67 NET 'ACCESS_SIGNAL_2_FROM_FPGA' U561-7 U1-AT31 # IO_L10N_T1U_N7_QBC_AD4N_67 NET 'ACCESS_SIGNAL_1_TO_RESISTOR' U561-3 R561-1 NET 'ACCESS_SIGNAL_2_TO_RESISTOR' U561-2 R562-1 NET 'ACCESS_SIGNAL_1_TO_FP_CONN' R561-2 J2-15 NET 'ACCESS_SIGNAL_2_TO_FP_CONN' R562-2 J2-16 NET 'GROUND' J2-13 J2-14 # # Connect the Power and Ground and DIR # to the U561 Translator # # The input "B" side has 1V8 power. # The output "A" side has 3V3 power. # NET 'BULK_1V8' U561-8 C2931-1 NET 'BULK_3V3' U561-1 C2932-1 NET 'GROUND' U561-4 C2931-2 C2932-2 # U561 DIR pin Low Data goes from B to A: NET 'GROUND' U561-5 # # Spare LVDS Crystal Oscillator # # U562 is a location for a spare 5 x 7 mm LVDS # crystal oscillator that connectes to a Global # Clock input on the U1 FPGA. # NET 'SPARE_OSC_TO_CAP_DIR' U562-4 C2934-1 NET 'SPARE_OSC_TO_CAP_CMP' U562-5 C2935-1 NET 'SPARE_OSC_TO_FPGA_DIR' C2934-2 U1-AU28 # IO_L11P_T1U_N8_GC_67 NET 'SPARE_OSC_TO_FPGA_CMP' C2935-2 U1-AV28 # IO_L11N_T1U_N9_GC_67 NET 'SPARE_OSC_ENB_DIS' U562-1 NET 'No_Conn_SPARE_OSC' U562-2 NET 'BULK_3V3' U562-6 C2933-1 NET 'GROUND' U562-3 C2933-2 # # The Hub PCB top surface layer has 3 Isolation Shields # # - between Hub and the ATCA Power Input Module # - between Hub and the ATCA Isolate 12V Module # - between Hub and the ROD # # The following nets connect these isolation shields # through resistors to the Hub's Ground Planes. # NET 'Shield_ATCA_Entry_Module' R991-2 NET 'Shield_ATCA_12V_Module' R992-1 NET 'Shield_Hub_ROD' R993-1 NET 'GROUND' R991-1 R992-2 R993-2 # # Ground connections to some of the Spare Layout Pads # on the backside of the Hub PCB # NET 'GROUND' X103-2 X104-3