# # This is the Key In Net List file for the Hub Module # # Clock 40.08 MHz Distribution Nets # ------------------------------------------------------ # # # Original Rev. 16-Apr-2015 # Most Recent Rev. 20-Jul-2016 # # # This file holds the Nets involved with the Distribution # of the 40.08 MHz LHC Clock signals. # # Specifically this nets file describes the outputs from # both the First and the Second 40.08 MHz Fanout chips, # i.e. the 4 way fanout U503 and the 16 way fanout U504. # # The outputs from the 4 way fanout U503 are always active # and they will be listed first. # # The outputs from the 16 way fanout U504 are only active # if this is the Hub Module that receives the FELIX Optical # TTC clock signal and distributes it over the backplane to # the 12 FEX cards and to the Other Hub. # # # #=========================================================== # # # Outputs from the 4 Way 40.08 MHz Fanout U503 # # # 40.08 MHz LHC Clock to the ROD Mezzanine. # NET 'Clk_to_Cap_to_ROD_Dir' U503-13 C1627-1 NET 'Clk_to_Cap_to_ROD_Cmp' U503-14 C1628-1 NET 'ROD_LHC_CLK_Dir' C1627-2 Meg_S1-C39 NET 'ROD_LHC_CLK_Cmp' C1628-2 Meg_S1-B39 # # 40.08 MHz Logic Clock to a Global Clock Input # on This Hub's Virtex FPGA. # NET 'Clk_40_to_Cap_to_FPGA_Logic_Dir' U503-15 C1629-1 NET 'Clk_40_to_Cap_to_FPGA_Logic_Cmp' U503-16 C1630-1 NET 'Logic_Clk_40.08_MHz_to_FPGA_Dir' C1629-2 U1-J24 # IO_L12P_T1U_N10_GC_71 NET 'Logic_Clk_40.08_MHz_to_FPGA_Cmp' C1630-2 U1-H24 # IO_L12N_T1U_N11_GC_71 # # 40.08 MHz Reference to the 320.64 MHz PLL # the high frequency clock generator for the Hub's # Virtex FPGA MGT Transceivers. # NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Dir' U503-9 NET 'Clk_40.08_MHz_Ref_to_HF_PLL_Cmp' U503-10 # # 40.08 MHz Clock output from the First Fanout that # drives the Input 0 of the Second 40.08 MHz Fanout. # NET 'Drive_to_Second_40.08_MHz_Fanout_Dir' U503-11 NET 'Drive_to_Second_40.08_MHz_Fanout_Cmp' U503-12 # # There are no spare outputs from the First 40.08 MHz # Fanout so there are no "No_Conn" pins in this section. # # #=========================================================== # # # Outputs from the 16 Way 40.08 MHz Fanout U504 # # # Nets to carry the 40.08 MHz LHC Clock from the # 16 Way Clock Fanout Chip to the AC Coupling Caps # for the Backplane Zone 2 distribution to FEX cards # and to the Other Hub. # NET 'Clk_to_Cap_to_Other_Hub_Dir' U504-18 C1601-1 NET 'Clk_to_Cap_to_Other_Hub_Cmp' U504-19 C1602-1 NET 'Clk_to_Cap_to_FEX_03_Dir' U504-20 C1603-1 NET 'Clk_to_Cap_to_FEX_03_Cmp' U504-21 C1604-1 NET 'Clk_to_Cap_to_FEX_04_Dir' U504-22 C1605-1 NET 'Clk_to_Cap_to_FEX_04_Cmp' U504-23 C1606-1 NET 'Clk_to_Cap_to_FEX_05_Dir' U504-25 C1607-1 NET 'Clk_to_Cap_to_FEX_05_Cmp' U504-26 C1608-1 NET 'Clk_to_Cap_to_FEX_06_Dir' U504-27 C1609-1 NET 'Clk_to_Cap_to_FEX_06_Cmp' U504-28 C1610-1 NET 'Clk_to_Cap_to_FEX_07_Dir' U504-29 C1611-1 NET 'Clk_to_Cap_to_FEX_07_Cmp' U504-30 C1612-1 NET 'Clk_to_Cap_to_FEX_08_Dir' U504-31 C1613-1 NET 'Clk_to_Cap_to_FEX_08_Cmp' U504-32 C1614-1 NET 'Clk_to_Cap_to_FEX_09_Dir' U504-33 C1615-1 NET 'Clk_to_Cap_to_FEX_09_Cmp' U504-34 C1616-1 NET 'Clk_to_Cap_to_FEX_10_Dir' U504-35 C1617-1 NET 'Clk_to_Cap_to_FEX_10_Cmp' U504-36 C1618-1 NET 'Clk_to_Cap_to_FEX_11_Dir' U504-38 C1619-1 NET 'Clk_to_Cap_to_FEX_11_Cmp' U504-39 C1620-1 NET 'Clk_to_Cap_to_FEX_12_Dir' U504-40 C1621-1 NET 'Clk_to_Cap_to_FEX_12_Cmp' U504-41 C1622-1 NET 'Clk_to_Cap_to_FEX_13_Dir' U504-42 C1623-1 NET 'Clk_to_Cap_to_FEX_13_Cmp' U504-43 C1624-1 NET 'Clk_to_Cap_to_FEX_14_Dir' U504-44 C1625-1 NET 'Clk_to_Cap_to_FEX_14_Cmp' U504-45 C1626-1 # # There are 3 spare outputs on the Second 40.08 MHz Fanout. # These 3 pairs are defined here as No_Conn pins. # NET 'No_Conn_Second_40_MHz_FO_Out_0_Dir' U504-14 NET 'No_Conn_Second_40_MHz_FO_Out_0_Cmp' U504-15 NET 'No_Conn_Second_40_MHz_FO_Out_1_Dir' U504-16 NET 'No_Conn_Second_40_MHz_FO_Out_1_Cmp' U504-17 NET 'No_Conn_Second_40_MHz_FO_Out_15_Dir' U504-46 NET 'No_Conn_Second_40_MHz_FO_Out_15_Cmp' U504-47 # #=========================================================== # # # AC Coupling Capacitor to Zone 2 Connector Nets # # In all cases the 40.08 MHz LHC Clock is carried over # the backplane on the Fabric Interface Tx Port 0 # to the 12 FEX cards and to the Other Hub Module. # # # Clock to Other Hub ATCA Tx0[01] NET 'Clk_to_Other_Hub_Dir' C1601-2 J23-A4 NET 'Clk_to_Other_Hub_Cmp' C1602-2 J23-B4 # # Clock to FEX-03 Logical Slot 3 ATCA Tx0[02] NET 'Clk_to_FEX_03_Dir' C1603-2 J23-A2 NET 'Clk_to_FEX_03_Cmp' C1604-2 J23-B2 # # Clock to FEX-04 Logical Slot 4 ATCA Tx0[03] NET 'Clk_to_FEX_04_Dir' C1605-2 J22-A10 NET 'Clk_to_FEX_04_Cmp' C1606-2 J22-B10 # # Clock to FEX-05 Logical Slot 5 ATCA Tx0[04] NET 'Clk_to_FEX_05_Dir' C1607-2 J22-A8 NET 'Clk_to_FEX_05_Cmp' C1608-2 J22-B8 # # Clock to FEX-06 Logical Slot 6 ATCA Tx0[05] NET 'Clk_to_FEX_06_Dir' C1609-2 J22-A6 NET 'Clk_to_FEX_06_Cmp' C1610-2 J22-B6 # # Clock to FEX-07 Logical Slot 7 ATCA Tx0[06] NET 'Clk_to_FEX_07_Dir' C1611-2 J22-A4 NET 'Clk_to_FEX_07_Cmp' C1612-2 J22-B4 # # Clock to FEX-08 Logical Slot 8 ATCA Tx0[07] NET 'Clk_to_FEX_08_Dir' C1613-2 J22-A2 NET 'Clk_to_FEX_08_Cmp' C1614-2 J22-B2 # # Clock to FEX-09 Logical Slot 9 ATCA Tx0[08] NET 'Clk_to_FEX_09_Dir' C1615-2 J21-A10 NET 'Clk_to_FEX_09_Cmp' C1616-2 J21-B10 # # Clock to FEX-10 Logical Slot 10 ATCA Tx0[09] NET 'Clk_to_FEX_10_Dir' C1617-2 J21-A8 NET 'Clk_to_FEX_10_Cmp' C1618-2 J21-B8 # # Clock to FEX-11 Logical Slot 11 ATCA Tx0[10] NET 'Clk_to_FEX_11_Dir' C1619-2 J21-A6 NET 'Clk_to_FEX_11_Cmp' C1620-2 J21-B6 # # Clock to FEX-12 Logical Slot 12 ATCA Tx0[11] NET 'Clk_to_FEX_12_Dir' C1621-2 J21-A4 NET 'Clk_to_FEX_12_Cmp' C1622-2 J21-B4 # # Clock to FEX-13 Logical Slot 13 ATCA Tx0[12] NET 'Clk_to_FEX_13_Dir' C1623-2 J21-A2 NET 'Clk_to_FEX_13_Cmp' C1624-2 J21-B2 # # Clock to FEX-14 Logical Slot 14 ATCA Tx0[13] NET 'Clk_to_FEX_14_Dir' C1625-2 J20-A10 NET 'Clk_to_FEX_14_Cmp' C1626-2 J20-B10