# # # LED and LEMO Translator and Driver Nets # # Key In Net List file for the Hub Module # ------------------------------------------------- # # # Original Rev. 25-Sep-2015 # Most Recent Rev. 5-Dec-2016 # # # This file holds the nets for the Translators and Drivers # for the LEDs and the LEMO Connector that are controlled # by both the ROD and by the Hub. # # # ROD - Front panel signal table: # # MegArray Old-Old Old New LED # S1 Pin# Name Name Current Name Color # -------- ------- ------ ---------------- ------ # # B1 FP1 LED-0 Phy_LED2_B Green # B2 FP3 LED-Y Phy_LED1_B Yellow # B3 FP5 LED-B Prog_Done_LED_B Green # B4 FP7 LEMO-0 LEMO -- # # C1 FP2 LED-1 Pwr_Good_LED_B Green # C2 FP4 LED-R SMB_Alert_LED_B RED # C3 FP6 LED-G GP_LED_B Blue # C4 FP8 LEMO-1 Run_LED_B Blue # # # # ROD Front-Panel LEDs & Lemo # # # Nets from the S1 MegArray Connector # to the 1V8 Inputs on the Translator # NET 'ROD_FP_MegArray_B1' Meg_S1-B1 U551-3 NET 'ROD_FP_MegArray_C1' Meg_S1-C1 U551-4 NET 'ROD_FP_MegArray_B2' Meg_S1-B2 U551-5 NET 'ROD_FP_MegArray_C2' Meg_S1-C2 U551-6 NET 'ROD_FP_MegArray_B3' Meg_S1-B3 U551-7 NET 'ROD_FP_MegArray_C3' Meg_S1-C3 U551-8 NET 'ROD_FP_MegArray_B4' Meg_S1-B4 U551-9 NET 'ROD_FP_MegArray_C4' Meg_S1-C4 U551-10 # # ROD Front-Panel LEDs & Lemo # # ROD Front Panel Connections from the ROD Translator # to the LED or LEMO through a Driver or Direct # # B1 FP1 LED-0 Phy_LED2_B Green # LED_57 RJ1-LED1 RJ1 Lower or Left Lnk Grn MegArray S1 B1 # led_connection_nets:NET 'LED_57_Cath_Res' R257-2 NET 'LED_57_Cath_Res' U551-21 # ROD_FP_B1_LED # B2 FP3 LED-Y Phy_LED1_B Yellow # LED_58 RJ1-LED4 RJ1 Lower or Left Act Yel MegArray S1 B2 # led_connection_nets:NET 'LED_58_Cath_Res' R258-2 NET 'LED_58_Cath_Res' U551-19 # ROD_FP_B2_LED # B3 FP5 LED-B Prog_Done_LED_B Green # LED_45 Prog_Done_LED_B Green MegArray S1 B3 # led_connection_nets:NET 'LED_45_Cath_Res' R245-2 NET 'LED_45_Cath_Res' U551-17 # ROD_FP_B3_LED # C1 FP2 LED-1 Pwr_Good_LED_B Green # LED_46 Pwr_Good_LED_B Green MegArray S1 C1 # led_connection_nets:NET 'LED_46_Cath_Res' R246-2 NET 'LED_46_Cath_Res' U551-20 # ROD_FP_C1_LED # C2 FP4 LED-R SMB_Alert_LED_B RED # LED_47 SMB_Alert_LED_B RED MegArray S1 C2 # led_connection_nets:NET 'LED_47_Cath_Res' R247-2 NET 'LED_47_Cath_Res' U551-18 # ROD_FP_C2_LED # C3 FP6 LED-G GP_LED_B Blue # LED_48 GP_LED_B Blue MegArray S1 C3 # led_connection_nets:NET 'LED_48_Cath_Res' R248-2 NET 'ROD_FP_MegArray_C3_Drv_In' U551-16 U552-1 NET 'LED_48_Cath_Res' U552-2 # ROD_FP_C3_LED # C4 FP8 LEMO-1 Run_LED_B Blue # LED_49 Run_LED_B Blue MegArray S1 C4 # led_connection_nets:NET 'LED_49_Cath_Res' R249-2 NET 'ROD_FP_MegArray_C4_Drv_In' U551-14 U552-3 NET 'LED_49_Cath_Res' U552-4 # ROD_FP_C4_LED # B4 FP7 LEMO-0 LEMO -- NET 'ROD_FP_MegArray_B4_Drv_In' U551-15 U552-5 U552-13 U552-11 U552-9 NET 'LEMO_Center' Wterm61-1 U552-6 U552-12 U552-10 U552-8 # ROD_FP_B4_LEMO NET 'GROUND' Wterm62-1 NET 'LEMO_Center' R2901-1 NET 'BULK_3V3' R2901-2 # # Hub Front-Panel LEDs # # Hub Front Panel Connections through the Hub Translator # to the Hub Front-Panel LEDs # # # Hub Phys Chip U21 & U22 Front-Panel LEDs # # # LED Ref # Desgntr Display Source -Pin # ------- --------------------- -------------------------- # # LE41 Hub FPGA to Sw Link Grn Phys U22 LED2-15 # LE42 Hub FPGA to Sw Active Yel Phys U22 LED1-17 # # LE43 Hub FPGA to BI Ch 2 Link Grn Phys U21 LED2-15 # LE44 Hub FPGA to BI Ch 2 Active Yel Phys U21 LED1-17 # NET 'PHYS_U22_LED1__PHYAD0' U553-5 NET 'LED_42_Cath_Res' U553-19 NET 'PHYS_U22_LED2__PHYAD1' U553-6 NET 'LED_41_Cath_Res' U553-18 NET 'PHYS_U21_LED1__PHYAD0' U553-3 NET 'LED_44_Cath_Res' U553-21 NET 'PHYS_U21_LED2__PHYAD1' U553-4 NET 'LED_43_Cath_Res' U553-20 # # Hub FPGA Driven LEDs # # The Hub Module's FPGA directly controls 3 Front Panel # LEDs using 3 of its Select I/O lines. # # LED Ref # Desgntr Display Source -Pin # ------- --------------------- -------------------------- # # LE50 Hub FPGA LED Grn Hub FPGA Select I/O ?? # LE51 Hub FPGA LED Yel Hub FPGA Select I/O ?? # LE52 Hub FPGA LED Red Hub FPGA Select I/O ?? # # For now I will connect these LED circuits for Bank 67 # a 1V8 HP Bank on the ultrascale FPGA. # NET 'HUB_FPGA_LED50_DRV' U553-7 U1-BF29 # IO_L22N_T3U_N7_DBC_AD0N_68 NET 'HUB_FPGA_LED51_DRV' U553-8 U1-BF30 # IO_L24P_T3U_N10_68 NET 'HUB_FPGA_LED52_DRV' U553-9 U1-BF31 # IO_L24N_T3U_N11_68 NET 'LED_50_Cath_Res' U553-17 NET 'LED_51_Cath_Res' U553-16 NET 'LED_52_Cath_Res' U553-15 # # There is currently one Un-Used Section in # the U553 Translator/Driver # Ground its input and No_Conn net its output. # NET 'GROUND' U553-10 NET 'No_Conn_U553_Pin_14' U553-14 # # Power Supply and ByPass Capacitor connections to these # Translators and Drivers & Connect their DIR and OE_B pins. # # The setup of the U551 and U553 Translators is the following: # # "A" side has 1.8 Volt Vcc # "B" side had 3.3 Volt Vcc # # The Direction is from "A" to "B" # which requires the DIR pin to be HI. # # Outputs are always Enabled # which requires the OE_B pin to be LOW. # # # Translator U551 VCC_A pin #1 1V8 # Translator U551 VCC_B pins #23, #24 3V3 # NET 'BULK_1V8' U551-1 NET 'BULK_3V3' U551-23 U551-24 NET 'GROUND' U551-11 U551-12 U551-13 NET 'BULK_1V8' C2902-1 NET 'BULK_3V3' C2901-2 NET 'GROUND' C2901-1 C2902-2 # # Translator U551 DIR pin #2 HI "A" --> "B" # Translator U551 OE_B pin #22 LOW Enabled # NET 'BULK_1V8' U551-2 NET 'GROUND' U551-22 # # Open-Drain Hex Buffer U552 is powered from Vcc of 3V3. # NET 'BULK_3V3' U552-14 C2903-1 NET 'GROUND' U552-7 C2903-2 # # Translator U553 VCC_A pin #1 1V8 # Translator U553 VCC_B pins #23, #24 3V3 # NET 'BULK_1V8' U553-1 NET 'BULK_3V3' U553-23 U553-24 NET 'GROUND' U553-11 U553-12 U553-13 NET 'BULK_1V8' C2905-1 NET 'BULK_3V3' C2904-2 NET 'GROUND' C2904-1 C2905-2 # # Translator U553 DIR pin #2 HI "A" --> "B" # Translator U553 OE_B pin #22 LOW Enabled # NET 'BULK_1V8' U553-2 NET 'GROUND' U553-22