#
#                      Sundry Hub-0 Nets
#
#                Hub-0  Key-In  Net List  File
#
#
#                                     Original Rev.  16-May-2015
#                                      Current Rev.  16-Jan-2017
#
#
#
#
#   Currently this  Sundry Net List  file contains:
#
#   - Ground the ROD's Mounting Screw Holes
#
#   - Ground the Hub FPGA Heat Sink Mounting Screw Holes
#
#   - Ground the Ground Rivets and the Scope Loops
#
#   - Nets for the Front Panel Access Output Signals
#
#   - Nets for the Spare LVDS Crystal Oscillator
#
#   - Nets for the Isolation Shields: ATCA Module and ROD
#
#   - Ground connections to some of the Spare Layout Pads
#     on the backside of the Hub PCB
#
#
#



#
#   Connect the  3  Mounting Screw Holes  for the
#   ROD Standoffs  to the Ground net.
#

NET  'GROUND'   ROD_Mezzanine-1   ROD_Mezzanine-2   ROD_Mezzanine-3




#
#   Connect the  4 FPGA Heat-Sink  Mounting Screw Holes
#   to the Ground net.
#

NET  'GROUND'   HS1-1   HS1-2   HS1-3   HS1-4





#
#   Ground Rivets:
#
#      by the High-Speed Signals  and
#      around the perimeter of the card
#

NET  'GROUND'   VR1-1    VR2-1    VR3-1    VR4-1    VR5-1
NET  'GROUND'   VR6-1    VR7-1    VR8-1    VR9-1    VR10-1
NET  'GROUND'   VR11-1   VR12-1   VR13-1   VR14-1   VR15-1
NET  'GROUND'   VR16-1   VR17-1   VR18-1   VR19-1   VR20-1

NET  'GROUND'   VR21-1   VR22-1   VR23-1   VR24-1   VR25-1
NET  'GROUND'   VR26-1   VR27-1   VR28-1   VR29-1   VR30-1
NET  'GROUND'   VR31-1   VR32-1   VR33-1   VR34-1   VR35-1
NET  'GROUND'   VR36-1   VR37-1   VR38-1   VR39-1   VR40-1




#
#   Scope Probe Ground Loops:
#

NET  'GROUND'   WTERM81-1    WTERM82-1    WTERM83-1    WTERM84-1
NET  'GROUND'   WTERM85-1    WTERM86-1    WTERM87-1    WTERM88-1





#
#     Access Output Signals  on  Front Panel J2 Connector
#
#   This is the 1V8 to 3V3 Translator Buffer  U561  to make
#   the two Front-Panel Access Signals  from the FPGA.
#
#   The associated series terminator resistors  R561, R562
#   and bypass capacitors  C2931, C2932  are included here.
#
#   Translator U561 is setup with its Direction pin Low to
#   send data from its  1V8 side B  to  its  3V3 side A.

NET  'ACCESS_SIGNAL_1_FROM_FPGA'     U561-6   U1-AT30    # IO_L10P_T1U_N6_QBC_AD4P_67
NET  'ACCESS_SIGNAL_2_FROM_FPGA'     U561-7   U1-AT31    # IO_L10N_T1U_N7_QBC_AD4N_67

NET  'ACCESS_SIGNAL_1_TO_RESISTOR'   U561-3   R561-1
NET  'ACCESS_SIGNAL_2_TO_RESISTOR'   U561-2   R562-1

NET  'ACCESS_SIGNAL_1_TO_FP_CONN'    R561-2   J2-15
NET  'ACCESS_SIGNAL_2_TO_FP_CONN'    R562-2   J2-16

NET  'GROUND'                         J2-13   J2-14



#
#   Connect the  Power and Ground and DIR
#   to the  U561  Translator
#
#      The  input "B" side has 1V8 power.
#      The output "A" side has 3V3 power.
#

NET  'BULK_1V8'   U561-8   C2931-1

NET  'BULK_3V3'   U561-1   C2932-1

NET  'GROUND'     U561-4   C2931-2   C2932-2



#   U561  DIR  pin Low  Data goes from B to A:

NET  'GROUND'     U561-5






#
#         Spare LVDS Crystal Oscillator
#
#   U562 is a location for a spare 5 x 7 mm LVDS
#   crystal oscillator that connectes to a Global
#   Clock input on the U1 FPGA.
#

NET  'SPARE_OSC_TO_CAP_DIR'    U562-4    C2934-1
NET  'SPARE_OSC_TO_CAP_CMP'    U562-5    C2935-1

NET  'SPARE_OSC_TO_FPGA_DIR'   C2934-2   U1-AU28    # IO_L11P_T1U_N8_GC_67
NET  'SPARE_OSC_TO_FPGA_CMP'   C2935-2   U1-AV28    # IO_L11N_T1U_N9_GC_67

NET  'SPARE_OSC_ENB_DIS'       U562-1
NET  'No_Conn_SPARE_OSC'       U562-2

NET  'BULK_3V3'                U562-6    C2933-1
NET  'GROUND'                  U562-3    C2933-2






#
#   The Hub PCB top surface layer has 3 Isolation Shields
#
#     - between Hub and the ATCA Power Input Module
#     - between Hub and the ATCA Isolate 12V Module
#     - between Hub and the ROD
#
#   The following nets connect these  isolation shields
#   through resistors  to the Hub's Ground Planes.
#

NET  'Shield_ATCA_Entry_Module'   R991-2
NET  'Shield_ATCA_12V_Module'     R992-1
NET  'Shield_Hub_ROD'             R993-1

NET  'GROUND'   R991-1   R992-2   R993-2






#
#   Ground connections to some of the Spare Layout Pads
#   on the backside of the Hub PCB
#

NET  'GROUND'   X103-2   X104-3