# # Ultra FPGA to U21 U22 Phys Chips Nets # ------------------------------------------ # # Initial Rev. 17-Sept-2015 # Current Rev. 22-Dec-2016 # # # This file holds all of the connections between the Hub's # FPGA and the U21 U22 Phys Chips. # # The 16 connections per Phys chip are: # # - RGMII data and clock Phys Chip --> FPGA 6 lines # # - RGMII data and clock FPGA --> Phys Chip 6 lines # # - MDC MDIO Management FPGA <--> Phys Chip 2 lines # # - Miscellaneous 2 lines # 125 MHz Clk Phys Chip --> FPGA # Interrupt Phys Chip --> FPGA # # # # *** Connection to/from the U21 Phys Chip *** # *** *** # *** with Select I/O Bank 68 *** # # # # RGMII Bus connections to U21 Phys Chip # NET 'Phys_U21_RXD0__MODE0' U1-BC31 # Output from FPGA IO_L23P_T3U_N8_68 NET 'Phys_U21_RXD1__MODE1' U1-AY32 # Input to FPGA IO_L15P_T2L_N4_AD11P_68 NET 'Phys_U21_RXD2__MODE2' U1-BB33 # Input to FPGA IO_L17N_T2U_N9_AD10N_68 NET 'Phys_U21_RXD3__MODE3' U1-AY33 # Input to FPGA IO_L14N_T2L_N3_GC_68 NET 'Phys_U21_RX_DV__CLK125_EN' U1-BB31 # Input to FPGA IO_L21N_T3L_N5_AD8N_68 NET 'Phys_U21_RX_CLK__PHYAD2' U1-AV33 # Input to FPGA IO_L11P_T1U_N8_GC_68 NET 'Phys_U21_TXD0' U1-BA36 # Output from FPGA IO_L18P_T2U_N10_AD2P_68 NET 'Phys_U21_TXD1' U1-AY35 # Output from FPGA IO_L13N_T2L_N1_GC_QBC_68 NET 'Phys_U21_TXD2' U1-BB36 # Output from FPGA IO_L18N_T2U_N11_AD2N_68 NET 'Phys_U21_TXD3' U1-BA35 # Output from FPGA IO_T2U_N12_68 NET 'Phys_U21_TX_EN' U1-BB34 # Output from FPGA IO_L16N_T2U_N7_QBC_AD3N_68 NET 'Phys_U21_GTX_CLK' U1-BA34 # Output from FPGA IO_L16P_T2U_N6_QBC_AD3P_68 # # Management Bus connections to U21 Phys Chip # NET 'Phys_U21_MDC' U1-BB32 # Input to FPGA IO_L17P_T2U_N8_AD10P_68 NET 'Phys_U21_MDIO' U1-BA30 # FPGA Input/Output IO_T3U_N12_68 # # Miscellaneous connections to U21 Phys Chip # NET 'Phys_U21_CLK125__LED_MODE' U1-AU33 # Input to FPGA IO_L12P_T1U_N10_GC_68 NET 'Phys_U21_INT_B' U1-BC30 # Input to FPGA IO_L19N_T3L_N1_DBC_AD9N_68 # # # *** Connection to/from the U22 Phys Chip *** # *** *** # *** with Select I/O Bank 68 *** # # # # RGMII Bus connections to U22 Phys Chip # NET 'Phys_U22_RXD0__MODE0' U1-AV35 # Input to FPGA IO_L9P_T1L_N4_AD12P_68 NET 'Phys_U22_RXD1__MODE1' U1-AV36 # Input to FPGA IO_L10P_T1U_N6_QBC_AD4P_68 NET 'Phys_U22_RXD2__MODE2' U1-AV34 # Input to FPGA IO_L11N_T1U_N9_GC_68 NET 'Phys_U22_RXD3__MODE3' U1-AU32 # Input to FPGA IO_L8N_T1L_N3_AD5N_68 NET 'Phys_U22_RX_DV__CLK125_EN' U1-AW32 # Input to FPGA IO_T1U_N12_68 NET 'Phys_U22_RX_CLK__PHYAD2' U1-AW33 # Input to FPGA IO_L14P_T2L_N2_GC_68 NET 'Phys_U22_TXD0' U1-AR36 # Output from FPGA IO_L6P_T0U_N10_AD6P_68 NET 'Phys_U22_TXD1' U1-AT36 # Output from FPGA IO_L6N_T0U_N11_AD6N_68 NET 'Phys_U22_TXD2' U1-AR35 # Output from FPGA IO_L4P_T0U_N6_DBC_AD7P_68 NET 'Phys_U22_TXD3' U1-AT35 # Output from FPGA IO_L4N_T0U_N7_DBC_AD7N_68 NET 'Phys_U22_TX_EN' U1-AU34 # Output from FPGA IO_L12N_T1U_N11_GC_68 NET 'Phys_U22_GTX_CLK' U1-AT34 # Output from FPGA IO_L2N_T0L_N3_68 # # Management Bus connections to U22 Phys Chip # NET 'Phys_U22_MDC' U1-AW36 # Input to FPGA IO_L10N_T1U_N7_QBC_AD4N_68 NET 'Phys_U22_MDIO' U1-AW35 # FPGA Input/Output IO_L9N_T1L_N5_AD12N_68 # # Miscellaneous connections to U22 Phys Chip # NET 'Phys_U22_CLK125__LED_MODE' U1-AY34 # Input to FPGA IO_L13P_T2L_N0_GC_QBC_68 NET 'Phys_U22_INT_B' U1-BA31 # Input to FPGA IO_L21P_T3L_N4_AD8P_68