Found 52 pins for U22 which is of type IC_KSZ9031RNX ------------------------------------------------------ Pins sorted by Pin Name 1 = Phys_U22_AVDDH AVDDH 3V3 from line 189 of rgmii_phys_chip_power_gnd_nets 2 = Phys_U22_TXRX_A_DIR TXRXP_A I/O from line 216 of rgmii_phys_chip_u22_nets 3 = Phys_U22_TXRX_A_CMP TXRXM_A I/O from line 217 of rgmii_phys_chip_u22_nets 4 = Phys_U22_AVDDL AVDDL 1V2 from line 139 of rgmii_phys_chip_power_gnd_nets 5 = Phys_U22_TXRX_B_DIR TXRXP_B I/O from line 219 of rgmii_phys_chip_u22_nets 6 = Phys_U22_TXRX_B_CMP TXRXM_B I/O from line 220 of rgmii_phys_chip_u22_nets 7 = Phys_U22_TXRX_C_DIR TXRXP_C I/O from line 222 of rgmii_phys_chip_u22_nets 8 = Phys_U22_TXRX_C_CMP TXRXM_C I/O from line 223 of rgmii_phys_chip_u22_nets 9 = Phys_U22_AVDDL AVDDL 1V2 from line 139 of rgmii_phys_chip_power_gnd_nets 10 = Phys_U22_TXRX_D_DIR TXRXP_D I/O from line 225 of rgmii_phys_chip_u22_nets 11 = Phys_U22_TXRX_D_CMP TXRXM_D I/O from line 226 of rgmii_phys_chip_u22_nets 12 = Phys_U22_AVDDH AVDDH 3V3 from line 189 of rgmii_phys_chip_power_gnd_nets 13 = NO_CONN_Phys_U22_NC_PIN_13 NC from line 139 of rgmii_phys_chip_u22_nets 14 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 15 = Phys_U22_LED2__PHYAD1 LED2/PHYAD1 I/O from line 124 of rgmii_phys_chip_u22_nets 16 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 17 = Phys_U22_LED1__PHYAD0 LED1/PHYAD0/PME_N1 I/O from line 120 of rgmii_phys_chip_u22_nets 18 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 19 = Phys_U22_TXD0 TXD0 I from line 162 of rgmii_phys_chip_u22_nets 20 = Phys_U22_TXD1 TXD1 I from line 163 of rgmii_phys_chip_u22_nets 21 = Phys_U22_TXD2 TXD2 I from line 164 of rgmii_phys_chip_u22_nets 22 = Phys_U22_TXD3 TXD3 I from line 165 of rgmii_phys_chip_u22_nets 23 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 24 = Phys_U22_GTX_CLK GTX_CLK I from line 167 of rgmii_phys_chip_u22_nets 25 = Phys_U22_TX_EN TX_EN I from line 169 of rgmii_phys_chip_u22_nets 26 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 27 = Phys_U22_RXD3__MODE3 RXD3/MODE3 I/O from line 61 of rgmii_phys_chip_u22_nets 28 = Phys_U22_RXD2__MODE2 RXD2/MODE2 I/O from line 64 of rgmii_phys_chip_u22_nets 29 = GROUND VSS GND from line 197 of rgmii_phys_chip_power_gnd_nets 30 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 31 = Phys_U22_RXD1__MODE1 RXD1/MODE1 I/O from line 68 of rgmii_phys_chip_u22_nets 32 = Phys_U22_RXD0__MODE0 RXD0/MODE0 I/O from line 73 of rgmii_phys_chip_u22_nets 33 = Phys_U22_RX_DV__CLK125_EN RX_DV/CLK125_EN I/O from line 96 of rgmii_phys_chip_u22_nets 34 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 35 = Phys_U22_RX_CLK__PHYAD2 RX_CLK/PHYAD2 I/O from line 128 of rgmii_phys_chip_u22_nets 36 = Phys_U22_MDC MDC Ipu from line 191 of rgmii_phys_chip_u22_nets 37 = Phys_U22_MDIO MDIO Ipu/O from line 192 of rgmii_phys_chip_u22_nets 38 = Phys_U22_INT_B INT_N/PME_N2 O from line 204 of rgmii_phys_chip_u22_nets 39 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 40 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 41 = Phys_U22_CLK125__LED_MODE CLK125_NDO/LED_MODE I/O from line 85 of rgmii_phys_chip_u22_nets 42 = Phys_Chips_RESET_B RESET_N Ipu from line 202 of rgmii_phys_chip_u22_nets 43 = NO_CONN_Phys_U22_LDO_PIN_43 LDO_O O from line 141 of rgmii_phys_chip_u22_nets 44 = Phys_U22_AVDD_PLL AVDDL_PLL 1V2 from line 143 of rgmii_phys_chip_power_gnd_nets 45 = NO_CONN_Phys_U22_X0_PIN_45 XO O from line 143 of rgmii_phys_chip_u22_nets 46 = Phys_U22_X1 XI I from line 180 of rgmii_phys_chip_u22_nets 47 = NO_CONN_Phys_U22_NC_PIN_47 NC from line 145 of rgmii_phys_chip_u22_nets 48 = Phys_U22_ISET ISET I/O from line 45 of rgmii_phys_chip_u22_nets 49 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 50 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 51 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 52 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets ------------------------------------------------------ Pins sorted by Net Name 52 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 49 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 51 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 50 = GROUND Paddle GND from line 197 of rgmii_phys_chip_power_gnd_nets 29 = GROUND VSS GND from line 197 of rgmii_phys_chip_power_gnd_nets 43 = NO_CONN_Phys_U22_LDO_PIN_43 LDO_O O from line 141 of rgmii_phys_chip_u22_nets 13 = NO_CONN_Phys_U22_NC_PIN_13 NC from line 139 of rgmii_phys_chip_u22_nets 47 = NO_CONN_Phys_U22_NC_PIN_47 NC from line 145 of rgmii_phys_chip_u22_nets 45 = NO_CONN_Phys_U22_X0_PIN_45 XO O from line 143 of rgmii_phys_chip_u22_nets 42 = Phys_Chips_RESET_B RESET_N Ipu from line 202 of rgmii_phys_chip_u22_nets 1 = Phys_U22_AVDDH AVDDH 3V3 from line 189 of rgmii_phys_chip_power_gnd_nets 12 = Phys_U22_AVDDH AVDDH 3V3 from line 189 of rgmii_phys_chip_power_gnd_nets 4 = Phys_U22_AVDDL AVDDL 1V2 from line 139 of rgmii_phys_chip_power_gnd_nets 9 = Phys_U22_AVDDL AVDDL 1V2 from line 139 of rgmii_phys_chip_power_gnd_nets 44 = Phys_U22_AVDD_PLL AVDDL_PLL 1V2 from line 143 of rgmii_phys_chip_power_gnd_nets 41 = Phys_U22_CLK125__LED_MODE CLK125_NDO/LED_MODE I/O from line 85 of rgmii_phys_chip_u22_nets 16 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 40 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 34 = Phys_U22_DVDDH DVDDH 1V8 from line 172 of rgmii_phys_chip_power_gnd_nets 18 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 23 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 14 = Phys_U22_DVDDL DVDDL 1V2 from line 154 of rgmii_phys_chip_power_gnd_nets 30 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 26 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 39 = Phys_U22_DVDDL DVDDL 1V2 from line 155 of rgmii_phys_chip_power_gnd_nets 24 = Phys_U22_GTX_CLK GTX_CLK I from line 167 of rgmii_phys_chip_u22_nets 38 = Phys_U22_INT_B INT_N/PME_N2 O from line 204 of rgmii_phys_chip_u22_nets 48 = Phys_U22_ISET ISET I/O from line 45 of rgmii_phys_chip_u22_nets 17 = Phys_U22_LED1__PHYAD0 LED1/PHYAD0/PME_N1 I/O from line 120 of rgmii_phys_chip_u22_nets 15 = Phys_U22_LED2__PHYAD1 LED2/PHYAD1 I/O from line 124 of rgmii_phys_chip_u22_nets 36 = Phys_U22_MDC MDC Ipu from line 191 of rgmii_phys_chip_u22_nets 37 = Phys_U22_MDIO MDIO Ipu/O from line 192 of rgmii_phys_chip_u22_nets 32 = Phys_U22_RXD0__MODE0 RXD0/MODE0 I/O from line 73 of rgmii_phys_chip_u22_nets 31 = Phys_U22_RXD1__MODE1 RXD1/MODE1 I/O from line 68 of rgmii_phys_chip_u22_nets 28 = Phys_U22_RXD2__MODE2 RXD2/MODE2 I/O from line 64 of rgmii_phys_chip_u22_nets 27 = Phys_U22_RXD3__MODE3 RXD3/MODE3 I/O from line 61 of rgmii_phys_chip_u22_nets 35 = Phys_U22_RX_CLK__PHYAD2 RX_CLK/PHYAD2 I/O from line 128 of rgmii_phys_chip_u22_nets 33 = Phys_U22_RX_DV__CLK125_EN RX_DV/CLK125_EN I/O from line 96 of rgmii_phys_chip_u22_nets 19 = Phys_U22_TXD0 TXD0 I from line 162 of rgmii_phys_chip_u22_nets 20 = Phys_U22_TXD1 TXD1 I from line 163 of rgmii_phys_chip_u22_nets 21 = Phys_U22_TXD2 TXD2 I from line 164 of rgmii_phys_chip_u22_nets 22 = Phys_U22_TXD3 TXD3 I from line 165 of rgmii_phys_chip_u22_nets 3 = Phys_U22_TXRX_A_CMP TXRXM_A I/O from line 217 of rgmii_phys_chip_u22_nets 2 = Phys_U22_TXRX_A_DIR TXRXP_A I/O from line 216 of rgmii_phys_chip_u22_nets 6 = Phys_U22_TXRX_B_CMP TXRXM_B I/O from line 220 of rgmii_phys_chip_u22_nets 5 = Phys_U22_TXRX_B_DIR TXRXP_B I/O from line 219 of rgmii_phys_chip_u22_nets 8 = Phys_U22_TXRX_C_CMP TXRXM_C I/O from line 223 of rgmii_phys_chip_u22_nets 7 = Phys_U22_TXRX_C_DIR TXRXP_C I/O from line 222 of rgmii_phys_chip_u22_nets 11 = Phys_U22_TXRX_D_CMP TXRXM_D I/O from line 226 of rgmii_phys_chip_u22_nets 10 = Phys_U22_TXRX_D_DIR TXRXP_D I/O from line 225 of rgmii_phys_chip_u22_nets 25 = Phys_U22_TX_EN TX_EN I from line 169 of rgmii_phys_chip_u22_nets 46 = Phys_U22_X1 XI I from line 180 of rgmii_phys_chip_u22_nets