Found 14 pins for U39 which is of type IC_TI_CDCLVC1106 ------------------------------------------------------ Pins sorted by Pin Name 1 = CLOCK_25_MHz_to_Fanout CLKIN from line 101 of clock_generation_nets 2 = ECLK_3V3 1G Output Enable from line 98 of clock_generation_nets 3 = CLOCK_25_MHz_Series_Term_FPGA Y0 Output from line 111 of clock_generation_nets 4 = GROUND GND from line 96 of clock_generation_nets 5 = ECLK_3V3 VDD from line 95 of clock_generation_nets 6 = CLOCK_for_SW_C Y4 Output from line 115 of clock_generation_nets 7 = GROUND GND from line 96 of clock_generation_nets 8 = ECLK_3V3 VDD from line 95 of clock_generation_nets 9 = CLOCK_for_SW_A Y5 Output from line 117 of clock_generation_nets 10 = GROUND GND from line 96 of clock_generation_nets 11 = CLOCK_for_SW_B Y2 Output from line 116 of clock_generation_nets 12 = ECLK_3V3 VDD from line 95 of clock_generation_nets 13 = CLOCK_for_Phys_U22 Y3 Output from line 105 of clock_generation_nets 14 = CLOCK_for_Phys_U21 Y1 Output from line 104 of clock_generation_nets ------------------------------------------------------ Pins sorted by Net Name 3 = CLOCK_25_MHz_Series_Term_FPGA Y0 Output from line 111 of clock_generation_nets 1 = CLOCK_25_MHz_to_Fanout CLKIN from line 101 of clock_generation_nets 14 = CLOCK_for_Phys_U21 Y1 Output from line 104 of clock_generation_nets 13 = CLOCK_for_Phys_U22 Y3 Output from line 105 of clock_generation_nets 9 = CLOCK_for_SW_A Y5 Output from line 117 of clock_generation_nets 11 = CLOCK_for_SW_B Y2 Output from line 116 of clock_generation_nets 6 = CLOCK_for_SW_C Y4 Output from line 115 of clock_generation_nets 2 = ECLK_3V3 1G Output Enable from line 98 of clock_generation_nets 12 = ECLK_3V3 VDD from line 95 of clock_generation_nets 5 = ECLK_3V3 VDD from line 95 of clock_generation_nets 8 = ECLK_3V3 VDD from line 95 of clock_generation_nets 10 = GROUND GND from line 96 of clock_generation_nets 4 = GROUND GND from line 96 of clock_generation_nets 7 = GROUND GND from line 96 of clock_generation_nets