Found 20 pins for U503 which is of type IC_CDCLVD1204 ------------------------------------------------------ Pins sorted by Pin Name 1 = GROUND GND from line 392 of clock_generation_nets 2 = Select_Input_First_40_Fanout IN_SEL from line 266 of clock_generation_nets 3 = Tie_Off_1st_40_FO_IN1_P INP1 from line 277 of clock_generation_nets 4 = First_Fanout_CMM_Ref INN1 from line 275 of clock_generation_nets 5 = CLK_2V5 VCC 2V5 from line 391 of clock_generation_nets 6 = Fanout_40.08_MHz_Input_Dir INP0 from line 251 of clock_generation_nets 7 = Fanout_40.08_MHz_Input_Cmp INN0 from line 252 of clock_generation_nets 8 = First_Fanout_CMM_Ref VAC_REF from line 254 of clock_generation_nets 9 = Clk_40.08_MHz_Ref_to_HF_PLL_Dir OUTP0 from line 70 of clock_40.08_MHz_distribution_nets 10 = Clk_40.08_MHz_Ref_to_HF_PLL_Cmp OUTN0 from line 71 of clock_40.08_MHz_distribution_nets 11 = Drive_to_Second_40.08_MHz_Fanout_Dir OUTP1 from line 80 of clock_40.08_MHz_distribution_nets 12 = Drive_to_Second_40.08_MHz_Fanout_Cmp OUTN1 from line 81 of clock_40.08_MHz_distribution_nets 13 = Clk_to_Cap_to_ROD_Dir OUTP2 from line 43 of clock_40.08_MHz_distribution_nets 14 = Clk_to_Cap_to_ROD_Cmp OUTN2 from line 44 of clock_40.08_MHz_distribution_nets 15 = Clk_40_to_Cap_to_FPGA_Logic_Dir OUTP3 from line 56 of clock_40.08_MHz_distribution_nets 16 = Clk_40_to_Cap_to_FPGA_Logic_Cmp OUTN3 from line 57 of clock_40.08_MHz_distribution_nets 17 = GROUND Thrm Gnd from line 392 of clock_generation_nets 18 = GROUND Thrm Gnd from line 392 of clock_generation_nets 19 = GROUND Thrm Gnd from line 392 of clock_generation_nets 20 = GROUND Thrm Gnd from line 392 of clock_generation_nets ------------------------------------------------------ Pins sorted by Net Name 5 = CLK_2V5 VCC 2V5 from line 391 of clock_generation_nets 10 = Clk_40.08_MHz_Ref_to_HF_PLL_Cmp OUTN0 from line 71 of clock_40.08_MHz_distribution_nets 9 = Clk_40.08_MHz_Ref_to_HF_PLL_Dir OUTP0 from line 70 of clock_40.08_MHz_distribution_nets 16 = Clk_40_to_Cap_to_FPGA_Logic_Cmp OUTN3 from line 57 of clock_40.08_MHz_distribution_nets 15 = Clk_40_to_Cap_to_FPGA_Logic_Dir OUTP3 from line 56 of clock_40.08_MHz_distribution_nets 14 = Clk_to_Cap_to_ROD_Cmp OUTN2 from line 44 of clock_40.08_MHz_distribution_nets 13 = Clk_to_Cap_to_ROD_Dir OUTP2 from line 43 of clock_40.08_MHz_distribution_nets 12 = Drive_to_Second_40.08_MHz_Fanout_Cmp OUTN1 from line 81 of clock_40.08_MHz_distribution_nets 11 = Drive_to_Second_40.08_MHz_Fanout_Dir OUTP1 from line 80 of clock_40.08_MHz_distribution_nets 7 = Fanout_40.08_MHz_Input_Cmp INN0 from line 252 of clock_generation_nets 6 = Fanout_40.08_MHz_Input_Dir INP0 from line 251 of clock_generation_nets 4 = First_Fanout_CMM_Ref INN1 from line 275 of clock_generation_nets 8 = First_Fanout_CMM_Ref VAC_REF from line 254 of clock_generation_nets 1 = GROUND GND from line 392 of clock_generation_nets 17 = GROUND Thrm Gnd from line 392 of clock_generation_nets 19 = GROUND Thrm Gnd from line 392 of clock_generation_nets 18 = GROUND Thrm Gnd from line 392 of clock_generation_nets 20 = GROUND Thrm Gnd from line 392 of clock_generation_nets 2 = Select_Input_First_40_Fanout IN_SEL from line 266 of clock_generation_nets 3 = Tie_Off_1st_40_FO_IN1_P INP1 from line 277 of clock_generation_nets