Found 2104 pins for U1 which is of type IC_XCVU125 ------------------------------------------------------ Pins sorted by Pin Name A3 = GROUND GND from line 51 of ultra_fpga_power_ground_nets A4 = MGT_AVTT MGTAVTT_RN from line 1312 of ultra_fpga_power_ground_nets A5 = GROUND GND from line 52 of ultra_fpga_power_ground_nets A6 = Comb_Data_to_Cap_to_FEX_11_Dir MGTHTXN3_232 from line 55 of combined_data_distribution_nets A7 = Comb_Data_to_Cap_to_FEX_11_Cmp MGTHTXP3_232 from line 54 of combined_data_distribution_nets A8 = No_Conn_FPGA_A8 NC from line 868 of ultra_no_connect_pins_nets A9 = No_Conn_FPGA_A9 NC from line 869 of ultra_no_connect_pins_nets B2 = GROUND GND from line 64 of ultra_fpga_power_ground_nets B3 = MGT_FO_CH_44_OUT_Hub_DIR MGTHRXN3_232 from line 10956 of mgt_fanout_channel_nets B4 = MGT_FO_CH_44_OUT_Hub_CMP MGTHRXP3_232 from line 10955 of mgt_fanout_channel_nets B5 = GROUND GND from line 65 of ultra_fpga_power_ground_nets B6 = GROUND GND from line 66 of ultra_fpga_power_ground_nets B7 = MGT_AVTT MGTAVTT_RN from line 1313 of ultra_fpga_power_ground_nets B8 = Comb_Data_to_Cap_to_FEX_10_Dir MGTHTXN2_233 from line 60 of combined_data_distribution_nets B9 = Comb_Data_to_Cap_to_FEX_10_Cmp MGTHTXP2_233 from line 59 of combined_data_distribution_nets C1 = MGT_FO_CH_43_OUT_Hub_CMP MGTHRXN2_232 from line 10960 of mgt_fanout_channel_nets C2 = MGT_FO_CH_43_OUT_Hub_DIR MGTHRXP2_232 from line 10959 of mgt_fanout_channel_nets C3 = GROUND GND from line 82 of ultra_fpga_power_ground_nets C4 = GROUND GND from line 83 of ultra_fpga_power_ground_nets C5 = GROUND GND from line 84 of ultra_fpga_power_ground_nets C6 = No_Conn_FPGA_C6 MGTHTXN2_232 from line 710 of ultra_no_connect_pins_nets C7 = No_Conn_FPGA_C7 MGTHTXP2_232 from line 709 of ultra_no_connect_pins_nets C8 = GROUND GND from line 85 of ultra_fpga_power_ground_nets C9 = MGT_AVTT MGTAVTT_RN from line 1315 of ultra_fpga_power_ground_nets D1 = GROUND GND from line 99 of ultra_fpga_power_ground_nets D2 = GROUND GND from line 100 of ultra_fpga_power_ground_nets D3 = MGT_FO_CH_42_OUT_Hub_DIR MGTHRXN1_232 from line 10964 of mgt_fanout_channel_nets D4 = MGT_FO_CH_42_OUT_Hub_CMP MGTHRXP1_232 from line 10963 of mgt_fanout_channel_nets D5 = GROUND GND from line 101 of ultra_fpga_power_ground_nets D6 = QUAD_231_MGTRREF MGTRREF_RN from line 128 of ultra_dci_vref_mgt_calib_resistors_nets D7 = MGT_AVTT MGTAVTTRCAL_RN from line 127 of ultra_dci_vref_mgt_calib_resistors_nets D8 = No_Conn_FPGA_D8 MGTHTXN0_233 from line 730 of ultra_no_connect_pins_nets D9 = No_Conn_FPGA_D9 MGTHTXP0_233 from line 729 of ultra_no_connect_pins_nets E1 = MGT_FO_CH_41_OUT_Hub_CMP MGTHRXN0_232 from line 10968 of mgt_fanout_channel_nets E2 = MGT_FO_CH_41_OUT_Hub_DIR MGTHRXP0_232 from line 10967 of mgt_fanout_channel_nets E3 = GROUND GND from line 116 of ultra_fpga_power_ground_nets E4 = GROUND GND from line 117 of ultra_fpga_power_ground_nets E5 = GROUND GND from line 118 of ultra_fpga_power_ground_nets E6 = No_Conn_FPGA_E6 MGTHTXN0_232 from line 716 of ultra_no_connect_pins_nets E7 = No_Conn_FPGA_E7 MGTHTXP0_232 from line 715 of ultra_no_connect_pins_nets E8 = MGT_AVTT MGTAVTT_RN from line 1317 of ultra_fpga_power_ground_nets E9 = GROUND GND from line 119 of ultra_fpga_power_ground_nets F1 = GROUND GND from line 133 of ultra_fpga_power_ground_nets F2 = GROUND GND from line 134 of ultra_fpga_power_ground_nets F3 = MGT_FO_CH_56_OUT_Hub_DIR MGTHRXN1_231 from line 10975 of mgt_fanout_channel_nets F4 = MGT_FO_CH_56_OUT_Hub_CMP MGTHRXP1_231 from line 10974 of mgt_fanout_channel_nets F5 = GROUND GND from line 135 of ultra_fpga_power_ground_nets F6 = GROUND GND from line 136 of ultra_fpga_power_ground_nets F7 = MGT_AVTT MGTAVTT_RN from line 1318 of ultra_fpga_power_ground_nets F8 = No_Conn_FPGA_F8 MGTHTXN1_231 from line 696 of ultra_no_connect_pins_nets F9 = No_Conn_FPGA_F9 MGTHTXP1_231 from line 695 of ultra_no_connect_pins_nets G1 = MGT_FO_CH_55_OUT_Hub_CMP MGTHRXN0_231 from line 10979 of mgt_fanout_channel_nets G2 = MGT_FO_CH_55_OUT_Hub_DIR MGTHRXP0_231 from line 10978 of mgt_fanout_channel_nets G3 = GROUND GND from line 152 of ultra_fpga_power_ground_nets G4 = GROUND GND from line 153 of ultra_fpga_power_ground_nets G5 = GROUND GND from line 154 of ultra_fpga_power_ground_nets G6 = No_Conn_FPGA_G6 MGTHTXN0_231 from line 699 of ultra_no_connect_pins_nets G7 = No_Conn_FPGA_G7 MGTHTXP0_231 from line 698 of ultra_no_connect_pins_nets G8 = GROUND GND from line 155 of ultra_fpga_power_ground_nets G9 = MGT_AVTT MGTAVTT_RN from line 1319 of ultra_fpga_power_ground_nets H1 = GROUND GND from line 167 of ultra_fpga_power_ground_nets H2 = GROUND GND from line 168 of ultra_fpga_power_ground_nets H3 = MGT_FO_CH_54_OUT_Hub_DIR MGTHRXN3_230 from line 10986 of mgt_fanout_channel_nets H4 = MGT_FO_CH_54_OUT_Hub_CMP MGTHRXP3_230 from line 10985 of mgt_fanout_channel_nets H5 = GROUND GND from line 169 of ultra_fpga_power_ground_nets H6 = MGT_AVTT MGTAVTT_RN from line 1320 of ultra_fpga_power_ground_nets H7 = GROUND GND from line 170 of ultra_fpga_power_ground_nets H8 = No_Conn_FPGA_H8 MGTHTXN3_230 from line 676 of ultra_no_connect_pins_nets H9 = No_Conn_FPGA_H9 MGTHTXP3_230 from line 675 of ultra_no_connect_pins_nets J1 = MGT_FO_CH_53_OUT_Hub_CMP MGTHRXN2_230 from line 10990 of mgt_fanout_channel_nets J2 = MGT_FO_CH_53_OUT_Hub_DIR MGTHRXP2_230 from line 10989 of mgt_fanout_channel_nets J3 = GROUND GND from line 186 of ultra_fpga_power_ground_nets J4 = GROUND GND from line 187 of ultra_fpga_power_ground_nets J5 = GROUND GND from line 188 of ultra_fpga_power_ground_nets J6 = Comb_Data_to_Cap_to_FEX_12_Dir MGTHTXN2_230 from line 49 of combined_data_distribution_nets J7 = Comb_Data_to_Cap_to_FEX_12_Cmp MGTHTXP2_230 from line 50 of combined_data_distribution_nets J8 = MGT_AVTT MGTAVTT_RN from line 1321 of ultra_fpga_power_ground_nets J9 = GROUND GND from line 189 of ultra_fpga_power_ground_nets K1 = GROUND GND from line 200 of ultra_fpga_power_ground_nets K2 = GROUND GND from line 201 of ultra_fpga_power_ground_nets K3 = MGT_FO_CH_52_OUT_Hub_DIR MGTHRXN1_230 from line 10994 of mgt_fanout_channel_nets K4 = MGT_FO_CH_52_OUT_Hub_CMP MGTHRXP1_230 from line 10993 of mgt_fanout_channel_nets K5 = GROUND GND from line 202 of ultra_fpga_power_ground_nets K6 = GROUND GND from line 203 of ultra_fpga_power_ground_nets K7 = MGT_AVTT MGTAVTT_RN from line 1322 of ultra_fpga_power_ground_nets K8 = No_Conn_FPGA_K8 MGTHTXN1_230 from line 679 of ultra_no_connect_pins_nets K9 = No_Conn_FPGA_K9 MGTHTXP1_230 from line 678 of ultra_no_connect_pins_nets L1 = MGT_FO_CH_51_OUT_Hub_CMP MGTHRXN0_230 from line 10998 of mgt_fanout_channel_nets L2 = MGT_FO_CH_51_OUT_Hub_DIR MGTHRXP0_230 from line 10997 of mgt_fanout_channel_nets L3 = GROUND GND from line 213 of ultra_fpga_power_ground_nets L4 = GROUND GND from line 214 of ultra_fpga_power_ground_nets L5 = GROUND GND from line 215 of ultra_fpga_power_ground_nets L6 = Comb_Data_to_Cap_to_FEX_13_Dir MGTHTXN0_230 from line 46 of combined_data_distribution_nets L7 = Comb_Data_to_Cap_to_FEX_13_Cmp MGTHTXP0_230 from line 47 of combined_data_distribution_nets L8 = GROUND GND from line 216 of ultra_fpga_power_ground_nets L9 = MGT_AVTT MGTAVTT_RN from line 1323 of ultra_fpga_power_ground_nets M1 = GROUND GND from line 227 of ultra_fpga_power_ground_nets M2 = GROUND GND from line 228 of ultra_fpga_power_ground_nets M3 = MGT_FO_CH_50_OUT_Hub_DIR MGTHRXN3_229 from line 11005 of mgt_fanout_channel_nets M4 = MGT_FO_CH_50_OUT_Hub_CMP MGTHRXP3_229 from line 11004 of mgt_fanout_channel_nets M5 = GROUND GND from line 229 of ultra_fpga_power_ground_nets M6 = MGT_AVTT MGTAVTT_RN from line 1324 of ultra_fpga_power_ground_nets M7 = GROUND GND from line 230 of ultra_fpga_power_ground_nets M8 = No_Conn_FPGA_M8 MGTHTXN3_229 from line 662 of ultra_no_connect_pins_nets M9 = No_Conn_FPGA_M9 MGTHTXP3_229 from line 661 of ultra_no_connect_pins_nets N1 = MGT_FO_CH_49_OUT_Hub_CMP MGTHRXN2_229 from line 11009 of mgt_fanout_channel_nets N2 = MGT_FO_CH_49_OUT_Hub_DIR MGTHRXP2_229 from line 11008 of mgt_fanout_channel_nets N3 = GROUND GND from line 240 of ultra_fpga_power_ground_nets N4 = GROUND GND from line 241 of ultra_fpga_power_ground_nets N5 = GROUND GND from line 242 of ultra_fpga_power_ground_nets N6 = Comb_Data_to_Cap_to_FEX_14_Dir MGTHTXN2_229 from line 41 of combined_data_distribution_nets N7 = Comb_Data_to_Cap_to_FEX_14_Cmp MGTHTXP2_229 from line 42 of combined_data_distribution_nets N8 = MGT_AVTT MGTAVTT_RN from line 1325 of ultra_fpga_power_ground_nets N9 = GROUND GND from line 243 of ultra_fpga_power_ground_nets P1 = GROUND GND from line 254 of ultra_fpga_power_ground_nets P2 = GROUND GND from line 255 of ultra_fpga_power_ground_nets P3 = MGT_FO_CH_64_OUT_Hub_DIR MGTHRXN1_229 from line 11013 of mgt_fanout_channel_nets P4 = MGT_FO_CH_64_OUT_Hub_CMP MGTHRXP1_229 from line 11012 of mgt_fanout_channel_nets P5 = GROUND GND from line 256 of ultra_fpga_power_ground_nets P6 = GROUND GND from line 257 of ultra_fpga_power_ground_nets P7 = MGT_AVTT MGTAVTT_RN from line 1326 of ultra_fpga_power_ground_nets P8 = No_Conn_FPGA_P8 MGTHTXN1_229 from line 665 of ultra_no_connect_pins_nets P9 = No_Conn_FPGA_P9 MGTHTXP1_229 from line 664 of ultra_no_connect_pins_nets R1 = MGT_FO_CH_63_OUT_Hub_CMP MGTHRXN0_229 from line 11017 of mgt_fanout_channel_nets R2 = MGT_FO_CH_63_OUT_Hub_DIR MGTHRXP0_229 from line 11016 of mgt_fanout_channel_nets R3 = GROUND GND from line 268 of ultra_fpga_power_ground_nets R4 = GROUND GND from line 269 of ultra_fpga_power_ground_nets R5 = GROUND GND from line 270 of ultra_fpga_power_ground_nets R6 = This_Hubs_RO_0_to_Cap_Its_ROD_Cmp MGTHTXN0_229 from line 281 of hub_all_other_mgt_nets R7 = This_Hubs_RO_0_to_Cap_Its_ROD_Dir MGTHTXP0_229 from line 280 of hub_all_other_mgt_nets R8 = GROUND GND from line 271 of ultra_fpga_power_ground_nets R9 = MGT_AVTT MGTAVTT_RN from line 1327 of ultra_fpga_power_ground_nets T1 = GROUND GND from line 289 of ultra_fpga_power_ground_nets T2 = GROUND GND from line 290 of ultra_fpga_power_ground_nets T3 = MGT_FO_CH_62_OUT_Hub_DIR MGTHRXN3_228 from line 11024 of mgt_fanout_channel_nets T4 = MGT_FO_CH_62_OUT_Hub_CMP MGTHRXP3_228 from line 11023 of mgt_fanout_channel_nets T5 = GROUND GND from line 291 of ultra_fpga_power_ground_nets T6 = MGT_AVTT MGTAVTT_RN from line 1328 of ultra_fpga_power_ground_nets T7 = GROUND GND from line 292 of ultra_fpga_power_ground_nets T8 = No_Conn_FPGA_T8 MGTHTXN3_228 from line 648 of ultra_no_connect_pins_nets T9 = No_Conn_FPGA_T9 MGTHTXP3_228 from line 647 of ultra_no_connect_pins_nets U1 = MGT_FO_CH_61_OUT_Hub_CMP MGTHRXN2_228 from line 11028 of mgt_fanout_channel_nets U2 = MGT_FO_CH_61_OUT_Hub_DIR MGTHRXP2_228 from line 11027 of mgt_fanout_channel_nets U3 = GROUND GND from line 309 of ultra_fpga_power_ground_nets U4 = GROUND GND from line 310 of ultra_fpga_power_ground_nets U5 = GROUND GND from line 311 of ultra_fpga_power_ground_nets U6 = This_Hubs_RO_1_to_Cap_Its_ROD_Cmp MGTHTXN2_228 from line 288 of hub_all_other_mgt_nets U7 = This_Hubs_RO_1_to_Cap_Its_ROD_Dir MGTHTXP2_228 from line 287 of hub_all_other_mgt_nets U8 = MGT_AVTT MGTAVTT_RC from line 1290 of ultra_fpga_power_ground_nets U9 = GROUND GND from line 312 of ultra_fpga_power_ground_nets V1 = GROUND GND from line 330 of ultra_fpga_power_ground_nets V2 = GROUND GND from line 331 of ultra_fpga_power_ground_nets V3 = MGT_FO_CH_60_OUT_Hub_DIR MGTHRXN1_228 from line 11032 of mgt_fanout_channel_nets V4 = MGT_FO_CH_60_OUT_Hub_CMP MGTHRXP1_228 from line 11031 of mgt_fanout_channel_nets V5 = GROUND GND from line 332 of ultra_fpga_power_ground_nets V6 = GROUND GND from line 333 of ultra_fpga_power_ground_nets V7 = MGT_AVTT MGTAVTT_RC from line 1291 of ultra_fpga_power_ground_nets V8 = No_Conn_FPGA_V8 MGTHTXN1_228 from line 651 of ultra_no_connect_pins_nets V9 = No_Conn_FPGA_V9 MGTHTXP1_228 from line 650 of ultra_no_connect_pins_nets W1 = MGT_FO_CH_59_OUT_Hub_CMP MGTHRXN0_228 from line 11036 of mgt_fanout_channel_nets W2 = MGT_FO_CH_59_OUT_Hub_DIR MGTHRXP0_228 from line 11035 of mgt_fanout_channel_nets W3 = GROUND GND from line 350 of ultra_fpga_power_ground_nets W4 = GROUND GND from line 351 of ultra_fpga_power_ground_nets W5 = GROUND GND from line 352 of ultra_fpga_power_ground_nets W6 = Comb_Data_to_Cap_to_ROD_Cmp MGTHTXN0_228 from line 36 of combined_data_distribution_nets W7 = Comb_Data_to_Cap_to_ROD_Dir MGTHTXP0_228 from line 37 of combined_data_distribution_nets W8 = GROUND GND from line 353 of ultra_fpga_power_ground_nets W9 = MGT_AVCC MGTAVCC_RC from line 1186 of ultra_fpga_power_ground_nets Y1 = GROUND GND from line 371 of ultra_fpga_power_ground_nets Y2 = GROUND GND from line 372 of ultra_fpga_power_ground_nets Y3 = MGT_FO_CH_58_OUT_Hub_DIR MGTHRXN3_227 from line 11043 of mgt_fanout_channel_nets Y4 = MGT_FO_CH_58_OUT_Hub_CMP MGTHRXP3_227 from line 11042 of mgt_fanout_channel_nets Y5 = GROUND GND from line 373 of ultra_fpga_power_ground_nets Y6 = MGT_AVTT MGTAVTT_RC from line 1292 of ultra_fpga_power_ground_nets Y7 = GROUND GND from line 374 of ultra_fpga_power_ground_nets Y8 = No_Conn_FPGA_Y8 MGTHTXN3_227 from line 634 of ultra_no_connect_pins_nets Y9 = No_Conn_FPGA_Y9 MGTHTXP3_227 from line 633 of ultra_no_connect_pins_nets A10 = Comb_Data_to_Cap_to_FEX_09_Dir MGTHTXN3_233 from line 63 of combined_data_distribution_nets A11 = Comb_Data_to_Cap_to_FEX_09_Cmp MGTHTXP3_233 from line 62 of combined_data_distribution_nets A12 = GROUND GND from line 53 of ultra_fpga_power_ground_nets A13 = GROUND GND from line 54 of ultra_fpga_power_ground_nets A14 = GROUND GND from line 55 of ultra_fpga_power_ground_nets A15 = MGT_FO_CH_48_OUT_Hub_CMP MGTHRXN3_233 from line 10937 of mgt_fanout_channel_nets A16 = MGT_FO_CH_48_OUT_Hub_DIR MGTHRXP3_233 from line 10936 of mgt_fanout_channel_nets A17 = GROUND GND from line 56 of ultra_fpga_power_ground_nets A18 = MGT_FO_EQU_ENB_GRP_13 IO_L24N_T3U_N11_72 from line 9221 of mgt_fanout_channel_nets A19 = MGT_FO_EQU_ENB_GRP_12 IO_L23N_T3U_N9_72 from line 9220 of mgt_fanout_channel_nets A20 = MGT_FO_EQU_ENB_GRP_11 IO_L23P_T3U_N8_72 from line 9219 of mgt_fanout_channel_nets A21 = MGT_FO_EQU_ENB_GRP_10 IO_L21N_T3L_N5_AD8N_72 from line 9218 of mgt_fanout_channel_nets A22 = GROUND GND from line 57 of ultra_fpga_power_ground_nets A23 = MGT_FO_EQU_ENB_GRP_9 IO_L20N_T3L_N3_AD1N_71 from line 9217 of mgt_fanout_channel_nets A24 = MGT_FO_EQU_ENB_GRP_4 IO_L20P_T3L_N2_AD1P_71 from line 9210 of mgt_fanout_channel_nets A25 = MGT_FO_EQU_ENB_GRP_2 IO_L23N_T3U_N9_71 from line 9208 of mgt_fanout_channel_nets A26 = Select_Input_Second_40_Fanout IO_L24N_T3U_N11_70 from line 353 of clock_generation_nets A27 = BULK_1V8 VCCO_70 from line 1086 of ultra_fpga_power_ground_nets A28 = No_Conn_FPGA_A28 IO_L20P_T3L_N2_AD1P_70 from line 235 of ultra_no_connect_pins_nets A29 = No_Conn_FPGA_A29 IO_L20N_T3L_N3_AD1N_70 from line 236 of ultra_no_connect_pins_nets A30 = GROUND GND from line 58 of ultra_fpga_power_ground_nets A31 = MGT_FO_CH_37_OUT_Hub_DIR MGTYRXP3_133 from line 10899 of mgt_fanout_channel_nets A32 = MGT_FO_CH_37_OUT_Hub_CMP MGTYRXN3_133 from line 10900 of mgt_fanout_channel_nets A33 = GROUND GND from line 59 of ultra_fpga_power_ground_nets A34 = GROUND GND from line 60 of ultra_fpga_power_ground_nets A35 = GROUND GND from line 61 of ultra_fpga_power_ground_nets A36 = Comb_Data_to_Cap_to_FEX_08_Dir MGTYTXP3_133 from line 69 of combined_data_distribution_nets A37 = Comb_Data_to_Cap_to_FEX_08_Cmp MGTYTXN3_133 from line 70 of combined_data_distribution_nets A38 = No_Conn_FPGA_A38 NC from line 870 of ultra_no_connect_pins_nets A39 = No_Conn_FPGA_A39 NC from line 871 of ultra_no_connect_pins_nets A40 = Comb_Data_to_Cap_to_FEX_06_Dir MGTYTXP3_132 from line 77 of combined_data_distribution_nets A41 = Comb_Data_to_Cap_to_FEX_06_Cmp MGTYTXN3_132 from line 78 of combined_data_distribution_nets A42 = GROUND GND from line 62 of ultra_fpga_power_ground_nets A43 = MGT_AVTT MGTAVTT_LN from line 1252 of ultra_fpga_power_ground_nets A44 = GROUND GND from line 63 of ultra_fpga_power_ground_nets AA1 = MGT_FO_CH_57_OUT_Hub_CMP MGTHRXN2_227 from line 11047 of mgt_fanout_channel_nets AA2 = MGT_FO_CH_57_OUT_Hub_DIR MGTHRXP2_227 from line 11046 of mgt_fanout_channel_nets AA3 = GROUND GND from line 391 of ultra_fpga_power_ground_nets AA4 = GROUND GND from line 392 of ultra_fpga_power_ground_nets AA5 = GROUND GND from line 393 of ultra_fpga_power_ground_nets AA6 = MiniPOD_Trans_Fiber_0_Data_Dir MGTHTXN2_227 from line 192 of hub_all_other_mgt_nets AA7 = MiniPOD_Trans_Fiber_0_Data_Cmp MGTHTXP2_227 from line 193 of hub_all_other_mgt_nets AA8 = MGT_AVTT MGTAVTT_RC from line 1293 of ultra_fpga_power_ground_nets AA9 = GROUND GND from line 394 of ultra_fpga_power_ground_nets AB1 = GROUND GND from line 413 of ultra_fpga_power_ground_nets AB2 = GROUND GND from line 414 of ultra_fpga_power_ground_nets AB3 = MGT_FO_CH_74_OUT_Hub_DIR MGTHRXN1_227 from line 11051 of mgt_fanout_channel_nets AB4 = MGT_FO_CH_74_OUT_Hub_CMP MGTHRXP1_227 from line 11050 of mgt_fanout_channel_nets AB5 = GROUND GND from line 415 of ultra_fpga_power_ground_nets AB6 = GROUND GND from line 416 of ultra_fpga_power_ground_nets AB7 = MGT_AVTT MGTAVTT_RC from line 1294 of ultra_fpga_power_ground_nets AB8 = No_Conn_FPGA_AB8 MGTHTXN1_227 from line 637 of ultra_no_connect_pins_nets AB9 = No_Conn_FPGA_AB9 MGTHTXP1_227 from line 636 of ultra_no_connect_pins_nets AC1 = MGT_FO_CH_73_OUT_Hub_CMP MGTHRXN0_227 from line 11055 of mgt_fanout_channel_nets AC2 = MGT_FO_CH_73_OUT_Hub_DIR MGTHRXP0_227 from line 11054 of mgt_fanout_channel_nets AC3 = GROUND GND from line 431 of ultra_fpga_power_ground_nets AC4 = GROUND GND from line 432 of ultra_fpga_power_ground_nets AC5 = GROUND GND from line 433 of ultra_fpga_power_ground_nets AC6 = MiniPOD_Trans_Fiber_1_Data_Dir MGTHTXN0_227 from line 196 of hub_all_other_mgt_nets AC7 = MiniPOD_Trans_Fiber_1_Data_Cmp MGTHTXP0_227 from line 197 of hub_all_other_mgt_nets AC8 = GROUND GND from line 434 of ultra_fpga_power_ground_nets AC9 = MGT_AVTT MGTAVTT_RC from line 1295 of ultra_fpga_power_ground_nets AD1 = GROUND GND from line 450 of ultra_fpga_power_ground_nets AD2 = GROUND GND from line 451 of ultra_fpga_power_ground_nets AD3 = MGT_FO_CH_72_OUT_Hub_DIR MGTHRXN3_226 from line 11062 of mgt_fanout_channel_nets AD4 = MGT_FO_CH_72_OUT_Hub_CMP MGTHRXP3_226 from line 11061 of mgt_fanout_channel_nets AD5 = GROUND GND from line 452 of ultra_fpga_power_ground_nets AD6 = MGT_AVTT MGTAVTT_RC from line 1296 of ultra_fpga_power_ground_nets AD7 = GROUND GND from line 453 of ultra_fpga_power_ground_nets AD8 = No_Conn_FPGA_AD8 MGTHTXN3_226 from line 620 of ultra_no_connect_pins_nets AD9 = No_Conn_FPGA_AD9 MGTHTXP3_226 from line 619 of ultra_no_connect_pins_nets AE1 = MGT_FO_CH_71_OUT_Hub_CMP MGTHRXN2_226 from line 11066 of mgt_fanout_channel_nets AE2 = MGT_FO_CH_71_OUT_Hub_DIR MGTHRXP2_226 from line 11065 of mgt_fanout_channel_nets AE3 = GROUND GND from line 469 of ultra_fpga_power_ground_nets AE4 = GROUND GND from line 470 of ultra_fpga_power_ground_nets AE5 = GROUND GND from line 471 of ultra_fpga_power_ground_nets AE6 = MiniPOD_Trans_Fiber_2_Data_Dir MGTHTXN2_226 from line 200 of hub_all_other_mgt_nets AE7 = MiniPOD_Trans_Fiber_2_Data_Cmp MGTHTXP2_226 from line 201 of hub_all_other_mgt_nets AE8 = MGT_AVTT MGTAVTT_RC from line 1297 of ultra_fpga_power_ground_nets AE9 = GROUND GND from line 472 of ultra_fpga_power_ground_nets AF1 = GROUND GND from line 488 of ultra_fpga_power_ground_nets AF2 = GROUND GND from line 489 of ultra_fpga_power_ground_nets AF3 = MGT_FO_CH_70_OUT_Hub_DIR MGTHRXN1_226 from line 11070 of mgt_fanout_channel_nets AF4 = MGT_FO_CH_70_OUT_Hub_CMP MGTHRXP1_226 from line 11069 of mgt_fanout_channel_nets AF5 = GROUND GND from line 490 of ultra_fpga_power_ground_nets AF6 = GROUND GND from line 491 of ultra_fpga_power_ground_nets AF7 = MGT_AVTT MGTAVTT_RC from line 1298 of ultra_fpga_power_ground_nets AF8 = No_Conn_FPGA_AF8 MGTHTXN1_226 from line 623 of ultra_no_connect_pins_nets AF9 = No_Conn_FPGA_AF9 MGTHTXP1_226 from line 622 of ultra_no_connect_pins_nets AG1 = MGT_FO_CH_69_OUT_Hub_CMP MGTHRXN0_226 from line 11074 of mgt_fanout_channel_nets AG2 = MGT_FO_CH_69_OUT_Hub_DIR MGTHRXP0_226 from line 11073 of mgt_fanout_channel_nets AG3 = GROUND GND from line 507 of ultra_fpga_power_ground_nets AG4 = GROUND GND from line 508 of ultra_fpga_power_ground_nets AG5 = GROUND GND from line 509 of ultra_fpga_power_ground_nets AG6 = MiniPOD_Trans_Fiber_4_Data_Dir MGTHTXN0_226 from line 204 of hub_all_other_mgt_nets AG7 = MiniPOD_Trans_Fiber_4_Data_Cmp MGTHTXP0_226 from line 205 of hub_all_other_mgt_nets AG8 = GROUND GND from line 510 of ultra_fpga_power_ground_nets AG9 = MGT_AVTT MGTAVTT_RC from line 1299 of ultra_fpga_power_ground_nets AH1 = GROUND GND from line 529 of ultra_fpga_power_ground_nets AH2 = GROUND GND from line 530 of ultra_fpga_power_ground_nets AH3 = MGT_FO_CH_68_OUT_Hub_DIR MGTHRXN3_225 from line 11081 of mgt_fanout_channel_nets AH4 = MGT_FO_CH_68_OUT_Hub_CMP MGTHRXP3_225 from line 11080 of mgt_fanout_channel_nets AH5 = GROUND GND from line 531 of ultra_fpga_power_ground_nets AH6 = QUAD_226_MGTRREF MGTRREF_RC from line 125 of ultra_dci_vref_mgt_calib_resistors_nets AH7 = MGT_AVTT MGTAVTTRCAL_RC from line 124 of ultra_dci_vref_mgt_calib_resistors_nets AH8 = No_Conn_FPGA_AH8 MGTHTXN3_225 from line 606 of ultra_no_connect_pins_nets AH9 = No_Conn_FPGA_AH9 MGTHTXP3_225 from line 605 of ultra_no_connect_pins_nets AJ1 = MGT_FO_CH_67_OUT_Hub_CMP MGTHRXN2_225 from line 11085 of mgt_fanout_channel_nets AJ2 = MGT_FO_CH_67_OUT_Hub_DIR MGTHRXP2_225 from line 11084 of mgt_fanout_channel_nets AJ3 = GROUND GND from line 547 of ultra_fpga_power_ground_nets AJ4 = GROUND GND from line 548 of ultra_fpga_power_ground_nets AJ5 = GROUND GND from line 549 of ultra_fpga_power_ground_nets AJ6 = MiniPOD_Trans_Fiber_6_Data_Dir MGTHTXN2_225 from line 208 of hub_all_other_mgt_nets AJ7 = MiniPOD_Trans_Fiber_6_Data_Cmp MGTHTXP2_225 from line 209 of hub_all_other_mgt_nets AJ8 = MGT_AVTT MGTAVTT_RC from line 1300 of ultra_fpga_power_ground_nets AJ9 = GROUND GND from line 550 of ultra_fpga_power_ground_nets AK1 = GROUND GND from line 568 of ultra_fpga_power_ground_nets AK2 = GROUND GND from line 569 of ultra_fpga_power_ground_nets AK3 = MGT_FO_CH_66_OUT_Hub_DIR MGTHRXN1_225 from line 11089 of mgt_fanout_channel_nets AK4 = MGT_FO_CH_66_OUT_Hub_CMP MGTHRXP1_225 from line 11088 of mgt_fanout_channel_nets AK5 = GROUND GND from line 570 of ultra_fpga_power_ground_nets AK6 = GROUND GND from line 571 of ultra_fpga_power_ground_nets AK7 = MGT_AVTT MGTAVTT_RC from line 1301 of ultra_fpga_power_ground_nets AK8 = No_Conn_FPGA_AK8 MGTHTXN1_225 from line 609 of ultra_no_connect_pins_nets AK9 = No_Conn_FPGA_AK9 MGTHTXP1_225 from line 608 of ultra_no_connect_pins_nets AL1 = MGT_FO_CH_65_OUT_Hub_CMP MGTHRXN0_225 from line 11093 of mgt_fanout_channel_nets AL2 = MGT_FO_CH_65_OUT_Hub_DIR MGTHRXP0_225 from line 11092 of mgt_fanout_channel_nets AL3 = GROUND GND from line 588 of ultra_fpga_power_ground_nets AL4 = GROUND GND from line 589 of ultra_fpga_power_ground_nets AL5 = GROUND GND from line 590 of ultra_fpga_power_ground_nets AL6 = MiniPOD_Trans_Fiber_8_Data_Dir MGTHTXN0_225 from line 212 of hub_all_other_mgt_nets AL7 = MiniPOD_Trans_Fiber_8_Data_Cmp MGTHTXP0_225 from line 213 of hub_all_other_mgt_nets AL8 = GROUND GND from line 591 of ultra_fpga_power_ground_nets AL9 = MGT_AVCC MGTAVCC_RS from line 1215 of ultra_fpga_power_ground_nets AM1 = GROUND GND from line 609 of ultra_fpga_power_ground_nets AM2 = GROUND GND from line 610 of ultra_fpga_power_ground_nets AM3 = This_RODs_Readout_Ctrl_to_GTH_Input_Dir MGTHRXN3_224 from line 93 of hub_all_other_mgt_nets AM4 = This_RODs_Readout_Ctrl_to_GTH_Input_Cmp MGTHRXP3_224 from line 94 of hub_all_other_mgt_nets AM5 = GROUND GND from line 611 of ultra_fpga_power_ground_nets AM6 = MGT_AVTT MGTAVTT_RC from line 1302 of ultra_fpga_power_ground_nets AM7 = GROUND GND from line 612 of ultra_fpga_power_ground_nets AM8 = No_Conn_FPGA_AM8 MGTHTXN3_224 from line 592 of ultra_no_connect_pins_nets AM9 = No_Conn_FPGA_AM9 MGTHTXP3_224 from line 591 of ultra_no_connect_pins_nets AN1 = Rec_MP_Fiber_2_to_FPGA_Cmp MGTHRXN2_224 from line 167 of hub_all_other_mgt_nets AN2 = Rec_MP_Fiber_2_to_FPGA_Dir MGTHRXP2_224 from line 166 of hub_all_other_mgt_nets AN3 = GROUND GND from line 622 of ultra_fpga_power_ground_nets AN4 = GROUND GND from line 623 of ultra_fpga_power_ground_nets AN5 = GROUND GND from line 624 of ultra_fpga_power_ground_nets AN6 = MiniPOD_Trans_Fiber_10_Data_Dir MGTHTXN2_224 from line 216 of hub_all_other_mgt_nets AN7 = MiniPOD_Trans_Fiber_10_Data_Cmp MGTHTXP2_224 from line 217 of hub_all_other_mgt_nets AN8 = MGT_AVTT MGTAVTT_RC from line 1303 of ultra_fpga_power_ground_nets AN9 = GROUND GND from line 625 of ultra_fpga_power_ground_nets AP1 = GROUND GND from line 636 of ultra_fpga_power_ground_nets AP2 = GROUND GND from line 637 of ultra_fpga_power_ground_nets AP3 = Rec_MP_Fiber_4_to_FPGA_Cmp MGTHRXN1_224 from line 154 of hub_all_other_mgt_nets AP4 = Rec_MP_Fiber_4_to_FPGA_Dir MGTHRXP1_224 from line 153 of hub_all_other_mgt_nets AP5 = GROUND GND from line 638 of ultra_fpga_power_ground_nets AP6 = GROUND GND from line 639 of ultra_fpga_power_ground_nets AP7 = MGT_AVTT MGTAVTT_RC from line 1304 of ultra_fpga_power_ground_nets AP8 = No_Conn_FPGA_AP8 MGTHTXN1_224 from line 595 of ultra_no_connect_pins_nets AP9 = No_Conn_FPGA_AP9 MGTHTXP1_224 from line 594 of ultra_no_connect_pins_nets AR1 = Rec_MP_Fiber_6_to_FPGA_Cmp MGTHRXN0_224 from line 141 of hub_all_other_mgt_nets AR2 = Rec_MP_Fiber_6_to_FPGA_Dir MGTHRXP0_224 from line 140 of hub_all_other_mgt_nets AR3 = GROUND GND from line 652 of ultra_fpga_power_ground_nets AR4 = GROUND GND from line 653 of ultra_fpga_power_ground_nets AR5 = GROUND GND from line 654 of ultra_fpga_power_ground_nets AR6 = MiniPOD_Trans_Fiber_11_Data_Dir MGTHTXN0_224 from line 220 of hub_all_other_mgt_nets AR7 = MiniPOD_Trans_Fiber_11_Data_Cmp MGTHTXP0_224 from line 221 of hub_all_other_mgt_nets AR8 = GROUND GND from line 655 of ultra_fpga_power_ground_nets AR9 = MGT_AVTT MGTAVTT_RC from line 1305 of ultra_fpga_power_ground_nets AT1 = GROUND GND from line 664 of ultra_fpga_power_ground_nets AT2 = GROUND GND from line 665 of ultra_fpga_power_ground_nets AT3 = No_Conn_FPGA_AT3 NC from line 978 of ultra_no_connect_pins_nets AT4 = No_Conn_FPGA_AT4 NC from line 977 of ultra_no_connect_pins_nets AT5 = GROUND GND from line 666 of ultra_fpga_power_ground_nets AT6 = MGT_AVTT MGTAVTT_RC from line 1306 of ultra_fpga_power_ground_nets AT7 = GROUND GND from line 667 of ultra_fpga_power_ground_nets AT8 = No_Conn_FPGA_AT8 NC from line 979 of ultra_no_connect_pins_nets AT9 = No_Conn_FPGA_AT9 NC from line 976 of ultra_no_connect_pins_nets AU1 = No_Conn_FPGA_AU1 NC from line 984 of ultra_no_connect_pins_nets AU2 = No_Conn_FPGA_AU2 NC from line 983 of ultra_no_connect_pins_nets AU3 = GROUND GND from line 677 of ultra_fpga_power_ground_nets AU4 = GROUND GND from line 678 of ultra_fpga_power_ground_nets AU5 = GROUND GND from line 679 of ultra_fpga_power_ground_nets AU6 = No_Conn_FPGA_AU6 NC from line 985 of ultra_no_connect_pins_nets AU7 = No_Conn_FPGA_AU7 NC from line 982 of ultra_no_connect_pins_nets AU8 = MGT_AVTT MGTAVTT_RS from line 1334 of ultra_fpga_power_ground_nets AU9 = GROUND GND from line 680 of ultra_fpga_power_ground_nets AV1 = GROUND GND from line 689 of ultra_fpga_power_ground_nets AV2 = GROUND GND from line 690 of ultra_fpga_power_ground_nets AV3 = No_Conn_FPGA_AV3 NC from line 988 of ultra_no_connect_pins_nets AV4 = No_Conn_FPGA_AV4 NC from line 987 of ultra_no_connect_pins_nets AV5 = GROUND GND from line 691 of ultra_fpga_power_ground_nets AV6 = GROUND GND from line 692 of ultra_fpga_power_ground_nets AV7 = MGT_AVTT MGTAVTT_RS from line 1335 of ultra_fpga_power_ground_nets AV8 = No_Conn_FPGA_AV8 NC from line 989 of ultra_no_connect_pins_nets AV9 = No_Conn_FPGA_AV9 NC from line 986 of ultra_no_connect_pins_nets AW1 = No_Conn_FPGA_AW1 NC from line 994 of ultra_no_connect_pins_nets AW2 = No_Conn_FPGA_AW2 NC from line 993 of ultra_no_connect_pins_nets AW3 = GROUND GND from line 701 of ultra_fpga_power_ground_nets AW4 = GROUND GND from line 702 of ultra_fpga_power_ground_nets AW5 = GROUND GND from line 703 of ultra_fpga_power_ground_nets AW6 = No_Conn_FPGA_AW6 NC from line 995 of ultra_no_connect_pins_nets AW7 = No_Conn_FPGA_AW7 NC from line 992 of ultra_no_connect_pins_nets AW8 = GROUND GND from line 704 of ultra_fpga_power_ground_nets AW9 = MGT_AVTT MGTAVTT_RS from line 1336 of ultra_fpga_power_ground_nets AY1 = GROUND GND from line 714 of ultra_fpga_power_ground_nets AY2 = GROUND GND from line 715 of ultra_fpga_power_ground_nets AY3 = No_Conn_FPGA_AY3 NC from line 956 of ultra_no_connect_pins_nets AY4 = No_Conn_FPGA_AY4 NC from line 955 of ultra_no_connect_pins_nets AY5 = GROUND GND from line 716 of ultra_fpga_power_ground_nets AY6 = MGT_AVTT MGTAVTT_RS from line 1337 of ultra_fpga_power_ground_nets AY7 = GROUND GND from line 717 of ultra_fpga_power_ground_nets AY8 = No_Conn_FPGA_AY8 NC from line 957 of ultra_no_connect_pins_nets AY9 = No_Conn_FPGA_AY9 NC from line 954 of ultra_no_connect_pins_nets B10 = GROUND GND from line 67 of ultra_fpga_power_ground_nets B11 = MGT_AVTT MGTAVTT_RN from line 1314 of ultra_fpga_power_ground_nets B12 = GROUND GND from line 68 of ultra_fpga_power_ground_nets B13 = MGT_FO_CH_47_OUT_Hub_CMP MGTHRXN2_233 from line 10941 of mgt_fanout_channel_nets B14 = MGT_FO_CH_47_OUT_Hub_DIR MGTHRXP2_233 from line 10940 of mgt_fanout_channel_nets B15 = GROUND GND from line 69 of ultra_fpga_power_ground_nets B16 = GROUND GND from line 70 of ultra_fpga_power_ground_nets B17 = GROUND GND from line 71 of ultra_fpga_power_ground_nets B18 = No_Conn_FPGA_B18 IO_L24P_T3U_N10_72 from line 353 of ultra_no_connect_pins_nets B19 = GROUND GND from line 72 of ultra_fpga_power_ground_nets B20 = No_Conn_FPGA_B20 IO_L19N_T3L_N1_DBC_AD9N_72 from line 363 of ultra_no_connect_pins_nets B21 = No_Conn_FPGA_B21 IO_L21P_T3L_N4_AD8P_72 from line 359 of ultra_no_connect_pins_nets B22 = MGT_FO_EQU_ENB_GRP_6 IO_L24N_T3U_N11_71 from line 9212 of mgt_fanout_channel_nets B23 = No_Conn_FPGA_B23 IO_L22N_T3U_N7_DBC_AD0N_71 from line 325 of ultra_no_connect_pins_nets B24 = BULK_1V8 VCCO_71 from line 1098 of ultra_fpga_power_ground_nets B25 = MGT_FO_EQU_ENB_GRP_3 IO_L23P_T3U_N8_71 from line 9209 of mgt_fanout_channel_nets B26 = PLL_320.64_MHz_Lock_Detect_to_FPGA IO_L24P_T3U_N10_70 from line 497 of clock_generation_nets B27 = PLL_40.08_MHz_Lock_Detect_to_FPGA IO_L22P_T3U_N6_DBC_AD0P_70 from line 366 of clock_generation_nets B28 = No_Conn_FPGA_B28 IO_L22N_T3U_N7_DBC_AD0N_70 from line 232 of ultra_no_connect_pins_nets B29 = GROUND GND from line 73 of ultra_fpga_power_ground_nets B30 = GROUND GND from line 74 of ultra_fpga_power_ground_nets B31 = GROUND GND from line 75 of ultra_fpga_power_ground_nets B32 = GROUND GND from line 76 of ultra_fpga_power_ground_nets B33 = MGT_FO_CH_38_OUT_Hub_DIR MGTYRXP2_133 from line 10895 of mgt_fanout_channel_nets B34 = MGT_FO_CH_38_OUT_Hub_CMP MGTYRXN2_133 from line 10896 of mgt_fanout_channel_nets B35 = GROUND GND from line 77 of ultra_fpga_power_ground_nets B36 = MGT_AVTT MGTAVTT_LN from line 1253 of ultra_fpga_power_ground_nets B37 = GROUND GND from line 78 of ultra_fpga_power_ground_nets B38 = Comb_Data_to_Cap_to_FEX_07_Dir MGTYTXP2_133 from line 72 of combined_data_distribution_nets B39 = Comb_Data_to_Cap_to_FEX_07_Cmp MGTYTXN2_133 from line 73 of combined_data_distribution_nets B40 = MGT_AVTT MGTAVTT_LN from line 1254 of ultra_fpga_power_ground_nets B41 = GROUND GND from line 79 of ultra_fpga_power_ground_nets B42 = GROUND GND from line 80 of ultra_fpga_power_ground_nets B43 = MGT_FO_CH_25_OUT_Hub_CMP MGTYRXP3_132 from line 10880 of mgt_fanout_channel_nets B44 = MGT_FO_CH_25_OUT_Hub_DIR MGTYRXN3_132 from line 10881 of mgt_fanout_channel_nets B45 = GROUND GND from line 81 of ultra_fpga_power_ground_nets BA1 = No_Conn_FPGA_BA1 NC from line 962 of ultra_no_connect_pins_nets BA2 = No_Conn_FPGA_BA2 NC from line 961 of ultra_no_connect_pins_nets BA3 = GROUND GND from line 727 of ultra_fpga_power_ground_nets BA4 = GROUND GND from line 728 of ultra_fpga_power_ground_nets BA5 = GROUND GND from line 729 of ultra_fpga_power_ground_nets BA6 = No_Conn_FPGA_BA6 NC from line 963 of ultra_no_connect_pins_nets BA7 = No_Conn_FPGA_BA7 NC from line 960 of ultra_no_connect_pins_nets BA8 = MGT_AVTT MGTAVTT_RS from line 1338 of ultra_fpga_power_ground_nets BA9 = GROUND GND from line 730 of ultra_fpga_power_ground_nets BB1 = GROUND GND from line 739 of ultra_fpga_power_ground_nets BB2 = GROUND GND from line 740 of ultra_fpga_power_ground_nets BB3 = No_Conn_FPGA_BB3 NC from line 968 of ultra_no_connect_pins_nets BB4 = No_Conn_FPGA_BB4 NC from line 967 of ultra_no_connect_pins_nets BB5 = GROUND GND from line 741 of ultra_fpga_power_ground_nets BB6 = GROUND GND from line 742 of ultra_fpga_power_ground_nets BB7 = MGT_AVTT MGTAVTT_RS from line 1339 of ultra_fpga_power_ground_nets BB8 = No_Conn_FPGA_BB8 NC from line 969 of ultra_no_connect_pins_nets BB9 = No_Conn_FPGA_BB9 NC from line 966 of ultra_no_connect_pins_nets BC1 = No_Conn_FPGA_BC1 NC from line 974 of ultra_no_connect_pins_nets BC2 = No_Conn_FPGA_BC2 NC from line 973 of ultra_no_connect_pins_nets BC3 = GROUND GND from line 751 of ultra_fpga_power_ground_nets BC4 = GROUND GND from line 752 of ultra_fpga_power_ground_nets BC5 = GROUND GND from line 753 of ultra_fpga_power_ground_nets BC6 = No_Conn_FPGA_BC6 NC from line 975 of ultra_no_connect_pins_nets BC7 = No_Conn_FPGA_BC7 NC from line 972 of ultra_no_connect_pins_nets BC8 = GROUND GND from line 754 of ultra_fpga_power_ground_nets BC9 = MGT_AVTT MGTAVTT_RS from line 1340 of ultra_fpga_power_ground_nets BD1 = GROUND GND from line 772 of ultra_fpga_power_ground_nets BD2 = GROUND GND from line 773 of ultra_fpga_power_ground_nets BD3 = No_Conn_FPGA_BD3 NC from line 936 of ultra_no_connect_pins_nets BD4 = No_Conn_FPGA_BD4 NC from line 935 of ultra_no_connect_pins_nets BD5 = GROUND GND from line 774 of ultra_fpga_power_ground_nets BD6 = MGT_AVTT MGTAVTT_RS from line 1341 of ultra_fpga_power_ground_nets BD7 = GROUND GND from line 775 of ultra_fpga_power_ground_nets BD8 = No_Conn_FPGA_BD8 NC from line 937 of ultra_no_connect_pins_nets BD9 = No_Conn_FPGA_BD9 NC from line 934 of ultra_no_connect_pins_nets BE2 = GROUND GND from line 786 of ultra_fpga_power_ground_nets BE3 = GROUND GND from line 787 of ultra_fpga_power_ground_nets BE4 = GROUND GND from line 788 of ultra_fpga_power_ground_nets BE5 = GROUND GND from line 789 of ultra_fpga_power_ground_nets BE6 = No_Conn_FPGA_BE6 NC from line 943 of ultra_no_connect_pins_nets BE7 = No_Conn_FPGA_BE7 NC from line 940 of ultra_no_connect_pins_nets BE8 = MGT_AVTT MGTAVTT_RS from line 1342 of ultra_fpga_power_ground_nets BE9 = GROUND GND from line 790 of ultra_fpga_power_ground_nets BF3 = No_Conn_FPGA_BF3 NC from line 942 of ultra_no_connect_pins_nets BF4 = No_Conn_FPGA_BF4 NC from line 941 of ultra_no_connect_pins_nets BF5 = GROUND GND from line 805 of ultra_fpga_power_ground_nets BF6 = GROUND GND from line 806 of ultra_fpga_power_ground_nets BF7 = MGT_AVTT MGTAVTT_RS from line 1343 of ultra_fpga_power_ground_nets BF8 = No_Conn_FPGA_BF8 NC from line 953 of ultra_no_connect_pins_nets BF9 = No_Conn_FPGA_BF9 NC from line 950 of ultra_no_connect_pins_nets C10 = No_Conn_FPGA_C10 MGTHTXN1_233 from line 727 of ultra_no_connect_pins_nets C11 = No_Conn_FPGA_C11 MGTHTXP1_233 from line 726 of ultra_no_connect_pins_nets C12 = GROUND GND from line 86 of ultra_fpga_power_ground_nets C13 = GROUND GND from line 87 of ultra_fpga_power_ground_nets C14 = GROUND GND from line 88 of ultra_fpga_power_ground_nets C15 = MGT_FO_CH_46_OUT_Hub_DIR MGTHRXN1_233 from line 10945 of mgt_fanout_channel_nets C16 = MGT_FO_CH_46_OUT_Hub_CMP MGTHRXP1_233 from line 10944 of mgt_fanout_channel_nets C17 = GROUND GND from line 89 of ultra_fpga_power_ground_nets C18 = No_Conn_FPGA_C18 IO_L22N_T3U_N7_DBC_AD0N_72 from line 358 of ultra_no_connect_pins_nets C19 = No_Conn_FPGA_C19 IO_L22P_T3U_N6_DBC_AD0P_72 from line 357 of ultra_no_connect_pins_nets C20 = MGT_FO_EQU_ENB_GRP_8 IO_L19P_T3L_N0_DBC_AD9P_72 from line 9216 of mgt_fanout_channel_nets C21 = BULK_1V8 VCCO_72 from line 1109 of ultra_fpga_power_ground_nets C22 = No_Conn_FPGA_C22 IO_L24P_T3U_N10_71 from line 327 of ultra_no_connect_pins_nets C23 = No_Conn_FPGA_C23 IO_L22P_T3U_N6_DBC_AD0P_71 from line 326 of ultra_no_connect_pins_nets C24 = MGT_FO_EQU_ENB_GRP_5 IO_L19N_T3L_N1_DBC_AD9N_71 from line 9211 of mgt_fanout_channel_nets C25 = MGT_FO_EQU_ENB_GRP_1 IO_L21N_T3L_N5_AD8N_71 from line 9207 of mgt_fanout_channel_nets C26 = GROUND GND from line 90 of ultra_fpga_power_ground_nets C27 = No_Conn_FPGA_C27 IO_L21P_T3L_N4_AD8P_70 from line 233 of ultra_no_connect_pins_nets C28 = No_Conn_FPGA_C28 IO_L21N_T3L_N5_AD8N_70 from line 234 of ultra_no_connect_pins_nets C29 = No_Conn_FPGA_C29 IO_L23N_T3U_N9_70 from line 230 of ultra_no_connect_pins_nets C30 = GROUND GND from line 91 of ultra_fpga_power_ground_nets C31 = MGT_FO_CH_39_OUT_Hub_CMP MGTYRXP1_133 from line 10891 of mgt_fanout_channel_nets C32 = MGT_FO_CH_39_OUT_Hub_DIR MGTYRXN1_133 from line 10892 of mgt_fanout_channel_nets C33 = GROUND GND from line 92 of ultra_fpga_power_ground_nets C34 = GROUND GND from line 93 of ultra_fpga_power_ground_nets C35 = GROUND GND from line 94 of ultra_fpga_power_ground_nets C36 = No_Conn_FPGA_C36 MGTYTXP1_133 from line 573 of ultra_no_connect_pins_nets C37 = No_Conn_FPGA_C37 MGTYTXN1_133 from line 574 of ultra_no_connect_pins_nets C38 = MGT_AVTT MGTAVTT_LN from line 1255 of ultra_fpga_power_ground_nets C39 = GROUND GND from line 95 of ultra_fpga_power_ground_nets C40 = No_Conn_FPGA_C40 MGTYTXP2_132 from line 556 of ultra_no_connect_pins_nets C41 = No_Conn_FPGA_C41 MGTYTXN2_132 from line 557 of ultra_no_connect_pins_nets C42 = GROUND GND from line 96 of ultra_fpga_power_ground_nets C43 = GROUND GND from line 97 of ultra_fpga_power_ground_nets C44 = GROUND GND from line 98 of ultra_fpga_power_ground_nets C45 = MGT_FO_CH_26_OUT_Hub_DIR MGTYRXP2_132 from line 10876 of mgt_fanout_channel_nets C46 = MGT_FO_CH_26_OUT_Hub_CMP MGTYRXN2_132 from line 10877 of mgt_fanout_channel_nets D10 = MGT_AVTT MGTAVTT_RN from line 1316 of ultra_fpga_power_ground_nets D11 = GROUND GND from line 102 of ultra_fpga_power_ground_nets D12 = GROUND GND from line 103 of ultra_fpga_power_ground_nets D13 = MGT_FO_CH_45_OUT_Hub_CMP MGTHRXN0_233 from line 10949 of mgt_fanout_channel_nets D14 = MGT_FO_CH_45_OUT_Hub_DIR MGTHRXP0_233 from line 10948 of mgt_fanout_channel_nets D15 = GROUND GND from line 104 of ultra_fpga_power_ground_nets D16 = GROUND GND from line 105 of ultra_fpga_power_ground_nets D17 = GROUND GND from line 106 of ultra_fpga_power_ground_nets D18 = BULK_1V8 VCCO_72 from line 1110 of ultra_fpga_power_ground_nets D19 = No_Conn_FPGA_D19 IO_L20N_T3L_N3_AD1N_72 from line 361 of ultra_no_connect_pins_nets D20 = MGT_FO_EQU_ENB_GRP_7 IO_L20P_T3L_N2_AD1P_72 from line 9214 of mgt_fanout_channel_nets D21 = No_Conn_FPGA_D21 IO_T3U_N12_72 from line 355 of ultra_no_connect_pins_nets D22 = No_Conn_FPGA_D22 IO_T3U_N12_71 from line 328 of ultra_no_connect_pins_nets D23 = GROUND GND from line 107 of ultra_fpga_power_ground_nets D24 = No_Conn_FPGA_D24 IO_L19P_T3L_N0_DBC_AD9P_71 from line 333 of ultra_no_connect_pins_nets D25 = No_Conn_FPGA_D25 IO_L21P_T3L_N4_AD8P_71 from line 331 of ultra_no_connect_pins_nets D26 = No_Conn_FPGA_D26 IO_L19P_T3L_N0_DBC_AD9P_70 from line 237 of ultra_no_connect_pins_nets D27 = No_Conn_FPGA_D27 IO_L19N_T3L_N1_DBC_AD9N_70 from line 238 of ultra_no_connect_pins_nets D28 = BULK_1V8 VCCO_70 from line 1087 of ultra_fpga_power_ground_nets D29 = No_Conn_FPGA_D29 IO_L23P_T3U_N8_70 from line 229 of ultra_no_connect_pins_nets D30 = GROUND GND from line 108 of ultra_fpga_power_ground_nets D31 = GROUND GND from line 109 of ultra_fpga_power_ground_nets D32 = GROUND GND from line 110 of ultra_fpga_power_ground_nets D33 = MGT_FO_CH_40_OUT_Hub_DIR MGTYRXP0_133 from line 10887 of mgt_fanout_channel_nets D34 = MGT_FO_CH_40_OUT_Hub_CMP MGTYRXN0_133 from line 10888 of mgt_fanout_channel_nets D35 = GROUND GND from line 111 of ultra_fpga_power_ground_nets D36 = GROUND GND from line 112 of ultra_fpga_power_ground_nets D37 = MGT_AVTT MGTAVTT_LN from line 1256 of ultra_fpga_power_ground_nets D38 = No_Conn_FPGA_D38 MGTYTXP0_133 from line 576 of ultra_no_connect_pins_nets D39 = No_Conn_FPGA_D39 MGTYTXN0_133 from line 577 of ultra_no_connect_pins_nets D40 = MGT_AVTT MGTAVTTRCAL_LN from line 121 of ultra_dci_vref_mgt_calib_resistors_nets D41 = QUAD_130_MGTRREF MGTRREF_LN from line 122 of ultra_dci_vref_mgt_calib_resistors_nets D42 = GROUND GND from line 113 of ultra_fpga_power_ground_nets D43 = MGT_FO_CH_27_OUT_Hub_CMP MGTYRXP1_132 from line 10872 of mgt_fanout_channel_nets D44 = MGT_FO_CH_27_OUT_Hub_DIR MGTYRXN1_132 from line 10873 of mgt_fanout_channel_nets D45 = GROUND GND from line 114 of ultra_fpga_power_ground_nets D46 = GROUND GND from line 115 of ultra_fpga_power_ground_nets E10 = No_Conn_FPGA_E10 MGTHTXN1_232 from line 713 of ultra_no_connect_pins_nets E11 = No_Conn_FPGA_E11 MGTHTXP1_232 from line 712 of ultra_no_connect_pins_nets E12 = GROUND GND from line 120 of ultra_fpga_power_ground_nets E13 = GROUND GND from line 121 of ultra_fpga_power_ground_nets E14 = GROUND GND from line 122 of ultra_fpga_power_ground_nets E15 = MGT_FO_CH_34_OUT_Hub_DIR MGTHRXN3_231 from line 10926 of mgt_fanout_channel_nets E16 = MGT_FO_CH_34_OUT_Hub_CMP MGTHRXP3_231 from line 10925 of mgt_fanout_channel_nets E17 = GROUND GND from line 123 of ultra_fpga_power_ground_nets E18 = No_Conn_FPGA_E18 IO_L18N_T2U_N11_AD2N_72 from line 365 of ultra_no_connect_pins_nets E19 = No_Conn_FPGA_E19 IO_L18P_T2U_N10_AD2P_72 from line 364 of ultra_no_connect_pins_nets E20 = GROUND GND from line 124 of ultra_fpga_power_ground_nets E21 = No_Conn_FPGA_E21 IO_T2U_N12_72 from line 374 of ultra_no_connect_pins_nets E22 = No_Conn_FPGA_E22 IO_T2U_N12_71 from line 334 of ultra_no_connect_pins_nets E23 = No_Conn_FPGA_E23 IO_L16N_T2U_N7_QBC_AD3N_71 from line 332 of ultra_no_connect_pins_nets E24 = No_Conn_FPGA_E24 IO_L17N_T2U_N9_AD10N_71 from line 330 of ultra_no_connect_pins_nets E25 = BULK_1V8 VCCO_71 from line 1099 of ultra_fpga_power_ground_nets E26 = No_Conn_FPGA_E26 IO_T3U_N12_70 from line 228 of ultra_no_connect_pins_nets E27 = No_Conn_FPGA_E27 IO_L18P_T2U_N10_AD2P_70 from line 239 of ultra_no_connect_pins_nets E28 = No_Conn_FPGA_E28 IO_L18N_T2U_N11_AD2N_70 from line 240 of ultra_no_connect_pins_nets E29 = No_Conn_FPGA_E29 IO_L17N_T2U_N9_AD10N_70 from line 242 of ultra_no_connect_pins_nets E30 = GROUND GND from line 125 of ultra_fpga_power_ground_nets E31 = MGT_FO_CH_35_OUT_Hub_CMP MGTYRXP3_131 from line 10910 of mgt_fanout_channel_nets E32 = MGT_FO_CH_35_OUT_Hub_DIR MGTYRXN3_131 from line 10911 of mgt_fanout_channel_nets E33 = GROUND GND from line 126 of ultra_fpga_power_ground_nets E34 = GROUND GND from line 127 of ultra_fpga_power_ground_nets E35 = GROUND GND from line 128 of ultra_fpga_power_ground_nets E36 = No_Conn_FPGA_E36 MGTYTXP1_132 from line 559 of ultra_no_connect_pins_nets E37 = No_Conn_FPGA_E37 MGTYTXN1_132 from line 560 of ultra_no_connect_pins_nets E38 = GROUND GND from line 129 of ultra_fpga_power_ground_nets E39 = MGT_AVTT MGTAVTT_LN from line 1257 of ultra_fpga_power_ground_nets E40 = No_Conn_FPGA_E40 MGTYTXP0_132 from line 562 of ultra_no_connect_pins_nets E41 = No_Conn_FPGA_E41 MGTYTXN0_132 from line 563 of ultra_no_connect_pins_nets E42 = GROUND GND from line 130 of ultra_fpga_power_ground_nets E43 = GROUND GND from line 131 of ultra_fpga_power_ground_nets E44 = GROUND GND from line 132 of ultra_fpga_power_ground_nets E45 = MGT_FO_CH_28_OUT_Hub_DIR MGTYRXP0_132 from line 10868 of mgt_fanout_channel_nets E46 = MGT_FO_CH_28_OUT_Hub_CMP MGTYRXN0_132 from line 10869 of mgt_fanout_channel_nets F10 = GROUND GND from line 137 of ultra_fpga_power_ground_nets F11 = MGT_AVCC MGTAVCC_RN from line 1198 of ultra_fpga_power_ground_nets F12 = No_Conn_FPGA_F12 MGTHTXN3_231 from line 690 of ultra_no_connect_pins_nets F13 = No_Conn_FPGA_F13 MGTHTXP3_231 from line 689 of ultra_no_connect_pins_nets F14 = GROUND GND from line 138 of ultra_fpga_power_ground_nets F15 = GROUND GND from line 139 of ultra_fpga_power_ground_nets F16 = GROUND GND from line 140 of ultra_fpga_power_ground_nets F17 = GROUND GND from line 141 of ultra_fpga_power_ground_nets F18 = No_Conn_FPGA_F18 IO_L15N_T2L_N5_AD11N_72 from line 371 of ultra_no_connect_pins_nets F19 = No_Conn_FPGA_F19 IO_L15P_T2L_N4_AD11P_72 from line 370 of ultra_no_connect_pins_nets F20 = No_Conn_FPGA_F20 IO_L17N_T2U_N9_AD10N_72 from line 367 of ultra_no_connect_pins_nets F21 = No_Conn_FPGA_F21 IO_L18N_T2U_N11_AD2N_71 from line 291 of ultra_no_connect_pins_nets F22 = BULK_1V8 VCCO_71 from line 1100 of ultra_fpga_power_ground_nets F23 = No_Conn_FPGA_F23 IO_L16P_T2U_N6_QBC_AD3P_71 from line 293 of ultra_no_connect_pins_nets F24 = No_Conn_FPGA_F24 IO_L17P_T2U_N8_AD10P_71 from line 292 of ultra_no_connect_pins_nets F25 = No_Conn_FPGA_F25 IO_L15N_T2L_N5_AD11N_71 from line 295 of ultra_no_connect_pins_nets F26 = No_Conn_FPGA_F26 IO_L16N_T2U_N7_QBC_AD3N_70 from line 244 of ultra_no_connect_pins_nets F27 = GROUND GND from line 142 of ultra_fpga_power_ground_nets F28 = No_Conn_FPGA_F28 IO_L15N_T2L_N5_AD11N_70 from line 246 of ultra_no_connect_pins_nets F29 = No_Conn_FPGA_F29 IO_L17P_T2U_N8_AD10P_70 from line 241 of ultra_no_connect_pins_nets F30 = GROUND GND from line 143 of ultra_fpga_power_ground_nets F31 = GROUND GND from line 144 of ultra_fpga_power_ground_nets F32 = GROUND GND from line 145 of ultra_fpga_power_ground_nets F33 = GROUND GND from line 146 of ultra_fpga_power_ground_nets F34 = No_Conn_FPGA_F34 MGTYTXP3_131 from line 536 of ultra_no_connect_pins_nets F35 = No_Conn_FPGA_F35 MGTYTXN3_131 from line 537 of ultra_no_connect_pins_nets F36 = MGT_AVCC MGTAVCC_LN from line 1160 of ultra_fpga_power_ground_nets F37 = GROUND GND from line 147 of ultra_fpga_power_ground_nets F38 = No_Conn_FPGA_F38 MGTYTXP1_131 from line 542 of ultra_no_connect_pins_nets F39 = No_Conn_FPGA_F39 MGTYTXN1_131 from line 543 of ultra_no_connect_pins_nets F40 = MGT_AVTT MGTAVTT_LN from line 1258 of ultra_fpga_power_ground_nets F41 = GROUND GND from line 148 of ultra_fpga_power_ground_nets F42 = GROUND GND from line 149 of ultra_fpga_power_ground_nets F43 = MGT_FO_CH_29_OUT_Hub_CMP MGTYRXP1_131 from line 10861 of mgt_fanout_channel_nets F44 = MGT_FO_CH_29_OUT_Hub_DIR MGTYRXN1_131 from line 10862 of mgt_fanout_channel_nets F45 = GROUND GND from line 150 of ultra_fpga_power_ground_nets F46 = GROUND GND from line 151 of ultra_fpga_power_ground_nets G10 = No_Conn_FPGA_G10 MGTHTXN2_231 from line 693 of ultra_no_connect_pins_nets G11 = No_Conn_FPGA_G11 MGTHTXP2_231 from line 692 of ultra_no_connect_pins_nets G12 = GROUND GND from line 156 of ultra_fpga_power_ground_nets G13 = MGT_AVCC MGTAVCC_RN from line 1199 of ultra_fpga_power_ground_nets G14 = GROUND GND from line 157 of ultra_fpga_power_ground_nets G15 = MGT_FO_CH_33_OUT_Hub_CMP MGTHRXN2_231 from line 10930 of mgt_fanout_channel_nets G16 = MGT_FO_CH_33_OUT_Hub_DIR MGTHRXP2_231 from line 10929 of mgt_fanout_channel_nets G17 = GROUND GND from line 158 of ultra_fpga_power_ground_nets G18 = No_Conn_FPGA_G18 IO_L16N_T2U_N7_QBC_AD3N_72 from line 369 of ultra_no_connect_pins_nets G19 = BULK_1V8 VCCO_72 from line 1111 of ultra_fpga_power_ground_nets G20 = No_Conn_FPGA_G20 IO_L17P_T2U_N8_AD10P_72 from line 366 of ultra_no_connect_pins_nets G21 = No_Conn_FPGA_G21 IO_L18P_T2U_N10_AD2P_71 from line 290 of ultra_no_connect_pins_nets G22 = No_Conn_FPGA_G22 IO_L13N_T2L_N1_GC_QBC_71 from line 298 of ultra_no_connect_pins_nets G23 = Ref_40.08_MHz_from_Other_Hub_Cmp IO_L14N_T2L_N3_GC_71 from line 208 of clock_generation_nets G24 = GROUND GND from line 159 of ultra_fpga_power_ground_nets G25 = No_Conn_FPGA_G25 IO_L15P_T2L_N4_AD11P_71 from line 294 of ultra_no_connect_pins_nets G26 = No_Conn_FPGA_G26 IO_L16P_T2U_N6_QBC_AD3P_70 from line 243 of ultra_no_connect_pins_nets G27 = No_Conn_FPGA_G27 IO_T2U_N12_70 from line 249 of ultra_no_connect_pins_nets G28 = No_Conn_FPGA_G28 IO_L15P_T2L_N4_AD11P_70 from line 245 of ultra_no_connect_pins_nets G29 = BULK_1V8 VCCO_70 from line 1088 of ultra_fpga_power_ground_nets G30 = GROUND GND from line 160 of ultra_fpga_power_ground_nets G31 = MGT_FO_CH_36_OUT_Hub_DIR MGTYRXP2_131 from line 10906 of mgt_fanout_channel_nets G32 = MGT_FO_CH_36_OUT_Hub_CMP MGTYRXN2_131 from line 10907 of mgt_fanout_channel_nets G33 = GROUND GND from line 161 of ultra_fpga_power_ground_nets G34 = MGT_AVCC MGTAVCC_LN from line 1161 of ultra_fpga_power_ground_nets G35 = GROUND GND from line 162 of ultra_fpga_power_ground_nets G36 = No_Conn_FPGA_G36 MGTYTXP2_131 from line 539 of ultra_no_connect_pins_nets G37 = No_Conn_FPGA_G37 MGTYTXN2_131 from line 540 of ultra_no_connect_pins_nets G38 = MGT_AVTT MGTAVTT_LN from line 1259 of ultra_fpga_power_ground_nets G39 = GROUND GND from line 163 of ultra_fpga_power_ground_nets G40 = No_Conn_FPGA_G40 MGTYTXP0_131 from line 545 of ultra_no_connect_pins_nets G41 = No_Conn_FPGA_G41 MGTYTXN0_131 from line 546 of ultra_no_connect_pins_nets G42 = GROUND GND from line 164 of ultra_fpga_power_ground_nets G43 = GROUND GND from line 165 of ultra_fpga_power_ground_nets G44 = GROUND GND from line 166 of ultra_fpga_power_ground_nets G45 = MGT_FO_CH_30_OUT_Hub_DIR MGTYRXP0_131 from line 10857 of mgt_fanout_channel_nets G46 = MGT_FO_CH_30_OUT_Hub_CMP MGTYRXN0_131 from line 10858 of mgt_fanout_channel_nets H10 = MGT_AVCC MGTAVCC_RN from line 1200 of ultra_fpga_power_ground_nets H11 = GROUND GND from line 171 of ultra_fpga_power_ground_nets H12 = No_Conn_FPGA_H12 MGTREFCLK1N_233 from line 853 of ultra_no_connect_pins_nets H13 = No_Conn_FPGA_H13 MGTREFCLK1P_233 from line 852 of ultra_no_connect_pins_nets H14 = GROUND GND from line 172 of ultra_fpga_power_ground_nets H15 = GROUND GND from line 173 of ultra_fpga_power_ground_nets H16 = GROUND GND from line 174 of ultra_fpga_power_ground_nets H17 = GROUND GND from line 175 of ultra_fpga_power_ground_nets H18 = No_Conn_FPGA_H18 IO_L16P_T2U_N6_QBC_AD3P_72 from line 368 of ultra_no_connect_pins_nets H19 = No_Conn_FPGA_H19 IO_L14N_T2L_N3_GC_72 from line 373 of ultra_no_connect_pins_nets H20 = No_Conn_FPGA_H20 IO_L14P_T2L_N2_GC_72 from line 372 of ultra_no_connect_pins_nets H21 = GROUND GND from line 176 of ultra_fpga_power_ground_nets H22 = No_Conn_FPGA_H22 IO_L13P_T2L_N0_GC_QBC_71 from line 297 of ultra_no_connect_pins_nets H23 = Ref_40.08_MHz_from_Other_Hub_Dir IO_L14P_T2L_N2_GC_71 from line 207 of clock_generation_nets H24 = Logic_Clk_40.08_MHz_to_FPGA_Cmp IO_L12N_T1U_N11_GC_71 from line 60 of clock_40.08_MHz_distribution_nets H25 = No_Conn_FPGA_H25 IO_L9N_T1L_N5_AD12N_71 from line 305 of ultra_no_connect_pins_nets H26 = BULK_1V8 VCCO_70 from line 1089 of ultra_fpga_power_ground_nets H27 = No_Conn_FPGA_H27 IO_L14N_T2L_N3_GC_70 from line 248 of ultra_no_connect_pins_nets H28 = No_Conn_FPGA_H28 IO_L13P_T2L_N0_GC_QBC_70 from line 250 of ultra_no_connect_pins_nets H29 = No_Conn_FPGA_H29 IO_L13N_T2L_N1_GC_QBC_70 from line 251 of ultra_no_connect_pins_nets H30 = GROUND GND from line 177 of ultra_fpga_power_ground_nets H31 = GROUND GND from line 178 of ultra_fpga_power_ground_nets H32 = GROUND GND from line 179 of ultra_fpga_power_ground_nets H33 = GROUND GND from line 180 of ultra_fpga_power_ground_nets H34 = No_Conn_FPGA_H34 MGTREFCLK1P_133 from line 794 of ultra_no_connect_pins_nets H35 = No_Conn_FPGA_H35 MGTREFCLK1N_133 from line 795 of ultra_no_connect_pins_nets H36 = GROUND GND from line 181 of ultra_fpga_power_ground_nets H37 = MGT_AVCC MGTAVCC_LN from line 1162 of ultra_fpga_power_ground_nets H38 = No_Conn_FPGA_H38 MGTYTXP3_130 from line 522 of ultra_no_connect_pins_nets H39 = No_Conn_FPGA_H39 MGTYTXN3_130 from line 523 of ultra_no_connect_pins_nets H40 = GROUND GND from line 182 of ultra_fpga_power_ground_nets H41 = MGT_AVTT MGTAVTT_LN from line 1260 of ultra_fpga_power_ground_nets H42 = GROUND GND from line 183 of ultra_fpga_power_ground_nets H43 = MGT_FO_CH_31_OUT_Hub_CMP MGTYRXP3_130 from line 10850 of mgt_fanout_channel_nets H44 = MGT_FO_CH_31_OUT_Hub_DIR MGTYRXN3_130 from line 10851 of mgt_fanout_channel_nets H45 = GROUND GND from line 184 of ultra_fpga_power_ground_nets H46 = GROUND GND from line 185 of ultra_fpga_power_ground_nets J10 = No_Conn_FPGA_J10 MGTREFCLK0N_233 from line 856 of ultra_no_connect_pins_nets J11 = No_Conn_FPGA_J11 MGTREFCLK0P_233 from line 855 of ultra_no_connect_pins_nets J12 = MGT_AVAUX MGTVCCAUX_RN from line 1386 of ultra_fpga_power_ground_nets J13 = GROUND GND from line 190 of ultra_fpga_power_ground_nets J14 = GROUND GND from line 191 of ultra_fpga_power_ground_nets J15 = No_Conn_FPGA_J15 IO_T1U_N12_72 from line 379 of ultra_no_connect_pins_nets J16 = No_Conn_FPGA_J16 IO_L10N_T1U_N7_QBC_AD4N_72 from line 383 of ultra_no_connect_pins_nets J17 = No_Conn_FPGA_J17 IO_L7N_T1L_N1_QBC_AD13N_72 from line 389 of ultra_no_connect_pins_nets J18 = GROUND GND from line 192 of ultra_fpga_power_ground_nets J19 = No_Conn_FPGA_J19 IO_L13N_T2L_N1_GC_QBC_72 from line 376 of ultra_no_connect_pins_nets J20 = No_Conn_FPGA_J20 IO_L13P_T2L_N0_GC_QBC_72 from line 375 of ultra_no_connect_pins_nets J21 = No_Conn_FPGA_J21 IO_L10N_T1U_N7_QBC_AD4N_71 from line 303 of ultra_no_connect_pins_nets J22 = Logic_Clk_320.64_MHz_to_FPGA_Cmp IO_L11N_T1U_N9_GC_71 from line 622 of clock_generation_nets J23 = BULK_1V8 VCCO_71 from line 1101 of ultra_fpga_power_ground_nets J24 = Logic_Clk_40.08_MHz_to_FPGA_Dir IO_L12P_T1U_N10_GC_71 from line 59 of clock_40.08_MHz_distribution_nets J25 = No_Conn_FPGA_J25 IO_L9P_T1L_N4_AD12P_71 from line 304 of ultra_no_connect_pins_nets J26 = No_Conn_FPGA_J26 IO_L10N_T1U_N7_QBC_AD4N_70 from line 258 of ultra_no_connect_pins_nets J27 = No_Conn_FPGA_J27 IO_L14P_T2L_N2_GC_70 from line 247 of ultra_no_connect_pins_nets J28 = GROUND GND from line 193 of ultra_fpga_power_ground_nets J29 = No_Conn_FPGA_J29 IO_L12N_T1U_N11_GC_70 from line 253 of ultra_no_connect_pins_nets J30 = No_Conn_FPGA_J30 IO_T0U_N12_VRP_70 from line 275 of ultra_no_connect_pins_nets J31 = No_Conn_FPGA_J31 IO_L5N_T0U_N9_AD14N_70 from line 268 of ultra_no_connect_pins_nets J32 = No_Conn_FPGA_J32 IO_L3N_T0L_N5_AD15N_70 from line 272 of ultra_no_connect_pins_nets J33 = GROUND GND from line 194 of ultra_fpga_power_ground_nets J34 = GROUND GND from line 195 of ultra_fpga_power_ground_nets J35 = MGT_AVAUX MGTVCCAUX_LN from line 1365 of ultra_fpga_power_ground_nets J36 = No_Conn_FPGA_J36 MGTREFCLK0P_133 from line 797 of ultra_no_connect_pins_nets J37 = No_Conn_FPGA_J37 MGTREFCLK0N_133 from line 798 of ultra_no_connect_pins_nets J38 = GROUND GND from line 196 of ultra_fpga_power_ground_nets J39 = MGT_AVTT MGTAVTT_LN from line 1261 of ultra_fpga_power_ground_nets J40 = Comb_Data_to_Cap_to_FEX_05_Dir MGTYTXP2_130 from line 82 of combined_data_distribution_nets J41 = Comb_Data_to_Cap_to_FEX_05_Cmp MGTYTXN2_130 from line 83 of combined_data_distribution_nets J42 = GROUND GND from line 197 of ultra_fpga_power_ground_nets J43 = GROUND GND from line 198 of ultra_fpga_power_ground_nets J44 = GROUND GND from line 199 of ultra_fpga_power_ground_nets J45 = MGT_FO_CH_32_OUT_Hub_DIR MGTYRXP2_130 from line 10846 of mgt_fanout_channel_nets J46 = MGT_FO_CH_32_OUT_Hub_CMP MGTYRXN2_130 from line 10847 of mgt_fanout_channel_nets K10 = GROUND GND from line 204 of ultra_fpga_power_ground_nets K11 = MGT_AVCC MGTAVCC_RN from line 1201 of ultra_fpga_power_ground_nets K12 = MHz_320.64_COPY_7_CMP MGTREFCLK1N_232 from line 643 of clock_generation_nets K13 = MHz_320.64_COPY_7_DIR MGTREFCLK1P_232 from line 642 of clock_generation_nets K14 = PUDC_B PUDC_B_0 from line 196 of bank_0_and_bank_65_config_mem_nets K15 = GROUND GND from line 205 of ultra_fpga_power_ground_nets K16 = No_Conn_FPGA_K16 IO_L10P_T1U_N6_QBC_AD4P_72 from line 382 of ultra_no_connect_pins_nets K17 = No_Conn_FPGA_K17 IO_L7P_T1L_N0_QBC_AD13P_72 from line 388 of ultra_no_connect_pins_nets K18 = No_Conn_FPGA_K18 IO_L12N_T1U_N11_GC_72 from line 378 of ultra_no_connect_pins_nets K19 = No_Conn_FPGA_K19 IO_L12P_T1U_N10_GC_72 from line 377 of ultra_no_connect_pins_nets K20 = BULK_1V8 VCCO_72 from line 1112 of ultra_fpga_power_ground_nets K21 = No_Conn_FPGA_K21 IO_L10P_T1U_N6_QBC_AD4P_71 from line 302 of ultra_no_connect_pins_nets K22 = Logic_Clk_320.64_MHz_to_FPGA_Dir IO_L11P_T1U_N8_GC_71 from line 621 of clock_generation_nets K23 = No_Conn_FPGA_K23 IO_L8N_T1L_N3_AD5N_71 from line 307 of ultra_no_connect_pins_nets K24 = No_Conn_FPGA_K24 IO_L7N_T1L_N1_QBC_AD13N_71 from line 309 of ultra_no_connect_pins_nets K25 = GROUND GND from line 206 of ultra_fpga_power_ground_nets K26 = No_Conn_FPGA_K26 IO_L10P_T1U_N6_QBC_AD4P_70 from line 257 of ultra_no_connect_pins_nets K27 = No_Conn_FPGA_K27 IO_L11P_T1U_N8_GC_70 from line 255 of ultra_no_connect_pins_nets K28 = No_Conn_FPGA_K28 IO_L11N_T1U_N9_GC_70 from line 256 of ultra_no_connect_pins_nets K29 = No_Conn_FPGA_K29 IO_L12P_T1U_N10_GC_70 from line 252 of ultra_no_connect_pins_nets K30 = BULK_1V8 VCCO_70 from line 1090 of ultra_fpga_power_ground_nets K31 = No_Conn_FPGA_K31 IO_L5P_T0U_N8_AD14P_70 from line 267 of ultra_no_connect_pins_nets K32 = No_Conn_FPGA_K32 IO_L3P_T0L_N4_AD15P_70 from line 271 of ultra_no_connect_pins_nets K33 = GROUND GND from line 207 of ultra_fpga_power_ground_nets K34 = MHz_320.64_COPY_2_DIR MGTREFCLK1P_132 from line 597 of clock_generation_nets K35 = MHz_320.64_COPY_2_CMP MGTREFCLK1N_132 from line 598 of clock_generation_nets K36 = MGT_AVCC MGTAVCC_LN from line 1163 of ultra_fpga_power_ground_nets K37 = GROUND GND from line 208 of ultra_fpga_power_ground_nets K38 = No_Conn_FPGA_K38 MGTYTXP1_130 from line 525 of ultra_no_connect_pins_nets K39 = No_Conn_FPGA_K39 MGTYTXN1_130 from line 526 of ultra_no_connect_pins_nets K40 = MGT_AVTT MGTAVTT_LN from line 1262 of ultra_fpga_power_ground_nets K41 = GROUND GND from line 209 of ultra_fpga_power_ground_nets K42 = GROUND GND from line 210 of ultra_fpga_power_ground_nets K43 = MGT_FO_CH_17_OUT_Hub_CMP MGTYRXP1_130 from line 10842 of mgt_fanout_channel_nets K44 = MGT_FO_CH_17_OUT_Hub_DIR MGTYRXN1_130 from line 10843 of mgt_fanout_channel_nets K45 = GROUND GND from line 211 of ultra_fpga_power_ground_nets K46 = GROUND GND from line 212 of ultra_fpga_power_ground_nets L10 = No_Conn_FPGA_L10 MGTREFCLK0N_232 from line 849 of ultra_no_connect_pins_nets L11 = No_Conn_FPGA_L11 MGTREFCLK0P_232 from line 848 of ultra_no_connect_pins_nets L12 = GROUND GND from line 217 of ultra_fpga_power_ground_nets L13 = MGT_AVAUX MGTVCCAUX_RN from line 1387 of ultra_fpga_power_ground_nets L14 = GROUND GND from line 218 of ultra_fpga_power_ground_nets L15 = No_Conn_FPGA_L15 IO_L8N_T1L_N3_AD5N_72 from line 387 of ultra_no_connect_pins_nets L16 = No_Conn_FPGA_L16 IO_L8P_T1L_N2_AD5P_72 from line 386 of ultra_no_connect_pins_nets L17 = BULK_1V8 VCCO_72 from line 1113 of ultra_fpga_power_ground_nets L18 = No_Conn_FPGA_L18 IO_L11N_T1U_N9_GC_72 from line 381 of ultra_no_connect_pins_nets L19 = No_Conn_FPGA_L19 IO_L11P_T1U_N8_GC_72 from line 380 of ultra_no_connect_pins_nets L20 = No_Conn_FPGA_L20 IO_L9N_T1L_N5_AD12N_72 from line 385 of ultra_no_connect_pins_nets L21 = No_Conn_FPGA_L21 IO_L6N_T0U_N11_AD6N_71 from line 311 of ultra_no_connect_pins_nets L22 = GROUND GND from line 219 of ultra_fpga_power_ground_nets L23 = No_Conn_FPGA_L23 IO_L8P_T1L_N2_AD5P_71 from line 306 of ultra_no_connect_pins_nets L24 = No_Conn_FPGA_L24 IO_L7P_T1L_N0_QBC_AD13P_71 from line 308 of ultra_no_connect_pins_nets L25 = No_Conn_FPGA_L25 IO_T1U_N12_71 from line 300 of ultra_no_connect_pins_nets L26 = No_Conn_FPGA_L26 IO_T1U_N12_70 from line 254 of ultra_no_connect_pins_nets L27 = BULK_1V8 VCCO_70 from line 1091 of ultra_fpga_power_ground_nets L28 = No_Conn_FPGA_L28 IO_L9P_T1L_N4_AD12P_70 from line 259 of ultra_no_connect_pins_nets L29 = No_Conn_FPGA_L29 IO_L9N_T1L_N5_AD12N_70 from line 260 of ultra_no_connect_pins_nets L30 = No_Conn_FPGA_L30 IO_L6N_T0U_N11_AD6N_70 from line 266 of ultra_no_connect_pins_nets L31 = No_Conn_FPGA_L31 IO_L1N_T0L_N1_DBC_70 from line 277 of ultra_no_connect_pins_nets L32 = GROUND GND from line 220 of ultra_fpga_power_ground_nets L33 = GROUND GND from line 221 of ultra_fpga_power_ground_nets L34 = MGT_AVAUX MGTVCCAUX_LN from line 1366 of ultra_fpga_power_ground_nets L35 = GROUND GND from line 222 of ultra_fpga_power_ground_nets L36 = No_Conn_FPGA_L36 MGTREFCLK0P_132 from line 790 of ultra_no_connect_pins_nets L37 = No_Conn_FPGA_L37 MGTREFCLK0N_132 from line 791 of ultra_no_connect_pins_nets L38 = MGT_AVTT MGTAVTT_LN from line 1263 of ultra_fpga_power_ground_nets L39 = GROUND GND from line 223 of ultra_fpga_power_ground_nets L40 = Comb_Data_to_Cap_to_FEX_04_Dir MGTYTXP0_130 from line 85 of combined_data_distribution_nets L41 = Comb_Data_to_Cap_to_FEX_04_Cmp MGTYTXN0_130 from line 86 of combined_data_distribution_nets L42 = GROUND GND from line 224 of ultra_fpga_power_ground_nets L43 = GROUND GND from line 225 of ultra_fpga_power_ground_nets L44 = GROUND GND from line 226 of ultra_fpga_power_ground_nets L45 = MGT_FO_CH_18_OUT_Hub_DIR MGTYRXP0_130 from line 10838 of mgt_fanout_channel_nets L46 = MGT_FO_CH_18_OUT_Hub_CMP MGTYRXN0_130 from line 10839 of mgt_fanout_channel_nets M10 = MGT_AVCC MGTAVCC_RN from line 1202 of ultra_fpga_power_ground_nets M11 = GROUND GND from line 231 of ultra_fpga_power_ground_nets M12 = No_Conn_FPGA_M12 MGTREFCLK1N_231 from line 842 of ultra_no_connect_pins_nets M13 = No_Conn_FPGA_M13 MGTREFCLK1P_231 from line 841 of ultra_no_connect_pins_nets M14 = CFGBVS CFGBVS_0 from line 188 of bank_0_and_bank_65_config_mem_nets M15 = No_Conn_FPGA_M15 IO_L4N_T0U_N7_DBC_AD7N_72 from line 395 of ultra_no_connect_pins_nets M16 = No_Conn_FPGA_M16 IO_L4P_T0U_N6_DBC_AD7P_72 from line 394 of ultra_no_connect_pins_nets M17 = No_Conn_FPGA_M17 IO_L2N_T0L_N3_72 from line 399 of ultra_no_connect_pins_nets M18 = No_Conn_FPGA_M18 IO_L1N_T0L_N1_DBC_72 from line 402 of ultra_no_connect_pins_nets M19 = GROUND GND from line 232 of ultra_fpga_power_ground_nets M20 = No_Conn_FPGA_M20 IO_L9P_T1L_N4_AD12P_72 from line 384 of ultra_no_connect_pins_nets M21 = No_Conn_FPGA_M21 IO_L6P_T0U_N10_AD6P_71 from line 310 of ultra_no_connect_pins_nets M22 = No_Conn_FPGA_M22 IO_L4N_T0U_N7_DBC_AD7N_71 from line 315 of ultra_no_connect_pins_nets M23 = No_Conn_FPGA_M23 IO_L1N_T0L_N1_DBC_71 from line 322 of ultra_no_connect_pins_nets M24 = BULK_1V8 VCCO_71 from line 1102 of ultra_fpga_power_ground_nets M25 = No_Conn_FPGA_M25 IO_L3N_T0L_N5_AD15N_71 from line 317 of ultra_no_connect_pins_nets M26 = No_Conn_FPGA_M26 IO_L3P_T0L_N4_AD15P_71 from line 316 of ultra_no_connect_pins_nets M27 = No_Conn_FPGA_M27 IO_L8N_T1L_N3_AD5N_70 from line 262 of ultra_no_connect_pins_nets M28 = No_Conn_FPGA_M28 IO_L7N_T1L_N1_QBC_AD13N_70 from line 264 of ultra_no_connect_pins_nets M29 = GROUND GND from line 233 of ultra_fpga_power_ground_nets M30 = No_Conn_FPGA_M30 IO_L6P_T0U_N10_AD6P_70 from line 265 of ultra_no_connect_pins_nets M31 = No_Conn_FPGA_M31 IO_L1P_T0L_N0_DBC_70 from line 276 of ultra_no_connect_pins_nets M32 = No_Conn_FPGA_M32 IO_L2N_T0L_N3_70 from line 274 of ultra_no_connect_pins_nets M33 = GROUND GND from line 234 of ultra_fpga_power_ground_nets M34 = No_Conn_FPGA_M34 MGTREFCLK1P_131 from line 783 of ultra_no_connect_pins_nets M35 = No_Conn_FPGA_M35 MGTREFCLK1N_131 from line 784 of ultra_no_connect_pins_nets M36 = GROUND GND from line 235 of ultra_fpga_power_ground_nets M37 = MGT_AVCC MGTAVCC_LN from line 1164 of ultra_fpga_power_ground_nets M38 = No_Conn_FPGA_M38 MGTYTXP3_129 from line 508 of ultra_no_connect_pins_nets M39 = No_Conn_FPGA_M39 MGTYTXN3_129 from line 509 of ultra_no_connect_pins_nets M40 = GROUND GND from line 236 of ultra_fpga_power_ground_nets M41 = MGT_AVTT MGTAVTT_LN from line 1264 of ultra_fpga_power_ground_nets M42 = GROUND GND from line 237 of ultra_fpga_power_ground_nets M43 = MGT_FO_CH_19_OUT_Hub_CMP MGTYRXP3_129 from line 10831 of mgt_fanout_channel_nets M44 = MGT_FO_CH_19_OUT_Hub_DIR MGTYRXN3_129 from line 10832 of mgt_fanout_channel_nets M45 = GROUND GND from line 238 of ultra_fpga_power_ground_nets M46 = GROUND GND from line 239 of ultra_fpga_power_ground_nets N10 = No_Conn_FPGA_N10 MGTREFCLK0N_231 from line 845 of ultra_no_connect_pins_nets N11 = No_Conn_FPGA_N11 MGTREFCLK0P_231 from line 844 of ultra_no_connect_pins_nets N12 = MGT_AVCC MGTAVCC_RN from line 1203 of ultra_fpga_power_ground_nets N13 = GROUND GND from line 244 of ultra_fpga_power_ground_nets N14 = GROUND GND from line 245 of ultra_fpga_power_ground_nets N15 = No_Conn_FPGA_N15 IO_T0U_N12_VRP_72 from line 400 of ultra_no_connect_pins_nets N16 = GROUND GND from line 246 of ultra_fpga_power_ground_nets N17 = No_Conn_FPGA_N17 IO_L2P_T0L_N2_72 from line 398 of ultra_no_connect_pins_nets N18 = No_Conn_FPGA_N18 IO_L1P_T0L_N0_DBC_72 from line 401 of ultra_no_connect_pins_nets N19 = No_Conn_FPGA_N19 IO_L3N_T0L_N5_AD15N_72 from line 397 of ultra_no_connect_pins_nets N20 = No_Conn_FPGA_N20 IO_L5N_T0U_N9_AD14N_72 from line 393 of ultra_no_connect_pins_nets N21 = BULK_1V8 VCCO_71 from line 1103 of ultra_fpga_power_ground_nets N22 = No_Conn_FPGA_N22 IO_L4P_T0U_N6_DBC_AD7P_71 from line 314 of ultra_no_connect_pins_nets N23 = No_Conn_FPGA_N23 IO_L1P_T0L_N0_DBC_71 from line 321 of ultra_no_connect_pins_nets N24 = No_Conn_FPGA_N24 IO_L2N_T0L_N3_71 from line 319 of ultra_no_connect_pins_nets N25 = No_Conn_FPGA_N25 IO_L5N_T0U_N9_AD14N_71 from line 313 of ultra_no_connect_pins_nets N26 = GROUND GND from line 247 of ultra_fpga_power_ground_nets N27 = No_Conn_FPGA_N27 IO_L8P_T1L_N2_AD5P_70 from line 261 of ultra_no_connect_pins_nets N28 = No_Conn_FPGA_N28 IO_L7P_T1L_N0_QBC_AD13P_70 from line 263 of ultra_no_connect_pins_nets N29 = No_Conn_FPGA_N29 IO_L4P_T0U_N6_DBC_AD7P_70 from line 269 of ultra_no_connect_pins_nets N30 = No_Conn_FPGA_N30 IO_L4N_T0U_N7_DBC_AD7N_70 from line 270 of ultra_no_connect_pins_nets N31 = BULK_1V8 VCCO_70 from line 1092 of ultra_fpga_power_ground_nets N32 = No_Conn_FPGA_N32 IO_L2P_T0L_N2_70 from line 273 of ultra_no_connect_pins_nets N33 = GROUND GND from line 248 of ultra_fpga_power_ground_nets N34 = GROUND GND from line 249 of ultra_fpga_power_ground_nets N35 = MGT_AVCC MGTAVCC_LN from line 1165 of ultra_fpga_power_ground_nets N36 = No_Conn_FPGA_N36 MGTREFCLK0P_131 from line 786 of ultra_no_connect_pins_nets N37 = No_Conn_FPGA_N37 MGTREFCLK0N_131 from line 787 of ultra_no_connect_pins_nets N38 = GROUND GND from line 250 of ultra_fpga_power_ground_nets N39 = MGT_AVTT MGTAVTT_LN from line 1265 of ultra_fpga_power_ground_nets N40 = Comb_Data_to_Cap_to_FEX_03_Dir MGTYTXP2_129 from line 90 of combined_data_distribution_nets N41 = Comb_Data_to_Cap_to_FEX_03_Cmp MGTYTXN2_129 from line 91 of combined_data_distribution_nets N42 = GROUND GND from line 251 of ultra_fpga_power_ground_nets N43 = GROUND GND from line 252 of ultra_fpga_power_ground_nets N44 = GROUND GND from line 253 of ultra_fpga_power_ground_nets N45 = MGT_FO_CH_20_OUT_Hub_DIR MGTYRXP2_129 from line 10827 of mgt_fanout_channel_nets N46 = MGT_FO_CH_20_OUT_Hub_CMP MGTYRXN2_129 from line 10828 of mgt_fanout_channel_nets P10 = GROUND GND from line 258 of ultra_fpga_power_ground_nets P11 = MGT_AVCC MGTAVCC_RN from line 1204 of ultra_fpga_power_ground_nets P12 = No_Conn_FPGA_P12 MGTREFCLK1N_230 from line 838 of ultra_no_connect_pins_nets P13 = No_Conn_FPGA_P13 MGTREFCLK1P_230 from line 837 of ultra_no_connect_pins_nets P14 = FLASH_RESET_B INIT_B_0 from line 126 of bank_0_and_bank_65_config_mem_nets P15 = No_Conn_FPGA_P15 VREF_72 from line 403 of ultra_no_connect_pins_nets P16 = No_Conn_FPGA_P16 IO_L6N_T0U_N11_AD6N_72 from line 391 of ultra_no_connect_pins_nets P17 = No_Conn_FPGA_P17 IO_L6P_T0U_N10_AD6P_72 from line 390 of ultra_no_connect_pins_nets P18 = BULK_1V8 VCCO_72 from line 1114 of ultra_fpga_power_ground_nets P19 = No_Conn_FPGA_P19 IO_L3P_T0L_N4_AD15P_72 from line 396 of ultra_no_connect_pins_nets P20 = No_Conn_FPGA_P20 IO_L5P_T0U_N8_AD14P_72 from line 392 of ultra_no_connect_pins_nets P21 = Bank_71_VREF VREF_71 from line 88 of ultra_dci_vref_mgt_calib_resistors_nets P22 = Bank_71_VRP_DCI IO_T0U_N12_VRP_71 from line 50 of ultra_dci_vref_mgt_calib_resistors_nets P23 = GROUND GND from line 259 of ultra_fpga_power_ground_nets P24 = No_Conn_FPGA_P24 IO_L2P_T0L_N2_71 from line 318 of ultra_no_connect_pins_nets P25 = No_Conn_FPGA_P25 IO_L5P_T0U_N8_AD14P_71 from line 312 of ultra_no_connect_pins_nets P26 = FPGA_CORE VCCINT from line 827 of ultra_fpga_power_ground_nets P27 = No_Conn_FPGA_P27 VREF_70 from line 278 of ultra_no_connect_pins_nets P28 = FPGA_CORE VCCINT from line 828 of ultra_fpga_power_ground_nets P29 = GROUND GND from line 260 of ultra_fpga_power_ground_nets P30 = FPGA_CORE VCCINT_IO from line 943 of ultra_fpga_power_ground_nets P31 = GROUND GND from line 261 of ultra_fpga_power_ground_nets P32 = BULK_1V8 VCCAUX from line 982 of ultra_fpga_power_ground_nets P33 = GROUND GND from line 262 of ultra_fpga_power_ground_nets P34 = No_Conn_FPGA_P34 MGTREFCLK1P_130 from line 779 of ultra_no_connect_pins_nets P35 = No_Conn_FPGA_P35 MGTREFCLK1N_130 from line 780 of ultra_no_connect_pins_nets P36 = MGT_AVCC MGTAVCC_LN from line 1166 of ultra_fpga_power_ground_nets P37 = GROUND GND from line 263 of ultra_fpga_power_ground_nets P38 = No_Conn_FPGA_P38 MGTYTXP1_129 from line 511 of ultra_no_connect_pins_nets P39 = No_Conn_FPGA_P39 MGTYTXN1_129 from line 512 of ultra_no_connect_pins_nets P40 = MGT_AVTT MGTAVTT_LN from line 1266 of ultra_fpga_power_ground_nets P41 = GROUND GND from line 264 of ultra_fpga_power_ground_nets P42 = GROUND GND from line 265 of ultra_fpga_power_ground_nets P43 = MGT_FO_CH_21_OUT_Hub_CMP MGTYRXP1_129 from line 10823 of mgt_fanout_channel_nets P44 = MGT_FO_CH_21_OUT_Hub_DIR MGTYRXN1_129 from line 10824 of mgt_fanout_channel_nets P45 = GROUND GND from line 266 of ultra_fpga_power_ground_nets P46 = GROUND GND from line 267 of ultra_fpga_power_ground_nets R10 = MHz_320.64_COPY_8_CMP MGTREFCLK0N_230 from line 652 of clock_generation_nets R11 = MHz_320.64_COPY_8_DIR MGTREFCLK0P_230 from line 651 of clock_generation_nets R12 = GROUND GND from line 272 of ultra_fpga_power_ground_nets R13 = MGT_AVCC MGTAVCC_RN from line 1205 of ultra_fpga_power_ground_nets R14 = GROUND GND from line 273 of ultra_fpga_power_ground_nets R15 = FPGA_CORE VCCINT from line 829 of ultra_fpga_power_ground_nets R16 = GROUND GND from line 274 of ultra_fpga_power_ground_nets R17 = FPGA_CORE VCCINT from line 830 of ultra_fpga_power_ground_nets R18 = GROUND GND from line 275 of ultra_fpga_power_ground_nets R19 = FPGA_CORE VCCINT from line 831 of ultra_fpga_power_ground_nets R20 = GROUND GND from line 276 of ultra_fpga_power_ground_nets R21 = FPGA_CORE VCCINT from line 832 of ultra_fpga_power_ground_nets R22 = GROUND GND from line 277 of ultra_fpga_power_ground_nets R23 = FPGA_CORE VCCINT from line 833 of ultra_fpga_power_ground_nets R24 = GROUND GND from line 278 of ultra_fpga_power_ground_nets R25 = FPGA_CORE VCCINT from line 834 of ultra_fpga_power_ground_nets R26 = GROUND GND from line 279 of ultra_fpga_power_ground_nets R27 = FPGA_CORE VCCINT from line 835 of ultra_fpga_power_ground_nets R28 = GROUND GND from line 280 of ultra_fpga_power_ground_nets R29 = FPGA_CORE VCCINT from line 836 of ultra_fpga_power_ground_nets R30 = GROUND GND from line 281 of ultra_fpga_power_ground_nets R31 = BULK_1V8 VCCAUX_IO from line 1004 of ultra_fpga_power_ground_nets R32 = GROUND GND from line 282 of ultra_fpga_power_ground_nets R33 = GROUND GND from line 283 of ultra_fpga_power_ground_nets R34 = MGT_AVCC MGTAVCC_LN from line 1167 of ultra_fpga_power_ground_nets R35 = GROUND GND from line 284 of ultra_fpga_power_ground_nets R36 = MHz_320.64_COPY_1_DIR MGTREFCLK0P_130 from line 588 of clock_generation_nets R37 = MHz_320.64_COPY_1_CMP MGTREFCLK0N_130 from line 589 of clock_generation_nets R38 = MGT_AVTT MGTAVTT_LN from line 1267 of ultra_fpga_power_ground_nets R39 = GROUND GND from line 285 of ultra_fpga_power_ground_nets R40 = Comb_Data_to_Cap_to_Other_Hub_Dir MGTYTXP0_129 from line 93 of combined_data_distribution_nets R41 = Comb_Data_to_Cap_to_Other_Hub_Cmp MGTYTXN0_129 from line 94 of combined_data_distribution_nets R42 = GROUND GND from line 286 of ultra_fpga_power_ground_nets R43 = GROUND GND from line 287 of ultra_fpga_power_ground_nets R44 = GROUND GND from line 288 of ultra_fpga_power_ground_nets R45 = MGT_FO_CH_22_OUT_Hub_DIR MGTYRXP0_129 from line 10819 of mgt_fanout_channel_nets R46 = MGT_FO_CH_22_OUT_Hub_CMP MGTYRXN0_129 from line 10820 of mgt_fanout_channel_nets T10 = MGT_AVCC MGTAVCC_RN from line 1206 of ultra_fpga_power_ground_nets T11 = GROUND GND from line 293 of ultra_fpga_power_ground_nets T12 = No_Conn_FPGA_T12 MGTREFCLK1N_229 from line 831 of ultra_no_connect_pins_nets T13 = No_Conn_FPGA_T13 MGTREFCLK1P_229 from line 830 of ultra_no_connect_pins_nets T14 = CONFIG_M2 M2_0 from line 173 of bank_0_and_bank_65_config_mem_nets T15 = GROUND GND from line 294 of ultra_fpga_power_ground_nets T16 = FPGA_CORE VCCINT from line 837 of ultra_fpga_power_ground_nets T17 = GROUND GND from line 295 of ultra_fpga_power_ground_nets T18 = FPGA_CORE VCCINT from line 838 of ultra_fpga_power_ground_nets T19 = GROUND GND from line 296 of ultra_fpga_power_ground_nets T20 = FPGA_CORE VCCINT from line 839 of ultra_fpga_power_ground_nets T21 = GROUND GND from line 297 of ultra_fpga_power_ground_nets T22 = FPGA_CORE VCCINT from line 840 of ultra_fpga_power_ground_nets T23 = GROUND GND from line 298 of ultra_fpga_power_ground_nets T24 = FPGA_CORE VCCINT from line 841 of ultra_fpga_power_ground_nets T25 = GROUND GND from line 299 of ultra_fpga_power_ground_nets T26 = FPGA_CORE VCCINT from line 842 of ultra_fpga_power_ground_nets T27 = GROUND GND from line 300 of ultra_fpga_power_ground_nets T28 = FPGA_CORE VCCINT from line 843 of ultra_fpga_power_ground_nets T29 = GROUND GND from line 301 of ultra_fpga_power_ground_nets T30 = FPGA_CORE VCCINT_IO from line 944 of ultra_fpga_power_ground_nets T31 = GROUND GND from line 302 of ultra_fpga_power_ground_nets T32 = BULK_1V8 VCCAUX from line 983 of ultra_fpga_power_ground_nets T33 = GROUND GND from line 303 of ultra_fpga_power_ground_nets T34 = No_Conn_FPGA_T34 MGTREFCLK1P_129 from line 772 of ultra_no_connect_pins_nets T35 = No_Conn_FPGA_T35 MGTREFCLK1N_129 from line 773 of ultra_no_connect_pins_nets T36 = GROUND GND from line 304 of ultra_fpga_power_ground_nets T37 = MGT_AVCC MGTAVCC_LN from line 1168 of ultra_fpga_power_ground_nets T38 = No_Conn_FPGA_T38 MGTYTXP3_128 from line 488 of ultra_no_connect_pins_nets T39 = No_Conn_FPGA_T39 MGTYTXN3_128 from line 489 of ultra_no_connect_pins_nets T40 = GROUND GND from line 305 of ultra_fpga_power_ground_nets T41 = MGT_AVTT MGTAVTT_LN from line 1268 of ultra_fpga_power_ground_nets T42 = GROUND GND from line 306 of ultra_fpga_power_ground_nets T43 = MGT_FO_CH_23_OUT_Hub_CMP MGTYRXP3_128 from line 10812 of mgt_fanout_channel_nets T44 = MGT_FO_CH_23_OUT_Hub_DIR MGTYRXN3_128 from line 10813 of mgt_fanout_channel_nets T45 = GROUND GND from line 307 of ultra_fpga_power_ground_nets T46 = GROUND GND from line 308 of ultra_fpga_power_ground_nets U10 = No_Conn_FPGA_U10 MGTREFCLK0N_229 from line 834 of ultra_no_connect_pins_nets U11 = No_Conn_FPGA_U11 MGTREFCLK0P_229 from line 833 of ultra_no_connect_pins_nets U12 = MGT_AVCC MGTAVCC_RC from line 1184 of ultra_fpga_power_ground_nets U13 = GROUND GND from line 313 of ultra_fpga_power_ground_nets U14 = GROUND GND from line 314 of ultra_fpga_power_ground_nets U15 = FPGA_CORE VCCINT from line 844 of ultra_fpga_power_ground_nets U16 = GROUND GND from line 315 of ultra_fpga_power_ground_nets U17 = FPGA_CORE VCCINT from line 845 of ultra_fpga_power_ground_nets U18 = GROUND GND from line 316 of ultra_fpga_power_ground_nets U19 = FPGA_CORE VCCINT from line 846 of ultra_fpga_power_ground_nets U20 = GROUND GND from line 317 of ultra_fpga_power_ground_nets U21 = FPGA_CORE VCCINT from line 847 of ultra_fpga_power_ground_nets U22 = GROUND GND from line 318 of ultra_fpga_power_ground_nets U23 = FPGA_CORE VCCINT from line 848 of ultra_fpga_power_ground_nets U24 = GROUND GND from line 319 of ultra_fpga_power_ground_nets U25 = FPGA_CORE VCCINT from line 849 of ultra_fpga_power_ground_nets U26 = GROUND GND from line 320 of ultra_fpga_power_ground_nets U27 = FPGA_CORE VCCINT from line 850 of ultra_fpga_power_ground_nets U28 = GROUND GND from line 321 of ultra_fpga_power_ground_nets U29 = FPGA_CORE VCCINT from line 851 of ultra_fpga_power_ground_nets U30 = GROUND GND from line 322 of ultra_fpga_power_ground_nets U31 = BULK_1V8 VCCAUX_IO from line 1005 of ultra_fpga_power_ground_nets U32 = GROUND GND from line 323 of ultra_fpga_power_ground_nets U33 = GROUND GND from line 324 of ultra_fpga_power_ground_nets U34 = GROUND GND from line 325 of ultra_fpga_power_ground_nets U35 = MGT_AVCC MGTAVCC_LC from line 1146 of ultra_fpga_power_ground_nets U36 = No_Conn_FPGA_U36 MGTREFCLK0P_129 from line 775 of ultra_no_connect_pins_nets U37 = No_Conn_FPGA_U37 MGTREFCLK0N_129 from line 776 of ultra_no_connect_pins_nets U38 = GROUND GND from line 326 of ultra_fpga_power_ground_nets U39 = MGT_AVTT MGTAVTT_LC from line 1230 of ultra_fpga_power_ground_nets U40 = No_Conn_FPGA_U40 MGTYTXP2_128 from line 491 of ultra_no_connect_pins_nets U41 = No_Conn_FPGA_U41 MGTYTXN2_128 from line 492 of ultra_no_connect_pins_nets U42 = GROUND GND from line 327 of ultra_fpga_power_ground_nets U43 = GROUND GND from line 328 of ultra_fpga_power_ground_nets U44 = GROUND GND from line 329 of ultra_fpga_power_ground_nets U45 = MGT_FO_CH_24_OUT_Hub_DIR MGTYRXP2_128 from line 10808 of mgt_fanout_channel_nets U46 = MGT_FO_CH_24_OUT_Hub_CMP MGTYRXN2_128 from line 10809 of mgt_fanout_channel_nets V10 = GROUND GND from line 334 of ultra_fpga_power_ground_nets V11 = MGT_AVCC MGTAVCC_RC from line 1185 of ultra_fpga_power_ground_nets V12 = No_Conn_FPGA_V12 MGTREFCLK1N_228 from line 824 of ultra_no_connect_pins_nets V13 = No_Conn_FPGA_V13 MGTREFCLK1P_228 from line 823 of ultra_no_connect_pins_nets V14 = CONFIG_M1 M1_0 from line 172 of bank_0_and_bank_65_config_mem_nets V15 = GROUND GND from line 335 of ultra_fpga_power_ground_nets V16 = FPGA_CORE VCCBRAM from line 963 of ultra_fpga_power_ground_nets V17 = GROUND GND from line 336 of ultra_fpga_power_ground_nets V18 = FPGA_CORE VCCINT from line 852 of ultra_fpga_power_ground_nets V19 = GROUND GND from line 337 of ultra_fpga_power_ground_nets V20 = FPGA_CORE VCCINT from line 853 of ultra_fpga_power_ground_nets V21 = GROUND GND from line 338 of ultra_fpga_power_ground_nets V22 = FPGA_CORE VCCINT from line 854 of ultra_fpga_power_ground_nets V23 = GROUND GND from line 339 of ultra_fpga_power_ground_nets V24 = FPGA_CORE VCCINT from line 855 of ultra_fpga_power_ground_nets V25 = GROUND GND from line 340 of ultra_fpga_power_ground_nets V26 = FPGA_CORE VCCINT from line 856 of ultra_fpga_power_ground_nets V27 = GROUND GND from line 341 of ultra_fpga_power_ground_nets V28 = FPGA_CORE VCCINT from line 857 of ultra_fpga_power_ground_nets V29 = GROUND GND from line 342 of ultra_fpga_power_ground_nets V30 = FPGA_CORE VCCINT_IO from line 945 of ultra_fpga_power_ground_nets V31 = GROUND GND from line 343 of ultra_fpga_power_ground_nets V32 = BULK_1V8 VCCAUX from line 984 of ultra_fpga_power_ground_nets V33 = GROUND GND from line 344 of ultra_fpga_power_ground_nets V34 = No_Conn_FPGA_V34 MGTREFCLK1P_128 from line 765 of ultra_no_connect_pins_nets V35 = No_Conn_FPGA_V35 MGTREFCLK1N_128 from line 766 of ultra_no_connect_pins_nets V36 = MGT_AVCC MGTAVCC_LC from line 1147 of ultra_fpga_power_ground_nets V37 = GROUND GND from line 345 of ultra_fpga_power_ground_nets V38 = No_Conn_FPGA_V38 MGTYTXP1_128 from line 494 of ultra_no_connect_pins_nets V39 = No_Conn_FPGA_V39 MGTYTXN1_128 from line 495 of ultra_no_connect_pins_nets V40 = MGT_AVTT MGTAVTT_LC from line 1231 of ultra_fpga_power_ground_nets V41 = GROUND GND from line 346 of ultra_fpga_power_ground_nets V42 = GROUND GND from line 347 of ultra_fpga_power_ground_nets V43 = MGT_FO_CH_9_OUT_Hub_CMP MGTYRXP1_128 from line 10804 of mgt_fanout_channel_nets V44 = MGT_FO_CH_9_OUT_Hub_DIR MGTYRXN1_128 from line 10805 of mgt_fanout_channel_nets V45 = GROUND GND from line 348 of ultra_fpga_power_ground_nets V46 = GROUND GND from line 349 of ultra_fpga_power_ground_nets W10 = No_Conn_FPGA_W10 MGTREFCLK0N_228 from line 827 of ultra_no_connect_pins_nets W11 = No_Conn_FPGA_W11 MGTREFCLK0P_228 from line 826 of ultra_no_connect_pins_nets W12 = GROUND GND from line 354 of ultra_fpga_power_ground_nets W13 = MGT_AVCC MGTAVCC_RC from line 1187 of ultra_fpga_power_ground_nets W14 = GROUND GND from line 355 of ultra_fpga_power_ground_nets W15 = FPGA_CORE VCCBRAM from line 964 of ultra_fpga_power_ground_nets W16 = GROUND GND from line 356 of ultra_fpga_power_ground_nets W17 = FPGA_CORE VCCBRAM from line 965 of ultra_fpga_power_ground_nets W18 = GROUND GND from line 357 of ultra_fpga_power_ground_nets W19 = FPGA_CORE VCCINT from line 858 of ultra_fpga_power_ground_nets W20 = GROUND GND from line 358 of ultra_fpga_power_ground_nets W21 = FPGA_CORE VCCINT from line 859 of ultra_fpga_power_ground_nets W22 = GROUND GND from line 359 of ultra_fpga_power_ground_nets W23 = FPGA_CORE VCCINT from line 860 of ultra_fpga_power_ground_nets W24 = GROUND GND from line 360 of ultra_fpga_power_ground_nets W25 = FPGA_CORE VCCINT from line 861 of ultra_fpga_power_ground_nets W26 = GROUND GND from line 361 of ultra_fpga_power_ground_nets W27 = FPGA_CORE VCCINT from line 862 of ultra_fpga_power_ground_nets W28 = GROUND GND from line 362 of ultra_fpga_power_ground_nets W29 = FPGA_CORE VCCINT from line 863 of ultra_fpga_power_ground_nets W30 = GROUND GND from line 363 of ultra_fpga_power_ground_nets W31 = BULK_1V8 VCCAUX_IO from line 1006 of ultra_fpga_power_ground_nets W32 = GROUND GND from line 364 of ultra_fpga_power_ground_nets W33 = GROUND GND from line 365 of ultra_fpga_power_ground_nets W34 = MGT_AVCC MGTAVCC_LC from line 1148 of ultra_fpga_power_ground_nets W35 = GROUND GND from line 366 of ultra_fpga_power_ground_nets W36 = No_Conn_FPGA_W36 MGTREFCLK0P_128 from line 768 of ultra_no_connect_pins_nets W37 = No_Conn_FPGA_W37 MGTREFCLK0N_128 from line 769 of ultra_no_connect_pins_nets W38 = MGT_AVCC MGTAVCC_LC from line 1149 of ultra_fpga_power_ground_nets W39 = GROUND GND from line 367 of ultra_fpga_power_ground_nets W40 = No_Conn_FPGA_W40 MGTYTXP0_128 from line 497 of ultra_no_connect_pins_nets W41 = No_Conn_FPGA_W41 MGTYTXN0_128 from line 498 of ultra_no_connect_pins_nets W42 = GROUND GND from line 368 of ultra_fpga_power_ground_nets W43 = GROUND GND from line 369 of ultra_fpga_power_ground_nets W44 = GROUND GND from line 370 of ultra_fpga_power_ground_nets W45 = MGT_FO_CH_10_OUT_Hub_DIR MGTYRXP0_128 from line 10800 of mgt_fanout_channel_nets W46 = MGT_FO_CH_10_OUT_Hub_CMP MGTYRXN0_128 from line 10801 of mgt_fanout_channel_nets Y10 = MGT_AVAUX MGTVCCAUX_RC from line 1379 of ultra_fpga_power_ground_nets Y11 = GROUND GND from line 375 of ultra_fpga_power_ground_nets Y12 = MHz_320.64_COPY_6_CMP MGTREFCLK1N_227 from line 634 of clock_generation_nets Y13 = MHz_320.64_COPY_6_DIR MGTREFCLK1P_227 from line 633 of clock_generation_nets Y14 = CONFIG_M0 M0_0 from line 171 of bank_0_and_bank_65_config_mem_nets Y15 = GROUND GND from line 376 of ultra_fpga_power_ground_nets Y16 = FPGA_CORE VCCBRAM from line 966 of ultra_fpga_power_ground_nets Y17 = GROUND GND from line 377 of ultra_fpga_power_ground_nets Y18 = FPGA_CORE VCCINT from line 864 of ultra_fpga_power_ground_nets Y19 = GROUND GND from line 378 of ultra_fpga_power_ground_nets Y20 = FPGA_CORE VCCINT from line 865 of ultra_fpga_power_ground_nets Y21 = GROUND GND from line 379 of ultra_fpga_power_ground_nets Y22 = FPGA_CORE VCCINT from line 866 of ultra_fpga_power_ground_nets Y23 = GROUND GND from line 380 of ultra_fpga_power_ground_nets Y24 = FPGA_CORE VCCINT from line 867 of ultra_fpga_power_ground_nets Y25 = GROUND GND from line 381 of ultra_fpga_power_ground_nets Y26 = FPGA_CORE VCCINT from line 868 of ultra_fpga_power_ground_nets Y27 = GROUND GND from line 382 of ultra_fpga_power_ground_nets Y28 = FPGA_CORE VCCINT from line 869 of ultra_fpga_power_ground_nets Y29 = GROUND GND from line 383 of ultra_fpga_power_ground_nets Y30 = BULK_1V8 VCCAUX_IO from line 1007 of ultra_fpga_power_ground_nets Y31 = GROUND GND from line 384 of ultra_fpga_power_ground_nets Y32 = BULK_1V8 VCCAUX from line 985 of ultra_fpga_power_ground_nets Y33 = GROUND GND from line 385 of ultra_fpga_power_ground_nets Y34 = MHz_320.64_COPY_3_DIR MGTREFCLK1P_127 from line 606 of clock_generation_nets Y35 = MHz_320.64_COPY_3_CMP MGTREFCLK1N_127 from line 607 of clock_generation_nets Y36 = GROUND GND from line 386 of ultra_fpga_power_ground_nets Y37 = MGT_AVAUX MGTVCCAUX_LC from line 1358 of ultra_fpga_power_ground_nets Y38 = No_Conn_FPGA_Y38 MGTYTXP3_127 from line 474 of ultra_no_connect_pins_nets Y39 = No_Conn_FPGA_Y39 MGTYTXN3_127 from line 475 of ultra_no_connect_pins_nets Y40 = GROUND GND from line 387 of ultra_fpga_power_ground_nets Y41 = MGT_AVTT MGTAVTT_LC from line 1232 of ultra_fpga_power_ground_nets Y42 = GROUND GND from line 388 of ultra_fpga_power_ground_nets Y43 = MGT_FO_CH_11_OUT_Hub_CMP MGTYRXP3_127 from line 10794 of mgt_fanout_channel_nets Y44 = MGT_FO_CH_11_OUT_Hub_DIR MGTYRXN3_127 from line 10795 of mgt_fanout_channel_nets Y45 = GROUND GND from line 389 of ultra_fpga_power_ground_nets Y46 = GROUND GND from line 390 of ultra_fpga_power_ground_nets AA10 = No_Conn_FPGA_AA10 MGTREFCLK0N_227 from line 820 of ultra_no_connect_pins_nets AA11 = No_Conn_FPGA_AA11 MGTREFCLK0P_227 from line 819 of ultra_no_connect_pins_nets AA12 = MGT_AVCC MGTAVCC_RC from line 1188 of ultra_fpga_power_ground_nets AA13 = GROUND GND from line 395 of ultra_fpga_power_ground_nets AA14 = GROUND GND from line 396 of ultra_fpga_power_ground_nets AA15 = GROUND GND from line 397 of ultra_fpga_power_ground_nets AA16 = GROUND GND from line 398 of ultra_fpga_power_ground_nets AA17 = FPGA_CORE VCCBRAM from line 967 of ultra_fpga_power_ground_nets AA18 = GROUND GND from line 399 of ultra_fpga_power_ground_nets AA19 = FPGA_CORE VCCINT from line 870 of ultra_fpga_power_ground_nets AA20 = GROUND GND from line 400 of ultra_fpga_power_ground_nets AA21 = FPGA_CORE VCCINT from line 871 of ultra_fpga_power_ground_nets AA22 = GROUND GND from line 401 of ultra_fpga_power_ground_nets AA23 = FPGA_CORE VCCINT from line 872 of ultra_fpga_power_ground_nets AA24 = GROUND GND from line 402 of ultra_fpga_power_ground_nets AA25 = FPGA_CORE VCCINT from line 873 of ultra_fpga_power_ground_nets AA26 = GROUND GND from line 403 of ultra_fpga_power_ground_nets AA27 = FPGA_CORE VCCINT from line 874 of ultra_fpga_power_ground_nets AA28 = GROUND GND from line 404 of ultra_fpga_power_ground_nets AA29 = FPGA_CORE VCCINT_IO from line 946 of ultra_fpga_power_ground_nets AA30 = GROUND GND from line 405 of ultra_fpga_power_ground_nets AA31 = BULK_1V8 VCCAUX_IO from line 1008 of ultra_fpga_power_ground_nets AA32 = GROUND GND from line 406 of ultra_fpga_power_ground_nets AA33 = GROUND GND from line 407 of ultra_fpga_power_ground_nets AA34 = GROUND GND from line 408 of ultra_fpga_power_ground_nets AA35 = MGT_AVCC MGTAVCC_LC from line 1150 of ultra_fpga_power_ground_nets AA36 = No_Conn_FPGA_AA36 MGTREFCLK0P_127 from line 761 of ultra_no_connect_pins_nets AA37 = No_Conn_FPGA_AA37 MGTREFCLK0N_127 from line 762 of ultra_no_connect_pins_nets AA38 = GROUND GND from line 409 of ultra_fpga_power_ground_nets AA39 = MGT_AVTT MGTAVTT_LC from line 1233 of ultra_fpga_power_ground_nets AA40 = This_Hubs_RO_0_to_Cap_Other_ROD_Dir MGTYTXP2_127 from line 303 of hub_all_other_mgt_nets AA41 = This_Hubs_RO_0_to_Cap_Other_ROD_Cmp MGTYTXN2_127 from line 304 of hub_all_other_mgt_nets AA42 = GROUND GND from line 410 of ultra_fpga_power_ground_nets AA43 = GROUND GND from line 411 of ultra_fpga_power_ground_nets AA44 = GROUND GND from line 412 of ultra_fpga_power_ground_nets AA45 = MGT_FO_CH_12_OUT_Hub_DIR MGTYRXP2_127 from line 10790 of mgt_fanout_channel_nets AA46 = MGT_FO_CH_12_OUT_Hub_CMP MGTYRXN2_127 from line 10791 of mgt_fanout_channel_nets AB10 = GROUND GND from line 417 of ultra_fpga_power_ground_nets AB11 = MGT_AVAUX MGTVCCAUX_RC from line 1380 of ultra_fpga_power_ground_nets AB12 = No_Conn_FPGA_AB12 MGTREFCLK1N_226 from line 813 of ultra_no_connect_pins_nets AB13 = No_Conn_FPGA_AB13 MGTREFCLK1P_226 from line 812 of ultra_no_connect_pins_nets AB14 = POR_OVERRIDE POR_OVERRIDE from line 180 of bank_0_and_bank_65_config_mem_nets AB15 = TMS_TO_HUB_FPGA TMS_0 from line 165 of jtag_and_associated_nets AB16 = NO_CONN_FPGA_BANK_0_CCLK CCLK_0 from line 211 of bank_0_and_bank_65_config_mem_nets AB17 = GROUND GND from line 418 of ultra_fpga_power_ground_nets AB18 = FPGA_CORE VCCINT from line 875 of ultra_fpga_power_ground_nets AB19 = SYSMON_GND GNDADC from line 77 of power_supply_all_other_nets AB20 = SYSMON_1V8 VCCADC from line 75 of power_supply_all_other_nets AB21 = GROUND GND from line 419 of ultra_fpga_power_ground_nets AB22 = FPGA_CORE VCCINT from line 876 of ultra_fpga_power_ground_nets AB23 = GROUND GND from line 420 of ultra_fpga_power_ground_nets AB24 = FPGA_CORE VCCINT from line 877 of ultra_fpga_power_ground_nets AB25 = GROUND GND from line 421 of ultra_fpga_power_ground_nets AB26 = FPGA_CORE VCCINT from line 878 of ultra_fpga_power_ground_nets AB27 = GROUND GND from line 422 of ultra_fpga_power_ground_nets AB28 = FPGA_CORE VCCINT from line 879 of ultra_fpga_power_ground_nets AB29 = GROUND GND from line 423 of ultra_fpga_power_ground_nets AB30 = BULK_1V8 VCCAUX_IO from line 1009 of ultra_fpga_power_ground_nets AB31 = GROUND GND from line 424 of ultra_fpga_power_ground_nets AB32 = BULK_1V8 VCCAUX from line 986 of ultra_fpga_power_ground_nets AB33 = GROUND GND from line 425 of ultra_fpga_power_ground_nets AB34 = No_Conn_FPGA_AB34 MGTREFCLK1P_126 from line 754 of ultra_no_connect_pins_nets AB35 = No_Conn_FPGA_AB35 MGTREFCLK1N_126 from line 755 of ultra_no_connect_pins_nets AB36 = MGT_AVAUX MGTVCCAUX_LC from line 1359 of ultra_fpga_power_ground_nets AB37 = GROUND GND from line 426 of ultra_fpga_power_ground_nets AB38 = No_Conn_FPGA_AB38 MGTYTXP1_127 from line 477 of ultra_no_connect_pins_nets AB39 = No_Conn_FPGA_AB39 MGTYTXN1_127 from line 478 of ultra_no_connect_pins_nets AB40 = MGT_AVTT MGTAVTT_LC from line 1234 of ultra_fpga_power_ground_nets AB41 = GROUND GND from line 427 of ultra_fpga_power_ground_nets AB42 = GROUND GND from line 428 of ultra_fpga_power_ground_nets AB43 = MGT_FO_CH_13_OUT_Hub_CMP MGTYRXP1_127 from line 10786 of mgt_fanout_channel_nets AB44 = MGT_FO_CH_13_OUT_Hub_DIR MGTYRXN1_127 from line 10787 of mgt_fanout_channel_nets AB45 = GROUND GND from line 429 of ultra_fpga_power_ground_nets AB46 = GROUND GND from line 430 of ultra_fpga_power_ground_nets AC10 = No_Conn_FPGA_AC10 MGTREFCLK0N_226 from line 816 of ultra_no_connect_pins_nets AC11 = No_Conn_FPGA_AC11 MGTREFCLK0P_226 from line 815 of ultra_no_connect_pins_nets AC12 = GROUND GND from line 435 of ultra_fpga_power_ground_nets AC13 = MGT_AVCC MGTAVCC_RC from line 1189 of ultra_fpga_power_ground_nets AC14 = FPGA_Config_DONE DONE_0 from line 165 of bank_0_and_bank_65_config_mem_nets AC15 = BULK_1V8 VCCO_0 from line 1032 of ultra_fpga_power_ground_nets AC16 = GROUND GND from line 436 of ultra_fpga_power_ground_nets AC17 = FPGA_CORE VCCBRAM from line 968 of ultra_fpga_power_ground_nets AC18 = GROUND GND from line 437 of ultra_fpga_power_ground_nets AC19 = SYSMON_GND VREFN from line 77 of power_supply_all_other_nets AC20 = SysMon_Main_Input_VP VP from line 82 of power_supply_all_other_nets AC21 = FPGA_CORE VCCINT from line 880 of ultra_fpga_power_ground_nets AC22 = GROUND GND from line 438 of ultra_fpga_power_ground_nets AC23 = FPGA_CORE VCCINT from line 881 of ultra_fpga_power_ground_nets AC24 = GROUND GND from line 439 of ultra_fpga_power_ground_nets AC25 = FPGA_CORE VCCINT from line 882 of ultra_fpga_power_ground_nets AC26 = GROUND GND from line 440 of ultra_fpga_power_ground_nets AC27 = FPGA_CORE VCCINT from line 883 of ultra_fpga_power_ground_nets AC28 = GROUND GND from line 441 of ultra_fpga_power_ground_nets AC29 = FPGA_CORE VCCINT_IO from line 947 of ultra_fpga_power_ground_nets AC30 = GROUND GND from line 442 of ultra_fpga_power_ground_nets AC31 = BULK_1V8 VCCAUX from line 987 of ultra_fpga_power_ground_nets AC32 = GROUND GND from line 443 of ultra_fpga_power_ground_nets AC33 = GROUND GND from line 444 of ultra_fpga_power_ground_nets AC34 = MGT_AVCC MGTAVCC_LC from line 1151 of ultra_fpga_power_ground_nets AC35 = GROUND GND from line 445 of ultra_fpga_power_ground_nets AC36 = No_Conn_FPGA_AC36 MGTREFCLK0P_126 from line 757 of ultra_no_connect_pins_nets AC37 = No_Conn_FPGA_AC37 MGTREFCLK0N_126 from line 758 of ultra_no_connect_pins_nets AC38 = MGT_AVTT MGTAVTT_LC from line 1235 of ultra_fpga_power_ground_nets AC39 = GROUND GND from line 446 of ultra_fpga_power_ground_nets AC40 = This_Hubs_RO_1_to_Cap_Other_ROD_Cmp MGTYTXP0_127 from line 316 of hub_all_other_mgt_nets AC41 = This_Hubs_RO_1_to_Cap_Other_ROD_Dir MGTYTXN0_127 from line 315 of hub_all_other_mgt_nets AC42 = GROUND GND from line 447 of ultra_fpga_power_ground_nets AC43 = GROUND GND from line 448 of ultra_fpga_power_ground_nets AC44 = GROUND GND from line 449 of ultra_fpga_power_ground_nets AC45 = MGT_FO_CH_14_OUT_Hub_DIR MGTYRXP0_127 from line 10782 of mgt_fanout_channel_nets AC46 = MGT_FO_CH_14_OUT_Hub_CMP MGTYRXN0_127 from line 10783 of mgt_fanout_channel_nets AD10 = MGT_AVCC MGTAVCC_RC from line 1190 of ultra_fpga_power_ground_nets AD11 = GROUND GND from line 454 of ultra_fpga_power_ground_nets AD12 = No_Conn_FPGA_AD12 MGTREFCLK1N_225 from line 809 of ultra_no_connect_pins_nets AD13 = No_Conn_FPGA_AD13 MGTREFCLK1P_225 from line 808 of ultra_no_connect_pins_nets AD14 = GROUND GND from line 455 of ultra_fpga_power_ground_nets AD15 = TD_HUB_FPGA_TO_JMP1 TDO_0 from line 201 of jtag_and_associated_nets AD16 = TCK_TO_HUB_FPGA TCK_0 from line 170 of jtag_and_associated_nets AD17 = GROUND GND from line 456 of ultra_fpga_power_ground_nets AD18 = FPGA_CORE VCCINT from line 884 of ultra_fpga_power_ground_nets AD19 = SysMon_Main_Input_VN VN from line 83 of power_supply_all_other_nets AD20 = SYSMON_VREFP VREFP from line 79 of power_supply_all_other_nets AD21 = GROUND GND from line 457 of ultra_fpga_power_ground_nets AD22 = FPGA_CORE VCCINT from line 885 of ultra_fpga_power_ground_nets AD23 = GROUND GND from line 458 of ultra_fpga_power_ground_nets AD24 = FPGA_CORE VCCINT from line 886 of ultra_fpga_power_ground_nets AD25 = GROUND GND from line 459 of ultra_fpga_power_ground_nets AD26 = FPGA_CORE VCCINT from line 887 of ultra_fpga_power_ground_nets AD27 = GROUND GND from line 460 of ultra_fpga_power_ground_nets AD28 = FPGA_CORE VCCINT from line 888 of ultra_fpga_power_ground_nets AD29 = GROUND GND from line 461 of ultra_fpga_power_ground_nets AD30 = BULK_1V8 VCCAUX_IO from line 1010 of ultra_fpga_power_ground_nets AD31 = GROUND GND from line 462 of ultra_fpga_power_ground_nets AD32 = BULK_1V8 VCCAUX from line 988 of ultra_fpga_power_ground_nets AD33 = GROUND GND from line 463 of ultra_fpga_power_ground_nets AD34 = No_Conn_FPGA_AD34 MGTREFCLK1P_125 from line 750 of ultra_no_connect_pins_nets AD35 = No_Conn_FPGA_AD35 MGTREFCLK1N_125 from line 751 of ultra_no_connect_pins_nets AD36 = GROUND GND from line 464 of ultra_fpga_power_ground_nets AD37 = MGT_AVCC MGTAVCC_LC from line 1152 of ultra_fpga_power_ground_nets AD38 = No_Conn_FPGA_AD38 MGTYTXP3_126 from line 454 of ultra_no_connect_pins_nets AD39 = No_Conn_FPGA_AD39 MGTYTXN3_126 from line 455 of ultra_no_connect_pins_nets AD40 = GROUND GND from line 465 of ultra_fpga_power_ground_nets AD41 = MGT_AVTT MGTAVTT_LC from line 1236 of ultra_fpga_power_ground_nets AD42 = GROUND GND from line 466 of ultra_fpga_power_ground_nets AD43 = MGT_FO_CH_15_OUT_Hub_CMP MGTYRXP3_126 from line 10776 of mgt_fanout_channel_nets AD44 = MGT_FO_CH_15_OUT_Hub_DIR MGTYRXN3_126 from line 10777 of mgt_fanout_channel_nets AD45 = GROUND GND from line 467 of ultra_fpga_power_ground_nets AD46 = GROUND GND from line 468 of ultra_fpga_power_ground_nets AE10 = MHz_320.64_COPY_9_CMP MGTREFCLK0N_225 from line 661 of clock_generation_nets AE11 = MHz_320.64_COPY_9_DIR MGTREFCLK0P_225 from line 660 of clock_generation_nets AE12 = MGT_AVCC MGTAVCC_RC from line 1191 of ultra_fpga_power_ground_nets AE13 = GROUND GND from line 473 of ultra_fpga_power_ground_nets AE14 = PROGRAM_B PROGRAM_B_0 from line 159 of bank_0_and_bank_65_config_mem_nets AE15 = BULK_1V8 VCCO_0 from line 1033 of ultra_fpga_power_ground_nets AE16 = GROUND GND from line 474 of ultra_fpga_power_ground_nets AE17 = FPGA_CORE VCCBRAM from line 969 of ultra_fpga_power_ground_nets AE18 = GROUND GND from line 475 of ultra_fpga_power_ground_nets AE19 = Temp_Diode_DXN DXN from line 86 of power_supply_all_other_nets AE20 = Temp_Diode_DXP DXP from line 87 of power_supply_all_other_nets AE21 = FPGA_CORE VCCINT from line 889 of ultra_fpga_power_ground_nets AE22 = GROUND GND from line 476 of ultra_fpga_power_ground_nets AE23 = FPGA_CORE VCCINT from line 890 of ultra_fpga_power_ground_nets AE24 = GROUND GND from line 477 of ultra_fpga_power_ground_nets AE25 = FPGA_CORE VCCINT from line 891 of ultra_fpga_power_ground_nets AE26 = GROUND GND from line 478 of ultra_fpga_power_ground_nets AE27 = FPGA_CORE VCCINT from line 892 of ultra_fpga_power_ground_nets AE28 = GROUND GND from line 479 of ultra_fpga_power_ground_nets AE29 = FPGA_CORE VCCINT_IO from line 948 of ultra_fpga_power_ground_nets AE30 = GROUND GND from line 480 of ultra_fpga_power_ground_nets AE31 = BULK_1V8 VCCAUX from line 989 of ultra_fpga_power_ground_nets AE32 = GROUND GND from line 481 of ultra_fpga_power_ground_nets AE33 = GROUND GND from line 482 of ultra_fpga_power_ground_nets AE34 = GROUND GND from line 483 of ultra_fpga_power_ground_nets AE35 = MGT_AVCC MGTAVCC_LC from line 1153 of ultra_fpga_power_ground_nets AE36 = MHz_320.64_COPY_0_DIR MGTREFCLK0P_125 from line 579 of clock_generation_nets AE37 = MHz_320.64_COPY_0_CMP MGTREFCLK0N_125 from line 580 of clock_generation_nets AE38 = GROUND GND from line 484 of ultra_fpga_power_ground_nets AE39 = MGT_AVTT MGTAVTT_LC from line 1237 of ultra_fpga_power_ground_nets AE40 = No_Conn_FPGA_AE40 MGTYTXP2_126 from line 457 of ultra_no_connect_pins_nets AE41 = No_Conn_FPGA_AE41 MGTYTXN2_126 from line 458 of ultra_no_connect_pins_nets AE42 = GROUND GND from line 485 of ultra_fpga_power_ground_nets AE43 = GROUND GND from line 486 of ultra_fpga_power_ground_nets AE44 = GROUND GND from line 487 of ultra_fpga_power_ground_nets AE45 = MGT_FO_CH_16_OUT_Hub_DIR MGTYRXP2_126 from line 10772 of mgt_fanout_channel_nets AE46 = MGT_FO_CH_16_OUT_Hub_CMP MGTYRXN2_126 from line 10773 of mgt_fanout_channel_nets AF10 = GROUND GND from line 492 of ultra_fpga_power_ground_nets AF11 = MGT_AVCC MGTAVCC_RC from line 1192 of ultra_fpga_power_ground_nets AF12 = No_Conn_FPGA_AF12 MGTREFCLK1N_224 from line 802 of ultra_no_connect_pins_nets AF13 = No_Conn_FPGA_AF13 MGTREFCLK1P_224 from line 801 of ultra_no_connect_pins_nets AF14 = FLASH_CHIP_ENB_B RDWR_FCS_B_0 from line 128 of bank_0_and_bank_65_config_mem_nets AF15 = TDI_SERIES_TO_HUB_FPGA TDI_0 from line 199 of jtag_and_associated_nets AF16 = FLASH_D02 D02_0 from line 58 of bank_0_and_bank_65_config_mem_nets AF17 = GROUND GND from line 493 of ultra_fpga_power_ground_nets AF18 = FPGA_CORE VCCINT from line 893 of ultra_fpga_power_ground_nets AF19 = GROUND GND from line 494 of ultra_fpga_power_ground_nets AF20 = FPGA_CORE VCCINT from line 894 of ultra_fpga_power_ground_nets AF21 = GROUND GND from line 495 of ultra_fpga_power_ground_nets AF22 = FPGA_CORE VCCINT from line 895 of ultra_fpga_power_ground_nets AF23 = GROUND GND from line 496 of ultra_fpga_power_ground_nets AF24 = FPGA_CORE VCCINT from line 896 of ultra_fpga_power_ground_nets AF25 = GROUND GND from line 497 of ultra_fpga_power_ground_nets AF26 = FPGA_CORE VCCINT from line 897 of ultra_fpga_power_ground_nets AF27 = GROUND GND from line 498 of ultra_fpga_power_ground_nets AF28 = FPGA_CORE VCCINT from line 898 of ultra_fpga_power_ground_nets AF29 = GROUND GND from line 499 of ultra_fpga_power_ground_nets AF30 = BULK_1V8 VCCAUX_IO from line 1011 of ultra_fpga_power_ground_nets AF31 = GROUND GND from line 500 of ultra_fpga_power_ground_nets AF32 = BULK_1V8 VCCAUX from line 990 of ultra_fpga_power_ground_nets AF33 = GROUND GND from line 501 of ultra_fpga_power_ground_nets AF34 = No_Conn_FPGA_AF34 MGTREFCLK1P_124 from line 743 of ultra_no_connect_pins_nets AF35 = No_Conn_FPGA_AF35 MGTREFCLK1N_124 from line 744 of ultra_no_connect_pins_nets AF36 = MGT_AVCC MGTAVCC_LC from line 1154 of ultra_fpga_power_ground_nets AF37 = GROUND GND from line 502 of ultra_fpga_power_ground_nets AF38 = No_Conn_FPGA_AF38 MGTYTXP1_126 from line 460 of ultra_no_connect_pins_nets AF39 = No_Conn_FPGA_AF39 MGTYTXN1_126 from line 461 of ultra_no_connect_pins_nets AF40 = MGT_AVTT MGTAVTT_LC from line 1238 of ultra_fpga_power_ground_nets AF41 = GROUND GND from line 503 of ultra_fpga_power_ground_nets AF42 = GROUND GND from line 504 of ultra_fpga_power_ground_nets AF43 = MGT_FO_CH_1_OUT_Hub_CMP MGTYRXP1_126 from line 10768 of mgt_fanout_channel_nets AF44 = MGT_FO_CH_1_OUT_Hub_DIR MGTYRXN1_126 from line 10769 of mgt_fanout_channel_nets AF45 = GROUND GND from line 505 of ultra_fpga_power_ground_nets AF46 = GROUND GND from line 506 of ultra_fpga_power_ground_nets AG10 = No_Conn_FPGA_AG10 MGTREFCLK0N_224 from line 805 of ultra_no_connect_pins_nets AG11 = No_Conn_FPGA_AG11 MGTREFCLK0P_224 from line 804 of ultra_no_connect_pins_nets AG12 = GROUND GND from line 511 of ultra_fpga_power_ground_nets AG13 = MGT_AVCC MGTAVCC_RS from line 1212 of ultra_fpga_power_ground_nets AG14 = GROUND GND from line 512 of ultra_fpga_power_ground_nets AG15 = GROUND GND from line 513 of ultra_fpga_power_ground_nets AG16 = GROUND GND from line 514 of ultra_fpga_power_ground_nets AG17 = FPGA_CORE VCCBRAM from line 970 of ultra_fpga_power_ground_nets AG18 = GROUND GND from line 515 of ultra_fpga_power_ground_nets AG19 = FPGA_CORE VCCINT from line 899 of ultra_fpga_power_ground_nets AG20 = GROUND GND from line 516 of ultra_fpga_power_ground_nets AG21 = FPGA_CORE VCCINT from line 900 of ultra_fpga_power_ground_nets AG22 = GROUND GND from line 517 of ultra_fpga_power_ground_nets AG23 = FPGA_CORE VCCINT from line 901 of ultra_fpga_power_ground_nets AG24 = GROUND GND from line 518 of ultra_fpga_power_ground_nets AG25 = FPGA_CORE VCCINT from line 902 of ultra_fpga_power_ground_nets AG26 = GROUND GND from line 519 of ultra_fpga_power_ground_nets AG27 = FPGA_CORE VCCINT from line 903 of ultra_fpga_power_ground_nets AG28 = GROUND GND from line 520 of ultra_fpga_power_ground_nets AG29 = FPGA_CORE VCCINT_IO from line 949 of ultra_fpga_power_ground_nets AG30 = GROUND GND from line 521 of ultra_fpga_power_ground_nets AG31 = BULK_1V8 VCCAUX_IO from line 1012 of ultra_fpga_power_ground_nets AG32 = GROUND GND from line 522 of ultra_fpga_power_ground_nets AG33 = GROUND GND from line 523 of ultra_fpga_power_ground_nets AG34 = MGT_AVCC MGTAVCC_LS from line 1174 of ultra_fpga_power_ground_nets AG35 = GROUND GND from line 524 of ultra_fpga_power_ground_nets AG36 = No_Conn_FPGA_AG36 MGTREFCLK0P_124 from line 746 of ultra_no_connect_pins_nets AG37 = No_Conn_FPGA_AG37 MGTREFCLK0N_124 from line 747 of ultra_no_connect_pins_nets AG38 = MGT_AVTT MGTAVTT_LC from line 1239 of ultra_fpga_power_ground_nets AG39 = GROUND GND from line 525 of ultra_fpga_power_ground_nets AG40 = No_Conn_FPGA_AG40 MGTYTXP0_126 from line 463 of ultra_no_connect_pins_nets AG41 = No_Conn_FPGA_AG41 MGTYTXN0_126 from line 464 of ultra_no_connect_pins_nets AG42 = GROUND GND from line 526 of ultra_fpga_power_ground_nets AG43 = GROUND GND from line 527 of ultra_fpga_power_ground_nets AG44 = GROUND GND from line 528 of ultra_fpga_power_ground_nets AG45 = MGT_FO_CH_2_OUT_Hub_DIR MGTYRXP0_126 from line 10764 of mgt_fanout_channel_nets AG46 = MGT_FO_CH_2_OUT_Hub_CMP MGTYRXN0_126 from line 10765 of mgt_fanout_channel_nets AH10 = MGT_AVCC MGTAVCC_RS from line 1213 of ultra_fpga_power_ground_nets AH11 = GROUND GND from line 532 of ultra_fpga_power_ground_nets AH12 = No_Conn_FPGA_AH12 NC from line 981 of ultra_no_connect_pins_nets AH13 = No_Conn_FPGA_AH13 NC from line 980 of ultra_no_connect_pins_nets AH14 = FLASH_D03 D03_0 from line 59 of bank_0_and_bank_65_config_mem_nets AH15 = GROUND GND from line 533 of ultra_fpga_power_ground_nets AH16 = FPGA_CORE VCCINT from line 904 of ultra_fpga_power_ground_nets AH17 = GROUND GND from line 534 of ultra_fpga_power_ground_nets AH18 = FPGA_CORE VCCINT from line 905 of ultra_fpga_power_ground_nets AH19 = GROUND GND from line 535 of ultra_fpga_power_ground_nets AH20 = FPGA_CORE VCCINT from line 906 of ultra_fpga_power_ground_nets AH21 = GROUND GND from line 536 of ultra_fpga_power_ground_nets AH22 = FPGA_CORE VCCINT from line 907 of ultra_fpga_power_ground_nets AH23 = GROUND GND from line 537 of ultra_fpga_power_ground_nets AH24 = FPGA_CORE VCCINT from line 908 of ultra_fpga_power_ground_nets AH25 = GROUND GND from line 538 of ultra_fpga_power_ground_nets AH26 = FPGA_CORE VCCINT from line 909 of ultra_fpga_power_ground_nets AH27 = GROUND GND from line 539 of ultra_fpga_power_ground_nets AH28 = FPGA_CORE VCCINT from line 910 of ultra_fpga_power_ground_nets AH29 = GROUND GND from line 540 of ultra_fpga_power_ground_nets AH30 = BULK_1V8 VCCAUX_IO from line 1013 of ultra_fpga_power_ground_nets AH31 = GROUND GND from line 541 of ultra_fpga_power_ground_nets AH32 = BULK_1V8 VCCAUX from line 991 of ultra_fpga_power_ground_nets AH33 = GROUND GND from line 542 of ultra_fpga_power_ground_nets AH34 = No_Conn_FPGA_AH34 NC from line 919 of ultra_no_connect_pins_nets AH35 = No_Conn_FPGA_AH35 NC from line 918 of ultra_no_connect_pins_nets AH36 = GROUND GND from line 543 of ultra_fpga_power_ground_nets AH37 = MGT_AVCC MGTAVCC_LS from line 1175 of ultra_fpga_power_ground_nets AH38 = No_Conn_FPGA_AH38 MGTYTXP3_125 from line 434 of ultra_no_connect_pins_nets AH39 = No_Conn_FPGA_AH39 MGTYTXN3_125 from line 435 of ultra_no_connect_pins_nets AH40 = MGT_AVTT MGTAVTTRCAL_LC from line 118 of ultra_dci_vref_mgt_calib_resistors_nets AH41 = QUAD_125_MGTRREF MGTRREF_LC from line 119 of ultra_dci_vref_mgt_calib_resistors_nets AH42 = GROUND GND from line 544 of ultra_fpga_power_ground_nets AH43 = MGT_FO_CH_3_OUT_Hub_CMP MGTYRXP3_125 from line 10758 of mgt_fanout_channel_nets AH44 = MGT_FO_CH_3_OUT_Hub_DIR MGTYRXN3_125 from line 10759 of mgt_fanout_channel_nets AH45 = GROUND GND from line 545 of ultra_fpga_power_ground_nets AH46 = GROUND GND from line 546 of ultra_fpga_power_ground_nets AJ10 = No_Conn_FPGA_AJ10 NC from line 991 of ultra_no_connect_pins_nets AJ11 = No_Conn_FPGA_AJ11 NC from line 990 of ultra_no_connect_pins_nets AJ12 = MGT_AVCC MGTAVCC_RS from line 1214 of ultra_fpga_power_ground_nets AJ13 = GROUND GND from line 551 of ultra_fpga_power_ground_nets AJ14 = GROUND GND from line 552 of ultra_fpga_power_ground_nets AJ15 = FPGA_CORE VCCINT from line 911 of ultra_fpga_power_ground_nets AJ16 = GROUND GND from line 553 of ultra_fpga_power_ground_nets AJ17 = FPGA_CORE VCCINT from line 912 of ultra_fpga_power_ground_nets AJ18 = GROUND GND from line 554 of ultra_fpga_power_ground_nets AJ19 = FPGA_CORE VCCINT from line 913 of ultra_fpga_power_ground_nets AJ20 = GROUND GND from line 555 of ultra_fpga_power_ground_nets AJ21 = FPGA_CORE VCCINT from line 914 of ultra_fpga_power_ground_nets AJ22 = GROUND GND from line 556 of ultra_fpga_power_ground_nets AJ23 = FPGA_CORE VCCINT from line 915 of ultra_fpga_power_ground_nets AJ24 = GROUND GND from line 557 of ultra_fpga_power_ground_nets AJ25 = FPGA_CORE VCCINT from line 916 of ultra_fpga_power_ground_nets AJ26 = GROUND GND from line 558 of ultra_fpga_power_ground_nets AJ27 = FPGA_CORE VCCINT from line 917 of ultra_fpga_power_ground_nets AJ28 = GROUND GND from line 559 of ultra_fpga_power_ground_nets AJ29 = FPGA_CORE VCCINT_IO from line 950 of ultra_fpga_power_ground_nets AJ30 = GROUND GND from line 560 of ultra_fpga_power_ground_nets AJ31 = BULK_1V8 VCCAUX_IO from line 1014 of ultra_fpga_power_ground_nets AJ32 = GROUND GND from line 561 of ultra_fpga_power_ground_nets AJ33 = GROUND GND from line 562 of ultra_fpga_power_ground_nets AJ34 = GROUND GND from line 563 of ultra_fpga_power_ground_nets AJ35 = MGT_AVCC MGTAVCC_LS from line 1176 of ultra_fpga_power_ground_nets AJ36 = No_Conn_FPGA_AJ36 NC from line 929 of ultra_no_connect_pins_nets AJ37 = No_Conn_FPGA_AJ37 NC from line 928 of ultra_no_connect_pins_nets AJ38 = GROUND GND from line 564 of ultra_fpga_power_ground_nets AJ39 = MGT_AVTT MGTAVTT_LC from line 1240 of ultra_fpga_power_ground_nets AJ40 = No_Conn_FPGA_AJ40 MGTYTXP2_125 from line 437 of ultra_no_connect_pins_nets AJ41 = No_Conn_FPGA_AJ41 MGTYTXN2_125 from line 438 of ultra_no_connect_pins_nets AJ42 = GROUND GND from line 565 of ultra_fpga_power_ground_nets AJ43 = GROUND GND from line 566 of ultra_fpga_power_ground_nets AJ44 = GROUND GND from line 567 of ultra_fpga_power_ground_nets AJ45 = MGT_FO_CH_4_OUT_Hub_DIR MGTYRXP2_125 from line 10754 of mgt_fanout_channel_nets AJ46 = MGT_FO_CH_4_OUT_Hub_CMP MGTYRXN2_125 from line 10755 of mgt_fanout_channel_nets AK10 = GROUND GND from line 572 of ultra_fpga_power_ground_nets AK11 = MGT_AVAUX MGTVCCAUX_RS from line 1393 of ultra_fpga_power_ground_nets AK12 = No_Conn_FPGA_AK12 NC from line 959 of ultra_no_connect_pins_nets AK13 = No_Conn_FPGA_AK13 NC from line 958 of ultra_no_connect_pins_nets AK14 = FLASH_D01 D01_DIN_0 from line 57 of bank_0_and_bank_65_config_mem_nets AK15 = GROUND GND from line 573 of ultra_fpga_power_ground_nets AK16 = FPGA_CORE VCCINT from line 918 of ultra_fpga_power_ground_nets AK17 = GROUND GND from line 574 of ultra_fpga_power_ground_nets AK18 = FPGA_CORE VCCINT from line 919 of ultra_fpga_power_ground_nets AK19 = GROUND GND from line 575 of ultra_fpga_power_ground_nets AK20 = FPGA_CORE VCCINT from line 920 of ultra_fpga_power_ground_nets AK21 = GROUND GND from line 576 of ultra_fpga_power_ground_nets AK22 = FPGA_CORE VCCINT from line 921 of ultra_fpga_power_ground_nets AK23 = GROUND GND from line 577 of ultra_fpga_power_ground_nets AK24 = FPGA_CORE VCCINT from line 922 of ultra_fpga_power_ground_nets AK25 = GROUND GND from line 578 of ultra_fpga_power_ground_nets AK26 = FPGA_CORE VCCINT from line 923 of ultra_fpga_power_ground_nets AK27 = GROUND GND from line 579 of ultra_fpga_power_ground_nets AK28 = FPGA_CORE VCCINT from line 924 of ultra_fpga_power_ground_nets AK29 = GROUND GND from line 580 of ultra_fpga_power_ground_nets AK30 = BULK_1V8 VCCAUX_IO from line 1015 of ultra_fpga_power_ground_nets AK31 = GROUND GND from line 581 of ultra_fpga_power_ground_nets AK32 = BULK_1V8 VCCAUX from line 992 of ultra_fpga_power_ground_nets AK33 = GROUND GND from line 582 of ultra_fpga_power_ground_nets AK34 = No_Conn_FPGA_AK34 NC from line 899 of ultra_no_connect_pins_nets AK35 = No_Conn_FPGA_AK35 NC from line 898 of ultra_no_connect_pins_nets AK36 = MGT_AVAUX MGTVCCAUX_LS from line 1372 of ultra_fpga_power_ground_nets AK37 = GROUND GND from line 583 of ultra_fpga_power_ground_nets AK38 = No_Conn_FPGA_AK38 MGTYTXP1_125 from line 440 of ultra_no_connect_pins_nets AK39 = No_Conn_FPGA_AK39 MGTYTXN1_125 from line 441 of ultra_no_connect_pins_nets AK40 = MGT_AVTT MGTAVTT_LC from line 1241 of ultra_fpga_power_ground_nets AK41 = GROUND GND from line 584 of ultra_fpga_power_ground_nets AK42 = GROUND GND from line 585 of ultra_fpga_power_ground_nets AK43 = MGT_FO_CH_5_OUT_Hub_CMP MGTYRXP1_125 from line 10750 of mgt_fanout_channel_nets AK44 = MGT_FO_CH_5_OUT_Hub_DIR MGTYRXN1_125 from line 10751 of mgt_fanout_channel_nets AK45 = GROUND GND from line 586 of ultra_fpga_power_ground_nets AK46 = GROUND GND from line 587 of ultra_fpga_power_ground_nets AL10 = No_Conn_FPGA_AL10 NC from line 971 of ultra_no_connect_pins_nets AL11 = No_Conn_FPGA_AL11 NC from line 970 of ultra_no_connect_pins_nets AL12 = GROUND GND from line 592 of ultra_fpga_power_ground_nets AL13 = MGT_AVCC MGTAVCC_RS from line 1216 of ultra_fpga_power_ground_nets AL14 = GROUND GND from line 593 of ultra_fpga_power_ground_nets AL15 = FPGA_CORE VCCINT from line 925 of ultra_fpga_power_ground_nets AL16 = GROUND GND from line 594 of ultra_fpga_power_ground_nets AL17 = FPGA_CORE VCCINT from line 926 of ultra_fpga_power_ground_nets AL18 = GROUND GND from line 595 of ultra_fpga_power_ground_nets AL19 = FPGA_CORE VCCINT from line 927 of ultra_fpga_power_ground_nets AL20 = GROUND GND from line 596 of ultra_fpga_power_ground_nets AL21 = FPGA_CORE VCCINT from line 928 of ultra_fpga_power_ground_nets AL22 = GROUND GND from line 597 of ultra_fpga_power_ground_nets AL23 = FPGA_CORE VCCINT from line 929 of ultra_fpga_power_ground_nets AL24 = GROUND GND from line 598 of ultra_fpga_power_ground_nets AL25 = FPGA_CORE VCCINT from line 930 of ultra_fpga_power_ground_nets AL26 = GROUND GND from line 599 of ultra_fpga_power_ground_nets AL27 = FPGA_CORE VCCINT from line 931 of ultra_fpga_power_ground_nets AL28 = GROUND GND from line 600 of ultra_fpga_power_ground_nets AL29 = FPGA_CORE VCCINT_IO from line 951 of ultra_fpga_power_ground_nets AL30 = GROUND GND from line 601 of ultra_fpga_power_ground_nets AL31 = BULK_1V8 VCCAUX_IO from line 1016 of ultra_fpga_power_ground_nets AL32 = GROUND GND from line 602 of ultra_fpga_power_ground_nets AL33 = GROUND GND from line 603 of ultra_fpga_power_ground_nets AL34 = MGT_AVCC MGTAVCC_LS from line 1177 of ultra_fpga_power_ground_nets AL35 = GROUND GND from line 604 of ultra_fpga_power_ground_nets AL36 = No_Conn_FPGA_AL36 NC from line 909 of ultra_no_connect_pins_nets AL37 = No_Conn_FPGA_AL37 NC from line 908 of ultra_no_connect_pins_nets AL38 = MGT_AVCC MGTAVCC_LS from line 1178 of ultra_fpga_power_ground_nets AL39 = GROUND GND from line 605 of ultra_fpga_power_ground_nets AL40 = No_Conn_FPGA_AL40 MGTYTXP0_125 from line 443 of ultra_no_connect_pins_nets AL41 = No_Conn_FPGA_AL41 MGTYTXN0_125 from line 444 of ultra_no_connect_pins_nets AL42 = GROUND GND from line 606 of ultra_fpga_power_ground_nets AL43 = GROUND GND from line 607 of ultra_fpga_power_ground_nets AL44 = GROUND GND from line 608 of ultra_fpga_power_ground_nets AL45 = MGT_FO_CH_6_OUT_Hub_DIR MGTYRXP0_125 from line 10746 of mgt_fanout_channel_nets AL46 = MGT_FO_CH_6_OUT_Hub_CMP MGTYRXN0_125 from line 10747 of mgt_fanout_channel_nets AM10 = MGT_AVAUX MGTVCCAUX_RS from line 1394 of ultra_fpga_power_ground_nets AM11 = GROUND GND from line 613 of ultra_fpga_power_ground_nets AM12 = No_Conn_FPGA_AM12 NC from line 939 of ultra_no_connect_pins_nets AM13 = No_Conn_FPGA_AM13 NC from line 938 of ultra_no_connect_pins_nets AM14 = FLASH_D00 D00_MOSI_0 from line 56 of bank_0_and_bank_65_config_mem_nets AM15 = GROUND GND from line 614 of ultra_fpga_power_ground_nets AM16 = ALL_HUB_POWER_GOOD_TO_FPGA IO_T3U_N12_84 from line 433 of power_supply_all_other_nets AM17 = Bank_84_VREF VREF_84 from line 92 of ultra_dci_vref_mgt_calib_resistors_nets AM18 = Bank_65_VREF VREF_65 from line 75 of ultra_dci_vref_mgt_calib_resistors_nets AM19 = NO_CONN_FPGA_BANK_65_AM19 IO_L3P_T0L_N4_AD15P_A26_65 from line 241 of bank_0_and_bank_65_config_mem_nets AM20 = BULK_1V8 VCCO_65 from line 1039 of ultra_fpga_power_ground_nets AM21 = FLASH_A24 IO_L4P_T0U_N6_DBC_AD7P_A24_65 from line 113 of bank_0_and_bank_65_config_mem_nets AM22 = Bank_66_VREF VREF_66 from line 78 of ultra_dci_vref_mgt_calib_resistors_nets AM23 = No_Conn_FPGA_AM23 IO_L1P_T0L_N0_DBC_66 from line 103 of ultra_no_connect_pins_nets AM24 = No_Conn_FPGA_AM24 IO_L5P_T0U_N8_AD14P_66 from line 95 of ultra_no_connect_pins_nets AM25 = GROUND GND from line 615 of ultra_fpga_power_ground_nets AM26 = No_Conn_FPGA_AM26 IO_L2P_T0L_N2_66 from line 101 of ultra_no_connect_pins_nets AM27 = Bank_66_VRP_DCI IO_T0U_N12_VRP_66 from line 41 of ultra_dci_vref_mgt_calib_resistors_nets AM28 = Bank_67_VREF VREF_67 from line 81 of ultra_dci_vref_mgt_calib_resistors_nets AM29 = No_Conn_FPGA_AM29 IO_L3P_T0L_N4_AD15P_67 from line 141 of ultra_no_connect_pins_nets AM30 = BULK_1V8 VCCO_67 from line 1062 of ultra_fpga_power_ground_nets AM31 = No_Conn_FPGA_AM31 IO_L2P_T0L_N2_67 from line 143 of ultra_no_connect_pins_nets AM32 = Bank_68_VREF VREF_68 from line 84 of ultra_dci_vref_mgt_calib_resistors_nets AM33 = GROUND GND from line 616 of ultra_fpga_power_ground_nets AM34 = No_Conn_FPGA_AM34 NC from line 877 of ultra_no_connect_pins_nets AM35 = No_Conn_FPGA_AM35 NC from line 876 of ultra_no_connect_pins_nets AM36 = GROUND GND from line 617 of ultra_fpga_power_ground_nets AM37 = MGT_AVAUX MGTVCCAUX_LS from line 1373 of ultra_fpga_power_ground_nets AM38 = No_Conn_FPGA_AM38 MGTYTXP3_124 from line 414 of ultra_no_connect_pins_nets AM39 = No_Conn_FPGA_AM39 MGTYTXN3_124 from line 415 of ultra_no_connect_pins_nets AM40 = GROUND GND from line 618 of ultra_fpga_power_ground_nets AM41 = MGT_AVTT MGTAVTT_LC from line 1242 of ultra_fpga_power_ground_nets AM42 = GROUND GND from line 619 of ultra_fpga_power_ground_nets AM43 = MGT_FO_CH_7_OUT_Hub_CMP MGTYRXP3_124 from line 10740 of mgt_fanout_channel_nets AM44 = MGT_FO_CH_7_OUT_Hub_DIR MGTYRXN3_124 from line 10741 of mgt_fanout_channel_nets AM45 = GROUND GND from line 620 of ultra_fpga_power_ground_nets AM46 = GROUND GND from line 621 of ultra_fpga_power_ground_nets AN10 = No_Conn_FPGA_AN10 NC from line 949 of ultra_no_connect_pins_nets AN11 = No_Conn_FPGA_AN11 NC from line 948 of ultra_no_connect_pins_nets AN12 = GROUND GND from line 626 of ultra_fpga_power_ground_nets AN13 = VBATT VBATT from line 205 of bank_0_and_bank_65_config_mem_nets AN14 = GROUND GND from line 627 of ultra_fpga_power_ground_nets AN15 = Trans_MiniPOD_SCL IO_L23P_T3U_N8_84 from line 156 of minipod_pow_gnd_ctrl_no_conn_nets AN16 = Trans_MiniPOD_INTR_B IO_L21P_T3L_N4_AD8P_84 from line 159 of minipod_pow_gnd_ctrl_no_conn_nets AN17 = BULK_3V3 VCCO_84 from line 1120 of ultra_fpga_power_ground_nets AN18 = NO_CONN_FPGA_BANK_65_AN18 IO_L1P_T0L_N0_DBC_RS0_65 from line 243 of bank_0_and_bank_65_config_mem_nets AN19 = NO_CONN_FPGA_BANK_65_AN19 IO_L3N_T0L_N5_AD15N_A27_65 from line 242 of bank_0_and_bank_65_config_mem_nets AN20 = FLASH_OUTPUT_ENB_B IO_L2P_T0L_N2_FOE_B_65 from line 132 of bank_0_and_bank_65_config_mem_nets AN21 = FLASH_A25 IO_L4N_T0U_N7_DBC_AD7N_A25_65 from line 114 of bank_0_and_bank_65_config_mem_nets AN22 = GROUND GND from line 628 of ultra_fpga_power_ground_nets AN23 = No_Conn_FPGA_AN23 IO_L1N_T0L_N1_DBC_66 from line 104 of ultra_no_connect_pins_nets AN24 = No_Conn_FPGA_AN24 IO_L5N_T0U_N9_AD14N_66 from line 96 of ultra_no_connect_pins_nets AN25 = No_Conn_FPGA_AN25 IO_L4P_T0U_N6_DBC_AD7P_66 from line 97 of ultra_no_connect_pins_nets AN26 = No_Conn_FPGA_AN26 IO_L2N_T0L_N3_66 from line 102 of ultra_no_connect_pins_nets AN27 = BULK_1V8 VCCO_66 from line 1050 of ultra_fpga_power_ground_nets AN28 = No_Conn_FPGA_AN28 IO_L1P_T0L_N0_DBC_67 from line 145 of ultra_no_connect_pins_nets AN29 = No_Conn_FPGA_AN29 IO_L3N_T0L_N5_AD15N_67 from line 142 of ultra_no_connect_pins_nets AN30 = No_Conn_FPGA_AN30 IO_L6P_T0U_N10_AD6P_67 from line 135 of ultra_no_connect_pins_nets AN31 = No_Conn_FPGA_AN31 IO_L2N_T0L_N3_67 from line 144 of ultra_no_connect_pins_nets AN32 = No_Conn_FPGA_AN32 IO_L1P_T0L_N0_DBC_68 from line 175 of ultra_no_connect_pins_nets AN33 = GROUND GND from line 629 of ultra_fpga_power_ground_nets AN34 = GROUND GND from line 630 of ultra_fpga_power_ground_nets AN35 = GROUND GND from line 631 of ultra_fpga_power_ground_nets AN36 = No_Conn_FPGA_AN36 NC from line 889 of ultra_no_connect_pins_nets AN37 = No_Conn_FPGA_AN37 NC from line 888 of ultra_no_connect_pins_nets AN38 = GROUND GND from line 632 of ultra_fpga_power_ground_nets AN39 = MGT_AVTT MGTAVTT_LC from line 1243 of ultra_fpga_power_ground_nets AN40 = No_Conn_FPGA_AN40 MGTYTXP2_124 from line 417 of ultra_no_connect_pins_nets AN41 = No_Conn_FPGA_AN41 MGTYTXN2_124 from line 418 of ultra_no_connect_pins_nets AN42 = GROUND GND from line 633 of ultra_fpga_power_ground_nets AN43 = GROUND GND from line 634 of ultra_fpga_power_ground_nets AN44 = GROUND GND from line 635 of ultra_fpga_power_ground_nets AN45 = MGT_FO_CH_8_OUT_Hub_DIR MGTYRXP2_124 from line 10736 of mgt_fanout_channel_nets AN46 = MGT_FO_CH_8_OUT_Hub_CMP MGTYRXN2_124 from line 10737 of mgt_fanout_channel_nets AP10 = GROUND GND from line 640 of ultra_fpga_power_ground_nets AP11 = GROUND GND from line 641 of ultra_fpga_power_ground_nets AP12 = GROUND GND from line 642 of ultra_fpga_power_ground_nets AP13 = Trans_MiniPOD_RESET_B IO_L18P_T2U_N10_AD2P_84 from line 162 of minipod_pow_gnd_ctrl_no_conn_nets AP14 = BULK_3V3 VCCO_84 from line 1121 of ultra_fpga_power_ground_nets AP15 = Trans_MiniPOD_SDA IO_L23N_T3U_N9_84 from line 153 of minipod_pow_gnd_ctrl_no_conn_nets AP16 = Hubs_SMB_Alert_B IO_L21N_T3L_N5_AD8N_84 from line 1035 of power_supply_all_other_nets AP17 = ROD_Power_Enable_B IO_L24P_T3U_N10_84 from line 697 of power_supply_all_other_nets AP18 = NO_CONN_FPGA_BANK_65_AP18 IO_L1N_T0L_N1_DBC_RS1_65 from line 244 of bank_0_and_bank_65_config_mem_nets AP19 = GROUND GND from line 643 of ultra_fpga_power_ground_nets AP20 = FLASH_WRITE_ENB_B IO_L2N_T0L_N3_FWE_FCS2_B_65 from line 130 of bank_0_and_bank_65_config_mem_nets AP21 = Bank_65_VRP_DCI IO_T0U_N12_VRP_A28_65 from line 38 of ultra_dci_vref_mgt_calib_resistors_nets AP22 = No_Conn_FPGA_AP22 IO_L3P_T0L_N4_AD15P_66 from line 99 of ultra_no_connect_pins_nets AP23 = No_Conn_FPGA_AP23 IO_L3N_T0L_N5_AD15N_66 from line 100 of ultra_no_connect_pins_nets AP24 = BULK_1V8 VCCO_66 from line 1051 of ultra_fpga_power_ground_nets AP25 = No_Conn_FPGA_AP25 IO_L4N_T0U_N7_DBC_AD7N_66 from line 98 of ultra_no_connect_pins_nets AP26 = No_Conn_FPGA_AP26 IO_L6P_T0U_N10_AD6P_66 from line 93 of ultra_no_connect_pins_nets AP27 = No_Conn_FPGA_AP27 IO_L6N_T0U_N11_AD6N_66 from line 94 of ultra_no_connect_pins_nets AP28 = No_Conn_FPGA_AP28 IO_L1N_T0L_N1_DBC_67 from line 146 of ultra_no_connect_pins_nets AP29 = GROUND GND from line 644 of ultra_fpga_power_ground_nets AP30 = No_Conn_FPGA_AP30 IO_L6N_T0U_N11_AD6N_67 from line 136 of ultra_no_connect_pins_nets AP31 = Bank_67_VRP_DCI IO_T0U_N12_VRP_67 from line 44 of ultra_dci_vref_mgt_calib_resistors_nets AP32 = No_Conn_FPGA_AP32 IO_L1N_T0L_N1_DBC_68 from line 176 of ultra_no_connect_pins_nets AP33 = No_Conn_FPGA_AP33 IO_L5P_T0U_N8_AD14P_68 from line 168 of ultra_no_connect_pins_nets AP34 = BULK_1V8 VCCO_68 from line 1074 of ultra_fpga_power_ground_nets AP35 = GROUND GND from line 645 of ultra_fpga_power_ground_nets AP36 = GROUND GND from line 646 of ultra_fpga_power_ground_nets AP37 = GROUND GND from line 647 of ultra_fpga_power_ground_nets AP38 = No_Conn_FPGA_AP38 MGTYTXP1_124 from line 420 of ultra_no_connect_pins_nets AP39 = No_Conn_FPGA_AP39 MGTYTXN1_124 from line 421 of ultra_no_connect_pins_nets AP40 = MGT_AVTT MGTAVTT_LC from line 1244 of ultra_fpga_power_ground_nets AP41 = GROUND GND from line 648 of ultra_fpga_power_ground_nets AP42 = GROUND GND from line 649 of ultra_fpga_power_ground_nets AP43 = Combined_Data_from_OTHER_Hub_Cmp MGTYRXP1_124 from line 76 of hub_all_other_mgt_nets AP44 = Combined_Data_from_OTHER_Hub_Dir MGTYRXN1_124 from line 75 of hub_all_other_mgt_nets AP45 = GROUND GND from line 650 of ultra_fpga_power_ground_nets AP46 = GROUND GND from line 651 of ultra_fpga_power_ground_nets AR10 = GROUND GND from line 656 of ultra_fpga_power_ground_nets AR11 = BULK_3V3 VCCO_84 from line 1122 of ultra_fpga_power_ground_nets AR12 = Recvr_MiniPOD_SCL IO_L15P_T2L_N4_AD11P_84 from line 186 of minipod_pow_gnd_ctrl_no_conn_nets AR13 = Recvr_MiniPOD_SDA IO_L18N_T2U_N11_AD2N_84 from line 183 of minipod_pow_gnd_ctrl_no_conn_nets AR14 = Recvr_MiniPOD_RESET_B IO_L16N_T2U_N7_QBC_AD3N_84 from line 192 of minipod_pow_gnd_ctrl_no_conn_nets AR15 = Recvr_MiniPOD_INTR_B IO_L16P_T2U_N6_QBC_AD3P_84 from line 189 of minipod_pow_gnd_ctrl_no_conn_nets AR16 = GROUND GND from line 657 of ultra_fpga_power_ground_nets AR17 = ROD_Power_Enable IO_L24N_T3U_N11_84 from line 695 of power_supply_all_other_nets AR18 = FLASH_A23 IO_L5N_T0U_N9_AD14N_A23_65 from line 111 of bank_0_and_bank_65_config_mem_nets AR19 = FLASH_A22 IO_L5P_T0U_N8_AD14P_A22_65 from line 110 of bank_0_and_bank_65_config_mem_nets AR20 = FLASH_A20 IO_L6P_T0U_N10_AD6P_A20_65 from line 108 of bank_0_and_bank_65_config_mem_nets AR21 = BULK_1V8 VCCO_65 from line 1040 of ultra_fpga_power_ground_nets AR22 = No_Conn_FPGA_AR22 IO_L7P_T1L_N0_QBC_AD13P_66 from line 91 of ultra_no_connect_pins_nets AR23 = No_Conn_FPGA_AR23 IO_L7N_T1L_N1_QBC_AD13N_66 from line 92 of ultra_no_connect_pins_nets AR24 = No_Conn_FPGA_AR24 IO_L8P_T1L_N2_AD5P_66 from line 89 of ultra_no_connect_pins_nets AR25 = No_Conn_FPGA_AR25 IO_L8N_T1L_N3_AD5N_66 from line 90 of ultra_no_connect_pins_nets AR26 = GROUND GND from line 658 of ultra_fpga_power_ground_nets AR27 = No_Conn_FPGA_AR27 IO_L5P_T0U_N8_AD14P_67 from line 137 of ultra_no_connect_pins_nets AR28 = No_Conn_FPGA_AR28 IO_L5N_T0U_N9_AD14N_67 from line 138 of ultra_no_connect_pins_nets AR29 = No_Conn_FPGA_AR29 IO_L4P_T0U_N6_DBC_AD7P_67 from line 139 of ultra_no_connect_pins_nets AR30 = No_Conn_FPGA_AR30 IO_L4N_T0U_N7_DBC_AD7N_67 from line 140 of ultra_no_connect_pins_nets AR31 = BULK_1V8 VCCO_67 from line 1063 of ultra_fpga_power_ground_nets AR32 = No_Conn_FPGA_AR32 IO_L3P_T0L_N4_AD15P_68 from line 171 of ultra_no_connect_pins_nets AR33 = No_Conn_FPGA_AR33 IO_L5N_T0U_N9_AD14N_68 from line 169 of ultra_no_connect_pins_nets AR34 = No_Conn_FPGA_AR34 IO_L2P_T0L_N2_68 from line 173 of ultra_no_connect_pins_nets AR35 = Phys_U22_TXD2 IO_L4P_T0U_N6_DBC_AD7P_68 from line 121 of ultra_fpga_to_phys_chips_nets AR36 = Phys_U22_TXD0 IO_L6P_T0U_N10_AD6P_68 from line 117 of ultra_fpga_to_phys_chips_nets AR37 = GROUND GND from line 659 of ultra_fpga_power_ground_nets AR38 = MGT_AVTT MGTAVTT_LC from line 1245 of ultra_fpga_power_ground_nets AR39 = GROUND GND from line 660 of ultra_fpga_power_ground_nets AR40 = No_Conn_FPGA_AR40 MGTYTXP0_124 from line 423 of ultra_no_connect_pins_nets AR41 = No_Conn_FPGA_AR41 MGTYTXN0_124 from line 424 of ultra_no_connect_pins_nets AR42 = GROUND GND from line 661 of ultra_fpga_power_ground_nets AR43 = GROUND GND from line 662 of ultra_fpga_power_ground_nets AR44 = GROUND GND from line 663 of ultra_fpga_power_ground_nets AR45 = Rec_MP_Fiber_8_to_FPGA_Dir MGTYRXP0_124 from line 126 of hub_all_other_mgt_nets AR46 = Rec_MP_Fiber_8_to_FPGA_Cmp MGTYRXN0_124 from line 127 of hub_all_other_mgt_nets AT10 = GROUND GND from line 668 of ultra_fpga_power_ground_nets AT11 = ISO_SLOT_HW_ADRS_1 IO_T2U_N12_84 from line 56 of hardware_address_to_rod_nets AT12 = ISO_SLOT_HW_ADRS_0 IO_L15N_T2L_N5_AD11N_84 from line 55 of hardware_address_to_rod_nets AT13 = GROUND GND from line 669 of ultra_fpga_power_ground_nets AT14 = FPGA_SW_B_ATC_LOOP_DET IO_L14N_T2L_N3_GC_84 from line 317 of switch_chips_all_other_nets AT15 = CLOCK_25_MHz_FPGA IO_L14P_T2L_N2_GC_84 from line 112 of clock_generation_nets AT16 = FPGA_SW_B_MDC IO_L19P_T3L_N0_DBC_AD9P_84 from line 285 of switch_chips_all_other_nets AT17 = No_Conn_FPGA_AT17 IO_L20P_T3L_N2_AD1P_84 from line 188 of ultra_no_connect_pins_nets AT18 = BULK_1V8 VCCO_65 from line 1041 of ultra_fpga_power_ground_nets AT19 = FLASH_A18 IO_L7P_T1L_N0_QBC_AD13P_A18_65 from line 105 of bank_0_and_bank_65_config_mem_nets AT20 = FLASH_A21 IO_L6N_T0U_N11_AD6N_A21_65 from line 109 of bank_0_and_bank_65_config_mem_nets AT21 = FLASH_A16 IO_L8P_T1L_N2_AD5P_A16_65 from line 103 of bank_0_and_bank_65_config_mem_nets AT22 = No_Conn_FPGA_AT22 IO_L9P_T1L_N4_AD12P_66 from line 87 of ultra_no_connect_pins_nets AT23 = GROUND GND from line 670 of ultra_fpga_power_ground_nets AT24 = No_Conn_FPGA_AT24 IO_L12P_T1U_N10_GC_66 from line 80 of ultra_no_connect_pins_nets AT25 = No_Conn_FPGA_AT25 IO_L12N_T1U_N11_GC_66 from line 81 of ultra_no_connect_pins_nets AT26 = No_Conn_FPGA_AT26 IO_L10P_T1U_N6_QBC_AD4P_66 from line 85 of ultra_no_connect_pins_nets AT27 = TBD_SPARE_LINK_1_DIR IO_L8P_T1L_N2_AD5P_67 from line 43 of rod_to_from_hub_spare_nets AT28 = BULK_1V8 VCCO_67 from line 1064 of ultra_fpga_power_ground_nets AT29 = TBD_SPARE_LINK_3_DIR IO_L9P_T1L_N4_AD12P_67 from line 49 of rod_to_from_hub_spare_nets AT30 = ACCESS_SIGNAL_1_FROM_FPGA IO_L10P_T1U_N6_QBC_AD4P_67 from line 100 of sundry_hub_nets AT31 = ACCESS_SIGNAL_2_FROM_FPGA IO_L10N_T1U_N7_QBC_AD4N_67 from line 101 of sundry_hub_nets AT32 = No_Conn_FPGA_AT32 IO_L3N_T0L_N5_AD15N_68 from line 172 of ultra_no_connect_pins_nets AT33 = GROUND GND from line 671 of ultra_fpga_power_ground_nets AT34 = Phys_U22_GTX_CLK IO_L2N_T0L_N3_68 from line 127 of ultra_fpga_to_phys_chips_nets AT35 = Phys_U22_TXD3 IO_L4N_T0U_N7_DBC_AD7N_68 from line 123 of ultra_fpga_to_phys_chips_nets AT36 = Phys_U22_TXD1 IO_L6N_T0U_N11_AD6N_68 from line 119 of ultra_fpga_to_phys_chips_nets AT37 = GROUND GND from line 672 of ultra_fpga_power_ground_nets AT38 = No_Conn_FPGA_AT38 NC from line 915 of ultra_no_connect_pins_nets AT39 = No_Conn_FPGA_AT39 NC from line 914 of ultra_no_connect_pins_nets AT40 = GROUND GND from line 673 of ultra_fpga_power_ground_nets AT41 = MGT_AVTT MGTAVTT_LC from line 1246 of ultra_fpga_power_ground_nets AT42 = GROUND GND from line 674 of ultra_fpga_power_ground_nets AT43 = No_Conn_FPGA_AT43 NC from line 916 of ultra_no_connect_pins_nets AT44 = No_Conn_FPGA_AT44 NC from line 917 of ultra_no_connect_pins_nets AT45 = GROUND GND from line 675 of ultra_fpga_power_ground_nets AT46 = GROUND GND from line 676 of ultra_fpga_power_ground_nets AU10 = GROUND GND from line 681 of ultra_fpga_power_ground_nets AU11 = ISO_SLOT_HW_ADRS_3 IO_L17N_T2U_N9_AD10N_84 from line 58 of hardware_address_to_rod_nets AU12 = ISO_SLOT_HW_ADRS_2 IO_L17P_T2U_N8_AD10P_84 from line 57 of hardware_address_to_rod_nets AU13 = FPGA_SW_B_LOOP_DETECTED IO_L13N_T2L_N1_GC_QBC_84 from line 320 of switch_chips_all_other_nets AU14 = No_Conn_FPGA_AU14 IO_L13P_T2L_N0_GC_QBC_84 from line 191 of ultra_no_connect_pins_nets AU15 = BULK_3V3 VCCO_84 from line 1123 of ultra_fpga_power_ground_nets AU16 = FPGA_SW_B_MDIO IO_L19N_T3L_N1_DBC_AD9N_84 from line 282 of switch_chips_all_other_nets AU17 = No_Conn_FPGA_AU17 IO_L20N_T3L_N3_AD1N_84 from line 189 of ultra_no_connect_pins_nets AU18 = FLASH_A14 IO_L9P_T1L_N4_AD12P_A14_D30_65 from line 100 of bank_0_and_bank_65_config_mem_nets AU19 = FLASH_A19 IO_L7N_T1L_N1_QBC_AD13N_A19_65 from line 106 of bank_0_and_bank_65_config_mem_nets AU20 = GROUND GND from line 682 of ultra_fpga_power_ground_nets AU21 = FLASH_A17 IO_L8N_T1L_N3_AD5N_A17_65 from line 104 of bank_0_and_bank_65_config_mem_nets AU22 = No_Conn_FPGA_AU22 IO_L9N_T1L_N5_AD12N_66 from line 88 of ultra_no_connect_pins_nets AU23 = No_Conn_FPGA_AU23 IO_L11P_T1U_N8_GC_66 from line 83 of ultra_no_connect_pins_nets AU24 = No_Conn_FPGA_AU24 IO_L11N_T1U_N9_GC_66 from line 84 of ultra_no_connect_pins_nets AU25 = BULK_1V8 VCCO_66 from line 1052 of ultra_fpga_power_ground_nets AU26 = No_Conn_FPGA_AU26 IO_L10N_T1U_N7_QBC_AD4N_66 from line 86 of ultra_no_connect_pins_nets AU27 = TBD_SPARE_LINK_1_CMP IO_L8N_T1L_N3_AD5N_67 from line 44 of rod_to_from_hub_spare_nets AU28 = SPARE_OSC_TO_FPGA_DIR IO_L11P_T1U_N8_GC_67 from line 149 of sundry_hub_nets AU29 = TBD_SPARE_LINK_3_CMP IO_L9N_T1L_N5_AD12N_67 from line 50 of rod_to_from_hub_spare_nets AU30 = GROUND GND from line 683 of ultra_fpga_power_ground_nets AU31 = No_Conn_FPGA_AU31 IO_L8P_T1L_N2_AD5P_68 from line 166 of ultra_no_connect_pins_nets AU32 = Phys_U22_RXD3__MODE3 IO_L8N_T1L_N3_AD5N_68 from line 109 of ultra_fpga_to_phys_chips_nets AU33 = Phys_U21_CLK125__LED_MODE IO_L12P_T1U_N10_GC_68 from line 82 of ultra_fpga_to_phys_chips_nets AU34 = Phys_U22_TX_EN IO_L12N_T1U_N11_GC_68 from line 125 of ultra_fpga_to_phys_chips_nets AU35 = BULK_1V8 VCCO_68 from line 1075 of ultra_fpga_power_ground_nets AU36 = Bank_68_VRP_DCI IO_T0U_N12_VRP_68 from line 47 of ultra_dci_vref_mgt_calib_resistors_nets AU37 = GROUND GND from line 684 of ultra_fpga_power_ground_nets AU38 = GROUND GND from line 685 of ultra_fpga_power_ground_nets AU39 = MGT_AVTT MGTAVTT_LS from line 1274 of ultra_fpga_power_ground_nets AU40 = No_Conn_FPGA_AU40 NC from line 921 of ultra_no_connect_pins_nets AU41 = No_Conn_FPGA_AU41 NC from line 920 of ultra_no_connect_pins_nets AU42 = GROUND GND from line 686 of ultra_fpga_power_ground_nets AU43 = GROUND GND from line 687 of ultra_fpga_power_ground_nets AU44 = GROUND GND from line 688 of ultra_fpga_power_ground_nets AU45 = No_Conn_FPGA_AU45 NC from line 922 of ultra_no_connect_pins_nets AU46 = No_Conn_FPGA_AU46 NC from line 923 of ultra_no_connect_pins_nets AV10 = GROUND GND from line 693 of ultra_fpga_power_ground_nets AV11 = ISO_SLOT_HW_ADRS_4 IO_L7P_T1L_N0_QBC_AD13P_94 from line 60 of hardware_address_to_rod_nets AV12 = BULK_3V3 VCCO_94 from line 1129 of ultra_fpga_power_ground_nets AV13 = FPGA_SW_A_ATC_LOOP_DET IO_L11N_T1U_N9_GC_94 from line 309 of switch_chips_all_other_nets AV14 = No_Conn_FPGA_AV14 IO_L11P_T1U_N8_GC_94 from line 203 of ultra_no_connect_pins_nets AV15 = FPGA_SW_C_ATC_LOOP_DET IO_L22N_T3U_N7_DBC_AD0N_84 from line 325 of switch_chips_all_other_nets AV16 = FPGA_SW_C_LOOP_DETECTED IO_L22P_T3U_N6_DBC_AD0P_84 from line 328 of switch_chips_all_other_nets AV17 = GROUND GND from line 694 of ultra_fpga_power_ground_nets AV18 = FLASH_A15 IO_L9N_T1L_N5_AD12N_A15_D31_65 from line 101 of bank_0_and_bank_65_config_mem_nets AV19 = NO_CONN_FPGA_BANK_65_AV19 IO_T1U_N12_PERSTN1_65 from line 240 of bank_0_and_bank_65_config_mem_nets AV20 = FLASH_A08 IO_L12P_T1U_N10_GC_A08_D24_65 from line 93 of bank_0_and_bank_65_config_mem_nets AV21 = FLASH_A12 IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 from line 98 of bank_0_and_bank_65_config_mem_nets AV22 = BULK_1V8 VCCO_66 from line 1053 of ultra_fpga_power_ground_nets AV23 = No_Conn_FPGA_AV23 IO_L13P_T2L_N0_GC_QBC_66 from line 78 of ultra_no_connect_pins_nets AV24 = No_Conn_FPGA_AV24 IO_L13N_T2L_N1_GC_QBC_66 from line 79 of ultra_no_connect_pins_nets AV25 = No_Conn_FPGA_AV25 IO_T1U_N12_66 from line 82 of ultra_no_connect_pins_nets AV26 = TBD_SPARE_LINK_0_DIR IO_L7P_T1L_N0_QBC_AD13P_67 from line 40 of rod_to_from_hub_spare_nets AV27 = GROUND GND from line 695 of ultra_fpga_power_ground_nets AV28 = SPARE_OSC_TO_FPGA_CMP IO_L11N_T1U_N9_GC_67 from line 150 of sundry_hub_nets AV29 = ROD_Power_Control_4_FPGA IO_L12P_T1U_N10_GC_67 from line 767 of power_supply_all_other_nets AV30 = ROD_Power_Control_3_FPGA IO_L12N_T1U_N11_GC_67 from line 765 of power_supply_all_other_nets AV31 = Ref_40.08_MHz_from_FPGA_to_Rec_Dir IO_L7P_T1L_N0_QBC_AD13P_68 from line 222 of clock_generation_nets AV32 = BULK_1V8 VCCO_68 from line 1076 of ultra_fpga_power_ground_nets AV33 = Phys_U21_RX_CLK__PHYAD2 IO_L11P_T1U_N8_GC_68 from line 50 of ultra_fpga_to_phys_chips_nets AV34 = Phys_U22_RXD2__MODE2 IO_L11N_T1U_N9_GC_68 from line 107 of ultra_fpga_to_phys_chips_nets AV35 = Phys_U22_RXD0__MODE0 IO_L9P_T1L_N4_AD12P_68 from line 103 of ultra_fpga_to_phys_chips_nets AV36 = Phys_U22_RXD1__MODE1 IO_L10P_T1U_N6_QBC_AD4P_68 from line 105 of ultra_fpga_to_phys_chips_nets AV37 = GROUND GND from line 696 of ultra_fpga_power_ground_nets AV38 = No_Conn_FPGA_AV38 NC from line 925 of ultra_no_connect_pins_nets AV39 = No_Conn_FPGA_AV39 NC from line 924 of ultra_no_connect_pins_nets AV40 = MGT_AVTT MGTAVTT_LS from line 1275 of ultra_fpga_power_ground_nets AV41 = GROUND GND from line 697 of ultra_fpga_power_ground_nets AV42 = GROUND GND from line 698 of ultra_fpga_power_ground_nets AV43 = No_Conn_FPGA_AV43 NC from line 926 of ultra_no_connect_pins_nets AV44 = No_Conn_FPGA_AV44 NC from line 927 of ultra_no_connect_pins_nets AV45 = GROUND GND from line 699 of ultra_fpga_power_ground_nets AV46 = GROUND GND from line 700 of ultra_fpga_power_ground_nets AW10 = GROUND GND from line 705 of ultra_fpga_power_ground_nets AW11 = ISO_SLOT_HW_ADRS_6 IO_L7N_T1L_N1_QBC_AD13N_94 from line 62 of hardware_address_to_rod_nets AW12 = ISO_SLOT_HW_ADRS_5 IO_L12N_T1U_N11_GC_94 from line 61 of hardware_address_to_rod_nets AW13 = FPGA_SW_A_MDC IO_L12P_T1U_N10_GC_94 from line 277 of switch_chips_all_other_nets AW14 = GROUND GND from line 706 of ultra_fpga_power_ground_nets AW15 = FPGA_SW_A_MDIO IO_L2P_T0L_N2_94 from line 274 of switch_chips_all_other_nets AW16 = Bank_94_VREF VREF_94 from line 95 of ultra_dci_vref_mgt_calib_resistors_nets AW17 = FLASH_A11 IO_L11N_T1U_N9_GC_A11_D27_65 from line 96 of bank_0_and_bank_65_config_mem_nets AW18 = FLASH_A10 IO_L11P_T1U_N8_GC_A10_D26_65 from line 95 of bank_0_and_bank_65_config_mem_nets AW19 = BULK_1V8 VCCO_65 from line 1042 of ultra_fpga_power_ground_nets AW20 = FLASH_A09 IO_L12N_T1U_N11_GC_A09_D25_65 from line 94 of bank_0_and_bank_65_config_mem_nets AW21 = FLASH_A13 IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 from line 99 of bank_0_and_bank_65_config_mem_nets AW22 = No_Conn_FPGA_AW22 IO_L14P_T2L_N2_GC_66 from line 75 of ultra_no_connect_pins_nets AW23 = No_Conn_FPGA_AW23 IO_L14N_T2L_N3_GC_66 from line 76 of ultra_no_connect_pins_nets AW24 = GROUND GND from line 707 of ultra_fpga_power_ground_nets AW25 = No_Conn_FPGA_AW25 IO_T2U_N12_66 from line 77 of ultra_no_connect_pins_nets AW26 = TBD_SPARE_LINK_0_CMP IO_L7N_T1L_N1_QBC_AD13N_67 from line 41 of rod_to_from_hub_spare_nets AW27 = ROD_PRESENT_B_TO_FPGA IO_L14P_T2L_N2_GC_67 from line 270 of jtag_and_associated_nets AW28 = ROD_Power_Control_2_FPGA IO_L14N_T2L_N3_GC_67 from line 763 of power_supply_all_other_nets AW29 = BULK_1V8 VCCO_67 from line 1065 of ultra_fpga_power_ground_nets AW30 = No_Conn_FPGA_AW30 IO_T1U_N12_67 from line 133 of ultra_no_connect_pins_nets AW31 = Ref_40.08_MHz_from_FPGA_to_Rec_Cmp IO_L7N_T1L_N1_QBC_AD13N_68 from line 223 of clock_generation_nets AW32 = Phys_U22_RX_DV__CLK125_EN IO_T1U_N12_68 from line 111 of ultra_fpga_to_phys_chips_nets AW33 = Phys_U22_RX_CLK__PHYAD2 IO_L14P_T2L_N2_GC_68 from line 113 of ultra_fpga_to_phys_chips_nets AW34 = GROUND GND from line 708 of ultra_fpga_power_ground_nets AW35 = Phys_U22_MDIO IO_L9N_T1L_N5_AD12N_68 from line 137 of ultra_fpga_to_phys_chips_nets AW36 = Phys_U22_MDC IO_L10N_T1U_N7_QBC_AD4N_68 from line 135 of ultra_fpga_to_phys_chips_nets AW37 = GROUND GND from line 709 of ultra_fpga_power_ground_nets AW38 = MGT_AVTT MGTAVTT_LS from line 1276 of ultra_fpga_power_ground_nets AW39 = GROUND GND from line 710 of ultra_fpga_power_ground_nets AW40 = No_Conn_FPGA_AW40 NC from line 931 of ultra_no_connect_pins_nets AW41 = No_Conn_FPGA_AW41 NC from line 930 of ultra_no_connect_pins_nets AW42 = GROUND GND from line 711 of ultra_fpga_power_ground_nets AW43 = GROUND GND from line 712 of ultra_fpga_power_ground_nets AW44 = GROUND GND from line 713 of ultra_fpga_power_ground_nets AW45 = No_Conn_FPGA_AW45 NC from line 932 of ultra_no_connect_pins_nets AW46 = No_Conn_FPGA_AW46 NC from line 933 of ultra_no_connect_pins_nets AY10 = GROUND GND from line 718 of ultra_fpga_power_ground_nets AY11 = GROUND GND from line 719 of ultra_fpga_power_ground_nets AY12 = ISO_SLOT_HW_ADRS_7 IO_L9P_T1L_N4_AD12P_94 from line 63 of hardware_address_to_rod_nets AY13 = FPGA_SW_C_MDC IO_T1U_N12_94 from line 293 of switch_chips_all_other_nets AY14 = FPGA_SW_C_MDIO IO_L2N_T0L_N3_94 from line 290 of switch_chips_all_other_nets AY15 = FPGA_SW_A_LOOP_DETECTED IO_L1P_T0L_N0_DBC_94 from line 312 of switch_chips_all_other_nets AY16 = BULK_3V3 VCCO_94 from line 1130 of ultra_fpga_power_ground_nets AY17 = No_Conn_FPGA_AY17 IO_L6P_T0U_N10_AD6P_94 from line 205 of ultra_no_connect_pins_nets AY18 = FLASH_A07 IO_L13N_T2L_N1_GC_QBC_A07_D23_65 from line 91 of bank_0_and_bank_65_config_mem_nets AY19 = FLASH_A06 IO_L13P_T2L_N0_GC_QBC_A06_D22_65 from line 90 of bank_0_and_bank_65_config_mem_nets AY20 = FLASH_A04 IO_L14P_T2L_N2_GC_A04_D20_65 from line 88 of bank_0_and_bank_65_config_mem_nets AY21 = GROUND GND from line 720 of ultra_fpga_power_ground_nets AY22 = No_Conn_FPGA_AY22 IO_L15P_T2L_N4_AD11P_66 from line 73 of ultra_no_connect_pins_nets AY23 = No_Conn_FPGA_AY23 IO_L15N_T2L_N5_AD11N_66 from line 74 of ultra_no_connect_pins_nets AY24 = No_Conn_FPGA_AY24 IO_L16P_T2U_N6_QBC_AD3P_66 from line 71 of ultra_no_connect_pins_nets AY25 = No_Conn_FPGA_AY25 IO_L18P_T2U_N10_AD2P_66 from line 67 of ultra_no_connect_pins_nets AY26 = BULK_1V8 VCCO_67 from line 1066 of ultra_fpga_power_ground_nets AY27 = TBD_SPARE_LINK_2_DIR IO_L13P_T2L_N0_GC_QBC_67 from line 46 of rod_to_from_hub_spare_nets AY28 = TBD_SPARE_LINK_2_CMP IO_L13N_T2L_N1_GC_QBC_67 from line 47 of rod_to_from_hub_spare_nets AY29 = No_Conn_FPGA_AY29 IO_L15P_T2L_N4_AD11P_67 from line 130 of ultra_no_connect_pins_nets AY30 = No_Conn_FPGA_AY30 IO_L15N_T2L_N5_AD11N_67 from line 131 of ultra_no_connect_pins_nets AY31 = GROUND GND from line 721 of ultra_fpga_power_ground_nets AY32 = Phys_U21_RXD1__MODE1 IO_L15P_T2L_N4_AD11P_68 from line 42 of ultra_fpga_to_phys_chips_nets AY33 = Phys_U21_RXD3__MODE3 IO_L14N_T2L_N3_GC_68 from line 46 of ultra_fpga_to_phys_chips_nets AY34 = Phys_U22_CLK125__LED_MODE IO_L13P_T2L_N0_GC_QBC_68 from line 145 of ultra_fpga_to_phys_chips_nets AY35 = Phys_U21_TXD1 IO_L13N_T2L_N1_GC_QBC_68 from line 56 of ultra_fpga_to_phys_chips_nets AY36 = BULK_1V8 VCCO_68 from line 1077 of ultra_fpga_power_ground_nets AY37 = GROUND GND from line 722 of ultra_fpga_power_ground_nets AY38 = No_Conn_FPGA_AY38 NC from line 895 of ultra_no_connect_pins_nets AY39 = No_Conn_FPGA_AY39 NC from line 894 of ultra_no_connect_pins_nets AY40 = GROUND GND from line 723 of ultra_fpga_power_ground_nets AY41 = MGT_AVTT MGTAVTT_LS from line 1277 of ultra_fpga_power_ground_nets AY42 = GROUND GND from line 724 of ultra_fpga_power_ground_nets AY43 = No_Conn_FPGA_AY43 NC from line 896 of ultra_no_connect_pins_nets AY44 = No_Conn_FPGA_AY44 NC from line 897 of ultra_no_connect_pins_nets AY45 = GROUND GND from line 725 of ultra_fpga_power_ground_nets AY46 = GROUND GND from line 726 of ultra_fpga_power_ground_nets BA10 = GROUND GND from line 731 of ultra_fpga_power_ground_nets BA11 = SHELF_ADRS_7_TO_FPGA IO_L10P_T1U_N6_QBC_AD4P_94 from line 109 of hardware_address_to_rod_nets BA12 = SHELF_ADRS_6_TO_FPGA IO_L9N_T1L_N5_AD12N_94 from line 108 of hardware_address_to_rod_nets BA13 = BULK_3V3 VCCO_94 from line 1131 of ultra_fpga_power_ground_nets BA14 = SHELF_ADRS_2_TO_FPGA IO_L5P_T0U_N8_AD14P_94 from line 103 of hardware_address_to_rod_nets BA15 = I2C_Buf_1502_ENABLE IO_L1N_T0L_N1_DBC_94 from line 75 of i2c_sensor_bus_nets BA16 = I2C_Buf_1501_ENABLE IO_L3P_T0L_N4_AD15P_94 from line 74 of i2c_sensor_bus_nets BA17 = No_Conn_FPGA_BA17 IO_L6N_T0U_N11_AD6N_94 from line 206 of ultra_no_connect_pins_nets BA18 = GROUND GND from line 732 of ultra_fpga_power_ground_nets BA19 = FLASH_D14 IO_L17P_T2U_N8_AD10P_D14_65 from line 73 of bank_0_and_bank_65_config_mem_nets BA20 = FLASH_A05 IO_L14N_T2L_N3_GC_A05_D21_65 from line 89 of bank_0_and_bank_65_config_mem_nets BA21 = FLASH_A00 IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 from line 83 of bank_0_and_bank_65_config_mem_nets BA22 = No_Conn_FPGA_BA22 IO_L17P_T2U_N8_AD10P_66 from line 69 of ultra_no_connect_pins_nets BA23 = BULK_1V8 VCCO_66 from line 1054 of ultra_fpga_power_ground_nets BA24 = No_Conn_FPGA_BA24 IO_L16N_T2U_N7_QBC_AD3N_66 from line 72 of ultra_no_connect_pins_nets BA25 = No_Conn_FPGA_BA25 IO_L18N_T2U_N11_AD2N_66 from line 68 of ultra_no_connect_pins_nets BA26 = No_Conn_FPGA_BA26 IO_L17P_T2U_N8_AD10P_67 from line 126 of ultra_no_connect_pins_nets BA27 = No_Conn_FPGA_BA27 IO_L16P_T2U_N6_QBC_AD3P_67 from line 128 of ultra_no_connect_pins_nets BA28 = GROUND GND from line 733 of ultra_fpga_power_ground_nets BA29 = Hub_I2C_to_FPGA_SCL IO_L18P_T2U_N10_AD2P_67 from line 144 of i2c_sensor_bus_nets BA30 = Phys_U21_MDIO IO_T3U_N12_68 from line 74 of ultra_fpga_to_phys_chips_nets BA31 = Phys_U22_INT_B IO_L21P_T3L_N4_AD8P_68 from line 147 of ultra_fpga_to_phys_chips_nets BA32 = No_Conn_FPGA_BA32 IO_L15N_T2L_N5_AD11N_68 from line 164 of ultra_no_connect_pins_nets BA33 = BULK_1V8 VCCO_68 from line 1078 of ultra_fpga_power_ground_nets BA34 = Phys_U21_GTX_CLK IO_L16P_T2U_N6_QBC_AD3P_68 from line 64 of ultra_fpga_to_phys_chips_nets BA35 = Phys_U21_TXD3 IO_T2U_N12_68 from line 60 of ultra_fpga_to_phys_chips_nets BA36 = Phys_U21_TXD0 IO_L18P_T2U_N10_AD2P_68 from line 54 of ultra_fpga_to_phys_chips_nets BA37 = GROUND GND from line 734 of ultra_fpga_power_ground_nets BA38 = GROUND GND from line 735 of ultra_fpga_power_ground_nets BA39 = MGT_AVTT MGTAVTT_LS from line 1278 of ultra_fpga_power_ground_nets BA40 = No_Conn_FPGA_BA40 NC from line 901 of ultra_no_connect_pins_nets BA41 = No_Conn_FPGA_BA41 NC from line 900 of ultra_no_connect_pins_nets BA42 = GROUND GND from line 736 of ultra_fpga_power_ground_nets BA43 = GROUND GND from line 737 of ultra_fpga_power_ground_nets BA44 = GROUND GND from line 738 of ultra_fpga_power_ground_nets BA45 = No_Conn_FPGA_BA45 NC from line 902 of ultra_no_connect_pins_nets BA46 = No_Conn_FPGA_BA46 NC from line 903 of ultra_no_connect_pins_nets BB10 = GROUND GND from line 743 of ultra_fpga_power_ground_nets BB11 = SHELF_ADRS_5_TO_FPGA IO_L10N_T1U_N7_QBC_AD4N_94 from line 107 of hardware_address_to_rod_nets BB12 = SHELF_ADRS_4_TO_FPGA IO_L8N_T1L_N3_AD5N_94 from line 106 of hardware_address_to_rod_nets BB13 = SHELF_ADRS_3_TO_FPGA IO_L8P_T1L_N2_AD5P_94 from line 104 of hardware_address_to_rod_nets BB14 = SHELF_ADRS_1_TO_FPGA IO_L5N_T0U_N9_AD14N_94 from line 102 of hardware_address_to_rod_nets BB15 = SHELF_ADRS_0_TO_FPGA IO_L3N_T0L_N5_AD15N_94 from line 101 of hardware_address_to_rod_nets BB16 = I2C_Buf_1503_ENABLE IO_L4N_T0U_N7_DBC_AD7N_94 from line 76 of i2c_sensor_bus_nets BB17 = No_Conn_FPGA_BB17 IO_L4P_T0U_N6_DBC_AD7P_94 from line 208 of ultra_no_connect_pins_nets BB18 = FLASH_A02 IO_L15P_T2L_N4_AD11P_A02_D18_65 from line 85 of bank_0_and_bank_65_config_mem_nets BB19 = FLASH_D15 IO_L17N_T2U_N9_AD10N_D15_65 from line 74 of bank_0_and_bank_65_config_mem_nets BB20 = BULK_1V8 VCCO_65 from line 1043 of ultra_fpga_power_ground_nets BB21 = FLASH_A01 IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 from line 84 of bank_0_and_bank_65_config_mem_nets BB22 = No_Conn_FPGA_BB22 IO_L17N_T2U_N9_AD10N_66 from line 70 of ultra_no_connect_pins_nets BB23 = No_Conn_FPGA_BB23 IO_L19P_T3L_N0_DBC_AD9P_66 from line 65 of ultra_no_connect_pins_nets BB24 = No_Conn_FPGA_BB24 IO_L21P_T3L_N4_AD8P_66 from line 61 of ultra_no_connect_pins_nets BB25 = GROUND GND from line 744 of ultra_fpga_power_ground_nets BB26 = No_Conn_FPGA_BB26 IO_L17N_T2U_N9_AD10N_67 from line 127 of ultra_no_connect_pins_nets BB27 = No_Conn_FPGA_BB27 IO_L16N_T2U_N7_QBC_AD3N_67 from line 129 of ultra_no_connect_pins_nets BB28 = FPGA_RODs_SMBALERT_B IO_T2U_N12_67 from line 856 of power_supply_all_other_nets BB29 = Hub_I2C_to_FPGA_SDA IO_L18N_T2U_N11_AD2N_67 from line 145 of i2c_sensor_bus_nets BB30 = BULK_1V8 VCCO_68 from line 1079 of ultra_fpga_power_ground_nets BB31 = Phys_U21_RX_DV__CLK125_EN IO_L21N_T3L_N5_AD8N_68 from line 48 of ultra_fpga_to_phys_chips_nets BB32 = Phys_U21_MDC IO_L17P_T2U_N8_AD10P_68 from line 72 of ultra_fpga_to_phys_chips_nets BB33 = Phys_U21_RXD2__MODE2 IO_L17N_T2U_N9_AD10N_68 from line 44 of ultra_fpga_to_phys_chips_nets BB34 = Phys_U21_TX_EN IO_L16N_T2U_N7_QBC_AD3N_68 from line 62 of ultra_fpga_to_phys_chips_nets BB35 = GROUND GND from line 745 of ultra_fpga_power_ground_nets BB36 = Phys_U21_TXD2 IO_L18N_T2U_N11_AD2N_68 from line 58 of ultra_fpga_to_phys_chips_nets BB37 = GROUND GND from line 746 of ultra_fpga_power_ground_nets BB38 = No_Conn_FPGA_BB38 NC from line 905 of ultra_no_connect_pins_nets BB39 = No_Conn_FPGA_BB39 NC from line 904 of ultra_no_connect_pins_nets BB40 = MGT_AVTT MGTAVTT_LS from line 1279 of ultra_fpga_power_ground_nets BB41 = GROUND GND from line 747 of ultra_fpga_power_ground_nets BB42 = GROUND GND from line 748 of ultra_fpga_power_ground_nets BB43 = No_Conn_FPGA_BB43 NC from line 906 of ultra_no_connect_pins_nets BB44 = No_Conn_FPGA_BB44 NC from line 907 of ultra_no_connect_pins_nets BB45 = GROUND GND from line 749 of ultra_fpga_power_ground_nets BB46 = GROUND GND from line 750 of ultra_fpga_power_ground_nets BC10 = GROUND GND from line 755 of ultra_fpga_power_ground_nets BC11 = GROUND GND from line 756 of ultra_fpga_power_ground_nets BC12 = GROUND GND from line 757 of ultra_fpga_power_ground_nets BC13 = GROUND GND from line 758 of ultra_fpga_power_ground_nets BC14 = GROUND GND from line 759 of ultra_fpga_power_ground_nets BC15 = GROUND GND from line 760 of ultra_fpga_power_ground_nets BC16 = No_Conn_FPGA_BC16 IO_T0U_N12_94 from line 210 of ultra_no_connect_pins_nets BC17 = BULK_3V3 VCCO_94 from line 1132 of ultra_fpga_power_ground_nets BC18 = FLASH_A03 IO_L15N_T2L_N5_AD11N_A03_D19_65 from line 86 of bank_0_and_bank_65_config_mem_nets BC19 = FLASH_D13 IO_L18N_T2U_N11_AD2N_D13_65 from line 72 of bank_0_and_bank_65_config_mem_nets BC20 = FLASH_D12 IO_L18P_T2U_N10_AD2P_D12_65 from line 71 of bank_0_and_bank_65_config_mem_nets BC21 = NO_CONN_FPGA_BANK_65_BC21 IO_T2U_N12_CSI_ADV_B_65 from line 239 of bank_0_and_bank_65_config_mem_nets BC22 = GROUND GND from line 761 of ultra_fpga_power_ground_nets BC23 = No_Conn_FPGA_BC23 IO_L19N_T3L_N1_DBC_AD9N_66 from line 66 of ultra_no_connect_pins_nets BC24 = No_Conn_FPGA_BC24 IO_L21N_T3L_N5_AD8N_66 from line 62 of ultra_no_connect_pins_nets BC25 = No_Conn_FPGA_BC25 IO_L19P_T3L_N0_DBC_AD9P_67 from line 123 of ultra_no_connect_pins_nets BC26 = No_Conn_FPGA_BC26 IO_L21P_T3L_N4_AD8P_67 from line 120 of ultra_no_connect_pins_nets BC27 = BULK_1V8 VCCO_67 from line 1067 of ultra_fpga_power_ground_nets BC28 = No_Conn_FPGA_BC28 IO_L24P_T3U_N10_67 from line 116 of ultra_no_connect_pins_nets BC29 = No_Conn_FPGA_BC29 IO_L19P_T3L_N0_DBC_AD9P_68 from line 162 of ultra_no_connect_pins_nets BC30 = Phys_U21_INT_B IO_L19N_T3L_N1_DBC_AD9N_68 from line 84 of ultra_fpga_to_phys_chips_nets BC31 = Phys_U21_RXD0__MODE0 IO_L23P_T3U_N8_68 from line 40 of ultra_fpga_to_phys_chips_nets BC32 = GROUND GND from line 762 of ultra_fpga_power_ground_nets BC33 = GROUND GND from line 763 of ultra_fpga_power_ground_nets BC34 = GROUND GND from line 764 of ultra_fpga_power_ground_nets BC35 = GROUND GND from line 765 of ultra_fpga_power_ground_nets BC36 = GROUND GND from line 766 of ultra_fpga_power_ground_nets BC37 = GROUND GND from line 767 of ultra_fpga_power_ground_nets BC38 = MGT_AVTT MGTAVTT_LS from line 1280 of ultra_fpga_power_ground_nets BC39 = GROUND GND from line 768 of ultra_fpga_power_ground_nets BC40 = No_Conn_FPGA_BC40 NC from line 911 of ultra_no_connect_pins_nets BC41 = No_Conn_FPGA_BC41 NC from line 910 of ultra_no_connect_pins_nets BC42 = GROUND GND from line 769 of ultra_fpga_power_ground_nets BC43 = GROUND GND from line 770 of ultra_fpga_power_ground_nets BC44 = GROUND GND from line 771 of ultra_fpga_power_ground_nets BC45 = No_Conn_FPGA_BC45 NC from line 912 of ultra_no_connect_pins_nets BC46 = No_Conn_FPGA_BC46 NC from line 913 of ultra_no_connect_pins_nets BD10 = No_Conn_FPGA_BD10 NC from line 964 of ultra_no_connect_pins_nets BD11 = No_Conn_FPGA_BD11 NC from line 965 of ultra_no_connect_pins_nets BD12 = GROUND GND from line 776 of ultra_fpga_power_ground_nets BD13 = No_Conn_FPGA_BD13 NC from line 946 of ultra_no_connect_pins_nets BD14 = No_Conn_FPGA_BD14 NC from line 945 of ultra_no_connect_pins_nets BD15 = GROUND GND from line 777 of ultra_fpga_power_ground_nets BD16 = FLASH_D11 IO_L19N_T3L_N1_DBC_AD9N_D11_65 from line 69 of bank_0_and_bank_65_config_mem_nets BD17 = FLASH_D10 IO_L19P_T3L_N0_DBC_AD9P_D10_65 from line 68 of bank_0_and_bank_65_config_mem_nets BD18 = FLASH_D06 IO_L21P_T3L_N4_AD8P_D06_65 from line 63 of bank_0_and_bank_65_config_mem_nets BD19 = GROUND GND from line 778 of ultra_fpga_power_ground_nets BD20 = NO_CONN_FPGA_BANK_65_BD20 IO_T3U_N12_PERSTN0_65 from line 238 of bank_0_and_bank_65_config_mem_nets BD21 = No_Conn_FPGA_BD21 IO_T3U_N12_66 from line 56 of ultra_no_connect_pins_nets BD22 = No_Conn_FPGA_BD22 IO_L20P_T3L_N2_AD1P_66 from line 63 of ultra_no_connect_pins_nets BD23 = No_Conn_FPGA_BD23 IO_L23P_T3U_N8_66 from line 57 of ultra_no_connect_pins_nets BD24 = BULK_1V8 VCCO_66 from line 1055 of ultra_fpga_power_ground_nets BD25 = No_Conn_FPGA_BD25 IO_L19N_T3L_N1_DBC_AD9N_67 from line 124 of ultra_no_connect_pins_nets BD26 = No_Conn_FPGA_BD26 IO_L21N_T3L_N5_AD8N_67 from line 121 of ultra_no_connect_pins_nets BD27 = No_Conn_FPGA_BD27 IO_T3U_N12_67 from line 118 of ultra_no_connect_pins_nets BD28 = No_Conn_FPGA_BD28 IO_L24N_T3U_N11_67 from line 117 of ultra_no_connect_pins_nets BD29 = GROUND GND from line 779 of ultra_fpga_power_ground_nets BD30 = No_Conn_FPGA_BD30 IO_L20P_T3L_N2_AD1P_68 from line 160 of ultra_no_connect_pins_nets BD31 = No_Conn_FPGA_BD31 IO_L23N_T3U_N9_68 from line 158 of ultra_no_connect_pins_nets BD32 = GROUND GND from line 780 of ultra_fpga_power_ground_nets BD33 = No_Conn_FPGA_BD33 NC from line 886 of ultra_no_connect_pins_nets BD34 = No_Conn_FPGA_BD34 NC from line 887 of ultra_no_connect_pins_nets BD35 = GROUND GND from line 781 of ultra_fpga_power_ground_nets BD36 = No_Conn_FPGA_BD36 NC from line 882 of ultra_no_connect_pins_nets BD37 = No_Conn_FPGA_BD37 NC from line 883 of ultra_no_connect_pins_nets BD38 = No_Conn_FPGA_BD38 NC from line 873 of ultra_no_connect_pins_nets BD39 = No_Conn_FPGA_BD39 NC from line 872 of ultra_no_connect_pins_nets BD40 = GROUND GND from line 782 of ultra_fpga_power_ground_nets BD41 = MGT_AVTT MGTAVTT_LS from line 1281 of ultra_fpga_power_ground_nets BD42 = GROUND GND from line 783 of ultra_fpga_power_ground_nets BD43 = No_Conn_FPGA_BD43 NC from line 874 of ultra_no_connect_pins_nets BD44 = No_Conn_FPGA_BD44 NC from line 875 of ultra_no_connect_pins_nets BD45 = GROUND GND from line 784 of ultra_fpga_power_ground_nets BD46 = GROUND GND from line 785 of ultra_fpga_power_ground_nets BE10 = No_Conn_FPGA_BE10 NC from line 947 of ultra_no_connect_pins_nets BE11 = No_Conn_FPGA_BE11 NC from line 944 of ultra_no_connect_pins_nets BE12 = GROUND GND from line 791 of ultra_fpga_power_ground_nets BE13 = GROUND GND from line 792 of ultra_fpga_power_ground_nets BE14 = GROUND GND from line 793 of ultra_fpga_power_ground_nets BE15 = GROUND GND from line 794 of ultra_fpga_power_ground_nets BE16 = Hub_I2C_to_FPGA_SCL IO_L23P_T3U_N8_I2C_SCLK_65 from line 141 of i2c_sensor_bus_nets BE17 = FLASH_D08 IO_L20P_T3L_N2_AD1P_D08_65 from line 66 of bank_0_and_bank_65_config_mem_nets BE18 = FLASH_D07 IO_L21N_T3L_N5_AD8N_D07_65 from line 64 of bank_0_and_bank_65_config_mem_nets BE19 = FLASH_D04 IO_L22P_T3U_N6_DBC_AD0P_D04_65 from line 61 of bank_0_and_bank_65_config_mem_nets BE20 = NO_CONN_FPGA_BANK_65_BE20 IO_L24P_T3U_N10_EMCCLK_65 from line 236 of bank_0_and_bank_65_config_mem_nets BE21 = BULK_1V8 VCCO_66 from line 1056 of ultra_fpga_power_ground_nets BE22 = No_Conn_FPGA_BE22 IO_L20N_T3L_N3_AD1N_66 from line 64 of ultra_no_connect_pins_nets BE23 = No_Conn_FPGA_BE23 IO_L23N_T3U_N9_66 from line 58 of ultra_no_connect_pins_nets BE24 = No_Conn_FPGA_BE24 IO_L24P_T3U_N10_66 from line 54 of ultra_no_connect_pins_nets BE25 = OVERALL_ADRS_1_TO_RES_NET IO_L23P_T3U_N8_67 from line 128 of hardware_address_to_rod_nets BE26 = GROUND GND from line 795 of ultra_fpga_power_ground_nets BE27 = OVERALL_ADRS_3_TO_RES_NET IO_L22P_T3U_N6_DBC_AD0P_67 from line 130 of hardware_address_to_rod_nets BE28 = OVERALL_ADRS_5_TO_RES_NET IO_L22N_T3U_N7_DBC_AD0N_67 from line 133 of hardware_address_to_rod_nets BE29 = OVERALL_ADRS_6_TO_RES_NET IO_L22P_T3U_N6_DBC_AD0P_68 from line 134 of hardware_address_to_rod_nets BE30 = OVERALL_ADRS_7_TO_RES_NET IO_L20N_T3L_N3_AD1N_68 from line 135 of hardware_address_to_rod_nets BE31 = BULK_1V8 VCCO_68 from line 1080 of ultra_fpga_power_ground_nets BE32 = GROUND GND from line 796 of ultra_fpga_power_ground_nets BE33 = GROUND GND from line 797 of ultra_fpga_power_ground_nets BE34 = GROUND GND from line 798 of ultra_fpga_power_ground_nets BE35 = GROUND GND from line 799 of ultra_fpga_power_ground_nets BE36 = No_Conn_FPGA_BE36 NC from line 885 of ultra_no_connect_pins_nets BE37 = No_Conn_FPGA_BE37 NC from line 884 of ultra_no_connect_pins_nets BE38 = GROUND GND from line 800 of ultra_fpga_power_ground_nets BE39 = MGT_AVTT MGTAVTT_LS from line 1282 of ultra_fpga_power_ground_nets BE40 = No_Conn_FPGA_BE40 NC from line 879 of ultra_no_connect_pins_nets BE41 = No_Conn_FPGA_BE41 NC from line 878 of ultra_no_connect_pins_nets BE42 = GROUND GND from line 801 of ultra_fpga_power_ground_nets BE43 = GROUND GND from line 802 of ultra_fpga_power_ground_nets BE44 = GROUND GND from line 803 of ultra_fpga_power_ground_nets BE45 = GROUND GND from line 804 of ultra_fpga_power_ground_nets BF10 = MGT_AVTT MGTAVTT_RS from line 1344 of ultra_fpga_power_ground_nets BF11 = GROUND GND from line 807 of ultra_fpga_power_ground_nets BF12 = GROUND GND from line 808 of ultra_fpga_power_ground_nets BF13 = No_Conn_FPGA_BF13 NC from line 952 of ultra_no_connect_pins_nets BF14 = No_Conn_FPGA_BF14 NC from line 951 of ultra_no_connect_pins_nets BF15 = GROUND GND from line 809 of ultra_fpga_power_ground_nets BF16 = Hub_I2C_to_FPGA_SDA IO_L23N_T3U_N9_I2C_SDA_65 from line 142 of i2c_sensor_bus_nets BF17 = FLASH_D09 IO_L20N_T3L_N3_AD1N_D09_65 from line 67 of bank_0_and_bank_65_config_mem_nets BF18 = BULK_1V8 VCCO_65 from line 1044 of ultra_fpga_power_ground_nets BF19 = FLASH_D05 IO_L22N_T3U_N7_DBC_AD0N_D05_65 from line 62 of bank_0_and_bank_65_config_mem_nets BF20 = NO_CONN_FPGA_BANK_65_BF20 IO_L24N_T3U_N11_DOUT_CSO_B_65 from line 237 of bank_0_and_bank_65_config_mem_nets BF21 = No_Conn_FPGA_BF21 IO_L22P_T3U_N6_DBC_AD0P_66 from line 59 of ultra_no_connect_pins_nets BF22 = No_Conn_FPGA_BF22 IO_L22N_T3U_N7_DBC_AD0N_66 from line 60 of ultra_no_connect_pins_nets BF23 = GROUND GND from line 810 of ultra_fpga_power_ground_nets BF24 = No_Conn_FPGA_BF24 IO_L24N_T3U_N11_66 from line 55 of ultra_no_connect_pins_nets BF25 = OVERALL_ADRS_0_TO_RES_NET IO_L23N_T3U_N9_67 from line 127 of hardware_address_to_rod_nets BF26 = OVERALL_ADRS_2_TO_RES_NET IO_L20P_T3L_N2_AD1P_67 from line 129 of hardware_address_to_rod_nets BF27 = OVERALL_ADRS_4_TO_RES_NET IO_L20N_T3L_N3_AD1N_67 from line 132 of hardware_address_to_rod_nets BF28 = BULK_1V8 VCCO_67 from line 1068 of ultra_fpga_power_ground_nets BF29 = HUB_FPGA_LED50_DRV IO_L22N_T3U_N7_DBC_AD0N_68 from line 205 of led_lemo_translator_driver_nets BF30 = HUB_FPGA_LED51_DRV IO_L24P_T3U_N10_68 from line 206 of led_lemo_translator_driver_nets BF31 = HUB_FPGA_LED52_DRV IO_L24N_T3U_N11_68 from line 207 of led_lemo_translator_driver_nets BF32 = GROUND GND from line 811 of ultra_fpga_power_ground_nets BF33 = No_Conn_FPGA_BF33 NC from line 892 of ultra_no_connect_pins_nets BF34 = No_Conn_FPGA_BF34 NC from line 893 of ultra_no_connect_pins_nets BF35 = GROUND GND from line 812 of ultra_fpga_power_ground_nets BF36 = GROUND GND from line 813 of ultra_fpga_power_ground_nets BF37 = MGT_AVTT MGTAVTT_LS from line 1283 of ultra_fpga_power_ground_nets BF38 = No_Conn_FPGA_BF38 NC from line 891 of ultra_no_connect_pins_nets BF39 = No_Conn_FPGA_BF39 NC from line 890 of ultra_no_connect_pins_nets BF40 = MGT_AVTT MGTAVTT_LS from line 1284 of ultra_fpga_power_ground_nets BF41 = GROUND GND from line 814 of ultra_fpga_power_ground_nets BF42 = GROUND GND from line 815 of ultra_fpga_power_ground_nets BF43 = No_Conn_FPGA_BF43 NC from line 880 of ultra_no_connect_pins_nets BF44 = No_Conn_FPGA_BF44 NC from line 881 of ultra_no_connect_pins_nets ------------------------------------------------------ Pins sorted by Net Name AT30 = ACCESS_SIGNAL_1_FROM_FPGA IO_L10P_T1U_N6_QBC_AD4P_67 from line 100 of sundry_hub_nets AT31 = ACCESS_SIGNAL_2_FROM_FPGA IO_L10N_T1U_N7_QBC_AD4N_67 from line 101 of sundry_hub_nets AM16 = ALL_HUB_POWER_GOOD_TO_FPGA IO_T3U_N12_84 from line 433 of power_supply_all_other_nets P32 = BULK_1V8 VCCAUX from line 982 of ultra_fpga_power_ground_nets T32 = BULK_1V8 VCCAUX from line 983 of ultra_fpga_power_ground_nets V32 = BULK_1V8 VCCAUX from line 984 of ultra_fpga_power_ground_nets Y32 = BULK_1V8 VCCAUX from line 985 of ultra_fpga_power_ground_nets AB32 = BULK_1V8 VCCAUX from line 986 of ultra_fpga_power_ground_nets AC31 = BULK_1V8 VCCAUX from line 987 of ultra_fpga_power_ground_nets AD32 = BULK_1V8 VCCAUX from line 988 of ultra_fpga_power_ground_nets AE31 = BULK_1V8 VCCAUX from line 989 of ultra_fpga_power_ground_nets AF32 = BULK_1V8 VCCAUX from line 990 of ultra_fpga_power_ground_nets AH32 = BULK_1V8 VCCAUX from line 991 of ultra_fpga_power_ground_nets AK32 = BULK_1V8 VCCAUX from line 992 of ultra_fpga_power_ground_nets R31 = BULK_1V8 VCCAUX_IO from line 1004 of ultra_fpga_power_ground_nets U31 = BULK_1V8 VCCAUX_IO from line 1005 of ultra_fpga_power_ground_nets W31 = BULK_1V8 VCCAUX_IO from line 1006 of ultra_fpga_power_ground_nets Y30 = BULK_1V8 VCCAUX_IO from line 1007 of ultra_fpga_power_ground_nets AA31 = BULK_1V8 VCCAUX_IO from line 1008 of ultra_fpga_power_ground_nets AB30 = BULK_1V8 VCCAUX_IO from line 1009 of ultra_fpga_power_ground_nets AD30 = BULK_1V8 VCCAUX_IO from line 1010 of ultra_fpga_power_ground_nets AF30 = BULK_1V8 VCCAUX_IO from line 1011 of ultra_fpga_power_ground_nets AG31 = BULK_1V8 VCCAUX_IO from line 1012 of ultra_fpga_power_ground_nets AH30 = BULK_1V8 VCCAUX_IO from line 1013 of ultra_fpga_power_ground_nets AJ31 = BULK_1V8 VCCAUX_IO from line 1014 of ultra_fpga_power_ground_nets AK30 = BULK_1V8 VCCAUX_IO from line 1015 of ultra_fpga_power_ground_nets AL31 = BULK_1V8 VCCAUX_IO from line 1016 of ultra_fpga_power_ground_nets AC15 = BULK_1V8 VCCO_0 from line 1032 of ultra_fpga_power_ground_nets AE15 = BULK_1V8 VCCO_0 from line 1033 of ultra_fpga_power_ground_nets AM20 = BULK_1V8 VCCO_65 from line 1039 of ultra_fpga_power_ground_nets AR21 = BULK_1V8 VCCO_65 from line 1040 of ultra_fpga_power_ground_nets AT18 = BULK_1V8 VCCO_65 from line 1041 of ultra_fpga_power_ground_nets AW19 = BULK_1V8 VCCO_65 from line 1042 of ultra_fpga_power_ground_nets BB20 = BULK_1V8 VCCO_65 from line 1043 of ultra_fpga_power_ground_nets BF18 = BULK_1V8 VCCO_65 from line 1044 of ultra_fpga_power_ground_nets AN27 = BULK_1V8 VCCO_66 from line 1050 of ultra_fpga_power_ground_nets AP24 = BULK_1V8 VCCO_66 from line 1051 of ultra_fpga_power_ground_nets AU25 = BULK_1V8 VCCO_66 from line 1052 of ultra_fpga_power_ground_nets AV22 = BULK_1V8 VCCO_66 from line 1053 of ultra_fpga_power_ground_nets BA23 = BULK_1V8 VCCO_66 from line 1054 of ultra_fpga_power_ground_nets BD24 = BULK_1V8 VCCO_66 from line 1055 of ultra_fpga_power_ground_nets BE21 = BULK_1V8 VCCO_66 from line 1056 of ultra_fpga_power_ground_nets AM30 = BULK_1V8 VCCO_67 from line 1062 of ultra_fpga_power_ground_nets AR31 = BULK_1V8 VCCO_67 from line 1063 of ultra_fpga_power_ground_nets AT28 = BULK_1V8 VCCO_67 from line 1064 of ultra_fpga_power_ground_nets AW29 = BULK_1V8 VCCO_67 from line 1065 of ultra_fpga_power_ground_nets AY26 = BULK_1V8 VCCO_67 from line 1066 of ultra_fpga_power_ground_nets BC27 = BULK_1V8 VCCO_67 from line 1067 of ultra_fpga_power_ground_nets BF28 = BULK_1V8 VCCO_67 from line 1068 of ultra_fpga_power_ground_nets AP34 = BULK_1V8 VCCO_68 from line 1074 of ultra_fpga_power_ground_nets AU35 = BULK_1V8 VCCO_68 from line 1075 of ultra_fpga_power_ground_nets AV32 = BULK_1V8 VCCO_68 from line 1076 of ultra_fpga_power_ground_nets AY36 = BULK_1V8 VCCO_68 from line 1077 of ultra_fpga_power_ground_nets BA33 = BULK_1V8 VCCO_68 from line 1078 of ultra_fpga_power_ground_nets BB30 = BULK_1V8 VCCO_68 from line 1079 of ultra_fpga_power_ground_nets BE31 = BULK_1V8 VCCO_68 from line 1080 of ultra_fpga_power_ground_nets A27 = BULK_1V8 VCCO_70 from line 1086 of ultra_fpga_power_ground_nets D28 = BULK_1V8 VCCO_70 from line 1087 of ultra_fpga_power_ground_nets G29 = BULK_1V8 VCCO_70 from line 1088 of ultra_fpga_power_ground_nets H26 = BULK_1V8 VCCO_70 from line 1089 of ultra_fpga_power_ground_nets K30 = BULK_1V8 VCCO_70 from line 1090 of ultra_fpga_power_ground_nets L27 = BULK_1V8 VCCO_70 from line 1091 of ultra_fpga_power_ground_nets N31 = BULK_1V8 VCCO_70 from line 1092 of ultra_fpga_power_ground_nets B24 = BULK_1V8 VCCO_71 from line 1098 of ultra_fpga_power_ground_nets E25 = BULK_1V8 VCCO_71 from line 1099 of ultra_fpga_power_ground_nets F22 = BULK_1V8 VCCO_71 from line 1100 of ultra_fpga_power_ground_nets J23 = BULK_1V8 VCCO_71 from line 1101 of ultra_fpga_power_ground_nets M24 = BULK_1V8 VCCO_71 from line 1102 of ultra_fpga_power_ground_nets N21 = BULK_1V8 VCCO_71 from line 1103 of ultra_fpga_power_ground_nets C21 = BULK_1V8 VCCO_72 from line 1109 of ultra_fpga_power_ground_nets D18 = BULK_1V8 VCCO_72 from line 1110 of ultra_fpga_power_ground_nets G19 = BULK_1V8 VCCO_72 from line 1111 of ultra_fpga_power_ground_nets K20 = BULK_1V8 VCCO_72 from line 1112 of ultra_fpga_power_ground_nets L17 = BULK_1V8 VCCO_72 from line 1113 of ultra_fpga_power_ground_nets P18 = BULK_1V8 VCCO_72 from line 1114 of ultra_fpga_power_ground_nets AN17 = BULK_3V3 VCCO_84 from line 1120 of ultra_fpga_power_ground_nets AP14 = BULK_3V3 VCCO_84 from line 1121 of ultra_fpga_power_ground_nets AR11 = BULK_3V3 VCCO_84 from line 1122 of ultra_fpga_power_ground_nets AU15 = BULK_3V3 VCCO_84 from line 1123 of ultra_fpga_power_ground_nets AV12 = BULK_3V3 VCCO_94 from line 1129 of ultra_fpga_power_ground_nets AY16 = BULK_3V3 VCCO_94 from line 1130 of ultra_fpga_power_ground_nets BA13 = BULK_3V3 VCCO_94 from line 1131 of ultra_fpga_power_ground_nets BC17 = BULK_3V3 VCCO_94 from line 1132 of ultra_fpga_power_ground_nets AM18 = Bank_65_VREF VREF_65 from line 75 of ultra_dci_vref_mgt_calib_resistors_nets AP21 = Bank_65_VRP_DCI IO_T0U_N12_VRP_A28_65 from line 38 of ultra_dci_vref_mgt_calib_resistors_nets AM22 = Bank_66_VREF VREF_66 from line 78 of ultra_dci_vref_mgt_calib_resistors_nets AM27 = Bank_66_VRP_DCI IO_T0U_N12_VRP_66 from line 41 of ultra_dci_vref_mgt_calib_resistors_nets AM28 = Bank_67_VREF VREF_67 from line 81 of ultra_dci_vref_mgt_calib_resistors_nets AP31 = Bank_67_VRP_DCI IO_T0U_N12_VRP_67 from line 44 of ultra_dci_vref_mgt_calib_resistors_nets AM32 = Bank_68_VREF VREF_68 from line 84 of ultra_dci_vref_mgt_calib_resistors_nets AU36 = Bank_68_VRP_DCI IO_T0U_N12_VRP_68 from line 47 of ultra_dci_vref_mgt_calib_resistors_nets P21 = Bank_71_VREF VREF_71 from line 88 of ultra_dci_vref_mgt_calib_resistors_nets P22 = Bank_71_VRP_DCI IO_T0U_N12_VRP_71 from line 50 of ultra_dci_vref_mgt_calib_resistors_nets AM17 = Bank_84_VREF VREF_84 from line 92 of ultra_dci_vref_mgt_calib_resistors_nets AW16 = Bank_94_VREF VREF_94 from line 95 of ultra_dci_vref_mgt_calib_resistors_nets M14 = CFGBVS CFGBVS_0 from line 188 of bank_0_and_bank_65_config_mem_nets AT15 = CLOCK_25_MHz_FPGA IO_L14P_T2L_N2_GC_84 from line 112 of clock_generation_nets Y14 = CONFIG_M0 M0_0 from line 171 of bank_0_and_bank_65_config_mem_nets V14 = CONFIG_M1 M1_0 from line 172 of bank_0_and_bank_65_config_mem_nets T14 = CONFIG_M2 M2_0 from line 173 of bank_0_and_bank_65_config_mem_nets N41 = Comb_Data_to_Cap_to_FEX_03_Cmp MGTYTXN2_129 from line 91 of combined_data_distribution_nets N40 = Comb_Data_to_Cap_to_FEX_03_Dir MGTYTXP2_129 from line 90 of combined_data_distribution_nets L41 = Comb_Data_to_Cap_to_FEX_04_Cmp MGTYTXN0_130 from line 86 of combined_data_distribution_nets L40 = Comb_Data_to_Cap_to_FEX_04_Dir MGTYTXP0_130 from line 85 of combined_data_distribution_nets J41 = Comb_Data_to_Cap_to_FEX_05_Cmp MGTYTXN2_130 from line 83 of combined_data_distribution_nets J40 = Comb_Data_to_Cap_to_FEX_05_Dir MGTYTXP2_130 from line 82 of combined_data_distribution_nets A41 = Comb_Data_to_Cap_to_FEX_06_Cmp MGTYTXN3_132 from line 78 of combined_data_distribution_nets A40 = Comb_Data_to_Cap_to_FEX_06_Dir MGTYTXP3_132 from line 77 of combined_data_distribution_nets B39 = Comb_Data_to_Cap_to_FEX_07_Cmp MGTYTXN2_133 from line 73 of combined_data_distribution_nets B38 = Comb_Data_to_Cap_to_FEX_07_Dir MGTYTXP2_133 from line 72 of combined_data_distribution_nets A37 = Comb_Data_to_Cap_to_FEX_08_Cmp MGTYTXN3_133 from line 70 of combined_data_distribution_nets A36 = Comb_Data_to_Cap_to_FEX_08_Dir MGTYTXP3_133 from line 69 of combined_data_distribution_nets A11 = Comb_Data_to_Cap_to_FEX_09_Cmp MGTHTXP3_233 from line 62 of combined_data_distribution_nets A10 = Comb_Data_to_Cap_to_FEX_09_Dir MGTHTXN3_233 from line 63 of combined_data_distribution_nets B9 = Comb_Data_to_Cap_to_FEX_10_Cmp MGTHTXP2_233 from line 59 of combined_data_distribution_nets B8 = Comb_Data_to_Cap_to_FEX_10_Dir MGTHTXN2_233 from line 60 of combined_data_distribution_nets A7 = Comb_Data_to_Cap_to_FEX_11_Cmp MGTHTXP3_232 from line 54 of combined_data_distribution_nets A6 = Comb_Data_to_Cap_to_FEX_11_Dir MGTHTXN3_232 from line 55 of combined_data_distribution_nets J7 = Comb_Data_to_Cap_to_FEX_12_Cmp MGTHTXP2_230 from line 50 of combined_data_distribution_nets J6 = Comb_Data_to_Cap_to_FEX_12_Dir MGTHTXN2_230 from line 49 of combined_data_distribution_nets L7 = Comb_Data_to_Cap_to_FEX_13_Cmp MGTHTXP0_230 from line 47 of combined_data_distribution_nets L6 = Comb_Data_to_Cap_to_FEX_13_Dir MGTHTXN0_230 from line 46 of combined_data_distribution_nets N7 = Comb_Data_to_Cap_to_FEX_14_Cmp MGTHTXP2_229 from line 42 of combined_data_distribution_nets N6 = Comb_Data_to_Cap_to_FEX_14_Dir MGTHTXN2_229 from line 41 of combined_data_distribution_nets R41 = Comb_Data_to_Cap_to_Other_Hub_Cmp MGTYTXN0_129 from line 94 of combined_data_distribution_nets R40 = Comb_Data_to_Cap_to_Other_Hub_Dir MGTYTXP0_129 from line 93 of combined_data_distribution_nets W6 = Comb_Data_to_Cap_to_ROD_Cmp MGTHTXN0_228 from line 36 of combined_data_distribution_nets W7 = Comb_Data_to_Cap_to_ROD_Dir MGTHTXP0_228 from line 37 of combined_data_distribution_nets AP43 = Combined_Data_from_OTHER_Hub_Cmp MGTYRXP1_124 from line 76 of hub_all_other_mgt_nets AP44 = Combined_Data_from_OTHER_Hub_Dir MGTYRXN1_124 from line 75 of hub_all_other_mgt_nets BA21 = FLASH_A00 IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 from line 83 of bank_0_and_bank_65_config_mem_nets BB21 = FLASH_A01 IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 from line 84 of bank_0_and_bank_65_config_mem_nets BB18 = FLASH_A02 IO_L15P_T2L_N4_AD11P_A02_D18_65 from line 85 of bank_0_and_bank_65_config_mem_nets BC18 = FLASH_A03 IO_L15N_T2L_N5_AD11N_A03_D19_65 from line 86 of bank_0_and_bank_65_config_mem_nets AY20 = FLASH_A04 IO_L14P_T2L_N2_GC_A04_D20_65 from line 88 of bank_0_and_bank_65_config_mem_nets BA20 = FLASH_A05 IO_L14N_T2L_N3_GC_A05_D21_65 from line 89 of bank_0_and_bank_65_config_mem_nets AY19 = FLASH_A06 IO_L13P_T2L_N0_GC_QBC_A06_D22_65 from line 90 of bank_0_and_bank_65_config_mem_nets AY18 = FLASH_A07 IO_L13N_T2L_N1_GC_QBC_A07_D23_65 from line 91 of bank_0_and_bank_65_config_mem_nets AV20 = FLASH_A08 IO_L12P_T1U_N10_GC_A08_D24_65 from line 93 of bank_0_and_bank_65_config_mem_nets AW20 = FLASH_A09 IO_L12N_T1U_N11_GC_A09_D25_65 from line 94 of bank_0_and_bank_65_config_mem_nets AW18 = FLASH_A10 IO_L11P_T1U_N8_GC_A10_D26_65 from line 95 of bank_0_and_bank_65_config_mem_nets AW17 = FLASH_A11 IO_L11N_T1U_N9_GC_A11_D27_65 from line 96 of bank_0_and_bank_65_config_mem_nets AV21 = FLASH_A12 IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 from line 98 of bank_0_and_bank_65_config_mem_nets AW21 = FLASH_A13 IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 from line 99 of bank_0_and_bank_65_config_mem_nets AU18 = FLASH_A14 IO_L9P_T1L_N4_AD12P_A14_D30_65 from line 100 of bank_0_and_bank_65_config_mem_nets AV18 = FLASH_A15 IO_L9N_T1L_N5_AD12N_A15_D31_65 from line 101 of bank_0_and_bank_65_config_mem_nets AT21 = FLASH_A16 IO_L8P_T1L_N2_AD5P_A16_65 from line 103 of bank_0_and_bank_65_config_mem_nets AU21 = FLASH_A17 IO_L8N_T1L_N3_AD5N_A17_65 from line 104 of bank_0_and_bank_65_config_mem_nets AT19 = FLASH_A18 IO_L7P_T1L_N0_QBC_AD13P_A18_65 from line 105 of bank_0_and_bank_65_config_mem_nets AU19 = FLASH_A19 IO_L7N_T1L_N1_QBC_AD13N_A19_65 from line 106 of bank_0_and_bank_65_config_mem_nets AR20 = FLASH_A20 IO_L6P_T0U_N10_AD6P_A20_65 from line 108 of bank_0_and_bank_65_config_mem_nets AT20 = FLASH_A21 IO_L6N_T0U_N11_AD6N_A21_65 from line 109 of bank_0_and_bank_65_config_mem_nets AR19 = FLASH_A22 IO_L5P_T0U_N8_AD14P_A22_65 from line 110 of bank_0_and_bank_65_config_mem_nets AR18 = FLASH_A23 IO_L5N_T0U_N9_AD14N_A23_65 from line 111 of bank_0_and_bank_65_config_mem_nets AM21 = FLASH_A24 IO_L4P_T0U_N6_DBC_AD7P_A24_65 from line 113 of bank_0_and_bank_65_config_mem_nets AN21 = FLASH_A25 IO_L4N_T0U_N7_DBC_AD7N_A25_65 from line 114 of bank_0_and_bank_65_config_mem_nets AF14 = FLASH_CHIP_ENB_B RDWR_FCS_B_0 from line 128 of bank_0_and_bank_65_config_mem_nets AM14 = FLASH_D00 D00_MOSI_0 from line 56 of bank_0_and_bank_65_config_mem_nets AK14 = FLASH_D01 D01_DIN_0 from line 57 of bank_0_and_bank_65_config_mem_nets AF16 = FLASH_D02 D02_0 from line 58 of bank_0_and_bank_65_config_mem_nets AH14 = FLASH_D03 D03_0 from line 59 of bank_0_and_bank_65_config_mem_nets BE19 = FLASH_D04 IO_L22P_T3U_N6_DBC_AD0P_D04_65 from line 61 of bank_0_and_bank_65_config_mem_nets BF19 = FLASH_D05 IO_L22N_T3U_N7_DBC_AD0N_D05_65 from line 62 of bank_0_and_bank_65_config_mem_nets BD18 = FLASH_D06 IO_L21P_T3L_N4_AD8P_D06_65 from line 63 of bank_0_and_bank_65_config_mem_nets BE18 = FLASH_D07 IO_L21N_T3L_N5_AD8N_D07_65 from line 64 of bank_0_and_bank_65_config_mem_nets BE17 = FLASH_D08 IO_L20P_T3L_N2_AD1P_D08_65 from line 66 of bank_0_and_bank_65_config_mem_nets BF17 = FLASH_D09 IO_L20N_T3L_N3_AD1N_D09_65 from line 67 of bank_0_and_bank_65_config_mem_nets BD17 = FLASH_D10 IO_L19P_T3L_N0_DBC_AD9P_D10_65 from line 68 of bank_0_and_bank_65_config_mem_nets BD16 = FLASH_D11 IO_L19N_T3L_N1_DBC_AD9N_D11_65 from line 69 of bank_0_and_bank_65_config_mem_nets BC20 = FLASH_D12 IO_L18P_T2U_N10_AD2P_D12_65 from line 71 of bank_0_and_bank_65_config_mem_nets BC19 = FLASH_D13 IO_L18N_T2U_N11_AD2N_D13_65 from line 72 of bank_0_and_bank_65_config_mem_nets BA19 = FLASH_D14 IO_L17P_T2U_N8_AD10P_D14_65 from line 73 of bank_0_and_bank_65_config_mem_nets BB19 = FLASH_D15 IO_L17N_T2U_N9_AD10N_D15_65 from line 74 of bank_0_and_bank_65_config_mem_nets AN20 = FLASH_OUTPUT_ENB_B IO_L2P_T0L_N2_FOE_B_65 from line 132 of bank_0_and_bank_65_config_mem_nets P14 = FLASH_RESET_B INIT_B_0 from line 126 of bank_0_and_bank_65_config_mem_nets AP20 = FLASH_WRITE_ENB_B IO_L2N_T0L_N3_FWE_FCS2_B_65 from line 130 of bank_0_and_bank_65_config_mem_nets V16 = FPGA_CORE VCCBRAM from line 963 of ultra_fpga_power_ground_nets W15 = FPGA_CORE VCCBRAM from line 964 of ultra_fpga_power_ground_nets W17 = FPGA_CORE VCCBRAM from line 965 of ultra_fpga_power_ground_nets Y16 = FPGA_CORE VCCBRAM from line 966 of ultra_fpga_power_ground_nets AA17 = FPGA_CORE VCCBRAM from line 967 of ultra_fpga_power_ground_nets AC17 = FPGA_CORE VCCBRAM from line 968 of ultra_fpga_power_ground_nets AE17 = FPGA_CORE VCCBRAM from line 969 of ultra_fpga_power_ground_nets AG17 = FPGA_CORE VCCBRAM from line 970 of ultra_fpga_power_ground_nets P26 = FPGA_CORE VCCINT from line 827 of ultra_fpga_power_ground_nets P28 = FPGA_CORE VCCINT from line 828 of ultra_fpga_power_ground_nets R15 = FPGA_CORE VCCINT from line 829 of ultra_fpga_power_ground_nets R17 = FPGA_CORE VCCINT from line 830 of ultra_fpga_power_ground_nets R19 = FPGA_CORE VCCINT from line 831 of ultra_fpga_power_ground_nets R21 = FPGA_CORE VCCINT from line 832 of ultra_fpga_power_ground_nets R23 = FPGA_CORE VCCINT from line 833 of ultra_fpga_power_ground_nets R25 = FPGA_CORE VCCINT from line 834 of ultra_fpga_power_ground_nets R27 = FPGA_CORE VCCINT from line 835 of ultra_fpga_power_ground_nets R29 = FPGA_CORE VCCINT from line 836 of ultra_fpga_power_ground_nets T16 = FPGA_CORE VCCINT from line 837 of ultra_fpga_power_ground_nets T18 = FPGA_CORE VCCINT from line 838 of ultra_fpga_power_ground_nets T20 = FPGA_CORE VCCINT from line 839 of ultra_fpga_power_ground_nets T22 = FPGA_CORE VCCINT from line 840 of ultra_fpga_power_ground_nets T24 = FPGA_CORE VCCINT from line 841 of ultra_fpga_power_ground_nets T26 = FPGA_CORE VCCINT from line 842 of ultra_fpga_power_ground_nets T28 = FPGA_CORE VCCINT from line 843 of ultra_fpga_power_ground_nets U15 = FPGA_CORE VCCINT from line 844 of ultra_fpga_power_ground_nets U17 = FPGA_CORE VCCINT from line 845 of ultra_fpga_power_ground_nets U19 = FPGA_CORE VCCINT from line 846 of ultra_fpga_power_ground_nets U21 = FPGA_CORE VCCINT from line 847 of ultra_fpga_power_ground_nets U23 = FPGA_CORE VCCINT from line 848 of ultra_fpga_power_ground_nets U25 = FPGA_CORE VCCINT from line 849 of ultra_fpga_power_ground_nets U27 = FPGA_CORE VCCINT from line 850 of ultra_fpga_power_ground_nets U29 = FPGA_CORE VCCINT from line 851 of ultra_fpga_power_ground_nets V18 = FPGA_CORE VCCINT from line 852 of ultra_fpga_power_ground_nets V20 = FPGA_CORE VCCINT from line 853 of ultra_fpga_power_ground_nets V22 = FPGA_CORE VCCINT from line 854 of ultra_fpga_power_ground_nets V24 = FPGA_CORE VCCINT from line 855 of ultra_fpga_power_ground_nets V26 = FPGA_CORE VCCINT from line 856 of ultra_fpga_power_ground_nets V28 = FPGA_CORE VCCINT from line 857 of ultra_fpga_power_ground_nets W19 = FPGA_CORE VCCINT from line 858 of ultra_fpga_power_ground_nets W21 = FPGA_CORE VCCINT from line 859 of ultra_fpga_power_ground_nets W23 = FPGA_CORE VCCINT from line 860 of ultra_fpga_power_ground_nets W25 = FPGA_CORE VCCINT from line 861 of ultra_fpga_power_ground_nets W27 = FPGA_CORE VCCINT from line 862 of ultra_fpga_power_ground_nets W29 = FPGA_CORE VCCINT from line 863 of ultra_fpga_power_ground_nets Y18 = FPGA_CORE VCCINT from line 864 of ultra_fpga_power_ground_nets Y20 = FPGA_CORE VCCINT from line 865 of ultra_fpga_power_ground_nets Y22 = FPGA_CORE VCCINT from line 866 of ultra_fpga_power_ground_nets Y24 = FPGA_CORE VCCINT from line 867 of ultra_fpga_power_ground_nets Y26 = FPGA_CORE VCCINT from line 868 of ultra_fpga_power_ground_nets Y28 = FPGA_CORE VCCINT from line 869 of ultra_fpga_power_ground_nets AA19 = FPGA_CORE VCCINT from line 870 of ultra_fpga_power_ground_nets AA21 = FPGA_CORE VCCINT from line 871 of ultra_fpga_power_ground_nets AA23 = FPGA_CORE VCCINT from line 872 of ultra_fpga_power_ground_nets AA25 = FPGA_CORE VCCINT from line 873 of ultra_fpga_power_ground_nets AA27 = FPGA_CORE VCCINT from line 874 of ultra_fpga_power_ground_nets AB18 = FPGA_CORE VCCINT from line 875 of ultra_fpga_power_ground_nets AB22 = FPGA_CORE VCCINT from line 876 of ultra_fpga_power_ground_nets AB24 = FPGA_CORE VCCINT from line 877 of ultra_fpga_power_ground_nets AB26 = FPGA_CORE VCCINT from line 878 of ultra_fpga_power_ground_nets AB28 = FPGA_CORE VCCINT from line 879 of ultra_fpga_power_ground_nets AC21 = FPGA_CORE VCCINT from line 880 of ultra_fpga_power_ground_nets AC23 = FPGA_CORE VCCINT from line 881 of ultra_fpga_power_ground_nets AC25 = FPGA_CORE VCCINT from line 882 of ultra_fpga_power_ground_nets AC27 = FPGA_CORE VCCINT from line 883 of ultra_fpga_power_ground_nets AD18 = FPGA_CORE VCCINT from line 884 of ultra_fpga_power_ground_nets AD22 = FPGA_CORE VCCINT from line 885 of ultra_fpga_power_ground_nets AD24 = FPGA_CORE VCCINT from line 886 of ultra_fpga_power_ground_nets AD26 = FPGA_CORE VCCINT from line 887 of ultra_fpga_power_ground_nets AD28 = FPGA_CORE VCCINT from line 888 of ultra_fpga_power_ground_nets AE21 = FPGA_CORE VCCINT from line 889 of ultra_fpga_power_ground_nets AE23 = FPGA_CORE VCCINT from line 890 of ultra_fpga_power_ground_nets AE25 = FPGA_CORE VCCINT from line 891 of ultra_fpga_power_ground_nets AE27 = FPGA_CORE VCCINT from line 892 of ultra_fpga_power_ground_nets AF18 = FPGA_CORE VCCINT from line 893 of ultra_fpga_power_ground_nets AF20 = FPGA_CORE VCCINT from line 894 of ultra_fpga_power_ground_nets AF22 = FPGA_CORE VCCINT from line 895 of ultra_fpga_power_ground_nets AF24 = FPGA_CORE VCCINT from line 896 of ultra_fpga_power_ground_nets AF26 = FPGA_CORE VCCINT from line 897 of ultra_fpga_power_ground_nets AF28 = FPGA_CORE VCCINT from line 898 of ultra_fpga_power_ground_nets AG19 = FPGA_CORE VCCINT from line 899 of ultra_fpga_power_ground_nets AG21 = FPGA_CORE VCCINT from line 900 of ultra_fpga_power_ground_nets AG23 = FPGA_CORE VCCINT from line 901 of ultra_fpga_power_ground_nets AG25 = FPGA_CORE VCCINT from line 902 of ultra_fpga_power_ground_nets AG27 = FPGA_CORE VCCINT from line 903 of ultra_fpga_power_ground_nets AH16 = FPGA_CORE VCCINT from line 904 of ultra_fpga_power_ground_nets AH18 = FPGA_CORE VCCINT from line 905 of ultra_fpga_power_ground_nets AH20 = FPGA_CORE VCCINT from line 906 of ultra_fpga_power_ground_nets AH22 = FPGA_CORE VCCINT from line 907 of ultra_fpga_power_ground_nets AH24 = FPGA_CORE VCCINT from line 908 of ultra_fpga_power_ground_nets AH26 = FPGA_CORE VCCINT from line 909 of ultra_fpga_power_ground_nets AH28 = FPGA_CORE VCCINT from line 910 of ultra_fpga_power_ground_nets AJ15 = FPGA_CORE VCCINT from line 911 of ultra_fpga_power_ground_nets AJ17 = FPGA_CORE VCCINT from line 912 of ultra_fpga_power_ground_nets AJ19 = FPGA_CORE VCCINT from line 913 of ultra_fpga_power_ground_nets AJ21 = FPGA_CORE VCCINT from line 914 of ultra_fpga_power_ground_nets AJ23 = FPGA_CORE VCCINT from line 915 of ultra_fpga_power_ground_nets AJ25 = FPGA_CORE VCCINT from line 916 of ultra_fpga_power_ground_nets AJ27 = FPGA_CORE VCCINT from line 917 of ultra_fpga_power_ground_nets AK16 = FPGA_CORE VCCINT from line 918 of ultra_fpga_power_ground_nets AK18 = FPGA_CORE VCCINT from line 919 of ultra_fpga_power_ground_nets AK20 = FPGA_CORE VCCINT from line 920 of ultra_fpga_power_ground_nets AK22 = FPGA_CORE VCCINT from line 921 of ultra_fpga_power_ground_nets AK24 = FPGA_CORE VCCINT from line 922 of ultra_fpga_power_ground_nets AK26 = FPGA_CORE VCCINT from line 923 of ultra_fpga_power_ground_nets AK28 = FPGA_CORE VCCINT from line 924 of ultra_fpga_power_ground_nets AL15 = FPGA_CORE VCCINT from line 925 of ultra_fpga_power_ground_nets AL17 = FPGA_CORE VCCINT from line 926 of ultra_fpga_power_ground_nets AL19 = FPGA_CORE VCCINT from line 927 of ultra_fpga_power_ground_nets AL21 = FPGA_CORE VCCINT from line 928 of ultra_fpga_power_ground_nets AL23 = FPGA_CORE VCCINT from line 929 of ultra_fpga_power_ground_nets AL25 = FPGA_CORE VCCINT from line 930 of ultra_fpga_power_ground_nets AL27 = FPGA_CORE VCCINT from line 931 of ultra_fpga_power_ground_nets P30 = FPGA_CORE VCCINT_IO from line 943 of ultra_fpga_power_ground_nets T30 = FPGA_CORE VCCINT_IO from line 944 of ultra_fpga_power_ground_nets V30 = FPGA_CORE VCCINT_IO from line 945 of ultra_fpga_power_ground_nets AA29 = FPGA_CORE VCCINT_IO from line 946 of ultra_fpga_power_ground_nets AC29 = FPGA_CORE VCCINT_IO from line 947 of ultra_fpga_power_ground_nets AE29 = FPGA_CORE VCCINT_IO from line 948 of ultra_fpga_power_ground_nets AG29 = FPGA_CORE VCCINT_IO from line 949 of ultra_fpga_power_ground_nets AJ29 = FPGA_CORE VCCINT_IO from line 950 of ultra_fpga_power_ground_nets AL29 = FPGA_CORE VCCINT_IO from line 951 of ultra_fpga_power_ground_nets AC14 = FPGA_Config_DONE DONE_0 from line 165 of bank_0_and_bank_65_config_mem_nets BB28 = FPGA_RODs_SMBALERT_B IO_T2U_N12_67 from line 856 of power_supply_all_other_nets AV13 = FPGA_SW_A_ATC_LOOP_DET IO_L11N_T1U_N9_GC_94 from line 309 of switch_chips_all_other_nets AY15 = FPGA_SW_A_LOOP_DETECTED IO_L1P_T0L_N0_DBC_94 from line 312 of switch_chips_all_other_nets AW13 = FPGA_SW_A_MDC IO_L12P_T1U_N10_GC_94 from line 277 of switch_chips_all_other_nets AW15 = FPGA_SW_A_MDIO IO_L2P_T0L_N2_94 from line 274 of switch_chips_all_other_nets AT14 = FPGA_SW_B_ATC_LOOP_DET IO_L14N_T2L_N3_GC_84 from line 317 of switch_chips_all_other_nets AU13 = FPGA_SW_B_LOOP_DETECTED IO_L13N_T2L_N1_GC_QBC_84 from line 320 of switch_chips_all_other_nets AT16 = FPGA_SW_B_MDC IO_L19P_T3L_N0_DBC_AD9P_84 from line 285 of switch_chips_all_other_nets AU16 = FPGA_SW_B_MDIO IO_L19N_T3L_N1_DBC_AD9N_84 from line 282 of switch_chips_all_other_nets AV15 = FPGA_SW_C_ATC_LOOP_DET IO_L22N_T3U_N7_DBC_AD0N_84 from line 325 of switch_chips_all_other_nets AV16 = FPGA_SW_C_LOOP_DETECTED IO_L22P_T3U_N6_DBC_AD0P_84 from line 328 of switch_chips_all_other_nets AY13 = FPGA_SW_C_MDC IO_T1U_N12_94 from line 293 of switch_chips_all_other_nets AY14 = FPGA_SW_C_MDIO IO_L2N_T0L_N3_94 from line 290 of switch_chips_all_other_nets A3 = GROUND GND from line 51 of ultra_fpga_power_ground_nets A5 = GROUND GND from line 52 of ultra_fpga_power_ground_nets A12 = GROUND GND from line 53 of ultra_fpga_power_ground_nets A13 = GROUND GND from line 54 of ultra_fpga_power_ground_nets A14 = GROUND GND from line 55 of ultra_fpga_power_ground_nets A17 = GROUND GND from line 56 of ultra_fpga_power_ground_nets A22 = GROUND GND from line 57 of ultra_fpga_power_ground_nets A30 = GROUND GND from line 58 of ultra_fpga_power_ground_nets A33 = GROUND GND from line 59 of ultra_fpga_power_ground_nets A34 = GROUND GND from line 60 of ultra_fpga_power_ground_nets A35 = GROUND GND from line 61 of ultra_fpga_power_ground_nets A42 = GROUND GND from line 62 of ultra_fpga_power_ground_nets A44 = GROUND GND from line 63 of ultra_fpga_power_ground_nets B2 = GROUND GND from line 64 of ultra_fpga_power_ground_nets B5 = GROUND GND from line 65 of ultra_fpga_power_ground_nets B6 = GROUND GND from line 66 of ultra_fpga_power_ground_nets B10 = GROUND GND from line 67 of ultra_fpga_power_ground_nets B12 = GROUND GND from line 68 of ultra_fpga_power_ground_nets B15 = GROUND GND from line 69 of ultra_fpga_power_ground_nets B16 = GROUND GND from line 70 of ultra_fpga_power_ground_nets B17 = GROUND GND from line 71 of ultra_fpga_power_ground_nets B19 = GROUND GND from line 72 of ultra_fpga_power_ground_nets B29 = GROUND GND from line 73 of ultra_fpga_power_ground_nets B30 = GROUND GND from line 74 of ultra_fpga_power_ground_nets B31 = GROUND GND from line 75 of ultra_fpga_power_ground_nets B32 = GROUND GND from line 76 of ultra_fpga_power_ground_nets B35 = GROUND GND from line 77 of ultra_fpga_power_ground_nets B37 = GROUND GND from line 78 of ultra_fpga_power_ground_nets B41 = GROUND GND from line 79 of ultra_fpga_power_ground_nets B42 = GROUND GND from line 80 of ultra_fpga_power_ground_nets B45 = GROUND GND from line 81 of ultra_fpga_power_ground_nets C3 = GROUND GND from line 82 of ultra_fpga_power_ground_nets C4 = GROUND GND from line 83 of ultra_fpga_power_ground_nets C5 = GROUND GND from line 84 of ultra_fpga_power_ground_nets C8 = GROUND GND from line 85 of ultra_fpga_power_ground_nets C12 = GROUND GND from line 86 of ultra_fpga_power_ground_nets C13 = GROUND GND from line 87 of ultra_fpga_power_ground_nets C14 = GROUND GND from line 88 of ultra_fpga_power_ground_nets C17 = GROUND GND from line 89 of ultra_fpga_power_ground_nets C26 = GROUND GND from line 90 of ultra_fpga_power_ground_nets C30 = GROUND GND from line 91 of ultra_fpga_power_ground_nets C33 = GROUND GND from line 92 of ultra_fpga_power_ground_nets C34 = GROUND GND from line 93 of ultra_fpga_power_ground_nets C35 = GROUND GND from line 94 of ultra_fpga_power_ground_nets C39 = GROUND GND from line 95 of ultra_fpga_power_ground_nets C42 = GROUND GND from line 96 of ultra_fpga_power_ground_nets C43 = GROUND GND from line 97 of ultra_fpga_power_ground_nets C44 = GROUND GND from line 98 of ultra_fpga_power_ground_nets D1 = GROUND GND from line 99 of ultra_fpga_power_ground_nets D2 = GROUND GND from line 100 of ultra_fpga_power_ground_nets D5 = GROUND GND from line 101 of ultra_fpga_power_ground_nets D11 = GROUND GND from line 102 of ultra_fpga_power_ground_nets D12 = GROUND GND from line 103 of ultra_fpga_power_ground_nets D15 = GROUND GND from line 104 of ultra_fpga_power_ground_nets D16 = GROUND GND from line 105 of ultra_fpga_power_ground_nets D17 = GROUND GND from line 106 of ultra_fpga_power_ground_nets D23 = GROUND GND from line 107 of ultra_fpga_power_ground_nets D30 = GROUND GND from line 108 of ultra_fpga_power_ground_nets D31 = GROUND GND from line 109 of ultra_fpga_power_ground_nets D32 = GROUND GND from line 110 of ultra_fpga_power_ground_nets D35 = GROUND GND from line 111 of ultra_fpga_power_ground_nets D36 = GROUND GND from line 112 of ultra_fpga_power_ground_nets D42 = GROUND GND from line 113 of ultra_fpga_power_ground_nets D45 = GROUND GND from line 114 of ultra_fpga_power_ground_nets D46 = GROUND GND from line 115 of ultra_fpga_power_ground_nets E3 = GROUND GND from line 116 of ultra_fpga_power_ground_nets E4 = GROUND GND from line 117 of ultra_fpga_power_ground_nets E5 = GROUND GND from line 118 of ultra_fpga_power_ground_nets E9 = GROUND GND from line 119 of ultra_fpga_power_ground_nets E12 = GROUND GND from line 120 of ultra_fpga_power_ground_nets E13 = GROUND GND from line 121 of ultra_fpga_power_ground_nets E14 = GROUND GND from line 122 of ultra_fpga_power_ground_nets E17 = GROUND GND from line 123 of ultra_fpga_power_ground_nets E20 = GROUND GND from line 124 of ultra_fpga_power_ground_nets E30 = GROUND GND from line 125 of ultra_fpga_power_ground_nets E33 = GROUND GND from line 126 of ultra_fpga_power_ground_nets E34 = GROUND GND from line 127 of ultra_fpga_power_ground_nets E35 = GROUND GND from line 128 of ultra_fpga_power_ground_nets E38 = GROUND GND from line 129 of ultra_fpga_power_ground_nets E42 = GROUND GND from line 130 of ultra_fpga_power_ground_nets E43 = GROUND GND from line 131 of ultra_fpga_power_ground_nets E44 = GROUND GND from line 132 of ultra_fpga_power_ground_nets F1 = GROUND GND from line 133 of ultra_fpga_power_ground_nets F2 = GROUND GND from line 134 of ultra_fpga_power_ground_nets F5 = GROUND GND from line 135 of ultra_fpga_power_ground_nets F6 = GROUND GND from line 136 of ultra_fpga_power_ground_nets F10 = GROUND GND from line 137 of ultra_fpga_power_ground_nets F14 = GROUND GND from line 138 of ultra_fpga_power_ground_nets F15 = GROUND GND from line 139 of ultra_fpga_power_ground_nets F16 = GROUND GND from line 140 of ultra_fpga_power_ground_nets F17 = GROUND GND from line 141 of ultra_fpga_power_ground_nets F27 = GROUND GND from line 142 of ultra_fpga_power_ground_nets F30 = GROUND GND from line 143 of ultra_fpga_power_ground_nets F31 = GROUND GND from line 144 of ultra_fpga_power_ground_nets F32 = GROUND GND from line 145 of ultra_fpga_power_ground_nets F33 = GROUND GND from line 146 of ultra_fpga_power_ground_nets F37 = GROUND GND from line 147 of ultra_fpga_power_ground_nets F41 = GROUND GND from line 148 of ultra_fpga_power_ground_nets F42 = GROUND GND from line 149 of ultra_fpga_power_ground_nets F45 = GROUND GND from line 150 of ultra_fpga_power_ground_nets F46 = GROUND GND from line 151 of ultra_fpga_power_ground_nets G3 = GROUND GND from line 152 of ultra_fpga_power_ground_nets G4 = GROUND GND from line 153 of ultra_fpga_power_ground_nets G5 = GROUND GND from line 154 of ultra_fpga_power_ground_nets G8 = GROUND GND from line 155 of ultra_fpga_power_ground_nets G12 = GROUND GND from line 156 of ultra_fpga_power_ground_nets G14 = GROUND GND from line 157 of ultra_fpga_power_ground_nets G17 = GROUND GND from line 158 of ultra_fpga_power_ground_nets G24 = GROUND GND from line 159 of ultra_fpga_power_ground_nets G30 = GROUND GND from line 160 of ultra_fpga_power_ground_nets G33 = GROUND GND from line 161 of ultra_fpga_power_ground_nets G35 = GROUND GND from line 162 of ultra_fpga_power_ground_nets G39 = GROUND GND from line 163 of ultra_fpga_power_ground_nets G42 = GROUND GND from line 164 of ultra_fpga_power_ground_nets G43 = GROUND GND from line 165 of ultra_fpga_power_ground_nets G44 = GROUND GND from line 166 of ultra_fpga_power_ground_nets H1 = GROUND GND from line 167 of ultra_fpga_power_ground_nets H2 = GROUND GND from line 168 of ultra_fpga_power_ground_nets H5 = GROUND GND from line 169 of ultra_fpga_power_ground_nets H7 = GROUND GND from line 170 of ultra_fpga_power_ground_nets H11 = GROUND GND from line 171 of ultra_fpga_power_ground_nets H14 = GROUND GND from line 172 of ultra_fpga_power_ground_nets H15 = GROUND GND from line 173 of ultra_fpga_power_ground_nets H16 = GROUND GND from line 174 of ultra_fpga_power_ground_nets H17 = GROUND GND from line 175 of ultra_fpga_power_ground_nets H21 = GROUND GND from line 176 of ultra_fpga_power_ground_nets H30 = GROUND GND from line 177 of ultra_fpga_power_ground_nets H31 = GROUND GND from line 178 of ultra_fpga_power_ground_nets H32 = GROUND GND from line 179 of ultra_fpga_power_ground_nets H33 = GROUND GND from line 180 of ultra_fpga_power_ground_nets H36 = GROUND GND from line 181 of ultra_fpga_power_ground_nets H40 = GROUND GND from line 182 of ultra_fpga_power_ground_nets H42 = GROUND GND from line 183 of ultra_fpga_power_ground_nets H45 = GROUND GND from line 184 of ultra_fpga_power_ground_nets H46 = GROUND GND from line 185 of ultra_fpga_power_ground_nets J3 = GROUND GND from line 186 of ultra_fpga_power_ground_nets J4 = GROUND GND from line 187 of ultra_fpga_power_ground_nets J5 = GROUND GND from line 188 of ultra_fpga_power_ground_nets J9 = GROUND GND from line 189 of ultra_fpga_power_ground_nets J13 = GROUND GND from line 190 of ultra_fpga_power_ground_nets J14 = GROUND GND from line 191 of ultra_fpga_power_ground_nets J18 = GROUND GND from line 192 of ultra_fpga_power_ground_nets J28 = GROUND GND from line 193 of ultra_fpga_power_ground_nets J33 = GROUND GND from line 194 of ultra_fpga_power_ground_nets J34 = GROUND GND from line 195 of ultra_fpga_power_ground_nets J38 = GROUND GND from line 196 of ultra_fpga_power_ground_nets J42 = GROUND GND from line 197 of ultra_fpga_power_ground_nets J43 = GROUND GND from line 198 of ultra_fpga_power_ground_nets J44 = GROUND GND from line 199 of ultra_fpga_power_ground_nets K1 = GROUND GND from line 200 of ultra_fpga_power_ground_nets K2 = GROUND GND from line 201 of ultra_fpga_power_ground_nets K5 = GROUND GND from line 202 of ultra_fpga_power_ground_nets K6 = GROUND GND from line 203 of ultra_fpga_power_ground_nets K10 = GROUND GND from line 204 of ultra_fpga_power_ground_nets K15 = GROUND GND from line 205 of ultra_fpga_power_ground_nets K25 = GROUND GND from line 206 of ultra_fpga_power_ground_nets K33 = GROUND GND from line 207 of ultra_fpga_power_ground_nets K37 = GROUND GND from line 208 of ultra_fpga_power_ground_nets K41 = GROUND GND from line 209 of ultra_fpga_power_ground_nets K42 = GROUND GND from line 210 of ultra_fpga_power_ground_nets K45 = GROUND GND from line 211 of ultra_fpga_power_ground_nets K46 = GROUND GND from line 212 of ultra_fpga_power_ground_nets L3 = GROUND GND from line 213 of ultra_fpga_power_ground_nets L4 = GROUND GND from line 214 of ultra_fpga_power_ground_nets L5 = GROUND GND from line 215 of ultra_fpga_power_ground_nets L8 = GROUND GND from line 216 of ultra_fpga_power_ground_nets L12 = GROUND GND from line 217 of ultra_fpga_power_ground_nets L14 = GROUND GND from line 218 of ultra_fpga_power_ground_nets L22 = GROUND GND from line 219 of ultra_fpga_power_ground_nets L32 = GROUND GND from line 220 of ultra_fpga_power_ground_nets L33 = GROUND GND from line 221 of ultra_fpga_power_ground_nets L35 = GROUND GND from line 222 of ultra_fpga_power_ground_nets L39 = GROUND GND from line 223 of ultra_fpga_power_ground_nets L42 = GROUND GND from line 224 of ultra_fpga_power_ground_nets L43 = GROUND GND from line 225 of ultra_fpga_power_ground_nets L44 = GROUND GND from line 226 of ultra_fpga_power_ground_nets M1 = GROUND GND from line 227 of ultra_fpga_power_ground_nets M2 = GROUND GND from line 228 of ultra_fpga_power_ground_nets M5 = GROUND GND from line 229 of ultra_fpga_power_ground_nets M7 = GROUND GND from line 230 of ultra_fpga_power_ground_nets M11 = GROUND GND from line 231 of ultra_fpga_power_ground_nets M19 = GROUND GND from line 232 of ultra_fpga_power_ground_nets M29 = GROUND GND from line 233 of ultra_fpga_power_ground_nets M33 = GROUND GND from line 234 of ultra_fpga_power_ground_nets M36 = GROUND GND from line 235 of ultra_fpga_power_ground_nets M40 = GROUND GND from line 236 of ultra_fpga_power_ground_nets M42 = GROUND GND from line 237 of ultra_fpga_power_ground_nets M45 = GROUND GND from line 238 of ultra_fpga_power_ground_nets M46 = GROUND GND from line 239 of ultra_fpga_power_ground_nets N3 = GROUND GND from line 240 of ultra_fpga_power_ground_nets N4 = GROUND GND from line 241 of ultra_fpga_power_ground_nets N5 = GROUND GND from line 242 of ultra_fpga_power_ground_nets N9 = GROUND GND from line 243 of ultra_fpga_power_ground_nets N13 = GROUND GND from line 244 of ultra_fpga_power_ground_nets N14 = GROUND GND from line 245 of ultra_fpga_power_ground_nets N16 = GROUND GND from line 246 of ultra_fpga_power_ground_nets N26 = GROUND GND from line 247 of ultra_fpga_power_ground_nets N33 = GROUND GND from line 248 of ultra_fpga_power_ground_nets N34 = GROUND GND from line 249 of ultra_fpga_power_ground_nets N38 = GROUND GND from line 250 of ultra_fpga_power_ground_nets N42 = GROUND GND from line 251 of ultra_fpga_power_ground_nets N43 = GROUND GND from line 252 of ultra_fpga_power_ground_nets N44 = GROUND GND from line 253 of ultra_fpga_power_ground_nets P1 = GROUND GND from line 254 of ultra_fpga_power_ground_nets P2 = GROUND GND from line 255 of ultra_fpga_power_ground_nets P5 = GROUND GND from line 256 of ultra_fpga_power_ground_nets P6 = GROUND GND from line 257 of ultra_fpga_power_ground_nets P10 = GROUND GND from line 258 of ultra_fpga_power_ground_nets P23 = GROUND GND from line 259 of ultra_fpga_power_ground_nets P29 = GROUND GND from line 260 of ultra_fpga_power_ground_nets P31 = GROUND GND from line 261 of ultra_fpga_power_ground_nets P33 = GROUND GND from line 262 of ultra_fpga_power_ground_nets P37 = GROUND GND from line 263 of ultra_fpga_power_ground_nets P41 = GROUND GND from line 264 of ultra_fpga_power_ground_nets P42 = GROUND GND from line 265 of ultra_fpga_power_ground_nets P45 = GROUND GND from line 266 of ultra_fpga_power_ground_nets P46 = GROUND GND from line 267 of ultra_fpga_power_ground_nets R3 = GROUND GND from line 268 of ultra_fpga_power_ground_nets R4 = GROUND GND from line 269 of ultra_fpga_power_ground_nets R5 = GROUND GND from line 270 of ultra_fpga_power_ground_nets R8 = GROUND GND from line 271 of ultra_fpga_power_ground_nets R12 = GROUND GND from line 272 of ultra_fpga_power_ground_nets R14 = GROUND GND from line 273 of ultra_fpga_power_ground_nets R16 = GROUND GND from line 274 of ultra_fpga_power_ground_nets R18 = GROUND GND from line 275 of ultra_fpga_power_ground_nets R20 = GROUND GND from line 276 of ultra_fpga_power_ground_nets R22 = GROUND GND from line 277 of ultra_fpga_power_ground_nets R24 = GROUND GND from line 278 of ultra_fpga_power_ground_nets R26 = GROUND GND from line 279 of ultra_fpga_power_ground_nets R28 = GROUND GND from line 280 of ultra_fpga_power_ground_nets R30 = GROUND GND from line 281 of ultra_fpga_power_ground_nets R32 = GROUND GND from line 282 of ultra_fpga_power_ground_nets R33 = GROUND GND from line 283 of ultra_fpga_power_ground_nets R35 = GROUND GND from line 284 of ultra_fpga_power_ground_nets R39 = GROUND GND from line 285 of ultra_fpga_power_ground_nets R42 = GROUND GND from line 286 of ultra_fpga_power_ground_nets R43 = GROUND GND from line 287 of ultra_fpga_power_ground_nets R44 = GROUND GND from line 288 of ultra_fpga_power_ground_nets T1 = GROUND GND from line 289 of ultra_fpga_power_ground_nets T2 = GROUND GND from line 290 of ultra_fpga_power_ground_nets T5 = GROUND GND from line 291 of ultra_fpga_power_ground_nets T7 = GROUND GND from line 292 of ultra_fpga_power_ground_nets T11 = GROUND GND from line 293 of ultra_fpga_power_ground_nets T15 = GROUND GND from line 294 of ultra_fpga_power_ground_nets T17 = GROUND GND from line 295 of ultra_fpga_power_ground_nets T19 = GROUND GND from line 296 of ultra_fpga_power_ground_nets T21 = GROUND GND from line 297 of ultra_fpga_power_ground_nets T23 = GROUND GND from line 298 of ultra_fpga_power_ground_nets T25 = GROUND GND from line 299 of ultra_fpga_power_ground_nets T27 = GROUND GND from line 300 of ultra_fpga_power_ground_nets T29 = GROUND GND from line 301 of ultra_fpga_power_ground_nets T31 = GROUND GND from line 302 of ultra_fpga_power_ground_nets T33 = GROUND GND from line 303 of ultra_fpga_power_ground_nets T36 = GROUND GND from line 304 of ultra_fpga_power_ground_nets T40 = GROUND GND from line 305 of ultra_fpga_power_ground_nets T42 = GROUND GND from line 306 of ultra_fpga_power_ground_nets T45 = GROUND GND from line 307 of ultra_fpga_power_ground_nets T46 = GROUND GND from line 308 of ultra_fpga_power_ground_nets U3 = GROUND GND from line 309 of ultra_fpga_power_ground_nets U4 = GROUND GND from line 310 of ultra_fpga_power_ground_nets U5 = GROUND GND from line 311 of ultra_fpga_power_ground_nets U9 = GROUND GND from line 312 of ultra_fpga_power_ground_nets U13 = GROUND GND from line 313 of ultra_fpga_power_ground_nets U14 = GROUND GND from line 314 of ultra_fpga_power_ground_nets U16 = GROUND GND from line 315 of ultra_fpga_power_ground_nets U18 = GROUND GND from line 316 of ultra_fpga_power_ground_nets U20 = GROUND GND from line 317 of ultra_fpga_power_ground_nets U22 = GROUND GND from line 318 of ultra_fpga_power_ground_nets U24 = GROUND GND from line 319 of ultra_fpga_power_ground_nets U26 = GROUND GND from line 320 of ultra_fpga_power_ground_nets U28 = GROUND GND from line 321 of ultra_fpga_power_ground_nets U30 = GROUND GND from line 322 of ultra_fpga_power_ground_nets U32 = GROUND GND from line 323 of ultra_fpga_power_ground_nets U33 = GROUND GND from line 324 of ultra_fpga_power_ground_nets U34 = GROUND GND from line 325 of ultra_fpga_power_ground_nets U38 = GROUND GND from line 326 of ultra_fpga_power_ground_nets U42 = GROUND GND from line 327 of ultra_fpga_power_ground_nets U43 = GROUND GND from line 328 of ultra_fpga_power_ground_nets U44 = GROUND GND from line 329 of ultra_fpga_power_ground_nets V1 = GROUND GND from line 330 of ultra_fpga_power_ground_nets V2 = GROUND GND from line 331 of ultra_fpga_power_ground_nets V5 = GROUND GND from line 332 of ultra_fpga_power_ground_nets V6 = GROUND GND from line 333 of ultra_fpga_power_ground_nets V10 = GROUND GND from line 334 of ultra_fpga_power_ground_nets V15 = GROUND GND from line 335 of ultra_fpga_power_ground_nets V17 = GROUND GND from line 336 of ultra_fpga_power_ground_nets V19 = GROUND GND from line 337 of ultra_fpga_power_ground_nets V21 = GROUND GND from line 338 of ultra_fpga_power_ground_nets V23 = GROUND GND from line 339 of ultra_fpga_power_ground_nets V25 = GROUND GND from line 340 of ultra_fpga_power_ground_nets V27 = GROUND GND from line 341 of ultra_fpga_power_ground_nets V29 = GROUND GND from line 342 of ultra_fpga_power_ground_nets V31 = GROUND GND from line 343 of ultra_fpga_power_ground_nets V33 = GROUND GND from line 344 of ultra_fpga_power_ground_nets V37 = GROUND GND from line 345 of ultra_fpga_power_ground_nets V41 = GROUND GND from line 346 of ultra_fpga_power_ground_nets V42 = GROUND GND from line 347 of ultra_fpga_power_ground_nets V45 = GROUND GND from line 348 of ultra_fpga_power_ground_nets V46 = GROUND GND from line 349 of ultra_fpga_power_ground_nets W3 = GROUND GND from line 350 of ultra_fpga_power_ground_nets W4 = GROUND GND from line 351 of ultra_fpga_power_ground_nets W5 = GROUND GND from line 352 of ultra_fpga_power_ground_nets W8 = GROUND GND from line 353 of ultra_fpga_power_ground_nets W12 = GROUND GND from line 354 of ultra_fpga_power_ground_nets W14 = GROUND GND from line 355 of ultra_fpga_power_ground_nets W16 = GROUND GND from line 356 of ultra_fpga_power_ground_nets W18 = GROUND GND from line 357 of ultra_fpga_power_ground_nets W20 = GROUND GND from line 358 of ultra_fpga_power_ground_nets W22 = GROUND GND from line 359 of ultra_fpga_power_ground_nets W24 = GROUND GND from line 360 of ultra_fpga_power_ground_nets W26 = GROUND GND from line 361 of ultra_fpga_power_ground_nets W28 = GROUND GND from line 362 of ultra_fpga_power_ground_nets W30 = GROUND GND from line 363 of ultra_fpga_power_ground_nets W32 = GROUND GND from line 364 of ultra_fpga_power_ground_nets W33 = GROUND GND from line 365 of ultra_fpga_power_ground_nets W35 = GROUND GND from line 366 of ultra_fpga_power_ground_nets W39 = GROUND GND from line 367 of ultra_fpga_power_ground_nets W42 = GROUND GND from line 368 of ultra_fpga_power_ground_nets W43 = GROUND GND from line 369 of ultra_fpga_power_ground_nets W44 = GROUND GND from line 370 of ultra_fpga_power_ground_nets Y1 = GROUND GND from line 371 of ultra_fpga_power_ground_nets Y2 = GROUND GND from line 372 of ultra_fpga_power_ground_nets Y5 = GROUND GND from line 373 of ultra_fpga_power_ground_nets Y7 = GROUND GND from line 374 of ultra_fpga_power_ground_nets Y11 = GROUND GND from line 375 of ultra_fpga_power_ground_nets Y15 = GROUND GND from line 376 of ultra_fpga_power_ground_nets Y17 = GROUND GND from line 377 of ultra_fpga_power_ground_nets Y19 = GROUND GND from line 378 of ultra_fpga_power_ground_nets Y21 = GROUND GND from line 379 of ultra_fpga_power_ground_nets Y23 = GROUND GND from line 380 of ultra_fpga_power_ground_nets Y25 = GROUND GND from line 381 of ultra_fpga_power_ground_nets Y27 = GROUND GND from line 382 of ultra_fpga_power_ground_nets Y29 = GROUND GND from line 383 of ultra_fpga_power_ground_nets Y31 = GROUND GND from line 384 of ultra_fpga_power_ground_nets Y33 = GROUND GND from line 385 of ultra_fpga_power_ground_nets Y36 = GROUND GND from line 386 of ultra_fpga_power_ground_nets Y40 = GROUND GND from line 387 of ultra_fpga_power_ground_nets Y42 = GROUND GND from line 388 of ultra_fpga_power_ground_nets Y45 = GROUND GND from line 389 of ultra_fpga_power_ground_nets Y46 = GROUND GND from line 390 of ultra_fpga_power_ground_nets AA3 = GROUND GND from line 391 of ultra_fpga_power_ground_nets AA4 = GROUND GND from line 392 of ultra_fpga_power_ground_nets AA5 = GROUND GND from line 393 of ultra_fpga_power_ground_nets AA9 = GROUND GND from line 394 of ultra_fpga_power_ground_nets AA13 = GROUND GND from line 395 of ultra_fpga_power_ground_nets AA14 = GROUND GND from line 396 of ultra_fpga_power_ground_nets AA15 = GROUND GND from line 397 of ultra_fpga_power_ground_nets AA16 = GROUND GND from line 398 of ultra_fpga_power_ground_nets AA18 = GROUND GND from line 399 of ultra_fpga_power_ground_nets AA20 = GROUND GND from line 400 of ultra_fpga_power_ground_nets AA22 = GROUND GND from line 401 of ultra_fpga_power_ground_nets AA24 = GROUND GND from line 402 of ultra_fpga_power_ground_nets AA26 = GROUND GND from line 403 of ultra_fpga_power_ground_nets AA28 = GROUND GND from line 404 of ultra_fpga_power_ground_nets AA30 = GROUND GND from line 405 of ultra_fpga_power_ground_nets AA32 = GROUND GND from line 406 of ultra_fpga_power_ground_nets AA33 = GROUND GND from line 407 of ultra_fpga_power_ground_nets AA34 = GROUND GND from line 408 of ultra_fpga_power_ground_nets AA38 = GROUND GND from line 409 of ultra_fpga_power_ground_nets AA42 = GROUND GND from line 410 of ultra_fpga_power_ground_nets AA43 = GROUND GND from line 411 of ultra_fpga_power_ground_nets AA44 = GROUND GND from line 412 of ultra_fpga_power_ground_nets AB1 = GROUND GND from line 413 of ultra_fpga_power_ground_nets AB2 = GROUND GND from line 414 of ultra_fpga_power_ground_nets AB5 = GROUND GND from line 415 of ultra_fpga_power_ground_nets AB6 = GROUND GND from line 416 of ultra_fpga_power_ground_nets AB10 = GROUND GND from line 417 of ultra_fpga_power_ground_nets AB17 = GROUND GND from line 418 of ultra_fpga_power_ground_nets AB21 = GROUND GND from line 419 of ultra_fpga_power_ground_nets AB23 = GROUND GND from line 420 of ultra_fpga_power_ground_nets AB25 = GROUND GND from line 421 of ultra_fpga_power_ground_nets AB27 = GROUND GND from line 422 of ultra_fpga_power_ground_nets AB29 = GROUND GND from line 423 of ultra_fpga_power_ground_nets AB31 = GROUND GND from line 424 of ultra_fpga_power_ground_nets AB33 = GROUND GND from line 425 of ultra_fpga_power_ground_nets AB37 = GROUND GND from line 426 of ultra_fpga_power_ground_nets AB41 = GROUND GND from line 427 of ultra_fpga_power_ground_nets AB42 = GROUND GND from line 428 of ultra_fpga_power_ground_nets AB45 = GROUND GND from line 429 of ultra_fpga_power_ground_nets AB46 = GROUND GND from line 430 of ultra_fpga_power_ground_nets AC3 = GROUND GND from line 431 of ultra_fpga_power_ground_nets AC4 = GROUND GND from line 432 of ultra_fpga_power_ground_nets AC5 = GROUND GND from line 433 of ultra_fpga_power_ground_nets AC8 = GROUND GND from line 434 of ultra_fpga_power_ground_nets AC12 = GROUND GND from line 435 of ultra_fpga_power_ground_nets AC16 = GROUND GND from line 436 of ultra_fpga_power_ground_nets AC18 = GROUND GND from line 437 of ultra_fpga_power_ground_nets AC22 = GROUND GND from line 438 of ultra_fpga_power_ground_nets AC24 = GROUND GND from line 439 of ultra_fpga_power_ground_nets AC26 = GROUND GND from line 440 of ultra_fpga_power_ground_nets AC28 = GROUND GND from line 441 of ultra_fpga_power_ground_nets AC30 = GROUND GND from line 442 of ultra_fpga_power_ground_nets AC32 = GROUND GND from line 443 of ultra_fpga_power_ground_nets AC33 = GROUND GND from line 444 of ultra_fpga_power_ground_nets AC35 = GROUND GND from line 445 of ultra_fpga_power_ground_nets AC39 = GROUND GND from line 446 of ultra_fpga_power_ground_nets AC42 = GROUND GND from line 447 of ultra_fpga_power_ground_nets AC43 = GROUND GND from line 448 of ultra_fpga_power_ground_nets AC44 = GROUND GND from line 449 of ultra_fpga_power_ground_nets AD1 = GROUND GND from line 450 of ultra_fpga_power_ground_nets AD2 = GROUND GND from line 451 of ultra_fpga_power_ground_nets AD5 = GROUND GND from line 452 of ultra_fpga_power_ground_nets AD7 = GROUND GND from line 453 of ultra_fpga_power_ground_nets AD11 = GROUND GND from line 454 of ultra_fpga_power_ground_nets AD14 = GROUND GND from line 455 of ultra_fpga_power_ground_nets AD17 = GROUND GND from line 456 of ultra_fpga_power_ground_nets AD21 = GROUND GND from line 457 of ultra_fpga_power_ground_nets AD23 = GROUND GND from line 458 of ultra_fpga_power_ground_nets AD25 = GROUND GND from line 459 of ultra_fpga_power_ground_nets AD27 = GROUND GND from line 460 of ultra_fpga_power_ground_nets AD29 = GROUND GND from line 461 of ultra_fpga_power_ground_nets AD31 = GROUND GND from line 462 of ultra_fpga_power_ground_nets AD33 = GROUND GND from line 463 of ultra_fpga_power_ground_nets AD36 = GROUND GND from line 464 of ultra_fpga_power_ground_nets AD40 = GROUND GND from line 465 of ultra_fpga_power_ground_nets AD42 = GROUND GND from line 466 of ultra_fpga_power_ground_nets AD45 = GROUND GND from line 467 of ultra_fpga_power_ground_nets AD46 = GROUND GND from line 468 of ultra_fpga_power_ground_nets AE3 = GROUND GND from line 469 of ultra_fpga_power_ground_nets AE4 = GROUND GND from line 470 of ultra_fpga_power_ground_nets AE5 = GROUND GND from line 471 of ultra_fpga_power_ground_nets AE9 = GROUND GND from line 472 of ultra_fpga_power_ground_nets AE13 = GROUND GND from line 473 of ultra_fpga_power_ground_nets AE16 = GROUND GND from line 474 of ultra_fpga_power_ground_nets AE18 = GROUND GND from line 475 of ultra_fpga_power_ground_nets AE22 = GROUND GND from line 476 of ultra_fpga_power_ground_nets AE24 = GROUND GND from line 477 of ultra_fpga_power_ground_nets AE26 = GROUND GND from line 478 of ultra_fpga_power_ground_nets AE28 = GROUND GND from line 479 of ultra_fpga_power_ground_nets AE30 = GROUND GND from line 480 of ultra_fpga_power_ground_nets AE32 = GROUND GND from line 481 of ultra_fpga_power_ground_nets AE33 = GROUND GND from line 482 of ultra_fpga_power_ground_nets AE34 = GROUND GND from line 483 of ultra_fpga_power_ground_nets AE38 = GROUND GND from line 484 of ultra_fpga_power_ground_nets AE42 = GROUND GND from line 485 of ultra_fpga_power_ground_nets AE43 = GROUND GND from line 486 of ultra_fpga_power_ground_nets AE44 = GROUND GND from line 487 of ultra_fpga_power_ground_nets AF1 = GROUND GND from line 488 of ultra_fpga_power_ground_nets AF2 = GROUND GND from line 489 of ultra_fpga_power_ground_nets AF5 = GROUND GND from line 490 of ultra_fpga_power_ground_nets AF6 = GROUND GND from line 491 of ultra_fpga_power_ground_nets AF10 = GROUND GND from line 492 of ultra_fpga_power_ground_nets AF17 = GROUND GND from line 493 of ultra_fpga_power_ground_nets AF19 = GROUND GND from line 494 of ultra_fpga_power_ground_nets AF21 = GROUND GND from line 495 of ultra_fpga_power_ground_nets AF23 = GROUND GND from line 496 of ultra_fpga_power_ground_nets AF25 = GROUND GND from line 497 of ultra_fpga_power_ground_nets AF27 = GROUND GND from line 498 of ultra_fpga_power_ground_nets AF29 = GROUND GND from line 499 of ultra_fpga_power_ground_nets AF31 = GROUND GND from line 500 of ultra_fpga_power_ground_nets AF33 = GROUND GND from line 501 of ultra_fpga_power_ground_nets AF37 = GROUND GND from line 502 of ultra_fpga_power_ground_nets AF41 = GROUND GND from line 503 of ultra_fpga_power_ground_nets AF42 = GROUND GND from line 504 of ultra_fpga_power_ground_nets AF45 = GROUND GND from line 505 of ultra_fpga_power_ground_nets AF46 = GROUND GND from line 506 of ultra_fpga_power_ground_nets AG3 = GROUND GND from line 507 of ultra_fpga_power_ground_nets AG4 = GROUND GND from line 508 of ultra_fpga_power_ground_nets AG5 = GROUND GND from line 509 of ultra_fpga_power_ground_nets AG8 = GROUND GND from line 510 of ultra_fpga_power_ground_nets AG12 = GROUND GND from line 511 of ultra_fpga_power_ground_nets AG14 = GROUND GND from line 512 of ultra_fpga_power_ground_nets AG15 = GROUND GND from line 513 of ultra_fpga_power_ground_nets AG16 = GROUND GND from line 514 of ultra_fpga_power_ground_nets AG18 = GROUND GND from line 515 of ultra_fpga_power_ground_nets AG20 = GROUND GND from line 516 of ultra_fpga_power_ground_nets AG22 = GROUND GND from line 517 of ultra_fpga_power_ground_nets AG24 = GROUND GND from line 518 of ultra_fpga_power_ground_nets AG26 = GROUND GND from line 519 of ultra_fpga_power_ground_nets AG28 = GROUND GND from line 520 of ultra_fpga_power_ground_nets AG30 = GROUND GND from line 521 of ultra_fpga_power_ground_nets AG32 = GROUND GND from line 522 of ultra_fpga_power_ground_nets AG33 = GROUND GND from line 523 of ultra_fpga_power_ground_nets AG35 = GROUND GND from line 524 of ultra_fpga_power_ground_nets AG39 = GROUND GND from line 525 of ultra_fpga_power_ground_nets AG42 = GROUND GND from line 526 of ultra_fpga_power_ground_nets AG43 = GROUND GND from line 527 of ultra_fpga_power_ground_nets AG44 = GROUND GND from line 528 of ultra_fpga_power_ground_nets AH1 = GROUND GND from line 529 of ultra_fpga_power_ground_nets AH2 = GROUND GND from line 530 of ultra_fpga_power_ground_nets AH5 = GROUND GND from line 531 of ultra_fpga_power_ground_nets AH11 = GROUND GND from line 532 of ultra_fpga_power_ground_nets AH15 = GROUND GND from line 533 of ultra_fpga_power_ground_nets AH17 = GROUND GND from line 534 of ultra_fpga_power_ground_nets AH19 = GROUND GND from line 535 of ultra_fpga_power_ground_nets AH21 = GROUND GND from line 536 of ultra_fpga_power_ground_nets AH23 = GROUND GND from line 537 of ultra_fpga_power_ground_nets AH25 = GROUND GND from line 538 of ultra_fpga_power_ground_nets AH27 = GROUND GND from line 539 of ultra_fpga_power_ground_nets AH29 = GROUND GND from line 540 of ultra_fpga_power_ground_nets AH31 = GROUND GND from line 541 of ultra_fpga_power_ground_nets AH33 = GROUND GND from line 542 of ultra_fpga_power_ground_nets AH36 = GROUND GND from line 543 of ultra_fpga_power_ground_nets AH42 = GROUND GND from line 544 of ultra_fpga_power_ground_nets AH45 = GROUND GND from line 545 of ultra_fpga_power_ground_nets AH46 = GROUND GND from line 546 of ultra_fpga_power_ground_nets AJ3 = GROUND GND from line 547 of ultra_fpga_power_ground_nets AJ4 = GROUND GND from line 548 of ultra_fpga_power_ground_nets AJ5 = GROUND GND from line 549 of ultra_fpga_power_ground_nets AJ9 = GROUND GND from line 550 of ultra_fpga_power_ground_nets AJ13 = GROUND GND from line 551 of ultra_fpga_power_ground_nets AJ14 = GROUND GND from line 552 of ultra_fpga_power_ground_nets AJ16 = GROUND GND from line 553 of ultra_fpga_power_ground_nets AJ18 = GROUND GND from line 554 of ultra_fpga_power_ground_nets AJ20 = GROUND GND from line 555 of ultra_fpga_power_ground_nets AJ22 = GROUND GND from line 556 of ultra_fpga_power_ground_nets AJ24 = GROUND GND from line 557 of ultra_fpga_power_ground_nets AJ26 = GROUND GND from line 558 of ultra_fpga_power_ground_nets AJ28 = GROUND GND from line 559 of ultra_fpga_power_ground_nets AJ30 = GROUND GND from line 560 of ultra_fpga_power_ground_nets AJ32 = GROUND GND from line 561 of ultra_fpga_power_ground_nets AJ33 = GROUND GND from line 562 of ultra_fpga_power_ground_nets AJ34 = GROUND GND from line 563 of ultra_fpga_power_ground_nets AJ38 = GROUND GND from line 564 of ultra_fpga_power_ground_nets AJ42 = GROUND GND from line 565 of ultra_fpga_power_ground_nets AJ43 = GROUND GND from line 566 of ultra_fpga_power_ground_nets AJ44 = GROUND GND from line 567 of ultra_fpga_power_ground_nets AK1 = GROUND GND from line 568 of ultra_fpga_power_ground_nets AK2 = GROUND GND from line 569 of ultra_fpga_power_ground_nets AK5 = GROUND GND from line 570 of ultra_fpga_power_ground_nets AK6 = GROUND GND from line 571 of ultra_fpga_power_ground_nets AK10 = GROUND GND from line 572 of ultra_fpga_power_ground_nets AK15 = GROUND GND from line 573 of ultra_fpga_power_ground_nets AK17 = GROUND GND from line 574 of ultra_fpga_power_ground_nets AK19 = GROUND GND from line 575 of ultra_fpga_power_ground_nets AK21 = GROUND GND from line 576 of ultra_fpga_power_ground_nets AK23 = GROUND GND from line 577 of ultra_fpga_power_ground_nets AK25 = GROUND GND from line 578 of ultra_fpga_power_ground_nets AK27 = GROUND GND from line 579 of ultra_fpga_power_ground_nets AK29 = GROUND GND from line 580 of ultra_fpga_power_ground_nets AK31 = GROUND GND from line 581 of ultra_fpga_power_ground_nets AK33 = GROUND GND from line 582 of ultra_fpga_power_ground_nets AK37 = GROUND GND from line 583 of ultra_fpga_power_ground_nets AK41 = GROUND GND from line 584 of ultra_fpga_power_ground_nets AK42 = GROUND GND from line 585 of ultra_fpga_power_ground_nets AK45 = GROUND GND from line 586 of ultra_fpga_power_ground_nets AK46 = GROUND GND from line 587 of ultra_fpga_power_ground_nets AL3 = GROUND GND from line 588 of ultra_fpga_power_ground_nets AL4 = GROUND GND from line 589 of ultra_fpga_power_ground_nets AL5 = GROUND GND from line 590 of ultra_fpga_power_ground_nets AL8 = GROUND GND from line 591 of ultra_fpga_power_ground_nets AL12 = GROUND GND from line 592 of ultra_fpga_power_ground_nets AL14 = GROUND GND from line 593 of ultra_fpga_power_ground_nets AL16 = GROUND GND from line 594 of ultra_fpga_power_ground_nets AL18 = GROUND GND from line 595 of ultra_fpga_power_ground_nets AL20 = GROUND GND from line 596 of ultra_fpga_power_ground_nets AL22 = GROUND GND from line 597 of ultra_fpga_power_ground_nets AL24 = GROUND GND from line 598 of ultra_fpga_power_ground_nets AL26 = GROUND GND from line 599 of ultra_fpga_power_ground_nets AL28 = GROUND GND from line 600 of ultra_fpga_power_ground_nets AL30 = GROUND GND from line 601 of ultra_fpga_power_ground_nets AL32 = GROUND GND from line 602 of ultra_fpga_power_ground_nets AL33 = GROUND GND from line 603 of ultra_fpga_power_ground_nets AL35 = GROUND GND from line 604 of ultra_fpga_power_ground_nets AL39 = GROUND GND from line 605 of ultra_fpga_power_ground_nets AL42 = GROUND GND from line 606 of ultra_fpga_power_ground_nets AL43 = GROUND GND from line 607 of ultra_fpga_power_ground_nets AL44 = GROUND GND from line 608 of ultra_fpga_power_ground_nets AM1 = GROUND GND from line 609 of ultra_fpga_power_ground_nets AM2 = GROUND GND from line 610 of ultra_fpga_power_ground_nets AM5 = GROUND GND from line 611 of ultra_fpga_power_ground_nets AM7 = GROUND GND from line 612 of ultra_fpga_power_ground_nets AM11 = GROUND GND from line 613 of ultra_fpga_power_ground_nets AM15 = GROUND GND from line 614 of ultra_fpga_power_ground_nets AM25 = GROUND GND from line 615 of ultra_fpga_power_ground_nets AM33 = GROUND GND from line 616 of ultra_fpga_power_ground_nets AM36 = GROUND GND from line 617 of ultra_fpga_power_ground_nets AM40 = GROUND GND from line 618 of ultra_fpga_power_ground_nets AM42 = GROUND GND from line 619 of ultra_fpga_power_ground_nets AM45 = GROUND GND from line 620 of ultra_fpga_power_ground_nets AM46 = GROUND GND from line 621 of ultra_fpga_power_ground_nets AN3 = GROUND GND from line 622 of ultra_fpga_power_ground_nets AN4 = GROUND GND from line 623 of ultra_fpga_power_ground_nets AN5 = GROUND GND from line 624 of ultra_fpga_power_ground_nets AN9 = GROUND GND from line 625 of ultra_fpga_power_ground_nets AN12 = GROUND GND from line 626 of ultra_fpga_power_ground_nets AN14 = GROUND GND from line 627 of ultra_fpga_power_ground_nets AN22 = GROUND GND from line 628 of ultra_fpga_power_ground_nets AN33 = GROUND GND from line 629 of ultra_fpga_power_ground_nets AN34 = GROUND GND from line 630 of ultra_fpga_power_ground_nets AN35 = GROUND GND from line 631 of ultra_fpga_power_ground_nets AN38 = GROUND GND from line 632 of ultra_fpga_power_ground_nets AN42 = GROUND GND from line 633 of ultra_fpga_power_ground_nets AN43 = GROUND GND from line 634 of ultra_fpga_power_ground_nets AN44 = GROUND GND from line 635 of ultra_fpga_power_ground_nets AP1 = GROUND GND from line 636 of ultra_fpga_power_ground_nets AP2 = GROUND GND from line 637 of ultra_fpga_power_ground_nets AP5 = GROUND GND from line 638 of ultra_fpga_power_ground_nets AP6 = GROUND GND from line 639 of ultra_fpga_power_ground_nets AP10 = GROUND GND from line 640 of ultra_fpga_power_ground_nets AP11 = GROUND GND from line 641 of ultra_fpga_power_ground_nets AP12 = GROUND GND from line 642 of ultra_fpga_power_ground_nets AP19 = GROUND GND from line 643 of ultra_fpga_power_ground_nets AP29 = GROUND GND from line 644 of ultra_fpga_power_ground_nets AP35 = GROUND GND from line 645 of ultra_fpga_power_ground_nets AP36 = GROUND GND from line 646 of ultra_fpga_power_ground_nets AP37 = GROUND GND from line 647 of ultra_fpga_power_ground_nets AP41 = GROUND GND from line 648 of ultra_fpga_power_ground_nets AP42 = GROUND GND from line 649 of ultra_fpga_power_ground_nets AP45 = GROUND GND from line 650 of ultra_fpga_power_ground_nets AP46 = GROUND GND from line 651 of ultra_fpga_power_ground_nets AR3 = GROUND GND from line 652 of ultra_fpga_power_ground_nets AR4 = GROUND GND from line 653 of ultra_fpga_power_ground_nets AR5 = GROUND GND from line 654 of ultra_fpga_power_ground_nets AR8 = GROUND GND from line 655 of ultra_fpga_power_ground_nets AR10 = GROUND GND from line 656 of ultra_fpga_power_ground_nets AR16 = GROUND GND from line 657 of ultra_fpga_power_ground_nets AR26 = GROUND GND from line 658 of ultra_fpga_power_ground_nets AR37 = GROUND GND from line 659 of ultra_fpga_power_ground_nets AR39 = GROUND GND from line 660 of ultra_fpga_power_ground_nets AR42 = GROUND GND from line 661 of ultra_fpga_power_ground_nets AR43 = GROUND GND from line 662 of ultra_fpga_power_ground_nets AR44 = GROUND GND from line 663 of ultra_fpga_power_ground_nets AT1 = GROUND GND from line 664 of ultra_fpga_power_ground_nets AT2 = GROUND GND from line 665 of ultra_fpga_power_ground_nets AT5 = GROUND GND from line 666 of ultra_fpga_power_ground_nets AT7 = GROUND GND from line 667 of ultra_fpga_power_ground_nets AT10 = GROUND GND from line 668 of ultra_fpga_power_ground_nets AT13 = GROUND GND from line 669 of ultra_fpga_power_ground_nets AT23 = GROUND GND from line 670 of ultra_fpga_power_ground_nets AT33 = GROUND GND from line 671 of ultra_fpga_power_ground_nets AT37 = GROUND GND from line 672 of ultra_fpga_power_ground_nets AT40 = GROUND GND from line 673 of ultra_fpga_power_ground_nets AT42 = GROUND GND from line 674 of ultra_fpga_power_ground_nets AT45 = GROUND GND from line 675 of ultra_fpga_power_ground_nets AT46 = GROUND GND from line 676 of ultra_fpga_power_ground_nets AU3 = GROUND GND from line 677 of ultra_fpga_power_ground_nets AU4 = GROUND GND from line 678 of ultra_fpga_power_ground_nets AU5 = GROUND GND from line 679 of ultra_fpga_power_ground_nets AU9 = GROUND GND from line 680 of ultra_fpga_power_ground_nets AU10 = GROUND GND from line 681 of ultra_fpga_power_ground_nets AU20 = GROUND GND from line 682 of ultra_fpga_power_ground_nets AU30 = GROUND GND from line 683 of ultra_fpga_power_ground_nets AU37 = GROUND GND from line 684 of ultra_fpga_power_ground_nets AU38 = GROUND GND from line 685 of ultra_fpga_power_ground_nets AU42 = GROUND GND from line 686 of ultra_fpga_power_ground_nets AU43 = GROUND GND from line 687 of ultra_fpga_power_ground_nets AU44 = GROUND GND from line 688 of ultra_fpga_power_ground_nets AV1 = GROUND GND from line 689 of ultra_fpga_power_ground_nets AV2 = GROUND GND from line 690 of ultra_fpga_power_ground_nets AV5 = GROUND GND from line 691 of ultra_fpga_power_ground_nets AV6 = GROUND GND from line 692 of ultra_fpga_power_ground_nets AV10 = GROUND GND from line 693 of ultra_fpga_power_ground_nets AV17 = GROUND GND from line 694 of ultra_fpga_power_ground_nets AV27 = GROUND GND from line 695 of ultra_fpga_power_ground_nets AV37 = GROUND GND from line 696 of ultra_fpga_power_ground_nets AV41 = GROUND GND from line 697 of ultra_fpga_power_ground_nets AV42 = GROUND GND from line 698 of ultra_fpga_power_ground_nets AV45 = GROUND GND from line 699 of ultra_fpga_power_ground_nets AV46 = GROUND GND from line 700 of ultra_fpga_power_ground_nets AW3 = GROUND GND from line 701 of ultra_fpga_power_ground_nets AW4 = GROUND GND from line 702 of ultra_fpga_power_ground_nets AW5 = GROUND GND from line 703 of ultra_fpga_power_ground_nets AW8 = GROUND GND from line 704 of ultra_fpga_power_ground_nets AW10 = GROUND GND from line 705 of ultra_fpga_power_ground_nets AW14 = GROUND GND from line 706 of ultra_fpga_power_ground_nets AW24 = GROUND GND from line 707 of ultra_fpga_power_ground_nets AW34 = GROUND GND from line 708 of ultra_fpga_power_ground_nets AW37 = GROUND GND from line 709 of ultra_fpga_power_ground_nets AW39 = GROUND GND from line 710 of ultra_fpga_power_ground_nets AW42 = GROUND GND from line 711 of ultra_fpga_power_ground_nets AW43 = GROUND GND from line 712 of ultra_fpga_power_ground_nets AW44 = GROUND GND from line 713 of ultra_fpga_power_ground_nets AY1 = GROUND GND from line 714 of ultra_fpga_power_ground_nets AY2 = GROUND GND from line 715 of ultra_fpga_power_ground_nets AY5 = GROUND GND from line 716 of ultra_fpga_power_ground_nets AY7 = GROUND GND from line 717 of ultra_fpga_power_ground_nets AY10 = GROUND GND from line 718 of ultra_fpga_power_ground_nets AY11 = GROUND GND from line 719 of ultra_fpga_power_ground_nets AY21 = GROUND GND from line 720 of ultra_fpga_power_ground_nets AY31 = GROUND GND from line 721 of ultra_fpga_power_ground_nets AY37 = GROUND GND from line 722 of ultra_fpga_power_ground_nets AY40 = GROUND GND from line 723 of ultra_fpga_power_ground_nets AY42 = GROUND GND from line 724 of ultra_fpga_power_ground_nets AY45 = GROUND GND from line 725 of ultra_fpga_power_ground_nets AY46 = GROUND GND from line 726 of ultra_fpga_power_ground_nets BA3 = GROUND GND from line 727 of ultra_fpga_power_ground_nets BA4 = GROUND GND from line 728 of ultra_fpga_power_ground_nets BA5 = GROUND GND from line 729 of ultra_fpga_power_ground_nets BA9 = GROUND GND from line 730 of ultra_fpga_power_ground_nets BA10 = GROUND GND from line 731 of ultra_fpga_power_ground_nets BA18 = GROUND GND from line 732 of ultra_fpga_power_ground_nets BA28 = GROUND GND from line 733 of ultra_fpga_power_ground_nets BA37 = GROUND GND from line 734 of ultra_fpga_power_ground_nets BA38 = GROUND GND from line 735 of ultra_fpga_power_ground_nets BA42 = GROUND GND from line 736 of ultra_fpga_power_ground_nets BA43 = GROUND GND from line 737 of ultra_fpga_power_ground_nets BA44 = GROUND GND from line 738 of ultra_fpga_power_ground_nets BB1 = GROUND GND from line 739 of ultra_fpga_power_ground_nets BB2 = GROUND GND from line 740 of ultra_fpga_power_ground_nets BB5 = GROUND GND from line 741 of ultra_fpga_power_ground_nets BB6 = GROUND GND from line 742 of ultra_fpga_power_ground_nets BB10 = GROUND GND from line 743 of ultra_fpga_power_ground_nets BB25 = GROUND GND from line 744 of ultra_fpga_power_ground_nets BB35 = GROUND GND from line 745 of ultra_fpga_power_ground_nets BB37 = GROUND GND from line 746 of ultra_fpga_power_ground_nets BB41 = GROUND GND from line 747 of ultra_fpga_power_ground_nets BB42 = GROUND GND from line 748 of ultra_fpga_power_ground_nets BB45 = GROUND GND from line 749 of ultra_fpga_power_ground_nets BB46 = GROUND GND from line 750 of ultra_fpga_power_ground_nets BC3 = GROUND GND from line 751 of ultra_fpga_power_ground_nets BC4 = GROUND GND from line 752 of ultra_fpga_power_ground_nets BC5 = GROUND GND from line 753 of ultra_fpga_power_ground_nets BC8 = GROUND GND from line 754 of ultra_fpga_power_ground_nets BC10 = GROUND GND from line 755 of ultra_fpga_power_ground_nets BC11 = GROUND GND from line 756 of ultra_fpga_power_ground_nets BC12 = GROUND GND from line 757 of ultra_fpga_power_ground_nets BC13 = GROUND GND from line 758 of ultra_fpga_power_ground_nets BC14 = GROUND GND from line 759 of ultra_fpga_power_ground_nets BC15 = GROUND GND from line 760 of ultra_fpga_power_ground_nets BC22 = GROUND GND from line 761 of ultra_fpga_power_ground_nets BC32 = GROUND GND from line 762 of ultra_fpga_power_ground_nets BC33 = GROUND GND from line 763 of ultra_fpga_power_ground_nets BC34 = GROUND GND from line 764 of ultra_fpga_power_ground_nets BC35 = GROUND GND from line 765 of ultra_fpga_power_ground_nets BC36 = GROUND GND from line 766 of ultra_fpga_power_ground_nets BC37 = GROUND GND from line 767 of ultra_fpga_power_ground_nets BC39 = GROUND GND from line 768 of ultra_fpga_power_ground_nets BC42 = GROUND GND from line 769 of ultra_fpga_power_ground_nets BC43 = GROUND GND from line 770 of ultra_fpga_power_ground_nets BC44 = GROUND GND from line 771 of ultra_fpga_power_ground_nets BD1 = GROUND GND from line 772 of ultra_fpga_power_ground_nets BD2 = GROUND GND from line 773 of ultra_fpga_power_ground_nets BD5 = GROUND GND from line 774 of ultra_fpga_power_ground_nets BD7 = GROUND GND from line 775 of ultra_fpga_power_ground_nets BD12 = GROUND GND from line 776 of ultra_fpga_power_ground_nets BD15 = GROUND GND from line 777 of ultra_fpga_power_ground_nets BD19 = GROUND GND from line 778 of ultra_fpga_power_ground_nets BD29 = GROUND GND from line 779 of ultra_fpga_power_ground_nets BD32 = GROUND GND from line 780 of ultra_fpga_power_ground_nets BD35 = GROUND GND from line 781 of ultra_fpga_power_ground_nets BD40 = GROUND GND from line 782 of ultra_fpga_power_ground_nets BD42 = GROUND GND from line 783 of ultra_fpga_power_ground_nets BD45 = GROUND GND from line 784 of ultra_fpga_power_ground_nets BD46 = GROUND GND from line 785 of ultra_fpga_power_ground_nets BE2 = GROUND GND from line 786 of ultra_fpga_power_ground_nets BE3 = GROUND GND from line 787 of ultra_fpga_power_ground_nets BE4 = GROUND GND from line 788 of ultra_fpga_power_ground_nets BE5 = GROUND GND from line 789 of ultra_fpga_power_ground_nets BE9 = GROUND GND from line 790 of ultra_fpga_power_ground_nets BE12 = GROUND GND from line 791 of ultra_fpga_power_ground_nets BE13 = GROUND GND from line 792 of ultra_fpga_power_ground_nets BE14 = GROUND GND from line 793 of ultra_fpga_power_ground_nets BE15 = GROUND GND from line 794 of ultra_fpga_power_ground_nets BE26 = GROUND GND from line 795 of ultra_fpga_power_ground_nets BE32 = GROUND GND from line 796 of ultra_fpga_power_ground_nets BE33 = GROUND GND from line 797 of ultra_fpga_power_ground_nets BE34 = GROUND GND from line 798 of ultra_fpga_power_ground_nets BE35 = GROUND GND from line 799 of ultra_fpga_power_ground_nets BE38 = GROUND GND from line 800 of ultra_fpga_power_ground_nets BE42 = GROUND GND from line 801 of ultra_fpga_power_ground_nets BE43 = GROUND GND from line 802 of ultra_fpga_power_ground_nets BE44 = GROUND GND from line 803 of ultra_fpga_power_ground_nets BE45 = GROUND GND from line 804 of ultra_fpga_power_ground_nets BF5 = GROUND GND from line 805 of ultra_fpga_power_ground_nets BF6 = GROUND GND from line 806 of ultra_fpga_power_ground_nets BF11 = GROUND GND from line 807 of ultra_fpga_power_ground_nets BF12 = GROUND GND from line 808 of ultra_fpga_power_ground_nets BF15 = GROUND GND from line 809 of ultra_fpga_power_ground_nets BF23 = GROUND GND from line 810 of ultra_fpga_power_ground_nets BF32 = GROUND GND from line 811 of ultra_fpga_power_ground_nets BF35 = GROUND GND from line 812 of ultra_fpga_power_ground_nets BF36 = GROUND GND from line 813 of ultra_fpga_power_ground_nets BF41 = GROUND GND from line 814 of ultra_fpga_power_ground_nets BF42 = GROUND GND from line 815 of ultra_fpga_power_ground_nets BF29 = HUB_FPGA_LED50_DRV IO_L22N_T3U_N7_DBC_AD0N_68 from line 205 of led_lemo_translator_driver_nets BF30 = HUB_FPGA_LED51_DRV IO_L24P_T3U_N10_68 from line 206 of led_lemo_translator_driver_nets BF31 = HUB_FPGA_LED52_DRV IO_L24N_T3U_N11_68 from line 207 of led_lemo_translator_driver_nets BA29 = Hub_I2C_to_FPGA_SCL IO_L18P_T2U_N10_AD2P_67 from line 144 of i2c_sensor_bus_nets BE16 = Hub_I2C_to_FPGA_SCL IO_L23P_T3U_N8_I2C_SCLK_65 from line 141 of i2c_sensor_bus_nets BB29 = Hub_I2C_to_FPGA_SDA IO_L18N_T2U_N11_AD2N_67 from line 145 of i2c_sensor_bus_nets BF16 = Hub_I2C_to_FPGA_SDA IO_L23N_T3U_N9_I2C_SDA_65 from line 142 of i2c_sensor_bus_nets AP16 = Hubs_SMB_Alert_B IO_L21N_T3L_N5_AD8N_84 from line 1035 of power_supply_all_other_nets BA16 = I2C_Buf_1501_ENABLE IO_L3P_T0L_N4_AD15P_94 from line 74 of i2c_sensor_bus_nets BA15 = I2C_Buf_1502_ENABLE IO_L1N_T0L_N1_DBC_94 from line 75 of i2c_sensor_bus_nets BB16 = I2C_Buf_1503_ENABLE IO_L4N_T0U_N7_DBC_AD7N_94 from line 76 of i2c_sensor_bus_nets AT12 = ISO_SLOT_HW_ADRS_0 IO_L15N_T2L_N5_AD11N_84 from line 55 of hardware_address_to_rod_nets AT11 = ISO_SLOT_HW_ADRS_1 IO_T2U_N12_84 from line 56 of hardware_address_to_rod_nets AU12 = ISO_SLOT_HW_ADRS_2 IO_L17P_T2U_N8_AD10P_84 from line 57 of hardware_address_to_rod_nets AU11 = ISO_SLOT_HW_ADRS_3 IO_L17N_T2U_N9_AD10N_84 from line 58 of hardware_address_to_rod_nets AV11 = ISO_SLOT_HW_ADRS_4 IO_L7P_T1L_N0_QBC_AD13P_94 from line 60 of hardware_address_to_rod_nets AW12 = ISO_SLOT_HW_ADRS_5 IO_L12N_T1U_N11_GC_94 from line 61 of hardware_address_to_rod_nets AW11 = ISO_SLOT_HW_ADRS_6 IO_L7N_T1L_N1_QBC_AD13N_94 from line 62 of hardware_address_to_rod_nets AY12 = ISO_SLOT_HW_ADRS_7 IO_L9P_T1L_N4_AD12P_94 from line 63 of hardware_address_to_rod_nets J22 = Logic_Clk_320.64_MHz_to_FPGA_Cmp IO_L11N_T1U_N9_GC_71 from line 622 of clock_generation_nets K22 = Logic_Clk_320.64_MHz_to_FPGA_Dir IO_L11P_T1U_N8_GC_71 from line 621 of clock_generation_nets H24 = Logic_Clk_40.08_MHz_to_FPGA_Cmp IO_L12N_T1U_N11_GC_71 from line 60 of clock_40.08_MHz_distribution_nets J24 = Logic_Clk_40.08_MHz_to_FPGA_Dir IO_L12P_T1U_N10_GC_71 from line 59 of clock_40.08_MHz_distribution_nets Y37 = MGT_AVAUX MGTVCCAUX_LC from line 1358 of ultra_fpga_power_ground_nets AB36 = MGT_AVAUX MGTVCCAUX_LC from line 1359 of ultra_fpga_power_ground_nets J35 = MGT_AVAUX MGTVCCAUX_LN from line 1365 of ultra_fpga_power_ground_nets L34 = MGT_AVAUX MGTVCCAUX_LN from line 1366 of ultra_fpga_power_ground_nets AK36 = MGT_AVAUX MGTVCCAUX_LS from line 1372 of ultra_fpga_power_ground_nets AM37 = MGT_AVAUX MGTVCCAUX_LS from line 1373 of ultra_fpga_power_ground_nets Y10 = MGT_AVAUX MGTVCCAUX_RC from line 1379 of ultra_fpga_power_ground_nets AB11 = MGT_AVAUX MGTVCCAUX_RC from line 1380 of ultra_fpga_power_ground_nets J12 = MGT_AVAUX MGTVCCAUX_RN from line 1386 of ultra_fpga_power_ground_nets L13 = MGT_AVAUX MGTVCCAUX_RN from line 1387 of ultra_fpga_power_ground_nets AK11 = MGT_AVAUX MGTVCCAUX_RS from line 1393 of ultra_fpga_power_ground_nets AM10 = MGT_AVAUX MGTVCCAUX_RS from line 1394 of ultra_fpga_power_ground_nets U35 = MGT_AVCC MGTAVCC_LC from line 1146 of ultra_fpga_power_ground_nets V36 = MGT_AVCC MGTAVCC_LC from line 1147 of ultra_fpga_power_ground_nets W34 = MGT_AVCC MGTAVCC_LC from line 1148 of ultra_fpga_power_ground_nets W38 = MGT_AVCC MGTAVCC_LC from line 1149 of ultra_fpga_power_ground_nets AA35 = MGT_AVCC MGTAVCC_LC from line 1150 of ultra_fpga_power_ground_nets AC34 = MGT_AVCC MGTAVCC_LC from line 1151 of ultra_fpga_power_ground_nets AD37 = MGT_AVCC MGTAVCC_LC from line 1152 of ultra_fpga_power_ground_nets AE35 = MGT_AVCC MGTAVCC_LC from line 1153 of ultra_fpga_power_ground_nets AF36 = MGT_AVCC MGTAVCC_LC from line 1154 of ultra_fpga_power_ground_nets F36 = MGT_AVCC MGTAVCC_LN from line 1160 of ultra_fpga_power_ground_nets G34 = MGT_AVCC MGTAVCC_LN from line 1161 of ultra_fpga_power_ground_nets H37 = MGT_AVCC MGTAVCC_LN from line 1162 of ultra_fpga_power_ground_nets K36 = MGT_AVCC MGTAVCC_LN from line 1163 of ultra_fpga_power_ground_nets M37 = MGT_AVCC MGTAVCC_LN from line 1164 of ultra_fpga_power_ground_nets N35 = MGT_AVCC MGTAVCC_LN from line 1165 of ultra_fpga_power_ground_nets P36 = MGT_AVCC MGTAVCC_LN from line 1166 of ultra_fpga_power_ground_nets R34 = MGT_AVCC MGTAVCC_LN from line 1167 of ultra_fpga_power_ground_nets T37 = MGT_AVCC MGTAVCC_LN from line 1168 of ultra_fpga_power_ground_nets AG34 = MGT_AVCC MGTAVCC_LS from line 1174 of ultra_fpga_power_ground_nets AH37 = MGT_AVCC MGTAVCC_LS from line 1175 of ultra_fpga_power_ground_nets AJ35 = MGT_AVCC MGTAVCC_LS from line 1176 of ultra_fpga_power_ground_nets AL34 = MGT_AVCC MGTAVCC_LS from line 1177 of ultra_fpga_power_ground_nets AL38 = MGT_AVCC MGTAVCC_LS from line 1178 of ultra_fpga_power_ground_nets U12 = MGT_AVCC MGTAVCC_RC from line 1184 of ultra_fpga_power_ground_nets V11 = MGT_AVCC MGTAVCC_RC from line 1185 of ultra_fpga_power_ground_nets W9 = MGT_AVCC MGTAVCC_RC from line 1186 of ultra_fpga_power_ground_nets W13 = MGT_AVCC MGTAVCC_RC from line 1187 of ultra_fpga_power_ground_nets AA12 = MGT_AVCC MGTAVCC_RC from line 1188 of ultra_fpga_power_ground_nets AC13 = MGT_AVCC MGTAVCC_RC from line 1189 of ultra_fpga_power_ground_nets AD10 = MGT_AVCC MGTAVCC_RC from line 1190 of ultra_fpga_power_ground_nets AE12 = MGT_AVCC MGTAVCC_RC from line 1191 of ultra_fpga_power_ground_nets AF11 = MGT_AVCC MGTAVCC_RC from line 1192 of ultra_fpga_power_ground_nets F11 = MGT_AVCC MGTAVCC_RN from line 1198 of ultra_fpga_power_ground_nets G13 = MGT_AVCC MGTAVCC_RN from line 1199 of ultra_fpga_power_ground_nets H10 = MGT_AVCC MGTAVCC_RN from line 1200 of ultra_fpga_power_ground_nets K11 = MGT_AVCC MGTAVCC_RN from line 1201 of ultra_fpga_power_ground_nets M10 = MGT_AVCC MGTAVCC_RN from line 1202 of ultra_fpga_power_ground_nets N12 = MGT_AVCC MGTAVCC_RN from line 1203 of ultra_fpga_power_ground_nets P11 = MGT_AVCC MGTAVCC_RN from line 1204 of ultra_fpga_power_ground_nets R13 = MGT_AVCC MGTAVCC_RN from line 1205 of ultra_fpga_power_ground_nets T10 = MGT_AVCC MGTAVCC_RN from line 1206 of ultra_fpga_power_ground_nets AG13 = MGT_AVCC MGTAVCC_RS from line 1212 of ultra_fpga_power_ground_nets AH10 = MGT_AVCC MGTAVCC_RS from line 1213 of ultra_fpga_power_ground_nets AJ12 = MGT_AVCC MGTAVCC_RS from line 1214 of ultra_fpga_power_ground_nets AL9 = MGT_AVCC MGTAVCC_RS from line 1215 of ultra_fpga_power_ground_nets AL13 = MGT_AVCC MGTAVCC_RS from line 1216 of ultra_fpga_power_ground_nets AH40 = MGT_AVTT MGTAVTTRCAL_LC from line 118 of ultra_dci_vref_mgt_calib_resistors_nets D40 = MGT_AVTT MGTAVTTRCAL_LN from line 121 of ultra_dci_vref_mgt_calib_resistors_nets AH7 = MGT_AVTT MGTAVTTRCAL_RC from line 124 of ultra_dci_vref_mgt_calib_resistors_nets D7 = MGT_AVTT MGTAVTTRCAL_RN from line 127 of ultra_dci_vref_mgt_calib_resistors_nets U39 = MGT_AVTT MGTAVTT_LC from line 1230 of ultra_fpga_power_ground_nets V40 = MGT_AVTT MGTAVTT_LC from line 1231 of ultra_fpga_power_ground_nets Y41 = MGT_AVTT MGTAVTT_LC from line 1232 of ultra_fpga_power_ground_nets AA39 = MGT_AVTT MGTAVTT_LC from line 1233 of ultra_fpga_power_ground_nets AB40 = MGT_AVTT MGTAVTT_LC from line 1234 of ultra_fpga_power_ground_nets AC38 = MGT_AVTT MGTAVTT_LC from line 1235 of ultra_fpga_power_ground_nets AD41 = MGT_AVTT MGTAVTT_LC from line 1236 of ultra_fpga_power_ground_nets AE39 = MGT_AVTT MGTAVTT_LC from line 1237 of ultra_fpga_power_ground_nets AF40 = MGT_AVTT MGTAVTT_LC from line 1238 of ultra_fpga_power_ground_nets AG38 = MGT_AVTT MGTAVTT_LC from line 1239 of ultra_fpga_power_ground_nets AJ39 = MGT_AVTT MGTAVTT_LC from line 1240 of ultra_fpga_power_ground_nets AK40 = MGT_AVTT MGTAVTT_LC from line 1241 of ultra_fpga_power_ground_nets AM41 = MGT_AVTT MGTAVTT_LC from line 1242 of ultra_fpga_power_ground_nets AN39 = MGT_AVTT MGTAVTT_LC from line 1243 of ultra_fpga_power_ground_nets AP40 = MGT_AVTT MGTAVTT_LC from line 1244 of ultra_fpga_power_ground_nets AR38 = MGT_AVTT MGTAVTT_LC from line 1245 of ultra_fpga_power_ground_nets AT41 = MGT_AVTT MGTAVTT_LC from line 1246 of ultra_fpga_power_ground_nets A43 = MGT_AVTT MGTAVTT_LN from line 1252 of ultra_fpga_power_ground_nets B36 = MGT_AVTT MGTAVTT_LN from line 1253 of ultra_fpga_power_ground_nets B40 = MGT_AVTT MGTAVTT_LN from line 1254 of ultra_fpga_power_ground_nets C38 = MGT_AVTT MGTAVTT_LN from line 1255 of ultra_fpga_power_ground_nets D37 = MGT_AVTT MGTAVTT_LN from line 1256 of ultra_fpga_power_ground_nets E39 = MGT_AVTT MGTAVTT_LN from line 1257 of ultra_fpga_power_ground_nets F40 = MGT_AVTT MGTAVTT_LN from line 1258 of ultra_fpga_power_ground_nets G38 = MGT_AVTT MGTAVTT_LN from line 1259 of ultra_fpga_power_ground_nets H41 = MGT_AVTT MGTAVTT_LN from line 1260 of ultra_fpga_power_ground_nets J39 = MGT_AVTT MGTAVTT_LN from line 1261 of ultra_fpga_power_ground_nets K40 = MGT_AVTT MGTAVTT_LN from line 1262 of ultra_fpga_power_ground_nets L38 = MGT_AVTT MGTAVTT_LN from line 1263 of ultra_fpga_power_ground_nets M41 = MGT_AVTT MGTAVTT_LN from line 1264 of ultra_fpga_power_ground_nets N39 = MGT_AVTT MGTAVTT_LN from line 1265 of ultra_fpga_power_ground_nets P40 = MGT_AVTT MGTAVTT_LN from line 1266 of ultra_fpga_power_ground_nets R38 = MGT_AVTT MGTAVTT_LN from line 1267 of ultra_fpga_power_ground_nets T41 = MGT_AVTT MGTAVTT_LN from line 1268 of ultra_fpga_power_ground_nets AU39 = MGT_AVTT MGTAVTT_LS from line 1274 of ultra_fpga_power_ground_nets AV40 = MGT_AVTT MGTAVTT_LS from line 1275 of ultra_fpga_power_ground_nets AW38 = MGT_AVTT MGTAVTT_LS from line 1276 of ultra_fpga_power_ground_nets AY41 = MGT_AVTT MGTAVTT_LS from line 1277 of ultra_fpga_power_ground_nets BA39 = MGT_AVTT MGTAVTT_LS from line 1278 of ultra_fpga_power_ground_nets BB40 = MGT_AVTT MGTAVTT_LS from line 1279 of ultra_fpga_power_ground_nets BC38 = MGT_AVTT MGTAVTT_LS from line 1280 of ultra_fpga_power_ground_nets BD41 = MGT_AVTT MGTAVTT_LS from line 1281 of ultra_fpga_power_ground_nets BE39 = MGT_AVTT MGTAVTT_LS from line 1282 of ultra_fpga_power_ground_nets BF37 = MGT_AVTT MGTAVTT_LS from line 1283 of ultra_fpga_power_ground_nets BF40 = MGT_AVTT MGTAVTT_LS from line 1284 of ultra_fpga_power_ground_nets U8 = MGT_AVTT MGTAVTT_RC from line 1290 of ultra_fpga_power_ground_nets V7 = MGT_AVTT MGTAVTT_RC from line 1291 of ultra_fpga_power_ground_nets Y6 = MGT_AVTT MGTAVTT_RC from line 1292 of ultra_fpga_power_ground_nets AA8 = MGT_AVTT MGTAVTT_RC from line 1293 of ultra_fpga_power_ground_nets AB7 = MGT_AVTT MGTAVTT_RC from line 1294 of ultra_fpga_power_ground_nets AC9 = MGT_AVTT MGTAVTT_RC from line 1295 of ultra_fpga_power_ground_nets AD6 = MGT_AVTT MGTAVTT_RC from line 1296 of ultra_fpga_power_ground_nets AE8 = MGT_AVTT MGTAVTT_RC from line 1297 of ultra_fpga_power_ground_nets AF7 = MGT_AVTT MGTAVTT_RC from line 1298 of ultra_fpga_power_ground_nets AG9 = MGT_AVTT MGTAVTT_RC from line 1299 of ultra_fpga_power_ground_nets AJ8 = MGT_AVTT MGTAVTT_RC from line 1300 of ultra_fpga_power_ground_nets AK7 = MGT_AVTT MGTAVTT_RC from line 1301 of ultra_fpga_power_ground_nets AM6 = MGT_AVTT MGTAVTT_RC from line 1302 of ultra_fpga_power_ground_nets AN8 = MGT_AVTT MGTAVTT_RC from line 1303 of ultra_fpga_power_ground_nets AP7 = MGT_AVTT MGTAVTT_RC from line 1304 of ultra_fpga_power_ground_nets AR9 = MGT_AVTT MGTAVTT_RC from line 1305 of ultra_fpga_power_ground_nets AT6 = MGT_AVTT MGTAVTT_RC from line 1306 of ultra_fpga_power_ground_nets A4 = MGT_AVTT MGTAVTT_RN from line 1312 of ultra_fpga_power_ground_nets B7 = MGT_AVTT MGTAVTT_RN from line 1313 of ultra_fpga_power_ground_nets B11 = MGT_AVTT MGTAVTT_RN from line 1314 of ultra_fpga_power_ground_nets C9 = MGT_AVTT MGTAVTT_RN from line 1315 of ultra_fpga_power_ground_nets D10 = MGT_AVTT MGTAVTT_RN from line 1316 of ultra_fpga_power_ground_nets E8 = MGT_AVTT MGTAVTT_RN from line 1317 of ultra_fpga_power_ground_nets F7 = MGT_AVTT MGTAVTT_RN from line 1318 of ultra_fpga_power_ground_nets G9 = MGT_AVTT MGTAVTT_RN from line 1319 of ultra_fpga_power_ground_nets H6 = MGT_AVTT MGTAVTT_RN from line 1320 of ultra_fpga_power_ground_nets J8 = MGT_AVTT MGTAVTT_RN from line 1321 of ultra_fpga_power_ground_nets K7 = MGT_AVTT MGTAVTT_RN from line 1322 of ultra_fpga_power_ground_nets L9 = MGT_AVTT MGTAVTT_RN from line 1323 of ultra_fpga_power_ground_nets M6 = MGT_AVTT MGTAVTT_RN from line 1324 of ultra_fpga_power_ground_nets N8 = MGT_AVTT MGTAVTT_RN from line 1325 of ultra_fpga_power_ground_nets P7 = MGT_AVTT MGTAVTT_RN from line 1326 of ultra_fpga_power_ground_nets R9 = MGT_AVTT MGTAVTT_RN from line 1327 of ultra_fpga_power_ground_nets T6 = MGT_AVTT MGTAVTT_RN from line 1328 of ultra_fpga_power_ground_nets AU8 = MGT_AVTT MGTAVTT_RS from line 1334 of ultra_fpga_power_ground_nets AV7 = MGT_AVTT MGTAVTT_RS from line 1335 of ultra_fpga_power_ground_nets AW9 = MGT_AVTT MGTAVTT_RS from line 1336 of ultra_fpga_power_ground_nets AY6 = MGT_AVTT MGTAVTT_RS from line 1337 of ultra_fpga_power_ground_nets BA8 = MGT_AVTT MGTAVTT_RS from line 1338 of ultra_fpga_power_ground_nets BB7 = MGT_AVTT MGTAVTT_RS from line 1339 of ultra_fpga_power_ground_nets BC9 = MGT_AVTT MGTAVTT_RS from line 1340 of ultra_fpga_power_ground_nets BD6 = MGT_AVTT MGTAVTT_RS from line 1341 of ultra_fpga_power_ground_nets BE8 = MGT_AVTT MGTAVTT_RS from line 1342 of ultra_fpga_power_ground_nets BF7 = MGT_AVTT MGTAVTT_RS from line 1343 of ultra_fpga_power_ground_nets BF10 = MGT_AVTT MGTAVTT_RS from line 1344 of ultra_fpga_power_ground_nets W46 = MGT_FO_CH_10_OUT_Hub_CMP MGTYRXN0_128 from line 10801 of mgt_fanout_channel_nets W45 = MGT_FO_CH_10_OUT_Hub_DIR MGTYRXP0_128 from line 10800 of mgt_fanout_channel_nets Y43 = MGT_FO_CH_11_OUT_Hub_CMP MGTYRXP3_127 from line 10794 of mgt_fanout_channel_nets Y44 = MGT_FO_CH_11_OUT_Hub_DIR MGTYRXN3_127 from line 10795 of mgt_fanout_channel_nets AA46 = MGT_FO_CH_12_OUT_Hub_CMP MGTYRXN2_127 from line 10791 of mgt_fanout_channel_nets AA45 = MGT_FO_CH_12_OUT_Hub_DIR MGTYRXP2_127 from line 10790 of mgt_fanout_channel_nets AB43 = MGT_FO_CH_13_OUT_Hub_CMP MGTYRXP1_127 from line 10786 of mgt_fanout_channel_nets AB44 = MGT_FO_CH_13_OUT_Hub_DIR MGTYRXN1_127 from line 10787 of mgt_fanout_channel_nets AC46 = MGT_FO_CH_14_OUT_Hub_CMP MGTYRXN0_127 from line 10783 of mgt_fanout_channel_nets AC45 = MGT_FO_CH_14_OUT_Hub_DIR MGTYRXP0_127 from line 10782 of mgt_fanout_channel_nets AD43 = MGT_FO_CH_15_OUT_Hub_CMP MGTYRXP3_126 from line 10776 of mgt_fanout_channel_nets AD44 = MGT_FO_CH_15_OUT_Hub_DIR MGTYRXN3_126 from line 10777 of mgt_fanout_channel_nets AE46 = MGT_FO_CH_16_OUT_Hub_CMP MGTYRXN2_126 from line 10773 of mgt_fanout_channel_nets AE45 = MGT_FO_CH_16_OUT_Hub_DIR MGTYRXP2_126 from line 10772 of mgt_fanout_channel_nets K43 = MGT_FO_CH_17_OUT_Hub_CMP MGTYRXP1_130 from line 10842 of mgt_fanout_channel_nets K44 = MGT_FO_CH_17_OUT_Hub_DIR MGTYRXN1_130 from line 10843 of mgt_fanout_channel_nets L46 = MGT_FO_CH_18_OUT_Hub_CMP MGTYRXN0_130 from line 10839 of mgt_fanout_channel_nets L45 = MGT_FO_CH_18_OUT_Hub_DIR MGTYRXP0_130 from line 10838 of mgt_fanout_channel_nets M43 = MGT_FO_CH_19_OUT_Hub_CMP MGTYRXP3_129 from line 10831 of mgt_fanout_channel_nets M44 = MGT_FO_CH_19_OUT_Hub_DIR MGTYRXN3_129 from line 10832 of mgt_fanout_channel_nets AF43 = MGT_FO_CH_1_OUT_Hub_CMP MGTYRXP1_126 from line 10768 of mgt_fanout_channel_nets AF44 = MGT_FO_CH_1_OUT_Hub_DIR MGTYRXN1_126 from line 10769 of mgt_fanout_channel_nets N46 = MGT_FO_CH_20_OUT_Hub_CMP MGTYRXN2_129 from line 10828 of mgt_fanout_channel_nets N45 = MGT_FO_CH_20_OUT_Hub_DIR MGTYRXP2_129 from line 10827 of mgt_fanout_channel_nets P43 = MGT_FO_CH_21_OUT_Hub_CMP MGTYRXP1_129 from line 10823 of mgt_fanout_channel_nets P44 = MGT_FO_CH_21_OUT_Hub_DIR MGTYRXN1_129 from line 10824 of mgt_fanout_channel_nets R46 = MGT_FO_CH_22_OUT_Hub_CMP MGTYRXN0_129 from line 10820 of mgt_fanout_channel_nets R45 = MGT_FO_CH_22_OUT_Hub_DIR MGTYRXP0_129 from line 10819 of mgt_fanout_channel_nets T43 = MGT_FO_CH_23_OUT_Hub_CMP MGTYRXP3_128 from line 10812 of mgt_fanout_channel_nets T44 = MGT_FO_CH_23_OUT_Hub_DIR MGTYRXN3_128 from line 10813 of mgt_fanout_channel_nets U46 = MGT_FO_CH_24_OUT_Hub_CMP MGTYRXN2_128 from line 10809 of mgt_fanout_channel_nets U45 = MGT_FO_CH_24_OUT_Hub_DIR MGTYRXP2_128 from line 10808 of mgt_fanout_channel_nets B43 = MGT_FO_CH_25_OUT_Hub_CMP MGTYRXP3_132 from line 10880 of mgt_fanout_channel_nets B44 = MGT_FO_CH_25_OUT_Hub_DIR MGTYRXN3_132 from line 10881 of mgt_fanout_channel_nets C46 = MGT_FO_CH_26_OUT_Hub_CMP MGTYRXN2_132 from line 10877 of mgt_fanout_channel_nets C45 = MGT_FO_CH_26_OUT_Hub_DIR MGTYRXP2_132 from line 10876 of mgt_fanout_channel_nets D43 = MGT_FO_CH_27_OUT_Hub_CMP MGTYRXP1_132 from line 10872 of mgt_fanout_channel_nets D44 = MGT_FO_CH_27_OUT_Hub_DIR MGTYRXN1_132 from line 10873 of mgt_fanout_channel_nets E46 = MGT_FO_CH_28_OUT_Hub_CMP MGTYRXN0_132 from line 10869 of mgt_fanout_channel_nets E45 = MGT_FO_CH_28_OUT_Hub_DIR MGTYRXP0_132 from line 10868 of mgt_fanout_channel_nets F43 = MGT_FO_CH_29_OUT_Hub_CMP MGTYRXP1_131 from line 10861 of mgt_fanout_channel_nets F44 = MGT_FO_CH_29_OUT_Hub_DIR MGTYRXN1_131 from line 10862 of mgt_fanout_channel_nets AG46 = MGT_FO_CH_2_OUT_Hub_CMP MGTYRXN0_126 from line 10765 of mgt_fanout_channel_nets AG45 = MGT_FO_CH_2_OUT_Hub_DIR MGTYRXP0_126 from line 10764 of mgt_fanout_channel_nets G46 = MGT_FO_CH_30_OUT_Hub_CMP MGTYRXN0_131 from line 10858 of mgt_fanout_channel_nets G45 = MGT_FO_CH_30_OUT_Hub_DIR MGTYRXP0_131 from line 10857 of mgt_fanout_channel_nets H43 = MGT_FO_CH_31_OUT_Hub_CMP MGTYRXP3_130 from line 10850 of mgt_fanout_channel_nets H44 = MGT_FO_CH_31_OUT_Hub_DIR MGTYRXN3_130 from line 10851 of mgt_fanout_channel_nets J46 = MGT_FO_CH_32_OUT_Hub_CMP MGTYRXN2_130 from line 10847 of mgt_fanout_channel_nets J45 = MGT_FO_CH_32_OUT_Hub_DIR MGTYRXP2_130 from line 10846 of mgt_fanout_channel_nets G15 = MGT_FO_CH_33_OUT_Hub_CMP MGTHRXN2_231 from line 10930 of mgt_fanout_channel_nets G16 = MGT_FO_CH_33_OUT_Hub_DIR MGTHRXP2_231 from line 10929 of mgt_fanout_channel_nets E16 = MGT_FO_CH_34_OUT_Hub_CMP MGTHRXP3_231 from line 10925 of mgt_fanout_channel_nets E15 = MGT_FO_CH_34_OUT_Hub_DIR MGTHRXN3_231 from line 10926 of mgt_fanout_channel_nets E31 = MGT_FO_CH_35_OUT_Hub_CMP MGTYRXP3_131 from line 10910 of mgt_fanout_channel_nets E32 = MGT_FO_CH_35_OUT_Hub_DIR MGTYRXN3_131 from line 10911 of mgt_fanout_channel_nets G32 = MGT_FO_CH_36_OUT_Hub_CMP MGTYRXN2_131 from line 10907 of mgt_fanout_channel_nets G31 = MGT_FO_CH_36_OUT_Hub_DIR MGTYRXP2_131 from line 10906 of mgt_fanout_channel_nets A32 = MGT_FO_CH_37_OUT_Hub_CMP MGTYRXN3_133 from line 10900 of mgt_fanout_channel_nets A31 = MGT_FO_CH_37_OUT_Hub_DIR MGTYRXP3_133 from line 10899 of mgt_fanout_channel_nets B34 = MGT_FO_CH_38_OUT_Hub_CMP MGTYRXN2_133 from line 10896 of mgt_fanout_channel_nets B33 = MGT_FO_CH_38_OUT_Hub_DIR MGTYRXP2_133 from line 10895 of mgt_fanout_channel_nets C31 = MGT_FO_CH_39_OUT_Hub_CMP MGTYRXP1_133 from line 10891 of mgt_fanout_channel_nets C32 = MGT_FO_CH_39_OUT_Hub_DIR MGTYRXN1_133 from line 10892 of mgt_fanout_channel_nets AH43 = MGT_FO_CH_3_OUT_Hub_CMP MGTYRXP3_125 from line 10758 of mgt_fanout_channel_nets AH44 = MGT_FO_CH_3_OUT_Hub_DIR MGTYRXN3_125 from line 10759 of mgt_fanout_channel_nets D34 = MGT_FO_CH_40_OUT_Hub_CMP MGTYRXN0_133 from line 10888 of mgt_fanout_channel_nets D33 = MGT_FO_CH_40_OUT_Hub_DIR MGTYRXP0_133 from line 10887 of mgt_fanout_channel_nets E1 = MGT_FO_CH_41_OUT_Hub_CMP MGTHRXN0_232 from line 10968 of mgt_fanout_channel_nets E2 = MGT_FO_CH_41_OUT_Hub_DIR MGTHRXP0_232 from line 10967 of mgt_fanout_channel_nets D4 = MGT_FO_CH_42_OUT_Hub_CMP MGTHRXP1_232 from line 10963 of mgt_fanout_channel_nets D3 = MGT_FO_CH_42_OUT_Hub_DIR MGTHRXN1_232 from line 10964 of mgt_fanout_channel_nets C1 = MGT_FO_CH_43_OUT_Hub_CMP MGTHRXN2_232 from line 10960 of mgt_fanout_channel_nets C2 = MGT_FO_CH_43_OUT_Hub_DIR MGTHRXP2_232 from line 10959 of mgt_fanout_channel_nets B4 = MGT_FO_CH_44_OUT_Hub_CMP MGTHRXP3_232 from line 10955 of mgt_fanout_channel_nets B3 = MGT_FO_CH_44_OUT_Hub_DIR MGTHRXN3_232 from line 10956 of mgt_fanout_channel_nets D13 = MGT_FO_CH_45_OUT_Hub_CMP MGTHRXN0_233 from line 10949 of mgt_fanout_channel_nets D14 = MGT_FO_CH_45_OUT_Hub_DIR MGTHRXP0_233 from line 10948 of mgt_fanout_channel_nets C16 = MGT_FO_CH_46_OUT_Hub_CMP MGTHRXP1_233 from line 10944 of mgt_fanout_channel_nets C15 = MGT_FO_CH_46_OUT_Hub_DIR MGTHRXN1_233 from line 10945 of mgt_fanout_channel_nets B13 = MGT_FO_CH_47_OUT_Hub_CMP MGTHRXN2_233 from line 10941 of mgt_fanout_channel_nets B14 = MGT_FO_CH_47_OUT_Hub_DIR MGTHRXP2_233 from line 10940 of mgt_fanout_channel_nets A15 = MGT_FO_CH_48_OUT_Hub_CMP MGTHRXN3_233 from line 10937 of mgt_fanout_channel_nets A16 = MGT_FO_CH_48_OUT_Hub_DIR MGTHRXP3_233 from line 10936 of mgt_fanout_channel_nets N1 = MGT_FO_CH_49_OUT_Hub_CMP MGTHRXN2_229 from line 11009 of mgt_fanout_channel_nets N2 = MGT_FO_CH_49_OUT_Hub_DIR MGTHRXP2_229 from line 11008 of mgt_fanout_channel_nets AJ46 = MGT_FO_CH_4_OUT_Hub_CMP MGTYRXN2_125 from line 10755 of mgt_fanout_channel_nets AJ45 = MGT_FO_CH_4_OUT_Hub_DIR MGTYRXP2_125 from line 10754 of mgt_fanout_channel_nets M4 = MGT_FO_CH_50_OUT_Hub_CMP MGTHRXP3_229 from line 11004 of mgt_fanout_channel_nets M3 = MGT_FO_CH_50_OUT_Hub_DIR MGTHRXN3_229 from line 11005 of mgt_fanout_channel_nets L1 = MGT_FO_CH_51_OUT_Hub_CMP MGTHRXN0_230 from line 10998 of mgt_fanout_channel_nets L2 = MGT_FO_CH_51_OUT_Hub_DIR MGTHRXP0_230 from line 10997 of mgt_fanout_channel_nets K4 = MGT_FO_CH_52_OUT_Hub_CMP MGTHRXP1_230 from line 10993 of mgt_fanout_channel_nets K3 = MGT_FO_CH_52_OUT_Hub_DIR MGTHRXN1_230 from line 10994 of mgt_fanout_channel_nets J1 = MGT_FO_CH_53_OUT_Hub_CMP MGTHRXN2_230 from line 10990 of mgt_fanout_channel_nets J2 = MGT_FO_CH_53_OUT_Hub_DIR MGTHRXP2_230 from line 10989 of mgt_fanout_channel_nets H4 = MGT_FO_CH_54_OUT_Hub_CMP MGTHRXP3_230 from line 10985 of mgt_fanout_channel_nets H3 = MGT_FO_CH_54_OUT_Hub_DIR MGTHRXN3_230 from line 10986 of mgt_fanout_channel_nets G1 = MGT_FO_CH_55_OUT_Hub_CMP MGTHRXN0_231 from line 10979 of mgt_fanout_channel_nets G2 = MGT_FO_CH_55_OUT_Hub_DIR MGTHRXP0_231 from line 10978 of mgt_fanout_channel_nets F4 = MGT_FO_CH_56_OUT_Hub_CMP MGTHRXP1_231 from line 10974 of mgt_fanout_channel_nets F3 = MGT_FO_CH_56_OUT_Hub_DIR MGTHRXN1_231 from line 10975 of mgt_fanout_channel_nets AA1 = MGT_FO_CH_57_OUT_Hub_CMP MGTHRXN2_227 from line 11047 of mgt_fanout_channel_nets AA2 = MGT_FO_CH_57_OUT_Hub_DIR MGTHRXP2_227 from line 11046 of mgt_fanout_channel_nets Y4 = MGT_FO_CH_58_OUT_Hub_CMP MGTHRXP3_227 from line 11042 of mgt_fanout_channel_nets Y3 = MGT_FO_CH_58_OUT_Hub_DIR MGTHRXN3_227 from line 11043 of mgt_fanout_channel_nets W1 = MGT_FO_CH_59_OUT_Hub_CMP MGTHRXN0_228 from line 11036 of mgt_fanout_channel_nets W2 = MGT_FO_CH_59_OUT_Hub_DIR MGTHRXP0_228 from line 11035 of mgt_fanout_channel_nets AK43 = MGT_FO_CH_5_OUT_Hub_CMP MGTYRXP1_125 from line 10750 of mgt_fanout_channel_nets AK44 = MGT_FO_CH_5_OUT_Hub_DIR MGTYRXN1_125 from line 10751 of mgt_fanout_channel_nets V4 = MGT_FO_CH_60_OUT_Hub_CMP MGTHRXP1_228 from line 11031 of mgt_fanout_channel_nets V3 = MGT_FO_CH_60_OUT_Hub_DIR MGTHRXN1_228 from line 11032 of mgt_fanout_channel_nets U1 = MGT_FO_CH_61_OUT_Hub_CMP MGTHRXN2_228 from line 11028 of mgt_fanout_channel_nets U2 = MGT_FO_CH_61_OUT_Hub_DIR MGTHRXP2_228 from line 11027 of mgt_fanout_channel_nets T4 = MGT_FO_CH_62_OUT_Hub_CMP MGTHRXP3_228 from line 11023 of mgt_fanout_channel_nets T3 = MGT_FO_CH_62_OUT_Hub_DIR MGTHRXN3_228 from line 11024 of mgt_fanout_channel_nets R1 = MGT_FO_CH_63_OUT_Hub_CMP MGTHRXN0_229 from line 11017 of mgt_fanout_channel_nets R2 = MGT_FO_CH_63_OUT_Hub_DIR MGTHRXP0_229 from line 11016 of mgt_fanout_channel_nets P4 = MGT_FO_CH_64_OUT_Hub_CMP MGTHRXP1_229 from line 11012 of mgt_fanout_channel_nets P3 = MGT_FO_CH_64_OUT_Hub_DIR MGTHRXN1_229 from line 11013 of mgt_fanout_channel_nets AL1 = MGT_FO_CH_65_OUT_Hub_CMP MGTHRXN0_225 from line 11093 of mgt_fanout_channel_nets AL2 = MGT_FO_CH_65_OUT_Hub_DIR MGTHRXP0_225 from line 11092 of mgt_fanout_channel_nets AK4 = MGT_FO_CH_66_OUT_Hub_CMP MGTHRXP1_225 from line 11088 of mgt_fanout_channel_nets AK3 = MGT_FO_CH_66_OUT_Hub_DIR MGTHRXN1_225 from line 11089 of mgt_fanout_channel_nets AJ1 = MGT_FO_CH_67_OUT_Hub_CMP MGTHRXN2_225 from line 11085 of mgt_fanout_channel_nets AJ2 = MGT_FO_CH_67_OUT_Hub_DIR MGTHRXP2_225 from line 11084 of mgt_fanout_channel_nets AH4 = MGT_FO_CH_68_OUT_Hub_CMP MGTHRXP3_225 from line 11080 of mgt_fanout_channel_nets AH3 = MGT_FO_CH_68_OUT_Hub_DIR MGTHRXN3_225 from line 11081 of mgt_fanout_channel_nets AG1 = MGT_FO_CH_69_OUT_Hub_CMP MGTHRXN0_226 from line 11074 of mgt_fanout_channel_nets AG2 = MGT_FO_CH_69_OUT_Hub_DIR MGTHRXP0_226 from line 11073 of mgt_fanout_channel_nets AL46 = MGT_FO_CH_6_OUT_Hub_CMP MGTYRXN0_125 from line 10747 of mgt_fanout_channel_nets AL45 = MGT_FO_CH_6_OUT_Hub_DIR MGTYRXP0_125 from line 10746 of mgt_fanout_channel_nets AF4 = MGT_FO_CH_70_OUT_Hub_CMP MGTHRXP1_226 from line 11069 of mgt_fanout_channel_nets AF3 = MGT_FO_CH_70_OUT_Hub_DIR MGTHRXN1_226 from line 11070 of mgt_fanout_channel_nets AE1 = MGT_FO_CH_71_OUT_Hub_CMP MGTHRXN2_226 from line 11066 of mgt_fanout_channel_nets AE2 = MGT_FO_CH_71_OUT_Hub_DIR MGTHRXP2_226 from line 11065 of mgt_fanout_channel_nets AD4 = MGT_FO_CH_72_OUT_Hub_CMP MGTHRXP3_226 from line 11061 of mgt_fanout_channel_nets AD3 = MGT_FO_CH_72_OUT_Hub_DIR MGTHRXN3_226 from line 11062 of mgt_fanout_channel_nets AC1 = MGT_FO_CH_73_OUT_Hub_CMP MGTHRXN0_227 from line 11055 of mgt_fanout_channel_nets AC2 = MGT_FO_CH_73_OUT_Hub_DIR MGTHRXP0_227 from line 11054 of mgt_fanout_channel_nets AB4 = MGT_FO_CH_74_OUT_Hub_CMP MGTHRXP1_227 from line 11050 of mgt_fanout_channel_nets AB3 = MGT_FO_CH_74_OUT_Hub_DIR MGTHRXN1_227 from line 11051 of mgt_fanout_channel_nets AM43 = MGT_FO_CH_7_OUT_Hub_CMP MGTYRXP3_124 from line 10740 of mgt_fanout_channel_nets AM44 = MGT_FO_CH_7_OUT_Hub_DIR MGTYRXN3_124 from line 10741 of mgt_fanout_channel_nets AN46 = MGT_FO_CH_8_OUT_Hub_CMP MGTYRXN2_124 from line 10737 of mgt_fanout_channel_nets AN45 = MGT_FO_CH_8_OUT_Hub_DIR MGTYRXP2_124 from line 10736 of mgt_fanout_channel_nets V43 = MGT_FO_CH_9_OUT_Hub_CMP MGTYRXP1_128 from line 10804 of mgt_fanout_channel_nets V44 = MGT_FO_CH_9_OUT_Hub_DIR MGTYRXN1_128 from line 10805 of mgt_fanout_channel_nets C25 = MGT_FO_EQU_ENB_GRP_1 IO_L21N_T3L_N5_AD8N_71 from line 9207 of mgt_fanout_channel_nets A21 = MGT_FO_EQU_ENB_GRP_10 IO_L21N_T3L_N5_AD8N_72 from line 9218 of mgt_fanout_channel_nets A20 = MGT_FO_EQU_ENB_GRP_11 IO_L23P_T3U_N8_72 from line 9219 of mgt_fanout_channel_nets A19 = MGT_FO_EQU_ENB_GRP_12 IO_L23N_T3U_N9_72 from line 9220 of mgt_fanout_channel_nets A18 = MGT_FO_EQU_ENB_GRP_13 IO_L24N_T3U_N11_72 from line 9221 of mgt_fanout_channel_nets A25 = MGT_FO_EQU_ENB_GRP_2 IO_L23N_T3U_N9_71 from line 9208 of mgt_fanout_channel_nets B25 = MGT_FO_EQU_ENB_GRP_3 IO_L23P_T3U_N8_71 from line 9209 of mgt_fanout_channel_nets A24 = MGT_FO_EQU_ENB_GRP_4 IO_L20P_T3L_N2_AD1P_71 from line 9210 of mgt_fanout_channel_nets C24 = MGT_FO_EQU_ENB_GRP_5 IO_L19N_T3L_N1_DBC_AD9N_71 from line 9211 of mgt_fanout_channel_nets B22 = MGT_FO_EQU_ENB_GRP_6 IO_L24N_T3U_N11_71 from line 9212 of mgt_fanout_channel_nets D20 = MGT_FO_EQU_ENB_GRP_7 IO_L20P_T3L_N2_AD1P_72 from line 9214 of mgt_fanout_channel_nets C20 = MGT_FO_EQU_ENB_GRP_8 IO_L19P_T3L_N0_DBC_AD9P_72 from line 9216 of mgt_fanout_channel_nets A23 = MGT_FO_EQU_ENB_GRP_9 IO_L20N_T3L_N3_AD1N_71 from line 9217 of mgt_fanout_channel_nets AE37 = MHz_320.64_COPY_0_CMP MGTREFCLK0N_125 from line 580 of clock_generation_nets AE36 = MHz_320.64_COPY_0_DIR MGTREFCLK0P_125 from line 579 of clock_generation_nets R37 = MHz_320.64_COPY_1_CMP MGTREFCLK0N_130 from line 589 of clock_generation_nets R36 = MHz_320.64_COPY_1_DIR MGTREFCLK0P_130 from line 588 of clock_generation_nets K35 = MHz_320.64_COPY_2_CMP MGTREFCLK1N_132 from line 598 of clock_generation_nets K34 = MHz_320.64_COPY_2_DIR MGTREFCLK1P_132 from line 597 of clock_generation_nets Y35 = MHz_320.64_COPY_3_CMP MGTREFCLK1N_127 from line 607 of clock_generation_nets Y34 = MHz_320.64_COPY_3_DIR MGTREFCLK1P_127 from line 606 of clock_generation_nets Y12 = MHz_320.64_COPY_6_CMP MGTREFCLK1N_227 from line 634 of clock_generation_nets Y13 = MHz_320.64_COPY_6_DIR MGTREFCLK1P_227 from line 633 of clock_generation_nets K12 = MHz_320.64_COPY_7_CMP MGTREFCLK1N_232 from line 643 of clock_generation_nets K13 = MHz_320.64_COPY_7_DIR MGTREFCLK1P_232 from line 642 of clock_generation_nets R10 = MHz_320.64_COPY_8_CMP MGTREFCLK0N_230 from line 652 of clock_generation_nets R11 = MHz_320.64_COPY_8_DIR MGTREFCLK0P_230 from line 651 of clock_generation_nets AE10 = MHz_320.64_COPY_9_CMP MGTREFCLK0N_225 from line 661 of clock_generation_nets AE11 = MHz_320.64_COPY_9_DIR MGTREFCLK0P_225 from line 660 of clock_generation_nets AA7 = MiniPOD_Trans_Fiber_0_Data_Cmp MGTHTXP2_227 from line 193 of hub_all_other_mgt_nets AA6 = MiniPOD_Trans_Fiber_0_Data_Dir MGTHTXN2_227 from line 192 of hub_all_other_mgt_nets AN7 = MiniPOD_Trans_Fiber_10_Data_Cmp MGTHTXP2_224 from line 217 of hub_all_other_mgt_nets AN6 = MiniPOD_Trans_Fiber_10_Data_Dir MGTHTXN2_224 from line 216 of hub_all_other_mgt_nets AR7 = MiniPOD_Trans_Fiber_11_Data_Cmp MGTHTXP0_224 from line 221 of hub_all_other_mgt_nets AR6 = MiniPOD_Trans_Fiber_11_Data_Dir MGTHTXN0_224 from line 220 of hub_all_other_mgt_nets AC7 = MiniPOD_Trans_Fiber_1_Data_Cmp MGTHTXP0_227 from line 197 of hub_all_other_mgt_nets AC6 = MiniPOD_Trans_Fiber_1_Data_Dir MGTHTXN0_227 from line 196 of hub_all_other_mgt_nets AE7 = MiniPOD_Trans_Fiber_2_Data_Cmp MGTHTXP2_226 from line 201 of hub_all_other_mgt_nets AE6 = MiniPOD_Trans_Fiber_2_Data_Dir MGTHTXN2_226 from line 200 of hub_all_other_mgt_nets AG7 = MiniPOD_Trans_Fiber_4_Data_Cmp MGTHTXP0_226 from line 205 of hub_all_other_mgt_nets AG6 = MiniPOD_Trans_Fiber_4_Data_Dir MGTHTXN0_226 from line 204 of hub_all_other_mgt_nets AJ7 = MiniPOD_Trans_Fiber_6_Data_Cmp MGTHTXP2_225 from line 209 of hub_all_other_mgt_nets AJ6 = MiniPOD_Trans_Fiber_6_Data_Dir MGTHTXN2_225 from line 208 of hub_all_other_mgt_nets AL7 = MiniPOD_Trans_Fiber_8_Data_Cmp MGTHTXP0_225 from line 213 of hub_all_other_mgt_nets AL6 = MiniPOD_Trans_Fiber_8_Data_Dir MGTHTXN0_225 from line 212 of hub_all_other_mgt_nets AB16 = NO_CONN_FPGA_BANK_0_CCLK CCLK_0 from line 211 of bank_0_and_bank_65_config_mem_nets AM19 = NO_CONN_FPGA_BANK_65_AM19 IO_L3P_T0L_N4_AD15P_A26_65 from line 241 of bank_0_and_bank_65_config_mem_nets AN18 = NO_CONN_FPGA_BANK_65_AN18 IO_L1P_T0L_N0_DBC_RS0_65 from line 243 of bank_0_and_bank_65_config_mem_nets AN19 = NO_CONN_FPGA_BANK_65_AN19 IO_L3N_T0L_N5_AD15N_A27_65 from line 242 of bank_0_and_bank_65_config_mem_nets AP18 = NO_CONN_FPGA_BANK_65_AP18 IO_L1N_T0L_N1_DBC_RS1_65 from line 244 of bank_0_and_bank_65_config_mem_nets AV19 = NO_CONN_FPGA_BANK_65_AV19 IO_T1U_N12_PERSTN1_65 from line 240 of bank_0_and_bank_65_config_mem_nets BC21 = NO_CONN_FPGA_BANK_65_BC21 IO_T2U_N12_CSI_ADV_B_65 from line 239 of bank_0_and_bank_65_config_mem_nets BD20 = NO_CONN_FPGA_BANK_65_BD20 IO_T3U_N12_PERSTN0_65 from line 238 of bank_0_and_bank_65_config_mem_nets BE20 = NO_CONN_FPGA_BANK_65_BE20 IO_L24P_T3U_N10_EMCCLK_65 from line 236 of bank_0_and_bank_65_config_mem_nets BF20 = NO_CONN_FPGA_BANK_65_BF20 IO_L24N_T3U_N11_DOUT_CSO_B_65 from line 237 of bank_0_and_bank_65_config_mem_nets A28 = No_Conn_FPGA_A28 IO_L20P_T3L_N2_AD1P_70 from line 235 of ultra_no_connect_pins_nets A29 = No_Conn_FPGA_A29 IO_L20N_T3L_N3_AD1N_70 from line 236 of ultra_no_connect_pins_nets A38 = No_Conn_FPGA_A38 NC from line 870 of ultra_no_connect_pins_nets A39 = No_Conn_FPGA_A39 NC from line 871 of ultra_no_connect_pins_nets A8 = No_Conn_FPGA_A8 NC from line 868 of ultra_no_connect_pins_nets A9 = No_Conn_FPGA_A9 NC from line 869 of ultra_no_connect_pins_nets AA10 = No_Conn_FPGA_AA10 MGTREFCLK0N_227 from line 820 of ultra_no_connect_pins_nets AA11 = No_Conn_FPGA_AA11 MGTREFCLK0P_227 from line 819 of ultra_no_connect_pins_nets AA36 = No_Conn_FPGA_AA36 MGTREFCLK0P_127 from line 761 of ultra_no_connect_pins_nets AA37 = No_Conn_FPGA_AA37 MGTREFCLK0N_127 from line 762 of ultra_no_connect_pins_nets AB12 = No_Conn_FPGA_AB12 MGTREFCLK1N_226 from line 813 of ultra_no_connect_pins_nets AB13 = No_Conn_FPGA_AB13 MGTREFCLK1P_226 from line 812 of ultra_no_connect_pins_nets AB34 = No_Conn_FPGA_AB34 MGTREFCLK1P_126 from line 754 of ultra_no_connect_pins_nets AB35 = No_Conn_FPGA_AB35 MGTREFCLK1N_126 from line 755 of ultra_no_connect_pins_nets AB38 = No_Conn_FPGA_AB38 MGTYTXP1_127 from line 477 of ultra_no_connect_pins_nets AB39 = No_Conn_FPGA_AB39 MGTYTXN1_127 from line 478 of ultra_no_connect_pins_nets AB8 = No_Conn_FPGA_AB8 MGTHTXN1_227 from line 637 of ultra_no_connect_pins_nets AB9 = No_Conn_FPGA_AB9 MGTHTXP1_227 from line 636 of ultra_no_connect_pins_nets AC10 = No_Conn_FPGA_AC10 MGTREFCLK0N_226 from line 816 of ultra_no_connect_pins_nets AC11 = No_Conn_FPGA_AC11 MGTREFCLK0P_226 from line 815 of ultra_no_connect_pins_nets AC36 = No_Conn_FPGA_AC36 MGTREFCLK0P_126 from line 757 of ultra_no_connect_pins_nets AC37 = No_Conn_FPGA_AC37 MGTREFCLK0N_126 from line 758 of ultra_no_connect_pins_nets AD12 = No_Conn_FPGA_AD12 MGTREFCLK1N_225 from line 809 of ultra_no_connect_pins_nets AD13 = No_Conn_FPGA_AD13 MGTREFCLK1P_225 from line 808 of ultra_no_connect_pins_nets AD34 = No_Conn_FPGA_AD34 MGTREFCLK1P_125 from line 750 of ultra_no_connect_pins_nets AD35 = No_Conn_FPGA_AD35 MGTREFCLK1N_125 from line 751 of ultra_no_connect_pins_nets AD38 = No_Conn_FPGA_AD38 MGTYTXP3_126 from line 454 of ultra_no_connect_pins_nets AD39 = No_Conn_FPGA_AD39 MGTYTXN3_126 from line 455 of ultra_no_connect_pins_nets AD8 = No_Conn_FPGA_AD8 MGTHTXN3_226 from line 620 of ultra_no_connect_pins_nets AD9 = No_Conn_FPGA_AD9 MGTHTXP3_226 from line 619 of ultra_no_connect_pins_nets AE40 = No_Conn_FPGA_AE40 MGTYTXP2_126 from line 457 of ultra_no_connect_pins_nets AE41 = No_Conn_FPGA_AE41 MGTYTXN2_126 from line 458 of ultra_no_connect_pins_nets AF12 = No_Conn_FPGA_AF12 MGTREFCLK1N_224 from line 802 of ultra_no_connect_pins_nets AF13 = No_Conn_FPGA_AF13 MGTREFCLK1P_224 from line 801 of ultra_no_connect_pins_nets AF34 = No_Conn_FPGA_AF34 MGTREFCLK1P_124 from line 743 of ultra_no_connect_pins_nets AF35 = No_Conn_FPGA_AF35 MGTREFCLK1N_124 from line 744 of ultra_no_connect_pins_nets AF38 = No_Conn_FPGA_AF38 MGTYTXP1_126 from line 460 of ultra_no_connect_pins_nets AF39 = No_Conn_FPGA_AF39 MGTYTXN1_126 from line 461 of ultra_no_connect_pins_nets AF8 = No_Conn_FPGA_AF8 MGTHTXN1_226 from line 623 of ultra_no_connect_pins_nets AF9 = No_Conn_FPGA_AF9 MGTHTXP1_226 from line 622 of ultra_no_connect_pins_nets AG10 = No_Conn_FPGA_AG10 MGTREFCLK0N_224 from line 805 of ultra_no_connect_pins_nets AG11 = No_Conn_FPGA_AG11 MGTREFCLK0P_224 from line 804 of ultra_no_connect_pins_nets AG36 = No_Conn_FPGA_AG36 MGTREFCLK0P_124 from line 746 of ultra_no_connect_pins_nets AG37 = No_Conn_FPGA_AG37 MGTREFCLK0N_124 from line 747 of ultra_no_connect_pins_nets AG40 = No_Conn_FPGA_AG40 MGTYTXP0_126 from line 463 of ultra_no_connect_pins_nets AG41 = No_Conn_FPGA_AG41 MGTYTXN0_126 from line 464 of ultra_no_connect_pins_nets AH12 = No_Conn_FPGA_AH12 NC from line 981 of ultra_no_connect_pins_nets AH13 = No_Conn_FPGA_AH13 NC from line 980 of ultra_no_connect_pins_nets AH34 = No_Conn_FPGA_AH34 NC from line 919 of ultra_no_connect_pins_nets AH35 = No_Conn_FPGA_AH35 NC from line 918 of ultra_no_connect_pins_nets AH38 = No_Conn_FPGA_AH38 MGTYTXP3_125 from line 434 of ultra_no_connect_pins_nets AH39 = No_Conn_FPGA_AH39 MGTYTXN3_125 from line 435 of ultra_no_connect_pins_nets AH8 = No_Conn_FPGA_AH8 MGTHTXN3_225 from line 606 of ultra_no_connect_pins_nets AH9 = No_Conn_FPGA_AH9 MGTHTXP3_225 from line 605 of ultra_no_connect_pins_nets AJ10 = No_Conn_FPGA_AJ10 NC from line 991 of ultra_no_connect_pins_nets AJ11 = No_Conn_FPGA_AJ11 NC from line 990 of ultra_no_connect_pins_nets AJ36 = No_Conn_FPGA_AJ36 NC from line 929 of ultra_no_connect_pins_nets AJ37 = No_Conn_FPGA_AJ37 NC from line 928 of ultra_no_connect_pins_nets AJ40 = No_Conn_FPGA_AJ40 MGTYTXP2_125 from line 437 of ultra_no_connect_pins_nets AJ41 = No_Conn_FPGA_AJ41 MGTYTXN2_125 from line 438 of ultra_no_connect_pins_nets AK12 = No_Conn_FPGA_AK12 NC from line 959 of ultra_no_connect_pins_nets AK13 = No_Conn_FPGA_AK13 NC from line 958 of ultra_no_connect_pins_nets AK34 = No_Conn_FPGA_AK34 NC from line 899 of ultra_no_connect_pins_nets AK35 = No_Conn_FPGA_AK35 NC from line 898 of ultra_no_connect_pins_nets AK38 = No_Conn_FPGA_AK38 MGTYTXP1_125 from line 440 of ultra_no_connect_pins_nets AK39 = No_Conn_FPGA_AK39 MGTYTXN1_125 from line 441 of ultra_no_connect_pins_nets AK8 = No_Conn_FPGA_AK8 MGTHTXN1_225 from line 609 of ultra_no_connect_pins_nets AK9 = No_Conn_FPGA_AK9 MGTHTXP1_225 from line 608 of ultra_no_connect_pins_nets AL10 = No_Conn_FPGA_AL10 NC from line 971 of ultra_no_connect_pins_nets AL11 = No_Conn_FPGA_AL11 NC from line 970 of ultra_no_connect_pins_nets AL36 = No_Conn_FPGA_AL36 NC from line 909 of ultra_no_connect_pins_nets AL37 = No_Conn_FPGA_AL37 NC from line 908 of ultra_no_connect_pins_nets AL40 = No_Conn_FPGA_AL40 MGTYTXP0_125 from line 443 of ultra_no_connect_pins_nets AL41 = No_Conn_FPGA_AL41 MGTYTXN0_125 from line 444 of ultra_no_connect_pins_nets AM12 = No_Conn_FPGA_AM12 NC from line 939 of ultra_no_connect_pins_nets AM13 = No_Conn_FPGA_AM13 NC from line 938 of ultra_no_connect_pins_nets AM23 = No_Conn_FPGA_AM23 IO_L1P_T0L_N0_DBC_66 from line 103 of ultra_no_connect_pins_nets AM24 = No_Conn_FPGA_AM24 IO_L5P_T0U_N8_AD14P_66 from line 95 of ultra_no_connect_pins_nets AM26 = No_Conn_FPGA_AM26 IO_L2P_T0L_N2_66 from line 101 of ultra_no_connect_pins_nets AM29 = No_Conn_FPGA_AM29 IO_L3P_T0L_N4_AD15P_67 from line 141 of ultra_no_connect_pins_nets AM31 = No_Conn_FPGA_AM31 IO_L2P_T0L_N2_67 from line 143 of ultra_no_connect_pins_nets AM34 = No_Conn_FPGA_AM34 NC from line 877 of ultra_no_connect_pins_nets AM35 = No_Conn_FPGA_AM35 NC from line 876 of ultra_no_connect_pins_nets AM38 = No_Conn_FPGA_AM38 MGTYTXP3_124 from line 414 of ultra_no_connect_pins_nets AM39 = No_Conn_FPGA_AM39 MGTYTXN3_124 from line 415 of ultra_no_connect_pins_nets AM8 = No_Conn_FPGA_AM8 MGTHTXN3_224 from line 592 of ultra_no_connect_pins_nets AM9 = No_Conn_FPGA_AM9 MGTHTXP3_224 from line 591 of ultra_no_connect_pins_nets AN10 = No_Conn_FPGA_AN10 NC from line 949 of ultra_no_connect_pins_nets AN11 = No_Conn_FPGA_AN11 NC from line 948 of ultra_no_connect_pins_nets AN23 = No_Conn_FPGA_AN23 IO_L1N_T0L_N1_DBC_66 from line 104 of ultra_no_connect_pins_nets AN24 = No_Conn_FPGA_AN24 IO_L5N_T0U_N9_AD14N_66 from line 96 of ultra_no_connect_pins_nets AN25 = No_Conn_FPGA_AN25 IO_L4P_T0U_N6_DBC_AD7P_66 from line 97 of ultra_no_connect_pins_nets AN26 = No_Conn_FPGA_AN26 IO_L2N_T0L_N3_66 from line 102 of ultra_no_connect_pins_nets AN28 = No_Conn_FPGA_AN28 IO_L1P_T0L_N0_DBC_67 from line 145 of ultra_no_connect_pins_nets AN29 = No_Conn_FPGA_AN29 IO_L3N_T0L_N5_AD15N_67 from line 142 of ultra_no_connect_pins_nets AN30 = No_Conn_FPGA_AN30 IO_L6P_T0U_N10_AD6P_67 from line 135 of ultra_no_connect_pins_nets AN31 = No_Conn_FPGA_AN31 IO_L2N_T0L_N3_67 from line 144 of ultra_no_connect_pins_nets AN32 = No_Conn_FPGA_AN32 IO_L1P_T0L_N0_DBC_68 from line 175 of ultra_no_connect_pins_nets AN36 = No_Conn_FPGA_AN36 NC from line 889 of ultra_no_connect_pins_nets AN37 = No_Conn_FPGA_AN37 NC from line 888 of ultra_no_connect_pins_nets AN40 = No_Conn_FPGA_AN40 MGTYTXP2_124 from line 417 of ultra_no_connect_pins_nets AN41 = No_Conn_FPGA_AN41 MGTYTXN2_124 from line 418 of ultra_no_connect_pins_nets AP22 = No_Conn_FPGA_AP22 IO_L3P_T0L_N4_AD15P_66 from line 99 of ultra_no_connect_pins_nets AP23 = No_Conn_FPGA_AP23 IO_L3N_T0L_N5_AD15N_66 from line 100 of ultra_no_connect_pins_nets AP25 = No_Conn_FPGA_AP25 IO_L4N_T0U_N7_DBC_AD7N_66 from line 98 of ultra_no_connect_pins_nets AP26 = No_Conn_FPGA_AP26 IO_L6P_T0U_N10_AD6P_66 from line 93 of ultra_no_connect_pins_nets AP27 = No_Conn_FPGA_AP27 IO_L6N_T0U_N11_AD6N_66 from line 94 of ultra_no_connect_pins_nets AP28 = No_Conn_FPGA_AP28 IO_L1N_T0L_N1_DBC_67 from line 146 of ultra_no_connect_pins_nets AP30 = No_Conn_FPGA_AP30 IO_L6N_T0U_N11_AD6N_67 from line 136 of ultra_no_connect_pins_nets AP32 = No_Conn_FPGA_AP32 IO_L1N_T0L_N1_DBC_68 from line 176 of ultra_no_connect_pins_nets AP33 = No_Conn_FPGA_AP33 IO_L5P_T0U_N8_AD14P_68 from line 168 of ultra_no_connect_pins_nets AP38 = No_Conn_FPGA_AP38 MGTYTXP1_124 from line 420 of ultra_no_connect_pins_nets AP39 = No_Conn_FPGA_AP39 MGTYTXN1_124 from line 421 of ultra_no_connect_pins_nets AP8 = No_Conn_FPGA_AP8 MGTHTXN1_224 from line 595 of ultra_no_connect_pins_nets AP9 = No_Conn_FPGA_AP9 MGTHTXP1_224 from line 594 of ultra_no_connect_pins_nets AR22 = No_Conn_FPGA_AR22 IO_L7P_T1L_N0_QBC_AD13P_66 from line 91 of ultra_no_connect_pins_nets AR23 = No_Conn_FPGA_AR23 IO_L7N_T1L_N1_QBC_AD13N_66 from line 92 of ultra_no_connect_pins_nets AR24 = No_Conn_FPGA_AR24 IO_L8P_T1L_N2_AD5P_66 from line 89 of ultra_no_connect_pins_nets AR25 = No_Conn_FPGA_AR25 IO_L8N_T1L_N3_AD5N_66 from line 90 of ultra_no_connect_pins_nets AR27 = No_Conn_FPGA_AR27 IO_L5P_T0U_N8_AD14P_67 from line 137 of ultra_no_connect_pins_nets AR28 = No_Conn_FPGA_AR28 IO_L5N_T0U_N9_AD14N_67 from line 138 of ultra_no_connect_pins_nets AR29 = No_Conn_FPGA_AR29 IO_L4P_T0U_N6_DBC_AD7P_67 from line 139 of ultra_no_connect_pins_nets AR30 = No_Conn_FPGA_AR30 IO_L4N_T0U_N7_DBC_AD7N_67 from line 140 of ultra_no_connect_pins_nets AR32 = No_Conn_FPGA_AR32 IO_L3P_T0L_N4_AD15P_68 from line 171 of ultra_no_connect_pins_nets AR33 = No_Conn_FPGA_AR33 IO_L5N_T0U_N9_AD14N_68 from line 169 of ultra_no_connect_pins_nets AR34 = No_Conn_FPGA_AR34 IO_L2P_T0L_N2_68 from line 173 of ultra_no_connect_pins_nets AR40 = No_Conn_FPGA_AR40 MGTYTXP0_124 from line 423 of ultra_no_connect_pins_nets AR41 = No_Conn_FPGA_AR41 MGTYTXN0_124 from line 424 of ultra_no_connect_pins_nets AT17 = No_Conn_FPGA_AT17 IO_L20P_T3L_N2_AD1P_84 from line 188 of ultra_no_connect_pins_nets AT22 = No_Conn_FPGA_AT22 IO_L9P_T1L_N4_AD12P_66 from line 87 of ultra_no_connect_pins_nets AT24 = No_Conn_FPGA_AT24 IO_L12P_T1U_N10_GC_66 from line 80 of ultra_no_connect_pins_nets AT25 = No_Conn_FPGA_AT25 IO_L12N_T1U_N11_GC_66 from line 81 of ultra_no_connect_pins_nets AT26 = No_Conn_FPGA_AT26 IO_L10P_T1U_N6_QBC_AD4P_66 from line 85 of ultra_no_connect_pins_nets AT3 = No_Conn_FPGA_AT3 NC from line 978 of ultra_no_connect_pins_nets AT32 = No_Conn_FPGA_AT32 IO_L3N_T0L_N5_AD15N_68 from line 172 of ultra_no_connect_pins_nets AT38 = No_Conn_FPGA_AT38 NC from line 915 of ultra_no_connect_pins_nets AT39 = No_Conn_FPGA_AT39 NC from line 914 of ultra_no_connect_pins_nets AT4 = No_Conn_FPGA_AT4 NC from line 977 of ultra_no_connect_pins_nets AT43 = No_Conn_FPGA_AT43 NC from line 916 of ultra_no_connect_pins_nets AT44 = No_Conn_FPGA_AT44 NC from line 917 of ultra_no_connect_pins_nets AT8 = No_Conn_FPGA_AT8 NC from line 979 of ultra_no_connect_pins_nets AT9 = No_Conn_FPGA_AT9 NC from line 976 of ultra_no_connect_pins_nets AU1 = No_Conn_FPGA_AU1 NC from line 984 of ultra_no_connect_pins_nets AU14 = No_Conn_FPGA_AU14 IO_L13P_T2L_N0_GC_QBC_84 from line 191 of ultra_no_connect_pins_nets AU17 = No_Conn_FPGA_AU17 IO_L20N_T3L_N3_AD1N_84 from line 189 of ultra_no_connect_pins_nets AU2 = No_Conn_FPGA_AU2 NC from line 983 of ultra_no_connect_pins_nets AU22 = No_Conn_FPGA_AU22 IO_L9N_T1L_N5_AD12N_66 from line 88 of ultra_no_connect_pins_nets AU23 = No_Conn_FPGA_AU23 IO_L11P_T1U_N8_GC_66 from line 83 of ultra_no_connect_pins_nets AU24 = No_Conn_FPGA_AU24 IO_L11N_T1U_N9_GC_66 from line 84 of ultra_no_connect_pins_nets AU26 = No_Conn_FPGA_AU26 IO_L10N_T1U_N7_QBC_AD4N_66 from line 86 of ultra_no_connect_pins_nets AU31 = No_Conn_FPGA_AU31 IO_L8P_T1L_N2_AD5P_68 from line 166 of ultra_no_connect_pins_nets AU40 = No_Conn_FPGA_AU40 NC from line 921 of ultra_no_connect_pins_nets AU41 = No_Conn_FPGA_AU41 NC from line 920 of ultra_no_connect_pins_nets AU45 = No_Conn_FPGA_AU45 NC from line 922 of ultra_no_connect_pins_nets AU46 = No_Conn_FPGA_AU46 NC from line 923 of ultra_no_connect_pins_nets AU6 = No_Conn_FPGA_AU6 NC from line 985 of ultra_no_connect_pins_nets AU7 = No_Conn_FPGA_AU7 NC from line 982 of ultra_no_connect_pins_nets AV14 = No_Conn_FPGA_AV14 IO_L11P_T1U_N8_GC_94 from line 203 of ultra_no_connect_pins_nets AV23 = No_Conn_FPGA_AV23 IO_L13P_T2L_N0_GC_QBC_66 from line 78 of ultra_no_connect_pins_nets AV24 = No_Conn_FPGA_AV24 IO_L13N_T2L_N1_GC_QBC_66 from line 79 of ultra_no_connect_pins_nets AV25 = No_Conn_FPGA_AV25 IO_T1U_N12_66 from line 82 of ultra_no_connect_pins_nets AV3 = No_Conn_FPGA_AV3 NC from line 988 of ultra_no_connect_pins_nets AV38 = No_Conn_FPGA_AV38 NC from line 925 of ultra_no_connect_pins_nets AV39 = No_Conn_FPGA_AV39 NC from line 924 of ultra_no_connect_pins_nets AV4 = No_Conn_FPGA_AV4 NC from line 987 of ultra_no_connect_pins_nets AV43 = No_Conn_FPGA_AV43 NC from line 926 of ultra_no_connect_pins_nets AV44 = No_Conn_FPGA_AV44 NC from line 927 of ultra_no_connect_pins_nets AV8 = No_Conn_FPGA_AV8 NC from line 989 of ultra_no_connect_pins_nets AV9 = No_Conn_FPGA_AV9 NC from line 986 of ultra_no_connect_pins_nets AW1 = No_Conn_FPGA_AW1 NC from line 994 of ultra_no_connect_pins_nets AW2 = No_Conn_FPGA_AW2 NC from line 993 of ultra_no_connect_pins_nets AW22 = No_Conn_FPGA_AW22 IO_L14P_T2L_N2_GC_66 from line 75 of ultra_no_connect_pins_nets AW23 = No_Conn_FPGA_AW23 IO_L14N_T2L_N3_GC_66 from line 76 of ultra_no_connect_pins_nets AW25 = No_Conn_FPGA_AW25 IO_T2U_N12_66 from line 77 of ultra_no_connect_pins_nets AW30 = No_Conn_FPGA_AW30 IO_T1U_N12_67 from line 133 of ultra_no_connect_pins_nets AW40 = No_Conn_FPGA_AW40 NC from line 931 of ultra_no_connect_pins_nets AW41 = No_Conn_FPGA_AW41 NC from line 930 of ultra_no_connect_pins_nets AW45 = No_Conn_FPGA_AW45 NC from line 932 of ultra_no_connect_pins_nets AW46 = No_Conn_FPGA_AW46 NC from line 933 of ultra_no_connect_pins_nets AW6 = No_Conn_FPGA_AW6 NC from line 995 of ultra_no_connect_pins_nets AW7 = No_Conn_FPGA_AW7 NC from line 992 of ultra_no_connect_pins_nets AY17 = No_Conn_FPGA_AY17 IO_L6P_T0U_N10_AD6P_94 from line 205 of ultra_no_connect_pins_nets AY22 = No_Conn_FPGA_AY22 IO_L15P_T2L_N4_AD11P_66 from line 73 of ultra_no_connect_pins_nets AY23 = No_Conn_FPGA_AY23 IO_L15N_T2L_N5_AD11N_66 from line 74 of ultra_no_connect_pins_nets AY24 = No_Conn_FPGA_AY24 IO_L16P_T2U_N6_QBC_AD3P_66 from line 71 of ultra_no_connect_pins_nets AY25 = No_Conn_FPGA_AY25 IO_L18P_T2U_N10_AD2P_66 from line 67 of ultra_no_connect_pins_nets AY29 = No_Conn_FPGA_AY29 IO_L15P_T2L_N4_AD11P_67 from line 130 of ultra_no_connect_pins_nets AY3 = No_Conn_FPGA_AY3 NC from line 956 of ultra_no_connect_pins_nets AY30 = No_Conn_FPGA_AY30 IO_L15N_T2L_N5_AD11N_67 from line 131 of ultra_no_connect_pins_nets AY38 = No_Conn_FPGA_AY38 NC from line 895 of ultra_no_connect_pins_nets AY39 = No_Conn_FPGA_AY39 NC from line 894 of ultra_no_connect_pins_nets AY4 = No_Conn_FPGA_AY4 NC from line 955 of ultra_no_connect_pins_nets AY43 = No_Conn_FPGA_AY43 NC from line 896 of ultra_no_connect_pins_nets AY44 = No_Conn_FPGA_AY44 NC from line 897 of ultra_no_connect_pins_nets AY8 = No_Conn_FPGA_AY8 NC from line 957 of ultra_no_connect_pins_nets AY9 = No_Conn_FPGA_AY9 NC from line 954 of ultra_no_connect_pins_nets B18 = No_Conn_FPGA_B18 IO_L24P_T3U_N10_72 from line 353 of ultra_no_connect_pins_nets B20 = No_Conn_FPGA_B20 IO_L19N_T3L_N1_DBC_AD9N_72 from line 363 of ultra_no_connect_pins_nets B21 = No_Conn_FPGA_B21 IO_L21P_T3L_N4_AD8P_72 from line 359 of ultra_no_connect_pins_nets B23 = No_Conn_FPGA_B23 IO_L22N_T3U_N7_DBC_AD0N_71 from line 325 of ultra_no_connect_pins_nets B28 = No_Conn_FPGA_B28 IO_L22N_T3U_N7_DBC_AD0N_70 from line 232 of ultra_no_connect_pins_nets BA1 = No_Conn_FPGA_BA1 NC from line 962 of ultra_no_connect_pins_nets BA17 = No_Conn_FPGA_BA17 IO_L6N_T0U_N11_AD6N_94 from line 206 of ultra_no_connect_pins_nets BA2 = No_Conn_FPGA_BA2 NC from line 961 of ultra_no_connect_pins_nets BA22 = No_Conn_FPGA_BA22 IO_L17P_T2U_N8_AD10P_66 from line 69 of ultra_no_connect_pins_nets BA24 = No_Conn_FPGA_BA24 IO_L16N_T2U_N7_QBC_AD3N_66 from line 72 of ultra_no_connect_pins_nets BA25 = No_Conn_FPGA_BA25 IO_L18N_T2U_N11_AD2N_66 from line 68 of ultra_no_connect_pins_nets BA26 = No_Conn_FPGA_BA26 IO_L17P_T2U_N8_AD10P_67 from line 126 of ultra_no_connect_pins_nets BA27 = No_Conn_FPGA_BA27 IO_L16P_T2U_N6_QBC_AD3P_67 from line 128 of ultra_no_connect_pins_nets BA32 = No_Conn_FPGA_BA32 IO_L15N_T2L_N5_AD11N_68 from line 164 of ultra_no_connect_pins_nets BA40 = No_Conn_FPGA_BA40 NC from line 901 of ultra_no_connect_pins_nets BA41 = No_Conn_FPGA_BA41 NC from line 900 of ultra_no_connect_pins_nets BA45 = No_Conn_FPGA_BA45 NC from line 902 of ultra_no_connect_pins_nets BA46 = No_Conn_FPGA_BA46 NC from line 903 of ultra_no_connect_pins_nets BA6 = No_Conn_FPGA_BA6 NC from line 963 of ultra_no_connect_pins_nets BA7 = No_Conn_FPGA_BA7 NC from line 960 of ultra_no_connect_pins_nets BB17 = No_Conn_FPGA_BB17 IO_L4P_T0U_N6_DBC_AD7P_94 from line 208 of ultra_no_connect_pins_nets BB22 = No_Conn_FPGA_BB22 IO_L17N_T2U_N9_AD10N_66 from line 70 of ultra_no_connect_pins_nets BB23 = No_Conn_FPGA_BB23 IO_L19P_T3L_N0_DBC_AD9P_66 from line 65 of ultra_no_connect_pins_nets BB24 = No_Conn_FPGA_BB24 IO_L21P_T3L_N4_AD8P_66 from line 61 of ultra_no_connect_pins_nets BB26 = No_Conn_FPGA_BB26 IO_L17N_T2U_N9_AD10N_67 from line 127 of ultra_no_connect_pins_nets BB27 = No_Conn_FPGA_BB27 IO_L16N_T2U_N7_QBC_AD3N_67 from line 129 of ultra_no_connect_pins_nets BB3 = No_Conn_FPGA_BB3 NC from line 968 of ultra_no_connect_pins_nets BB38 = No_Conn_FPGA_BB38 NC from line 905 of ultra_no_connect_pins_nets BB39 = No_Conn_FPGA_BB39 NC from line 904 of ultra_no_connect_pins_nets BB4 = No_Conn_FPGA_BB4 NC from line 967 of ultra_no_connect_pins_nets BB43 = No_Conn_FPGA_BB43 NC from line 906 of ultra_no_connect_pins_nets BB44 = No_Conn_FPGA_BB44 NC from line 907 of ultra_no_connect_pins_nets BB8 = No_Conn_FPGA_BB8 NC from line 969 of ultra_no_connect_pins_nets BB9 = No_Conn_FPGA_BB9 NC from line 966 of ultra_no_connect_pins_nets BC1 = No_Conn_FPGA_BC1 NC from line 974 of ultra_no_connect_pins_nets BC16 = No_Conn_FPGA_BC16 IO_T0U_N12_94 from line 210 of ultra_no_connect_pins_nets BC2 = No_Conn_FPGA_BC2 NC from line 973 of ultra_no_connect_pins_nets BC23 = No_Conn_FPGA_BC23 IO_L19N_T3L_N1_DBC_AD9N_66 from line 66 of ultra_no_connect_pins_nets BC24 = No_Conn_FPGA_BC24 IO_L21N_T3L_N5_AD8N_66 from line 62 of ultra_no_connect_pins_nets BC25 = No_Conn_FPGA_BC25 IO_L19P_T3L_N0_DBC_AD9P_67 from line 123 of ultra_no_connect_pins_nets BC26 = No_Conn_FPGA_BC26 IO_L21P_T3L_N4_AD8P_67 from line 120 of ultra_no_connect_pins_nets BC28 = No_Conn_FPGA_BC28 IO_L24P_T3U_N10_67 from line 116 of ultra_no_connect_pins_nets BC29 = No_Conn_FPGA_BC29 IO_L19P_T3L_N0_DBC_AD9P_68 from line 162 of ultra_no_connect_pins_nets BC40 = No_Conn_FPGA_BC40 NC from line 911 of ultra_no_connect_pins_nets BC41 = No_Conn_FPGA_BC41 NC from line 910 of ultra_no_connect_pins_nets BC45 = No_Conn_FPGA_BC45 NC from line 912 of ultra_no_connect_pins_nets BC46 = No_Conn_FPGA_BC46 NC from line 913 of ultra_no_connect_pins_nets BC6 = No_Conn_FPGA_BC6 NC from line 975 of ultra_no_connect_pins_nets BC7 = No_Conn_FPGA_BC7 NC from line 972 of ultra_no_connect_pins_nets BD10 = No_Conn_FPGA_BD10 NC from line 964 of ultra_no_connect_pins_nets BD11 = No_Conn_FPGA_BD11 NC from line 965 of ultra_no_connect_pins_nets BD13 = No_Conn_FPGA_BD13 NC from line 946 of ultra_no_connect_pins_nets BD14 = No_Conn_FPGA_BD14 NC from line 945 of ultra_no_connect_pins_nets BD21 = No_Conn_FPGA_BD21 IO_T3U_N12_66 from line 56 of ultra_no_connect_pins_nets BD22 = No_Conn_FPGA_BD22 IO_L20P_T3L_N2_AD1P_66 from line 63 of ultra_no_connect_pins_nets BD23 = No_Conn_FPGA_BD23 IO_L23P_T3U_N8_66 from line 57 of ultra_no_connect_pins_nets BD25 = No_Conn_FPGA_BD25 IO_L19N_T3L_N1_DBC_AD9N_67 from line 124 of ultra_no_connect_pins_nets BD26 = No_Conn_FPGA_BD26 IO_L21N_T3L_N5_AD8N_67 from line 121 of ultra_no_connect_pins_nets BD27 = No_Conn_FPGA_BD27 IO_T3U_N12_67 from line 118 of ultra_no_connect_pins_nets BD28 = No_Conn_FPGA_BD28 IO_L24N_T3U_N11_67 from line 117 of ultra_no_connect_pins_nets BD3 = No_Conn_FPGA_BD3 NC from line 936 of ultra_no_connect_pins_nets BD30 = No_Conn_FPGA_BD30 IO_L20P_T3L_N2_AD1P_68 from line 160 of ultra_no_connect_pins_nets BD31 = No_Conn_FPGA_BD31 IO_L23N_T3U_N9_68 from line 158 of ultra_no_connect_pins_nets BD33 = No_Conn_FPGA_BD33 NC from line 886 of ultra_no_connect_pins_nets BD34 = No_Conn_FPGA_BD34 NC from line 887 of ultra_no_connect_pins_nets BD36 = No_Conn_FPGA_BD36 NC from line 882 of ultra_no_connect_pins_nets BD37 = No_Conn_FPGA_BD37 NC from line 883 of ultra_no_connect_pins_nets BD38 = No_Conn_FPGA_BD38 NC from line 873 of ultra_no_connect_pins_nets BD39 = No_Conn_FPGA_BD39 NC from line 872 of ultra_no_connect_pins_nets BD4 = No_Conn_FPGA_BD4 NC from line 935 of ultra_no_connect_pins_nets BD43 = No_Conn_FPGA_BD43 NC from line 874 of ultra_no_connect_pins_nets BD44 = No_Conn_FPGA_BD44 NC from line 875 of ultra_no_connect_pins_nets BD8 = No_Conn_FPGA_BD8 NC from line 937 of ultra_no_connect_pins_nets BD9 = No_Conn_FPGA_BD9 NC from line 934 of ultra_no_connect_pins_nets BE10 = No_Conn_FPGA_BE10 NC from line 947 of ultra_no_connect_pins_nets BE11 = No_Conn_FPGA_BE11 NC from line 944 of ultra_no_connect_pins_nets BE22 = No_Conn_FPGA_BE22 IO_L20N_T3L_N3_AD1N_66 from line 64 of ultra_no_connect_pins_nets BE23 = No_Conn_FPGA_BE23 IO_L23N_T3U_N9_66 from line 58 of ultra_no_connect_pins_nets BE24 = No_Conn_FPGA_BE24 IO_L24P_T3U_N10_66 from line 54 of ultra_no_connect_pins_nets BE36 = No_Conn_FPGA_BE36 NC from line 885 of ultra_no_connect_pins_nets BE37 = No_Conn_FPGA_BE37 NC from line 884 of ultra_no_connect_pins_nets BE40 = No_Conn_FPGA_BE40 NC from line 879 of ultra_no_connect_pins_nets BE41 = No_Conn_FPGA_BE41 NC from line 878 of ultra_no_connect_pins_nets BE6 = No_Conn_FPGA_BE6 NC from line 943 of ultra_no_connect_pins_nets BE7 = No_Conn_FPGA_BE7 NC from line 940 of ultra_no_connect_pins_nets BF13 = No_Conn_FPGA_BF13 NC from line 952 of ultra_no_connect_pins_nets BF14 = No_Conn_FPGA_BF14 NC from line 951 of ultra_no_connect_pins_nets BF21 = No_Conn_FPGA_BF21 IO_L22P_T3U_N6_DBC_AD0P_66 from line 59 of ultra_no_connect_pins_nets BF22 = No_Conn_FPGA_BF22 IO_L22N_T3U_N7_DBC_AD0N_66 from line 60 of ultra_no_connect_pins_nets BF24 = No_Conn_FPGA_BF24 IO_L24N_T3U_N11_66 from line 55 of ultra_no_connect_pins_nets BF3 = No_Conn_FPGA_BF3 NC from line 942 of ultra_no_connect_pins_nets BF33 = No_Conn_FPGA_BF33 NC from line 892 of ultra_no_connect_pins_nets BF34 = No_Conn_FPGA_BF34 NC from line 893 of ultra_no_connect_pins_nets BF38 = No_Conn_FPGA_BF38 NC from line 891 of ultra_no_connect_pins_nets BF39 = No_Conn_FPGA_BF39 NC from line 890 of ultra_no_connect_pins_nets BF4 = No_Conn_FPGA_BF4 NC from line 941 of ultra_no_connect_pins_nets BF43 = No_Conn_FPGA_BF43 NC from line 880 of ultra_no_connect_pins_nets BF44 = No_Conn_FPGA_BF44 NC from line 881 of ultra_no_connect_pins_nets BF8 = No_Conn_FPGA_BF8 NC from line 953 of ultra_no_connect_pins_nets BF9 = No_Conn_FPGA_BF9 NC from line 950 of ultra_no_connect_pins_nets C10 = No_Conn_FPGA_C10 MGTHTXN1_233 from line 727 of ultra_no_connect_pins_nets C11 = No_Conn_FPGA_C11 MGTHTXP1_233 from line 726 of ultra_no_connect_pins_nets C18 = No_Conn_FPGA_C18 IO_L22N_T3U_N7_DBC_AD0N_72 from line 358 of ultra_no_connect_pins_nets C19 = No_Conn_FPGA_C19 IO_L22P_T3U_N6_DBC_AD0P_72 from line 357 of ultra_no_connect_pins_nets C22 = No_Conn_FPGA_C22 IO_L24P_T3U_N10_71 from line 327 of ultra_no_connect_pins_nets C23 = No_Conn_FPGA_C23 IO_L22P_T3U_N6_DBC_AD0P_71 from line 326 of ultra_no_connect_pins_nets C27 = No_Conn_FPGA_C27 IO_L21P_T3L_N4_AD8P_70 from line 233 of ultra_no_connect_pins_nets C28 = No_Conn_FPGA_C28 IO_L21N_T3L_N5_AD8N_70 from line 234 of ultra_no_connect_pins_nets C29 = No_Conn_FPGA_C29 IO_L23N_T3U_N9_70 from line 230 of ultra_no_connect_pins_nets C36 = No_Conn_FPGA_C36 MGTYTXP1_133 from line 573 of ultra_no_connect_pins_nets C37 = No_Conn_FPGA_C37 MGTYTXN1_133 from line 574 of ultra_no_connect_pins_nets C40 = No_Conn_FPGA_C40 MGTYTXP2_132 from line 556 of ultra_no_connect_pins_nets C41 = No_Conn_FPGA_C41 MGTYTXN2_132 from line 557 of ultra_no_connect_pins_nets C6 = No_Conn_FPGA_C6 MGTHTXN2_232 from line 710 of ultra_no_connect_pins_nets C7 = No_Conn_FPGA_C7 MGTHTXP2_232 from line 709 of ultra_no_connect_pins_nets D19 = No_Conn_FPGA_D19 IO_L20N_T3L_N3_AD1N_72 from line 361 of ultra_no_connect_pins_nets D21 = No_Conn_FPGA_D21 IO_T3U_N12_72 from line 355 of ultra_no_connect_pins_nets D22 = No_Conn_FPGA_D22 IO_T3U_N12_71 from line 328 of ultra_no_connect_pins_nets D24 = No_Conn_FPGA_D24 IO_L19P_T3L_N0_DBC_AD9P_71 from line 333 of ultra_no_connect_pins_nets D25 = No_Conn_FPGA_D25 IO_L21P_T3L_N4_AD8P_71 from line 331 of ultra_no_connect_pins_nets D26 = No_Conn_FPGA_D26 IO_L19P_T3L_N0_DBC_AD9P_70 from line 237 of ultra_no_connect_pins_nets D27 = No_Conn_FPGA_D27 IO_L19N_T3L_N1_DBC_AD9N_70 from line 238 of ultra_no_connect_pins_nets D29 = No_Conn_FPGA_D29 IO_L23P_T3U_N8_70 from line 229 of ultra_no_connect_pins_nets D38 = No_Conn_FPGA_D38 MGTYTXP0_133 from line 576 of ultra_no_connect_pins_nets D39 = No_Conn_FPGA_D39 MGTYTXN0_133 from line 577 of ultra_no_connect_pins_nets D8 = No_Conn_FPGA_D8 MGTHTXN0_233 from line 730 of ultra_no_connect_pins_nets D9 = No_Conn_FPGA_D9 MGTHTXP0_233 from line 729 of ultra_no_connect_pins_nets E10 = No_Conn_FPGA_E10 MGTHTXN1_232 from line 713 of ultra_no_connect_pins_nets E11 = No_Conn_FPGA_E11 MGTHTXP1_232 from line 712 of ultra_no_connect_pins_nets E18 = No_Conn_FPGA_E18 IO_L18N_T2U_N11_AD2N_72 from line 365 of ultra_no_connect_pins_nets E19 = No_Conn_FPGA_E19 IO_L18P_T2U_N10_AD2P_72 from line 364 of ultra_no_connect_pins_nets E21 = No_Conn_FPGA_E21 IO_T2U_N12_72 from line 374 of ultra_no_connect_pins_nets E22 = No_Conn_FPGA_E22 IO_T2U_N12_71 from line 334 of ultra_no_connect_pins_nets E23 = No_Conn_FPGA_E23 IO_L16N_T2U_N7_QBC_AD3N_71 from line 332 of ultra_no_connect_pins_nets E24 = No_Conn_FPGA_E24 IO_L17N_T2U_N9_AD10N_71 from line 330 of ultra_no_connect_pins_nets E26 = No_Conn_FPGA_E26 IO_T3U_N12_70 from line 228 of ultra_no_connect_pins_nets E27 = No_Conn_FPGA_E27 IO_L18P_T2U_N10_AD2P_70 from line 239 of ultra_no_connect_pins_nets E28 = No_Conn_FPGA_E28 IO_L18N_T2U_N11_AD2N_70 from line 240 of ultra_no_connect_pins_nets E29 = No_Conn_FPGA_E29 IO_L17N_T2U_N9_AD10N_70 from line 242 of ultra_no_connect_pins_nets E36 = No_Conn_FPGA_E36 MGTYTXP1_132 from line 559 of ultra_no_connect_pins_nets E37 = No_Conn_FPGA_E37 MGTYTXN1_132 from line 560 of ultra_no_connect_pins_nets E40 = No_Conn_FPGA_E40 MGTYTXP0_132 from line 562 of ultra_no_connect_pins_nets E41 = No_Conn_FPGA_E41 MGTYTXN0_132 from line 563 of ultra_no_connect_pins_nets E6 = No_Conn_FPGA_E6 MGTHTXN0_232 from line 716 of ultra_no_connect_pins_nets E7 = No_Conn_FPGA_E7 MGTHTXP0_232 from line 715 of ultra_no_connect_pins_nets F12 = No_Conn_FPGA_F12 MGTHTXN3_231 from line 690 of ultra_no_connect_pins_nets F13 = No_Conn_FPGA_F13 MGTHTXP3_231 from line 689 of ultra_no_connect_pins_nets F18 = No_Conn_FPGA_F18 IO_L15N_T2L_N5_AD11N_72 from line 371 of ultra_no_connect_pins_nets F19 = No_Conn_FPGA_F19 IO_L15P_T2L_N4_AD11P_72 from line 370 of ultra_no_connect_pins_nets F20 = No_Conn_FPGA_F20 IO_L17N_T2U_N9_AD10N_72 from line 367 of ultra_no_connect_pins_nets F21 = No_Conn_FPGA_F21 IO_L18N_T2U_N11_AD2N_71 from line 291 of ultra_no_connect_pins_nets F23 = No_Conn_FPGA_F23 IO_L16P_T2U_N6_QBC_AD3P_71 from line 293 of ultra_no_connect_pins_nets F24 = No_Conn_FPGA_F24 IO_L17P_T2U_N8_AD10P_71 from line 292 of ultra_no_connect_pins_nets F25 = No_Conn_FPGA_F25 IO_L15N_T2L_N5_AD11N_71 from line 295 of ultra_no_connect_pins_nets F26 = No_Conn_FPGA_F26 IO_L16N_T2U_N7_QBC_AD3N_70 from line 244 of ultra_no_connect_pins_nets F28 = No_Conn_FPGA_F28 IO_L15N_T2L_N5_AD11N_70 from line 246 of ultra_no_connect_pins_nets F29 = No_Conn_FPGA_F29 IO_L17P_T2U_N8_AD10P_70 from line 241 of ultra_no_connect_pins_nets F34 = No_Conn_FPGA_F34 MGTYTXP3_131 from line 536 of ultra_no_connect_pins_nets F35 = No_Conn_FPGA_F35 MGTYTXN3_131 from line 537 of ultra_no_connect_pins_nets F38 = No_Conn_FPGA_F38 MGTYTXP1_131 from line 542 of ultra_no_connect_pins_nets F39 = No_Conn_FPGA_F39 MGTYTXN1_131 from line 543 of ultra_no_connect_pins_nets F8 = No_Conn_FPGA_F8 MGTHTXN1_231 from line 696 of ultra_no_connect_pins_nets F9 = No_Conn_FPGA_F9 MGTHTXP1_231 from line 695 of ultra_no_connect_pins_nets G10 = No_Conn_FPGA_G10 MGTHTXN2_231 from line 693 of ultra_no_connect_pins_nets G11 = No_Conn_FPGA_G11 MGTHTXP2_231 from line 692 of ultra_no_connect_pins_nets G18 = No_Conn_FPGA_G18 IO_L16N_T2U_N7_QBC_AD3N_72 from line 369 of ultra_no_connect_pins_nets G20 = No_Conn_FPGA_G20 IO_L17P_T2U_N8_AD10P_72 from line 366 of ultra_no_connect_pins_nets G21 = No_Conn_FPGA_G21 IO_L18P_T2U_N10_AD2P_71 from line 290 of ultra_no_connect_pins_nets G22 = No_Conn_FPGA_G22 IO_L13N_T2L_N1_GC_QBC_71 from line 298 of ultra_no_connect_pins_nets G25 = No_Conn_FPGA_G25 IO_L15P_T2L_N4_AD11P_71 from line 294 of ultra_no_connect_pins_nets G26 = No_Conn_FPGA_G26 IO_L16P_T2U_N6_QBC_AD3P_70 from line 243 of ultra_no_connect_pins_nets G27 = No_Conn_FPGA_G27 IO_T2U_N12_70 from line 249 of ultra_no_connect_pins_nets G28 = No_Conn_FPGA_G28 IO_L15P_T2L_N4_AD11P_70 from line 245 of ultra_no_connect_pins_nets G36 = No_Conn_FPGA_G36 MGTYTXP2_131 from line 539 of ultra_no_connect_pins_nets G37 = No_Conn_FPGA_G37 MGTYTXN2_131 from line 540 of ultra_no_connect_pins_nets G40 = No_Conn_FPGA_G40 MGTYTXP0_131 from line 545 of ultra_no_connect_pins_nets G41 = No_Conn_FPGA_G41 MGTYTXN0_131 from line 546 of ultra_no_connect_pins_nets G6 = No_Conn_FPGA_G6 MGTHTXN0_231 from line 699 of ultra_no_connect_pins_nets G7 = No_Conn_FPGA_G7 MGTHTXP0_231 from line 698 of ultra_no_connect_pins_nets H12 = No_Conn_FPGA_H12 MGTREFCLK1N_233 from line 853 of ultra_no_connect_pins_nets H13 = No_Conn_FPGA_H13 MGTREFCLK1P_233 from line 852 of ultra_no_connect_pins_nets H18 = No_Conn_FPGA_H18 IO_L16P_T2U_N6_QBC_AD3P_72 from line 368 of ultra_no_connect_pins_nets H19 = No_Conn_FPGA_H19 IO_L14N_T2L_N3_GC_72 from line 373 of ultra_no_connect_pins_nets H20 = No_Conn_FPGA_H20 IO_L14P_T2L_N2_GC_72 from line 372 of ultra_no_connect_pins_nets H22 = No_Conn_FPGA_H22 IO_L13P_T2L_N0_GC_QBC_71 from line 297 of ultra_no_connect_pins_nets H25 = No_Conn_FPGA_H25 IO_L9N_T1L_N5_AD12N_71 from line 305 of ultra_no_connect_pins_nets H27 = No_Conn_FPGA_H27 IO_L14N_T2L_N3_GC_70 from line 248 of ultra_no_connect_pins_nets H28 = No_Conn_FPGA_H28 IO_L13P_T2L_N0_GC_QBC_70 from line 250 of ultra_no_connect_pins_nets H29 = No_Conn_FPGA_H29 IO_L13N_T2L_N1_GC_QBC_70 from line 251 of ultra_no_connect_pins_nets H34 = No_Conn_FPGA_H34 MGTREFCLK1P_133 from line 794 of ultra_no_connect_pins_nets H35 = No_Conn_FPGA_H35 MGTREFCLK1N_133 from line 795 of ultra_no_connect_pins_nets H38 = No_Conn_FPGA_H38 MGTYTXP3_130 from line 522 of ultra_no_connect_pins_nets H39 = No_Conn_FPGA_H39 MGTYTXN3_130 from line 523 of ultra_no_connect_pins_nets H8 = No_Conn_FPGA_H8 MGTHTXN3_230 from line 676 of ultra_no_connect_pins_nets H9 = No_Conn_FPGA_H9 MGTHTXP3_230 from line 675 of ultra_no_connect_pins_nets J10 = No_Conn_FPGA_J10 MGTREFCLK0N_233 from line 856 of ultra_no_connect_pins_nets J11 = No_Conn_FPGA_J11 MGTREFCLK0P_233 from line 855 of ultra_no_connect_pins_nets J15 = No_Conn_FPGA_J15 IO_T1U_N12_72 from line 379 of ultra_no_connect_pins_nets J16 = No_Conn_FPGA_J16 IO_L10N_T1U_N7_QBC_AD4N_72 from line 383 of ultra_no_connect_pins_nets J17 = No_Conn_FPGA_J17 IO_L7N_T1L_N1_QBC_AD13N_72 from line 389 of ultra_no_connect_pins_nets J19 = No_Conn_FPGA_J19 IO_L13N_T2L_N1_GC_QBC_72 from line 376 of ultra_no_connect_pins_nets J20 = No_Conn_FPGA_J20 IO_L13P_T2L_N0_GC_QBC_72 from line 375 of ultra_no_connect_pins_nets J21 = No_Conn_FPGA_J21 IO_L10N_T1U_N7_QBC_AD4N_71 from line 303 of ultra_no_connect_pins_nets J25 = No_Conn_FPGA_J25 IO_L9P_T1L_N4_AD12P_71 from line 304 of ultra_no_connect_pins_nets J26 = No_Conn_FPGA_J26 IO_L10N_T1U_N7_QBC_AD4N_70 from line 258 of ultra_no_connect_pins_nets J27 = No_Conn_FPGA_J27 IO_L14P_T2L_N2_GC_70 from line 247 of ultra_no_connect_pins_nets J29 = No_Conn_FPGA_J29 IO_L12N_T1U_N11_GC_70 from line 253 of ultra_no_connect_pins_nets J30 = No_Conn_FPGA_J30 IO_T0U_N12_VRP_70 from line 275 of ultra_no_connect_pins_nets J31 = No_Conn_FPGA_J31 IO_L5N_T0U_N9_AD14N_70 from line 268 of ultra_no_connect_pins_nets J32 = No_Conn_FPGA_J32 IO_L3N_T0L_N5_AD15N_70 from line 272 of ultra_no_connect_pins_nets J36 = No_Conn_FPGA_J36 MGTREFCLK0P_133 from line 797 of ultra_no_connect_pins_nets J37 = No_Conn_FPGA_J37 MGTREFCLK0N_133 from line 798 of ultra_no_connect_pins_nets K16 = No_Conn_FPGA_K16 IO_L10P_T1U_N6_QBC_AD4P_72 from line 382 of ultra_no_connect_pins_nets K17 = No_Conn_FPGA_K17 IO_L7P_T1L_N0_QBC_AD13P_72 from line 388 of ultra_no_connect_pins_nets K18 = No_Conn_FPGA_K18 IO_L12N_T1U_N11_GC_72 from line 378 of ultra_no_connect_pins_nets K19 = No_Conn_FPGA_K19 IO_L12P_T1U_N10_GC_72 from line 377 of ultra_no_connect_pins_nets K21 = No_Conn_FPGA_K21 IO_L10P_T1U_N6_QBC_AD4P_71 from line 302 of ultra_no_connect_pins_nets K23 = No_Conn_FPGA_K23 IO_L8N_T1L_N3_AD5N_71 from line 307 of ultra_no_connect_pins_nets K24 = No_Conn_FPGA_K24 IO_L7N_T1L_N1_QBC_AD13N_71 from line 309 of ultra_no_connect_pins_nets K26 = No_Conn_FPGA_K26 IO_L10P_T1U_N6_QBC_AD4P_70 from line 257 of ultra_no_connect_pins_nets K27 = No_Conn_FPGA_K27 IO_L11P_T1U_N8_GC_70 from line 255 of ultra_no_connect_pins_nets K28 = No_Conn_FPGA_K28 IO_L11N_T1U_N9_GC_70 from line 256 of ultra_no_connect_pins_nets K29 = No_Conn_FPGA_K29 IO_L12P_T1U_N10_GC_70 from line 252 of ultra_no_connect_pins_nets K31 = No_Conn_FPGA_K31 IO_L5P_T0U_N8_AD14P_70 from line 267 of ultra_no_connect_pins_nets K32 = No_Conn_FPGA_K32 IO_L3P_T0L_N4_AD15P_70 from line 271 of ultra_no_connect_pins_nets K38 = No_Conn_FPGA_K38 MGTYTXP1_130 from line 525 of ultra_no_connect_pins_nets K39 = No_Conn_FPGA_K39 MGTYTXN1_130 from line 526 of ultra_no_connect_pins_nets K8 = No_Conn_FPGA_K8 MGTHTXN1_230 from line 679 of ultra_no_connect_pins_nets K9 = No_Conn_FPGA_K9 MGTHTXP1_230 from line 678 of ultra_no_connect_pins_nets L10 = No_Conn_FPGA_L10 MGTREFCLK0N_232 from line 849 of ultra_no_connect_pins_nets L11 = No_Conn_FPGA_L11 MGTREFCLK0P_232 from line 848 of ultra_no_connect_pins_nets L15 = No_Conn_FPGA_L15 IO_L8N_T1L_N3_AD5N_72 from line 387 of ultra_no_connect_pins_nets L16 = No_Conn_FPGA_L16 IO_L8P_T1L_N2_AD5P_72 from line 386 of ultra_no_connect_pins_nets L18 = No_Conn_FPGA_L18 IO_L11N_T1U_N9_GC_72 from line 381 of ultra_no_connect_pins_nets L19 = No_Conn_FPGA_L19 IO_L11P_T1U_N8_GC_72 from line 380 of ultra_no_connect_pins_nets L20 = No_Conn_FPGA_L20 IO_L9N_T1L_N5_AD12N_72 from line 385 of ultra_no_connect_pins_nets L21 = No_Conn_FPGA_L21 IO_L6N_T0U_N11_AD6N_71 from line 311 of ultra_no_connect_pins_nets L23 = No_Conn_FPGA_L23 IO_L8P_T1L_N2_AD5P_71 from line 306 of ultra_no_connect_pins_nets L24 = No_Conn_FPGA_L24 IO_L7P_T1L_N0_QBC_AD13P_71 from line 308 of ultra_no_connect_pins_nets L25 = No_Conn_FPGA_L25 IO_T1U_N12_71 from line 300 of ultra_no_connect_pins_nets L26 = No_Conn_FPGA_L26 IO_T1U_N12_70 from line 254 of ultra_no_connect_pins_nets L28 = No_Conn_FPGA_L28 IO_L9P_T1L_N4_AD12P_70 from line 259 of ultra_no_connect_pins_nets L29 = No_Conn_FPGA_L29 IO_L9N_T1L_N5_AD12N_70 from line 260 of ultra_no_connect_pins_nets L30 = No_Conn_FPGA_L30 IO_L6N_T0U_N11_AD6N_70 from line 266 of ultra_no_connect_pins_nets L31 = No_Conn_FPGA_L31 IO_L1N_T0L_N1_DBC_70 from line 277 of ultra_no_connect_pins_nets L36 = No_Conn_FPGA_L36 MGTREFCLK0P_132 from line 790 of ultra_no_connect_pins_nets L37 = No_Conn_FPGA_L37 MGTREFCLK0N_132 from line 791 of ultra_no_connect_pins_nets M12 = No_Conn_FPGA_M12 MGTREFCLK1N_231 from line 842 of ultra_no_connect_pins_nets M13 = No_Conn_FPGA_M13 MGTREFCLK1P_231 from line 841 of ultra_no_connect_pins_nets M15 = No_Conn_FPGA_M15 IO_L4N_T0U_N7_DBC_AD7N_72 from line 395 of ultra_no_connect_pins_nets M16 = No_Conn_FPGA_M16 IO_L4P_T0U_N6_DBC_AD7P_72 from line 394 of ultra_no_connect_pins_nets M17 = No_Conn_FPGA_M17 IO_L2N_T0L_N3_72 from line 399 of ultra_no_connect_pins_nets M18 = No_Conn_FPGA_M18 IO_L1N_T0L_N1_DBC_72 from line 402 of ultra_no_connect_pins_nets M20 = No_Conn_FPGA_M20 IO_L9P_T1L_N4_AD12P_72 from line 384 of ultra_no_connect_pins_nets M21 = No_Conn_FPGA_M21 IO_L6P_T0U_N10_AD6P_71 from line 310 of ultra_no_connect_pins_nets M22 = No_Conn_FPGA_M22 IO_L4N_T0U_N7_DBC_AD7N_71 from line 315 of ultra_no_connect_pins_nets M23 = No_Conn_FPGA_M23 IO_L1N_T0L_N1_DBC_71 from line 322 of ultra_no_connect_pins_nets M25 = No_Conn_FPGA_M25 IO_L3N_T0L_N5_AD15N_71 from line 317 of ultra_no_connect_pins_nets M26 = No_Conn_FPGA_M26 IO_L3P_T0L_N4_AD15P_71 from line 316 of ultra_no_connect_pins_nets M27 = No_Conn_FPGA_M27 IO_L8N_T1L_N3_AD5N_70 from line 262 of ultra_no_connect_pins_nets M28 = No_Conn_FPGA_M28 IO_L7N_T1L_N1_QBC_AD13N_70 from line 264 of ultra_no_connect_pins_nets M30 = No_Conn_FPGA_M30 IO_L6P_T0U_N10_AD6P_70 from line 265 of ultra_no_connect_pins_nets M31 = No_Conn_FPGA_M31 IO_L1P_T0L_N0_DBC_70 from line 276 of ultra_no_connect_pins_nets M32 = No_Conn_FPGA_M32 IO_L2N_T0L_N3_70 from line 274 of ultra_no_connect_pins_nets M34 = No_Conn_FPGA_M34 MGTREFCLK1P_131 from line 783 of ultra_no_connect_pins_nets M35 = No_Conn_FPGA_M35 MGTREFCLK1N_131 from line 784 of ultra_no_connect_pins_nets M38 = No_Conn_FPGA_M38 MGTYTXP3_129 from line 508 of ultra_no_connect_pins_nets M39 = No_Conn_FPGA_M39 MGTYTXN3_129 from line 509 of ultra_no_connect_pins_nets M8 = No_Conn_FPGA_M8 MGTHTXN3_229 from line 662 of ultra_no_connect_pins_nets M9 = No_Conn_FPGA_M9 MGTHTXP3_229 from line 661 of ultra_no_connect_pins_nets N10 = No_Conn_FPGA_N10 MGTREFCLK0N_231 from line 845 of ultra_no_connect_pins_nets N11 = No_Conn_FPGA_N11 MGTREFCLK0P_231 from line 844 of ultra_no_connect_pins_nets N15 = No_Conn_FPGA_N15 IO_T0U_N12_VRP_72 from line 400 of ultra_no_connect_pins_nets N17 = No_Conn_FPGA_N17 IO_L2P_T0L_N2_72 from line 398 of ultra_no_connect_pins_nets N18 = No_Conn_FPGA_N18 IO_L1P_T0L_N0_DBC_72 from line 401 of ultra_no_connect_pins_nets N19 = No_Conn_FPGA_N19 IO_L3N_T0L_N5_AD15N_72 from line 397 of ultra_no_connect_pins_nets N20 = No_Conn_FPGA_N20 IO_L5N_T0U_N9_AD14N_72 from line 393 of ultra_no_connect_pins_nets N22 = No_Conn_FPGA_N22 IO_L4P_T0U_N6_DBC_AD7P_71 from line 314 of ultra_no_connect_pins_nets N23 = No_Conn_FPGA_N23 IO_L1P_T0L_N0_DBC_71 from line 321 of ultra_no_connect_pins_nets N24 = No_Conn_FPGA_N24 IO_L2N_T0L_N3_71 from line 319 of ultra_no_connect_pins_nets N25 = No_Conn_FPGA_N25 IO_L5N_T0U_N9_AD14N_71 from line 313 of ultra_no_connect_pins_nets N27 = No_Conn_FPGA_N27 IO_L8P_T1L_N2_AD5P_70 from line 261 of ultra_no_connect_pins_nets N28 = No_Conn_FPGA_N28 IO_L7P_T1L_N0_QBC_AD13P_70 from line 263 of ultra_no_connect_pins_nets N29 = No_Conn_FPGA_N29 IO_L4P_T0U_N6_DBC_AD7P_70 from line 269 of ultra_no_connect_pins_nets N30 = No_Conn_FPGA_N30 IO_L4N_T0U_N7_DBC_AD7N_70 from line 270 of ultra_no_connect_pins_nets N32 = No_Conn_FPGA_N32 IO_L2P_T0L_N2_70 from line 273 of ultra_no_connect_pins_nets N36 = No_Conn_FPGA_N36 MGTREFCLK0P_131 from line 786 of ultra_no_connect_pins_nets N37 = No_Conn_FPGA_N37 MGTREFCLK0N_131 from line 787 of ultra_no_connect_pins_nets P12 = No_Conn_FPGA_P12 MGTREFCLK1N_230 from line 838 of ultra_no_connect_pins_nets P13 = No_Conn_FPGA_P13 MGTREFCLK1P_230 from line 837 of ultra_no_connect_pins_nets P15 = No_Conn_FPGA_P15 VREF_72 from line 403 of ultra_no_connect_pins_nets P16 = No_Conn_FPGA_P16 IO_L6N_T0U_N11_AD6N_72 from line 391 of ultra_no_connect_pins_nets P17 = No_Conn_FPGA_P17 IO_L6P_T0U_N10_AD6P_72 from line 390 of ultra_no_connect_pins_nets P19 = No_Conn_FPGA_P19 IO_L3P_T0L_N4_AD15P_72 from line 396 of ultra_no_connect_pins_nets P20 = No_Conn_FPGA_P20 IO_L5P_T0U_N8_AD14P_72 from line 392 of ultra_no_connect_pins_nets P24 = No_Conn_FPGA_P24 IO_L2P_T0L_N2_71 from line 318 of ultra_no_connect_pins_nets P25 = No_Conn_FPGA_P25 IO_L5P_T0U_N8_AD14P_71 from line 312 of ultra_no_connect_pins_nets P27 = No_Conn_FPGA_P27 VREF_70 from line 278 of ultra_no_connect_pins_nets P34 = No_Conn_FPGA_P34 MGTREFCLK1P_130 from line 779 of ultra_no_connect_pins_nets P35 = No_Conn_FPGA_P35 MGTREFCLK1N_130 from line 780 of ultra_no_connect_pins_nets P38 = No_Conn_FPGA_P38 MGTYTXP1_129 from line 511 of ultra_no_connect_pins_nets P39 = No_Conn_FPGA_P39 MGTYTXN1_129 from line 512 of ultra_no_connect_pins_nets P8 = No_Conn_FPGA_P8 MGTHTXN1_229 from line 665 of ultra_no_connect_pins_nets P9 = No_Conn_FPGA_P9 MGTHTXP1_229 from line 664 of ultra_no_connect_pins_nets T12 = No_Conn_FPGA_T12 MGTREFCLK1N_229 from line 831 of ultra_no_connect_pins_nets T13 = No_Conn_FPGA_T13 MGTREFCLK1P_229 from line 830 of ultra_no_connect_pins_nets T34 = No_Conn_FPGA_T34 MGTREFCLK1P_129 from line 772 of ultra_no_connect_pins_nets T35 = No_Conn_FPGA_T35 MGTREFCLK1N_129 from line 773 of ultra_no_connect_pins_nets T38 = No_Conn_FPGA_T38 MGTYTXP3_128 from line 488 of ultra_no_connect_pins_nets T39 = No_Conn_FPGA_T39 MGTYTXN3_128 from line 489 of ultra_no_connect_pins_nets T8 = No_Conn_FPGA_T8 MGTHTXN3_228 from line 648 of ultra_no_connect_pins_nets T9 = No_Conn_FPGA_T9 MGTHTXP3_228 from line 647 of ultra_no_connect_pins_nets U10 = No_Conn_FPGA_U10 MGTREFCLK0N_229 from line 834 of ultra_no_connect_pins_nets U11 = No_Conn_FPGA_U11 MGTREFCLK0P_229 from line 833 of ultra_no_connect_pins_nets U36 = No_Conn_FPGA_U36 MGTREFCLK0P_129 from line 775 of ultra_no_connect_pins_nets U37 = No_Conn_FPGA_U37 MGTREFCLK0N_129 from line 776 of ultra_no_connect_pins_nets U40 = No_Conn_FPGA_U40 MGTYTXP2_128 from line 491 of ultra_no_connect_pins_nets U41 = No_Conn_FPGA_U41 MGTYTXN2_128 from line 492 of ultra_no_connect_pins_nets V12 = No_Conn_FPGA_V12 MGTREFCLK1N_228 from line 824 of ultra_no_connect_pins_nets V13 = No_Conn_FPGA_V13 MGTREFCLK1P_228 from line 823 of ultra_no_connect_pins_nets V34 = No_Conn_FPGA_V34 MGTREFCLK1P_128 from line 765 of ultra_no_connect_pins_nets V35 = No_Conn_FPGA_V35 MGTREFCLK1N_128 from line 766 of ultra_no_connect_pins_nets V38 = No_Conn_FPGA_V38 MGTYTXP1_128 from line 494 of ultra_no_connect_pins_nets V39 = No_Conn_FPGA_V39 MGTYTXN1_128 from line 495 of ultra_no_connect_pins_nets V8 = No_Conn_FPGA_V8 MGTHTXN1_228 from line 651 of ultra_no_connect_pins_nets V9 = No_Conn_FPGA_V9 MGTHTXP1_228 from line 650 of ultra_no_connect_pins_nets W10 = No_Conn_FPGA_W10 MGTREFCLK0N_228 from line 827 of ultra_no_connect_pins_nets W11 = No_Conn_FPGA_W11 MGTREFCLK0P_228 from line 826 of ultra_no_connect_pins_nets W36 = No_Conn_FPGA_W36 MGTREFCLK0P_128 from line 768 of ultra_no_connect_pins_nets W37 = No_Conn_FPGA_W37 MGTREFCLK0N_128 from line 769 of ultra_no_connect_pins_nets W40 = No_Conn_FPGA_W40 MGTYTXP0_128 from line 497 of ultra_no_connect_pins_nets W41 = No_Conn_FPGA_W41 MGTYTXN0_128 from line 498 of ultra_no_connect_pins_nets Y38 = No_Conn_FPGA_Y38 MGTYTXP3_127 from line 474 of ultra_no_connect_pins_nets Y39 = No_Conn_FPGA_Y39 MGTYTXN3_127 from line 475 of ultra_no_connect_pins_nets Y8 = No_Conn_FPGA_Y8 MGTHTXN3_227 from line 634 of ultra_no_connect_pins_nets Y9 = No_Conn_FPGA_Y9 MGTHTXP3_227 from line 633 of ultra_no_connect_pins_nets BF25 = OVERALL_ADRS_0_TO_RES_NET IO_L23N_T3U_N9_67 from line 127 of hardware_address_to_rod_nets BE25 = OVERALL_ADRS_1_TO_RES_NET IO_L23P_T3U_N8_67 from line 128 of hardware_address_to_rod_nets BF26 = OVERALL_ADRS_2_TO_RES_NET IO_L20P_T3L_N2_AD1P_67 from line 129 of hardware_address_to_rod_nets BE27 = OVERALL_ADRS_3_TO_RES_NET IO_L22P_T3U_N6_DBC_AD0P_67 from line 130 of hardware_address_to_rod_nets BF27 = OVERALL_ADRS_4_TO_RES_NET IO_L20N_T3L_N3_AD1N_67 from line 132 of hardware_address_to_rod_nets BE28 = OVERALL_ADRS_5_TO_RES_NET IO_L22N_T3U_N7_DBC_AD0N_67 from line 133 of hardware_address_to_rod_nets BE29 = OVERALL_ADRS_6_TO_RES_NET IO_L22P_T3U_N6_DBC_AD0P_68 from line 134 of hardware_address_to_rod_nets BE30 = OVERALL_ADRS_7_TO_RES_NET IO_L20N_T3L_N3_AD1N_68 from line 135 of hardware_address_to_rod_nets B26 = PLL_320.64_MHz_Lock_Detect_to_FPGA IO_L24P_T3U_N10_70 from line 497 of clock_generation_nets B27 = PLL_40.08_MHz_Lock_Detect_to_FPGA IO_L22P_T3U_N6_DBC_AD0P_70 from line 366 of clock_generation_nets AB14 = POR_OVERRIDE POR_OVERRIDE from line 180 of bank_0_and_bank_65_config_mem_nets AE14 = PROGRAM_B PROGRAM_B_0 from line 159 of bank_0_and_bank_65_config_mem_nets K14 = PUDC_B PUDC_B_0 from line 196 of bank_0_and_bank_65_config_mem_nets AU33 = Phys_U21_CLK125__LED_MODE IO_L12P_T1U_N10_GC_68 from line 82 of ultra_fpga_to_phys_chips_nets BA34 = Phys_U21_GTX_CLK IO_L16P_T2U_N6_QBC_AD3P_68 from line 64 of ultra_fpga_to_phys_chips_nets BC30 = Phys_U21_INT_B IO_L19N_T3L_N1_DBC_AD9N_68 from line 84 of ultra_fpga_to_phys_chips_nets BB32 = Phys_U21_MDC IO_L17P_T2U_N8_AD10P_68 from line 72 of ultra_fpga_to_phys_chips_nets BA30 = Phys_U21_MDIO IO_T3U_N12_68 from line 74 of ultra_fpga_to_phys_chips_nets BC31 = Phys_U21_RXD0__MODE0 IO_L23P_T3U_N8_68 from line 40 of ultra_fpga_to_phys_chips_nets AY32 = Phys_U21_RXD1__MODE1 IO_L15P_T2L_N4_AD11P_68 from line 42 of ultra_fpga_to_phys_chips_nets BB33 = Phys_U21_RXD2__MODE2 IO_L17N_T2U_N9_AD10N_68 from line 44 of ultra_fpga_to_phys_chips_nets AY33 = Phys_U21_RXD3__MODE3 IO_L14N_T2L_N3_GC_68 from line 46 of ultra_fpga_to_phys_chips_nets AV33 = Phys_U21_RX_CLK__PHYAD2 IO_L11P_T1U_N8_GC_68 from line 50 of ultra_fpga_to_phys_chips_nets BB31 = Phys_U21_RX_DV__CLK125_EN IO_L21N_T3L_N5_AD8N_68 from line 48 of ultra_fpga_to_phys_chips_nets BA36 = Phys_U21_TXD0 IO_L18P_T2U_N10_AD2P_68 from line 54 of ultra_fpga_to_phys_chips_nets AY35 = Phys_U21_TXD1 IO_L13N_T2L_N1_GC_QBC_68 from line 56 of ultra_fpga_to_phys_chips_nets BB36 = Phys_U21_TXD2 IO_L18N_T2U_N11_AD2N_68 from line 58 of ultra_fpga_to_phys_chips_nets BA35 = Phys_U21_TXD3 IO_T2U_N12_68 from line 60 of ultra_fpga_to_phys_chips_nets BB34 = Phys_U21_TX_EN IO_L16N_T2U_N7_QBC_AD3N_68 from line 62 of ultra_fpga_to_phys_chips_nets AY34 = Phys_U22_CLK125__LED_MODE IO_L13P_T2L_N0_GC_QBC_68 from line 145 of ultra_fpga_to_phys_chips_nets AT34 = Phys_U22_GTX_CLK IO_L2N_T0L_N3_68 from line 127 of ultra_fpga_to_phys_chips_nets BA31 = Phys_U22_INT_B IO_L21P_T3L_N4_AD8P_68 from line 147 of ultra_fpga_to_phys_chips_nets AW36 = Phys_U22_MDC IO_L10N_T1U_N7_QBC_AD4N_68 from line 135 of ultra_fpga_to_phys_chips_nets AW35 = Phys_U22_MDIO IO_L9N_T1L_N5_AD12N_68 from line 137 of ultra_fpga_to_phys_chips_nets AV35 = Phys_U22_RXD0__MODE0 IO_L9P_T1L_N4_AD12P_68 from line 103 of ultra_fpga_to_phys_chips_nets AV36 = Phys_U22_RXD1__MODE1 IO_L10P_T1U_N6_QBC_AD4P_68 from line 105 of ultra_fpga_to_phys_chips_nets AV34 = Phys_U22_RXD2__MODE2 IO_L11N_T1U_N9_GC_68 from line 107 of ultra_fpga_to_phys_chips_nets AU32 = Phys_U22_RXD3__MODE3 IO_L8N_T1L_N3_AD5N_68 from line 109 of ultra_fpga_to_phys_chips_nets AW33 = Phys_U22_RX_CLK__PHYAD2 IO_L14P_T2L_N2_GC_68 from line 113 of ultra_fpga_to_phys_chips_nets AW32 = Phys_U22_RX_DV__CLK125_EN IO_T1U_N12_68 from line 111 of ultra_fpga_to_phys_chips_nets AR36 = Phys_U22_TXD0 IO_L6P_T0U_N10_AD6P_68 from line 117 of ultra_fpga_to_phys_chips_nets AT36 = Phys_U22_TXD1 IO_L6N_T0U_N11_AD6N_68 from line 119 of ultra_fpga_to_phys_chips_nets AR35 = Phys_U22_TXD2 IO_L4P_T0U_N6_DBC_AD7P_68 from line 121 of ultra_fpga_to_phys_chips_nets AT35 = Phys_U22_TXD3 IO_L4N_T0U_N7_DBC_AD7N_68 from line 123 of ultra_fpga_to_phys_chips_nets AU34 = Phys_U22_TX_EN IO_L12N_T1U_N11_GC_68 from line 125 of ultra_fpga_to_phys_chips_nets AH41 = QUAD_125_MGTRREF MGTRREF_LC from line 119 of ultra_dci_vref_mgt_calib_resistors_nets D41 = QUAD_130_MGTRREF MGTRREF_LN from line 122 of ultra_dci_vref_mgt_calib_resistors_nets AH6 = QUAD_226_MGTRREF MGTRREF_RC from line 125 of ultra_dci_vref_mgt_calib_resistors_nets D6 = QUAD_231_MGTRREF MGTRREF_RN from line 128 of ultra_dci_vref_mgt_calib_resistors_nets AW27 = ROD_PRESENT_B_TO_FPGA IO_L14P_T2L_N2_GC_67 from line 270 of jtag_and_associated_nets AW28 = ROD_Power_Control_2_FPGA IO_L14N_T2L_N3_GC_67 from line 763 of power_supply_all_other_nets AV30 = ROD_Power_Control_3_FPGA IO_L12N_T1U_N11_GC_67 from line 765 of power_supply_all_other_nets AV29 = ROD_Power_Control_4_FPGA IO_L12P_T1U_N10_GC_67 from line 767 of power_supply_all_other_nets AR17 = ROD_Power_Enable IO_L24N_T3U_N11_84 from line 695 of power_supply_all_other_nets AP17 = ROD_Power_Enable_B IO_L24P_T3U_N10_84 from line 697 of power_supply_all_other_nets AN1 = Rec_MP_Fiber_2_to_FPGA_Cmp MGTHRXN2_224 from line 167 of hub_all_other_mgt_nets AN2 = Rec_MP_Fiber_2_to_FPGA_Dir MGTHRXP2_224 from line 166 of hub_all_other_mgt_nets AP3 = Rec_MP_Fiber_4_to_FPGA_Cmp MGTHRXN1_224 from line 154 of hub_all_other_mgt_nets AP4 = Rec_MP_Fiber_4_to_FPGA_Dir MGTHRXP1_224 from line 153 of hub_all_other_mgt_nets AR1 = Rec_MP_Fiber_6_to_FPGA_Cmp MGTHRXN0_224 from line 141 of hub_all_other_mgt_nets AR2 = Rec_MP_Fiber_6_to_FPGA_Dir MGTHRXP0_224 from line 140 of hub_all_other_mgt_nets AR46 = Rec_MP_Fiber_8_to_FPGA_Cmp MGTYRXN0_124 from line 127 of hub_all_other_mgt_nets AR45 = Rec_MP_Fiber_8_to_FPGA_Dir MGTYRXP0_124 from line 126 of hub_all_other_mgt_nets AR15 = Recvr_MiniPOD_INTR_B IO_L16P_T2U_N6_QBC_AD3P_84 from line 189 of minipod_pow_gnd_ctrl_no_conn_nets AR14 = Recvr_MiniPOD_RESET_B IO_L16N_T2U_N7_QBC_AD3N_84 from line 192 of minipod_pow_gnd_ctrl_no_conn_nets AR12 = Recvr_MiniPOD_SCL IO_L15P_T2L_N4_AD11P_84 from line 186 of minipod_pow_gnd_ctrl_no_conn_nets AR13 = Recvr_MiniPOD_SDA IO_L18N_T2U_N11_AD2N_84 from line 183 of minipod_pow_gnd_ctrl_no_conn_nets AW31 = Ref_40.08_MHz_from_FPGA_to_Rec_Cmp IO_L7N_T1L_N1_QBC_AD13N_68 from line 223 of clock_generation_nets AV31 = Ref_40.08_MHz_from_FPGA_to_Rec_Dir IO_L7P_T1L_N0_QBC_AD13P_68 from line 222 of clock_generation_nets G23 = Ref_40.08_MHz_from_Other_Hub_Cmp IO_L14N_T2L_N3_GC_71 from line 208 of clock_generation_nets H23 = Ref_40.08_MHz_from_Other_Hub_Dir IO_L14P_T2L_N2_GC_71 from line 207 of clock_generation_nets BB15 = SHELF_ADRS_0_TO_FPGA IO_L3N_T0L_N5_AD15N_94 from line 101 of hardware_address_to_rod_nets BB14 = SHELF_ADRS_1_TO_FPGA IO_L5N_T0U_N9_AD14N_94 from line 102 of hardware_address_to_rod_nets BA14 = SHELF_ADRS_2_TO_FPGA IO_L5P_T0U_N8_AD14P_94 from line 103 of hardware_address_to_rod_nets BB13 = SHELF_ADRS_3_TO_FPGA IO_L8P_T1L_N2_AD5P_94 from line 104 of hardware_address_to_rod_nets BB12 = SHELF_ADRS_4_TO_FPGA IO_L8N_T1L_N3_AD5N_94 from line 106 of hardware_address_to_rod_nets BB11 = SHELF_ADRS_5_TO_FPGA IO_L10N_T1U_N7_QBC_AD4N_94 from line 107 of hardware_address_to_rod_nets BA12 = SHELF_ADRS_6_TO_FPGA IO_L9N_T1L_N5_AD12N_94 from line 108 of hardware_address_to_rod_nets BA11 = SHELF_ADRS_7_TO_FPGA IO_L10P_T1U_N6_QBC_AD4P_94 from line 109 of hardware_address_to_rod_nets AV28 = SPARE_OSC_TO_FPGA_CMP IO_L11N_T1U_N9_GC_67 from line 150 of sundry_hub_nets AU28 = SPARE_OSC_TO_FPGA_DIR IO_L11P_T1U_N8_GC_67 from line 149 of sundry_hub_nets AB20 = SYSMON_1V8 VCCADC from line 75 of power_supply_all_other_nets AB19 = SYSMON_GND GNDADC from line 77 of power_supply_all_other_nets AC19 = SYSMON_GND VREFN from line 77 of power_supply_all_other_nets AD20 = SYSMON_VREFP VREFP from line 79 of power_supply_all_other_nets A26 = Select_Input_Second_40_Fanout IO_L24N_T3U_N11_70 from line 353 of clock_generation_nets AD19 = SysMon_Main_Input_VN VN from line 83 of power_supply_all_other_nets AC20 = SysMon_Main_Input_VP VP from line 82 of power_supply_all_other_nets AW26 = TBD_SPARE_LINK_0_CMP IO_L7N_T1L_N1_QBC_AD13N_67 from line 41 of rod_to_from_hub_spare_nets AV26 = TBD_SPARE_LINK_0_DIR IO_L7P_T1L_N0_QBC_AD13P_67 from line 40 of rod_to_from_hub_spare_nets AU27 = TBD_SPARE_LINK_1_CMP IO_L8N_T1L_N3_AD5N_67 from line 44 of rod_to_from_hub_spare_nets AT27 = TBD_SPARE_LINK_1_DIR IO_L8P_T1L_N2_AD5P_67 from line 43 of rod_to_from_hub_spare_nets AY28 = TBD_SPARE_LINK_2_CMP IO_L13N_T2L_N1_GC_QBC_67 from line 47 of rod_to_from_hub_spare_nets AY27 = TBD_SPARE_LINK_2_DIR IO_L13P_T2L_N0_GC_QBC_67 from line 46 of rod_to_from_hub_spare_nets AU29 = TBD_SPARE_LINK_3_CMP IO_L9N_T1L_N5_AD12N_67 from line 50 of rod_to_from_hub_spare_nets AT29 = TBD_SPARE_LINK_3_DIR IO_L9P_T1L_N4_AD12P_67 from line 49 of rod_to_from_hub_spare_nets AD16 = TCK_TO_HUB_FPGA TCK_0 from line 170 of jtag_and_associated_nets AF15 = TDI_SERIES_TO_HUB_FPGA TDI_0 from line 199 of jtag_and_associated_nets AD15 = TD_HUB_FPGA_TO_JMP1 TDO_0 from line 201 of jtag_and_associated_nets AB15 = TMS_TO_HUB_FPGA TMS_0 from line 165 of jtag_and_associated_nets AE19 = Temp_Diode_DXN DXN from line 86 of power_supply_all_other_nets AE20 = Temp_Diode_DXP DXP from line 87 of power_supply_all_other_nets R6 = This_Hubs_RO_0_to_Cap_Its_ROD_Cmp MGTHTXN0_229 from line 281 of hub_all_other_mgt_nets R7 = This_Hubs_RO_0_to_Cap_Its_ROD_Dir MGTHTXP0_229 from line 280 of hub_all_other_mgt_nets AA41 = This_Hubs_RO_0_to_Cap_Other_ROD_Cmp MGTYTXN2_127 from line 304 of hub_all_other_mgt_nets AA40 = This_Hubs_RO_0_to_Cap_Other_ROD_Dir MGTYTXP2_127 from line 303 of hub_all_other_mgt_nets U6 = This_Hubs_RO_1_to_Cap_Its_ROD_Cmp MGTHTXN2_228 from line 288 of hub_all_other_mgt_nets U7 = This_Hubs_RO_1_to_Cap_Its_ROD_Dir MGTHTXP2_228 from line 287 of hub_all_other_mgt_nets AC40 = This_Hubs_RO_1_to_Cap_Other_ROD_Cmp MGTYTXP0_127 from line 316 of hub_all_other_mgt_nets AC41 = This_Hubs_RO_1_to_Cap_Other_ROD_Dir MGTYTXN0_127 from line 315 of hub_all_other_mgt_nets AM4 = This_RODs_Readout_Ctrl_to_GTH_Input_Cmp MGTHRXP3_224 from line 94 of hub_all_other_mgt_nets AM3 = This_RODs_Readout_Ctrl_to_GTH_Input_Dir MGTHRXN3_224 from line 93 of hub_all_other_mgt_nets AN16 = Trans_MiniPOD_INTR_B IO_L21P_T3L_N4_AD8P_84 from line 159 of minipod_pow_gnd_ctrl_no_conn_nets AP13 = Trans_MiniPOD_RESET_B IO_L18P_T2U_N10_AD2P_84 from line 162 of minipod_pow_gnd_ctrl_no_conn_nets AN15 = Trans_MiniPOD_SCL IO_L23P_T3U_N8_84 from line 156 of minipod_pow_gnd_ctrl_no_conn_nets AP15 = Trans_MiniPOD_SDA IO_L23N_T3U_N9_84 from line 153 of minipod_pow_gnd_ctrl_no_conn_nets AN13 = VBATT VBATT from line 205 of bank_0_and_bank_65_config_mem_nets