Found 64 pins for U25 which is of type IC_Micron_MT28GU01G ------------------------------------------------------ Pins sorted by Pin Name A1 = FLASH_A00 A0 from line 83 of bank_0_and_bank_65_config_mem_nets A2 = FLASH_A05 A5 from line 89 of bank_0_and_bank_65_config_mem_nets A3 = FLASH_A07 A7 from line 91 of bank_0_and_bank_65_config_mem_nets A4 = BULK_1V8 V_PP from line 38 of bank_0_and_bank_65_config_mem_nets A5 = FLASH_A12 A12 from line 98 of bank_0_and_bank_65_config_mem_nets A6 = BULK_1V8 V_CC from line 38 of bank_0_and_bank_65_config_mem_nets A7 = FLASH_A17 A17 from line 104 of bank_0_and_bank_65_config_mem_nets A8 = FLASH_A21 A21 from line 109 of bank_0_and_bank_65_config_mem_nets B1 = FLASH_A01 A1 from line 84 of bank_0_and_bank_65_config_mem_nets B2 = GROUND V_SS from line 41 of bank_0_and_bank_65_config_mem_nets B3 = FLASH_A08 A8 from line 93 of bank_0_and_bank_65_config_mem_nets B4 = FLASH_CHIP_ENB_B CE# from line 128 of bank_0_and_bank_65_config_mem_nets B5 = FLASH_A13 A13 from line 99 of bank_0_and_bank_65_config_mem_nets B6 = FLASH_A24 A24 from line 113 of bank_0_and_bank_65_config_mem_nets B7 = FLASH_A18 A18 from line 105 of bank_0_and_bank_65_config_mem_nets B8 = FLASH_A25 A25 from line 114 of bank_0_and_bank_65_config_mem_nets C1 = FLASH_A02 A2 from line 85 of bank_0_and_bank_65_config_mem_nets C2 = FLASH_A06 A6 from line 90 of bank_0_and_bank_65_config_mem_nets C3 = FLASH_A09 A9 from line 94 of bank_0_and_bank_65_config_mem_nets C4 = FLASH_A11 A11 from line 96 of bank_0_and_bank_65_config_mem_nets C5 = FLASH_A14 A14 from line 100 of bank_0_and_bank_65_config_mem_nets C6 = FLASH_WRITE_PROTECT_B WP# from line 143 of bank_0_and_bank_65_config_mem_nets C7 = FLASH_A19 A19 from line 106 of bank_0_and_bank_65_config_mem_nets C8 = FLASH_A20 A20 from line 108 of bank_0_and_bank_65_config_mem_nets D1 = FLASH_A03 A3 from line 86 of bank_0_and_bank_65_config_mem_nets D2 = FLASH_A04 A4 from line 88 of bank_0_and_bank_65_config_mem_nets D3 = FLASH_A10 A10 from line 95 of bank_0_and_bank_65_config_mem_nets D4 = FLASH_RESET_B RST# from line 126 of bank_0_and_bank_65_config_mem_nets D5 = BULK_1V8 V_CCQ from line 38 of bank_0_and_bank_65_config_mem_nets D6 = BULK_1V8 V_CCQ from line 39 of bank_0_and_bank_65_config_mem_nets D7 = FLASH_A15 A15 from line 101 of bank_0_and_bank_65_config_mem_nets D8 = FLASH_A16 A16 from line 103 of bank_0_and_bank_65_config_mem_nets E1 = FLASH_D08 DQ8 from line 66 of bank_0_and_bank_65_config_mem_nets E2 = FLASH_D01 DQ1 from line 57 of bank_0_and_bank_65_config_mem_nets E3 = FLASH_D09 DQ9 from line 67 of bank_0_and_bank_65_config_mem_nets E4 = FLASH_D03 DQ3 from line 59 of bank_0_and_bank_65_config_mem_nets E5 = FLASH_D04 DQ4 from line 61 of bank_0_and_bank_65_config_mem_nets E6 = GROUND CLK from line 147 of bank_0_and_bank_65_config_mem_nets E7 = FLASH_D15 DQ15 from line 74 of bank_0_and_bank_65_config_mem_nets E8 = NO_CONN_FLASH_MEM_U25_E8 RFU from line 224 of bank_0_and_bank_65_config_mem_nets F1 = NO_CONN_FLASH_MEM_U25_F1 RFU from line 225 of bank_0_and_bank_65_config_mem_nets F2 = FLASH_D00 DQ0 from line 56 of bank_0_and_bank_65_config_mem_nets F3 = FLASH_D10 DQ10 from line 68 of bank_0_and_bank_65_config_mem_nets F4 = FLASH_D11 DQ11 from line 69 of bank_0_and_bank_65_config_mem_nets F5 = FLASH_D12 DQ12 from line 71 of bank_0_and_bank_65_config_mem_nets F6 = GROUND ADV# from line 145 of bank_0_and_bank_65_config_mem_nets F7 = NO_CONN_FLASH_MEM_U25_F7 WAIT from line 222 of bank_0_and_bank_65_config_mem_nets F8 = FLASH_OUTPUT_ENB_B OE# from line 132 of bank_0_and_bank_65_config_mem_nets G1 = FLASH_A22 A22 from line 110 of bank_0_and_bank_65_config_mem_nets G2 = NO_CONN_FLASH_MEM_U25_G2 RFU from line 226 of bank_0_and_bank_65_config_mem_nets G3 = FLASH_D02 DQ2 from line 58 of bank_0_and_bank_65_config_mem_nets G4 = BULK_1V8 V_CCQ from line 39 of bank_0_and_bank_65_config_mem_nets G5 = FLASH_D05 DQ5 from line 62 of bank_0_and_bank_65_config_mem_nets G6 = FLASH_D06 DQ6 from line 63 of bank_0_and_bank_65_config_mem_nets G7 = FLASH_D14 DQ14 from line 73 of bank_0_and_bank_65_config_mem_nets G8 = FLASH_WRITE_ENB_B WE# from line 130 of bank_0_and_bank_65_config_mem_nets H1 = NO_CONN_FLASH_MEM_U25_H1 RFU from line 227 of bank_0_and_bank_65_config_mem_nets H2 = GROUND V_SSQ from line 41 of bank_0_and_bank_65_config_mem_nets H3 = BULK_1V8 V_CC from line 39 of bank_0_and_bank_65_config_mem_nets H4 = GROUND V_SS from line 41 of bank_0_and_bank_65_config_mem_nets H5 = FLASH_D13 DQ13 from line 72 of bank_0_and_bank_65_config_mem_nets H6 = GROUND V_SSQ from line 41 of bank_0_and_bank_65_config_mem_nets H7 = FLASH_D07 DQ7 from line 64 of bank_0_and_bank_65_config_mem_nets H8 = FLASH_A23 A23 from line 111 of bank_0_and_bank_65_config_mem_nets ------------------------------------------------------ Pins sorted by Net Name A6 = BULK_1V8 V_CC from line 38 of bank_0_and_bank_65_config_mem_nets H3 = BULK_1V8 V_CC from line 39 of bank_0_and_bank_65_config_mem_nets D5 = BULK_1V8 V_CCQ from line 38 of bank_0_and_bank_65_config_mem_nets G4 = BULK_1V8 V_CCQ from line 39 of bank_0_and_bank_65_config_mem_nets D6 = BULK_1V8 V_CCQ from line 39 of bank_0_and_bank_65_config_mem_nets A4 = BULK_1V8 V_PP from line 38 of bank_0_and_bank_65_config_mem_nets A1 = FLASH_A00 A0 from line 83 of bank_0_and_bank_65_config_mem_nets B1 = FLASH_A01 A1 from line 84 of bank_0_and_bank_65_config_mem_nets C1 = FLASH_A02 A2 from line 85 of bank_0_and_bank_65_config_mem_nets D1 = FLASH_A03 A3 from line 86 of bank_0_and_bank_65_config_mem_nets D2 = FLASH_A04 A4 from line 88 of bank_0_and_bank_65_config_mem_nets A2 = FLASH_A05 A5 from line 89 of bank_0_and_bank_65_config_mem_nets C2 = FLASH_A06 A6 from line 90 of bank_0_and_bank_65_config_mem_nets A3 = FLASH_A07 A7 from line 91 of bank_0_and_bank_65_config_mem_nets B3 = FLASH_A08 A8 from line 93 of bank_0_and_bank_65_config_mem_nets C3 = FLASH_A09 A9 from line 94 of bank_0_and_bank_65_config_mem_nets D3 = FLASH_A10 A10 from line 95 of bank_0_and_bank_65_config_mem_nets C4 = FLASH_A11 A11 from line 96 of bank_0_and_bank_65_config_mem_nets A5 = FLASH_A12 A12 from line 98 of bank_0_and_bank_65_config_mem_nets B5 = FLASH_A13 A13 from line 99 of bank_0_and_bank_65_config_mem_nets C5 = FLASH_A14 A14 from line 100 of bank_0_and_bank_65_config_mem_nets D7 = FLASH_A15 A15 from line 101 of bank_0_and_bank_65_config_mem_nets D8 = FLASH_A16 A16 from line 103 of bank_0_and_bank_65_config_mem_nets A7 = FLASH_A17 A17 from line 104 of bank_0_and_bank_65_config_mem_nets B7 = FLASH_A18 A18 from line 105 of bank_0_and_bank_65_config_mem_nets C7 = FLASH_A19 A19 from line 106 of bank_0_and_bank_65_config_mem_nets C8 = FLASH_A20 A20 from line 108 of bank_0_and_bank_65_config_mem_nets A8 = FLASH_A21 A21 from line 109 of bank_0_and_bank_65_config_mem_nets G1 = FLASH_A22 A22 from line 110 of bank_0_and_bank_65_config_mem_nets H8 = FLASH_A23 A23 from line 111 of bank_0_and_bank_65_config_mem_nets B6 = FLASH_A24 A24 from line 113 of bank_0_and_bank_65_config_mem_nets B8 = FLASH_A25 A25 from line 114 of bank_0_and_bank_65_config_mem_nets B4 = FLASH_CHIP_ENB_B CE# from line 128 of bank_0_and_bank_65_config_mem_nets F2 = FLASH_D00 DQ0 from line 56 of bank_0_and_bank_65_config_mem_nets E2 = FLASH_D01 DQ1 from line 57 of bank_0_and_bank_65_config_mem_nets G3 = FLASH_D02 DQ2 from line 58 of bank_0_and_bank_65_config_mem_nets E4 = FLASH_D03 DQ3 from line 59 of bank_0_and_bank_65_config_mem_nets E5 = FLASH_D04 DQ4 from line 61 of bank_0_and_bank_65_config_mem_nets G5 = FLASH_D05 DQ5 from line 62 of bank_0_and_bank_65_config_mem_nets G6 = FLASH_D06 DQ6 from line 63 of bank_0_and_bank_65_config_mem_nets H7 = FLASH_D07 DQ7 from line 64 of bank_0_and_bank_65_config_mem_nets E1 = FLASH_D08 DQ8 from line 66 of bank_0_and_bank_65_config_mem_nets E3 = FLASH_D09 DQ9 from line 67 of bank_0_and_bank_65_config_mem_nets F3 = FLASH_D10 DQ10 from line 68 of bank_0_and_bank_65_config_mem_nets F4 = FLASH_D11 DQ11 from line 69 of bank_0_and_bank_65_config_mem_nets F5 = FLASH_D12 DQ12 from line 71 of bank_0_and_bank_65_config_mem_nets H5 = FLASH_D13 DQ13 from line 72 of bank_0_and_bank_65_config_mem_nets G7 = FLASH_D14 DQ14 from line 73 of bank_0_and_bank_65_config_mem_nets E7 = FLASH_D15 DQ15 from line 74 of bank_0_and_bank_65_config_mem_nets F8 = FLASH_OUTPUT_ENB_B OE# from line 132 of bank_0_and_bank_65_config_mem_nets D4 = FLASH_RESET_B RST# from line 126 of bank_0_and_bank_65_config_mem_nets G8 = FLASH_WRITE_ENB_B WE# from line 130 of bank_0_and_bank_65_config_mem_nets C6 = FLASH_WRITE_PROTECT_B WP# from line 143 of bank_0_and_bank_65_config_mem_nets F6 = GROUND ADV# from line 145 of bank_0_and_bank_65_config_mem_nets E6 = GROUND CLK from line 147 of bank_0_and_bank_65_config_mem_nets H4 = GROUND V_SS from line 41 of bank_0_and_bank_65_config_mem_nets B2 = GROUND V_SS from line 41 of bank_0_and_bank_65_config_mem_nets H2 = GROUND V_SSQ from line 41 of bank_0_and_bank_65_config_mem_nets H6 = GROUND V_SSQ from line 41 of bank_0_and_bank_65_config_mem_nets E8 = NO_CONN_FLASH_MEM_U25_E8 RFU from line 224 of bank_0_and_bank_65_config_mem_nets F1 = NO_CONN_FLASH_MEM_U25_F1 RFU from line 225 of bank_0_and_bank_65_config_mem_nets F7 = NO_CONN_FLASH_MEM_U25_F7 WAIT from line 222 of bank_0_and_bank_65_config_mem_nets G2 = NO_CONN_FLASH_MEM_U25_G2 RFU from line 226 of bank_0_and_bank_65_config_mem_nets H1 = NO_CONN_FLASH_MEM_U25_H1 RFU from line 227 of bank_0_and_bank_65_config_mem_nets