Found 10 pins for U502 which is of type IC_PLL_40M0787 ------------------------------------------------------ Pins sorted by Pin Name 1 = Ref_40.08_MHz_from_Term_to_PLL Input Frequency from line 227 of clock_generation_nets 2 = GROUND Ground from line 385 of clock_generation_nets 3 = No_Conn_40_PLL_pin_3 Active Low Reset from line 414 of clock_generation_nets 4 = No_Conn_40_PLL_pin_4 Do Not Connect from line 415 of clock_generation_nets 5 = No_Conn_40_PLL_pin_5 Do Not Connect from line 416 of clock_generation_nets 6 = PLL_40.08_MHz_Output_Dir Direct Freq Output from line 245 of clock_generation_nets 7 = PLL_40.08_MHz_Output_Cmp Compl Freq Output from line 246 of clock_generation_nets 8 = GROUND Ground from line 385 of clock_generation_nets 9 = CLK_3V3 VCC 3V3 from line 384 of clock_generation_nets 10 = PLL_40.08_MHz_Lock_Detect_Output Lock Detect from line 364 of clock_generation_nets ------------------------------------------------------ Pins sorted by Net Name 9 = CLK_3V3 VCC 3V3 from line 384 of clock_generation_nets 2 = GROUND Ground from line 385 of clock_generation_nets 8 = GROUND Ground from line 385 of clock_generation_nets 3 = No_Conn_40_PLL_pin_3 Active Low Reset from line 414 of clock_generation_nets 4 = No_Conn_40_PLL_pin_4 Do Not Connect from line 415 of clock_generation_nets 5 = No_Conn_40_PLL_pin_5 Do Not Connect from line 416 of clock_generation_nets 10 = PLL_40.08_MHz_Lock_Detect_Output Lock Detect from line 364 of clock_generation_nets 7 = PLL_40.08_MHz_Output_Cmp Compl Freq Output from line 246 of clock_generation_nets 6 = PLL_40.08_MHz_Output_Dir Direct Freq Output from line 245 of clock_generation_nets 1 = Ref_40.08_MHz_from_Term_to_PLL Input Frequency from line 227 of clock_generation_nets