// ============================================================================ // FRU Inventory Device Data source file // ------------------------------------- // // Automatically generated file, do not edit // Created by hubuser - Thu 17 Oct 2019 10:54:20 AM EDT // // Copyright © 2014, LAPP/CNRS // // ============================================================================ #define PICMG_BOARD_P2P_CONNECTIVITY_RECORD_CHECKSUM_0 0x1C #define PICMG_BOARD_P2P_CONNECTIVITY_HEADER_CHECKSUM_0 0x84 typedef struct __attribute__((packed)) { uint8_t oem_guid[16]; } fru_oem_guid_0_t; typedef struct __attribute__((packed)) { uint32_t link_designator:12, // [11:0] Link Designator. Identifies the Interface Channel and // the Ports within the Channel that are being described; see // Table 3-37, "Link Designator." link_type:8, // [19:12] Link Type. Identifies the PICMG® 3.x subsidiary // specification that governs this description or identifies the // description as proprietary; see Table 3-38, ~SLink Type. link_type_extension:4, // [23:20] Link Type Extension. Identifies the subset of a // subsidiary specification that is implemented and is defined // entirely by the subsidiary specification identified in the // Link Type field. link_grouping_id:8; // [31:24] Link Grouping ID. Indicates whether the Ports of this // Channel are operated together with Ports in other Channels. // A value of 0 always indicates a Single-Channel Link. A common, // non-zero Link Grouping ID in multiple Link Descriptors indicates // that the Ports covered by those Link Descriptors must be operated // together. A unique non-zero Link Grouping ID also indicates // Single-Channel Link. } fru_link_desc_0_t; typedef struct __attribute__((packed)) { MULTIRECORD_AREA_HEADER hdr; uint8_t oem_guid_count; // The number, n, of OEM GUIDs defined in this record. fru_oem_guid_0_t oem_guid_list[1]; // A list 16*n bytes of OEM GUIDs fru_link_desc_0_t link_desc_list[2]; // Link Descriptor list. A variable length list of four byte // Link Descriptors (LS Byte first) (see Table 3-50, "Link Descriptor"; // Table 3-51, "Link Designator"; and Table 3-52, "Link Type") // totaling m bytes in length. Each Link Descriptor details one type // of point-to-point protocol supported by the referenced Channels. } fru_board_P2P_connectivity_rec_0_t; typedef struct __attribute__((packed, section(".data.fru"))) { FRU_COMMON_HEADER header; // 8 bytes uint8_t board[64]; uint8_t product[56]; fru_board_P2P_connectivity_rec_0_t board_P2P_connectivity; // 35 bytes } fru0_data_t; #define PICMG_ADDRESS_TABLE_RECORD_CHECKSUM_1 0x45 #define PICMG_ADDRESS_TABLE_HEADER_CHECKSUM_1 0xAE #define PICMG_SHELF_POWER_DISTRIBUTION_RECORD_CHECKSUM_1 0xA7 #define PICMG_SHELF_POWER_DISTRIBUTION_HEADER_CHECKSUM_1 0x6B #define PICMG_SHELF_ACTIVATION_AND_POWER_MGMT_RECORD_CHECKSUM_1 0xEB #define PICMG_SHELF_ACTIVATION_AND_POWER_MGMT_HEADER_CHECKSUM_1 0xFC #define PICMG_BACKPLANE_P2P_CONNECTIVITY_RECORD_CHECKSUM_1 0x2B #define PICMG_BACKPLANE_P2P_CONNECTIVITY_HEADER_CHECKSUM_1 0x2E typedef struct __attribute__((packed)) { // ofs len Description // 0 1 Hardware Address. This is the Hardware Address of the device. uint8_t hw_addr; // 1 1 Site Number. This is the number portion of the device´s Physical Address. uint8_t addr_key; // 2 1 Site Type. This is the type portion of the device´s Physical Address. uint8_t site_type; } fru_addr_table_entry_1_t; typedef struct __attribute__((packed)) { //ofs len Definition // 0 1 Record Type ID. For all records defined in this specification, a value of C0h // (OEM) is used. // 1 1 End of List/version // [7] - End of list. Set to one for the last record // [6:4] - Reserved, write as 0h // [3:0]- Record format version (=2h for this definition) // 2 1 Record Length // 3 1 Record Checksum. Holds the zero of the record. // 4 1 Header Checksum. Holds the zero of the header. // 5 3 Manufacturer ID. LS byte first. Write as the three-byte ID assigned to // PICMG. For this specification the value 12634 (00315Ah) is used. // 8 1 PICMG Record ID. For the Address Table, the value 10h is used. // 9 1 Record Format Version. For this specification the value Oh is used. MULTIRECORD_AREA_HEADER hdr; // 10 1 Shelf Address Type/Length Byte (FRU Information variant) // [7:6]- Type // [5:0] - Length (=000000b if Shelf Address is not configured) uint8_t type_len; // 11 20 Shelf Address bytes as a fixed size field, with Length bytes of the Shelf // address, encoded according to the Shelf Address Type/Length Byte field in // byte 10. The values of the unused bytes of the fixed size field - // bytes (11 + Length) - 30 are undefined. uint8_t addr[20]; // 31 1 Address Table Entries Count. Indicates the number of entries in the // Address Table Entries. uint8_t addr_count; // 32 N Address Table Entries. This is essentially an of Address Table // Entries. Each entry is formatted as shown in Table 3-8, "Address Table // Entry." N = (Address Table Entries Count x 3) // ADD (N) ADDRESS ENTRIES HEREAFTER fru_addr_table_entry_1_t entries[16]; } fru_address_table_rec_1_t; typedef struct __attribute__((packed)) { //ofs len Definition // 0 1 Hardware Address. This is the Hardware Address of the Intelligent // FRU that represents this FRU. Since a single Hardware Address may // have multiple associated FRUs, the Feed-to-FRU mapping needs to // have both a Hardware Address and FRU Device ID. uint8_t hw_addr; // 1 1 FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. For instance, this // would be true for Boards that have mezzanines attached. uint8_t fru_dev_id; } fru_feed_to_fru_mapping_1_t; typedef struct __attribute__((packed)) { //ofs len Definition // 0 2 Maximum External Available Current. LS Byte first. This holds the // maximum current, in 1/10th A, that is available into the Feed to the // Shelf. uint8_t max_ext_current_lsb; uint8_t max_ext_current_msb; // 2 2 Maximum Internal Current. LS Byte first. This holds the maximum // current, in 1/1Oth A, that the internal Shelf circuitry can handle for this // Feed. The Shelf manufacturer sets this value. uint8_t max_int_current_lsb; uint8_t max_int_current_msb; // 4 1 Minimum Expected Operating Voltage. Holds the minimum Voltage, // in 1/2 V increments, used to determine worse case current draw of // the Shelf. Service personnel can enter a value for this field. A value of // FFh indicates that no value has been set. Only values from 48h // (equivalent to 72 decimal indicating -36 V) to and including 90h // (equivalent to 144 decimal indicating -72 V) are valid for purposes of // computation. A default value of 48h (indicating -36 V) is used when a // valid entry is not found in this field. uint8_t min_voltage; // 5 1 Feed-to-FRU Mapping Entries Count. This contains a count of the // number of entries (M) in the Feed-to-FRU Mapping Entries Table. uint8_t map_count; // 6 M*2 Feed-to-FRU Mapping Entries. This describes all the FRUs that // are powered from this Feed. Each entry follows the format found in // Table 3-77, "Feed-to-FRU Mapping Entry," and is 2 bytes in size. fru_feed_to_fru_mapping_1_t feed_table[16]; } fru_power_distribution_map_1_t; typedef struct __attribute__((packed)) { // ofs len Definition // 0 1 Record Type ID. For all records defined in this specification, a value // of COh (OEM) is used. // 1 1 End of List/version // [7] - End of list. Set to one for the last record // [6:4] - Reserved, write as Oh // [3:0]- Record format version (=2h for this definition) // 2 1 Record Length // 3 1 Record Checksum. Holds the zero of the record. // 4 1 Header Checksum. Holds the zero of the header. // 5 3 Manufacturer ID. LS byte first. Write as the three byte 10 assigned to // PICMG. For this specification the value 12634 (00315Ah) is used. // 8 1 PICMG Record ID. For the Shelf Power Distribution record, the // value 11 h is used. // 9 1 Record Format Version. For this specification, the value Oh is used. MULTIRECORD_AREA_HEADER hdr; // 10 1 Number of Power Feeds. This field specifies the number of power // Feeds (N) defined in this Shelf Power Distribution record. uint8_t feed_count; // 11 x Power Distribution Map. This table contains N variable sized Power // Distribution Maps, one for each Feed (see Table 3-76, "Power // Distribution Map"). fru_power_distribution_map_1_t power_feed_table[1]; } fru_shelf_power_distribution_rec_1_t; typedef struct __attribute__((packed)) { // FRU activation and power descriptor(s) - see table 3-79. // This contains an of activation and power descriptors for each FRU location. // byte 1 : hardware address uint8_t hw_addr; // byte 2 : FRU device ID (0xfe ?) uint8_t fru_dev_id; // byte 3 : Maximum FRU Power Capability in Watts, LSB uint8_t max_power_cap_lsb; // byte 4 : Maximum FRU Power Capability, MSB uint8_t max_power_cap_msb; // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device ID set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. uint8_t activation; } fru_activation_and_power_descriptor_1_t; typedef struct __attribute__((packed)) { MULTIRECORD_AREA_HEADER hdr; uint8_t ready_time; // Allowance for FRU Activation Readiness. uint8_t descr_count; // FRU Activation and Power Descriptor Count. This contains a count of // the number of entries (M) in the FRU Activation and Power Descriptor Table. // ADD (M) POWER DESCRIPTORS HEREAFTER // FRU Activation and Power Descriptors. This contains an of // activation and power descriptors for each FRU location. fru_activation_and_power_descriptor_1_t descr_table[16]; } shelf_activation_and_power_mgmt_rec_1_t; typedef struct __attribute__((packed)) { uint8_t remote_slot; // Remote Slot In PICMG® 3.0 systems, this is the // Hardware Address of the remote Slot. uint16_t remote_channel:5, // Remote Channel Indicates the Channel number within the // remote Slot to which this point-to-point connection is routed. local_channel:5, // Local Channel Indicates the Channel number within the local Slot. reserved:6; // Reserved. Fixed to O. } fru_p2p_channel_descr_1_t; typedef struct __attribute__((packed)) { uint8_t p2p_channel; // Point-to-Point Channel Type uint8_t slot_address; // Slot address for this Slot. For PICMG® 3.0 // systems, this is the Hardware Address. uint8_t p2p_channel_count; // number of point-to-point Channels in this // Slot of the type specified in Point-to-Point // Channel Type. fru_p2p_channel_descr_1_t p2p_channel_descr[15]; // Point-to-Point Channel Descriptors. An of n Point-to-Point // Channel Descriptors (each with LS Byte first) where n is specified in // the Point-to-Point Channel Count byte. } fru_p2p_slot_descr_1_t; typedef struct __attribute__((packed)) { MULTIRECORD_AREA_HEADER hdr; fru_p2p_slot_descr_1_t p2p_slot_descr[2]; // Point-to-Point Slot Descriptor List. A list of // variable length Point-to-Point Slot Descriptors // (see Table 3-33, "Point-to-Point Slot Descriptor"). // Each Point-to-Point Slot Descriptor describes the // number of Channels and the connectivity for a // specific type of point-to-point Channel from // one Slot. } fru_backplane_P2P_connectivity_rec_1_t; typedef struct __attribute__((packed, section(".data.fru"))) { FRU_COMMON_HEADER header; // 8 bytes uint8_t chassis[24]; uint8_t board[56]; uint8_t product[48]; fru_address_table_rec_1_t address_table; // 80 bytes fru_shelf_power_distribution_rec_1_t power_distribution; // 49 bytes shelf_activation_and_power_mgmt_rec_1_t activation_and_power_mgmt; // 92 bytes fru_backplane_P2P_connectivity_rec_1_t backplane_P2P_connectivity; // 106 bytes } fru1_data_t; static fru0_data_t fru0_data = { { /*--- COMMON HEADER ---*/ 0x1, // 3:0 - format version number = 1h for this specification 0, // 7:4 - reserved, write as 0000b 0, // Internal Use Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 0, // Chassis Info Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 1, // Board Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 9, // Product Info Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 16, // MultiRecord Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 0, // PAD, write as 00h 0xE5, // Common Header Checksum (zero ) }, { /*--- BOARD INFO AREA ---*/ 0x01, // 1 Board Area Format Version // 7:4 - reserved, write as 0000b // 3:0 - format version number = 1h for this specification. 8, // 1 Board Area Length (in multiples of 8 bytes) 25, // 1 Language Code (See section 15) 0x40, 0x6E, 0xAB, // 3 Mfg. Date / Time // Number of minutes from 0:00 hrs 1/1/96, LSbyte first (little endian) 0xC3, // 1 Board Manufacturer type/length byte // P Board Manufacturer bytes 'M', 'S', 'U', 0xC7, // 1 Board Product Name type/length byte // Q Board Product Name bytes 'F', 'E', 'X', '-', 'H', 'u', 'b', 0xD0, // 1 Board Serial Number type/length byte* // N Board Serial Number bytes* 'M', 'S', 'U', '_', 'F', 'E', 'X', '-', 'H', 'u', 'b', '_', '0', '0', '0', '0', 0xC7, // 1 Board Part Number type/length byte // M Board Part Number bytes 'F', 'E', 'X', '-', 'H', 'u', 'b', 0xCC, // 1 FRU File ID type/length byte* // R FRU File ID bytes* The FRU File version field is a pre-defined field // provided as a manufacturing aid for verifying the file that was used // during manufacture or field update to load the FRU information. The // content is manufacturer-specific. This field is also provided in the // Product Info area. Either or both fields may be null. 'f', 'r', 'u', '_', 'd', 'a', 't', 'a', '.', 'b', 'i', 'n', 0xC1, // xx Additional custom Mfg. Info fields. Defined by manufacturing. Each // field must be preceded by a type/length byte // 1 C1h (type/length byte encoded to indicate no more info fields). // Y 00h - any remaining unused space (pad to a multiple of 8, including ) 0, 0, 0, 0, 0, 0, 0x35, // 1 Board Info Area Checksum (zero ) // (*) These areas are always encoded as if the Language Code were English }, { /*--- PRODUCT INFO AREA ---*/ 0x01, // 1 Product Area Format Version // 7:4 - reserved, write as 0000b // 3:0 - format version number = 1h for this specification 7, // 1 Product Area Length (in multiples of 8 bytes) 25, // 1 Language Code (See section 15) 0xC3, // 1 Manufacturer Name type/length byte // N Manufacturer Name bytes 'M', 'S', 'U', 0xC7, // 1 Product Name type/length byte // M Product Name bytes 'F', 'E', 'X', '-', 'H', 'u', 'b', 0xC7, // 1 Product Part/Model Number type/length byte // O Product Part/Model Number bytes 'F', 'E', 'X', '-', 'H', 'u', 'b', 0xC4, // 1 Product Version type/length byte // R Product Version bytes 'v', '0', '.', '1', 0xD0, // 1 Product Serial Number type/length byte* // P Product Serial Number bytes* 'M', 'S', 'U', '_', 'F', 'E', 'X', '-', 'H', 'u', 'b', '_', '0', '0', '0', '0', 0xC0, // 1 Asset Tag type/length byte // Q Asset Tag 0xC0, // 1 FRU File ID type/length byte // R FRU File ID bytes. The FRU File version field is a pre-defined field // provided as a manufacturing aid for verifying the file that was used // during manufacture or field update to load the FRU information. The // content is manufacturer-specific. This field is also provided in the // Board Info area. Either or both fields may be ~Qnull~R. 0xC1, // xx Custom product info area fields, if any (must be preceded with // type/length byte) // 1 C1h (type/length byte encoded to indicate no more info fields). // Y 00h - any remaining unused space 0, 0, 0, 0, 0, 0, 0, 0xBF, // 1 Product Info Area Checksum (zero ) // (*) These fields are always encoded as if the Language Code were English. I.e. if the type/length code bits // 7:6=11b the serial number will always be interpreted as ASCII+Latin 1, not UNICODE }, { /*--- BOARD POINT TO POINT CONNECTIVITY RECORD ---*/ { 0xC0, // Record Type ID. For all records defined in this specification a value of C0h (OEM) // shall be used. 0x2, // [3:0] record format version (2h for this definition) 0, // [6:4] Reserved, write as 0h 1, // [7] End of list. Set to one for the last record 30, // Record Length PICMG_BOARD_P2P_CONNECTIVITY_RECORD_CHECKSUM_0, // Record Checksum. Holds the zero of the record data, including the following // activation and power management data records PICMG_BOARD_P2P_CONNECTIVITY_HEADER_CHECKSUM_0, // Header Checksum. Holds the zero of the header // record data // Manufacturer ID. LS Byte first. Write as the three byte // ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) shall be used. { 0x5A, 0x31, 0x00 }, 0x14, // PICMG Record ID 0x00 // Record Format Version. For this specification, the value 0h shall be used }, 1, // OEM GUID Count. The number, n, of OEM GUlDs // defined in this record. { { /*--- OEM GUID ENTRY ---*/ { 0x43, 0x3D, 0x33, 0x49, 0xAC, 0xC8, 0x4E, 0x35, 0xA3, 0x7F, 0xEB, 0x09, 0xF5, 0xEE, 0x75, 0xBE, } }, }, // Link Descriptor list. A variable length list of four byte Link Descriptors // (LS Byte first) (see Table 3-50, "Link Descriptor"; Table 3-51, "Link // Designator"; and Table 3-52, "Link Type") totaling m bytes in length. // Each Link Descriptor details one type of point-to-point protocol // supported by the referenced Channels. { { /*--- LINK DESCRIPTION ENTRY ---*/ 0x101, // [11:0] Link Designator. Identifies the Interface Channel and // the Ports within the Channel that are being described; see // Table 3-37, "Link Designator". 0x1, // [19:12] Link Type. Identifies the PICMG® 3.x subsidiary // specification that governs this description or identifies the // description as proprietary; see Table 3-38, "SLink Type". 0, // [23:20] Link Type Extension. Identifies the subset of a // subsidiary specification that is implemented and is defined // entirely by the subsidiary specification identified in the // Link Type field. 0x0 // [31:24] Link Grouping ID. Indicates whether the Ports of this // Channel are operated together with Ports in other Channels. // A value of 0 always indicates a Single-Channel Link. A common, // non-zero Link Grouping ID in multiple Link Descriptors indicates // that the Ports covered by those Link Descriptors must be operated // together. A unique non-zero Link Grouping ID also indicates // Single-Channel Link. }, { /*--- LINK DESCRIPTION ENTRY ---*/ 0x102, // [11:0] Link Designator. Identifies the Interface Channel and // the Ports within the Channel that are being described; see // Table 3-37, "Link Designator". 0x1, // [19:12] Link Type. Identifies the PICMG® 3.x subsidiary // specification that governs this description or identifies the // description as proprietary; see Table 3-38, "SLink Type". 0, // [23:20] Link Type Extension. Identifies the subset of a // subsidiary specification that is implemented and is defined // entirely by the subsidiary specification identified in the // Link Type field. 0x0 // [31:24] Link Grouping ID. Indicates whether the Ports of this // Channel are operated together with Ports in other Channels. // A value of 0 always indicates a Single-Channel Link. A common, // non-zero Link Grouping ID in multiple Link Descriptors indicates // that the Ports covered by those Link Descriptors must be operated // together. A unique non-zero Link Grouping ID also indicates // Single-Channel Link. }, }, }, }; static fru1_data_t fru1_data = { { /*--- COMMON HEADER ---*/ 0x1, // 3:0 - format version number = 1h for this specification 0, // 7:4 - reserved, write as 0000b 0, // Internal Use Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 1, // Chassis Info Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 4, // Board Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 11, // Product Info Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 17, // MultiRecord Area Starting Offset (in multiples of 8 bytes) // 00h indicates that this area is not present 0, // PAD, write as 00h 0xDE, // Common Header Checksum (zero ) }, { /*--- CHASSIS INFO AREA ---*/ 0x01, // 1 Chassis Info Area Format Version // 7:4 - reserved, write as 0000b // 3:0 - format version number = 1h for this specification. 3, // 1 Chassis Info Area Length (in multiples of 8 bytes) 1, // 1 Chassis Type (enumeration) 0xC3, // 1 Chassis Part Number type/length // N Chassis Part Number bytes 'M', 'S', 'U', 0xCC, // 1 Chassis Serial Number type/length(*) // M Chassis Serial Number bytes(*) '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', 0xC1, // xx Custom Chassis Info fields, if any. Each fields must be preceded // with type/length byte. // 1 C1h (type/length byte encoded to indicate no more info fields). // Y 00h - any remaining unused space 0, 0, 0x76, // 1 Chassis Info Checksum (zero ) // (*) These areas are always encoded as if the Language Code were English. }, { /*--- BOARD INFO AREA ---*/ 0x01, // 1 Board Area Format Version // 7:4 - reserved, write as 0000b // 3:0 - format version number = 1h for this specification. 7, // 1 Board Area Length (in multiples of 8 bytes) 25, // 1 Language Code (See section 15) 0x80, 0x68, 0x80, // 3 Mfg. Date / Time // Number of minutes from 0:00 hrs 1/1/96, LSbyte first (little endian) 0xC3, // 1 Board Manufacturer type/length byte // P Board Manufacturer bytes 'M', 'S', 'U', 0xCA, // 1 Board Product Name type/length byte // Q Board Product Name bytes 'I', 'P', 'M', 'C', ' ', 's', 'h', 'e', 'l', 'f', 0xD2, // 1 Board Serial Number type/length byte* // N Board Serial Number bytes* 'M', 'S', 'U', '-', 'I', 'P', 'M', 'C', '-', '2', '0', '1', '7', '-', '0', '0', '0', '0', 0xC5, // 1 Board Part Number type/length byte // M Board Part Number bytes 'I', 'C', 'A', 'R', 'E', 0xC0, // 1 FRU File ID type/length byte* // R FRU File ID bytes* The FRU File version field is a pre-defined field // provided as a manufacturing aid for verifying the file that was used // during manufacture or field update to load the FRU information. The // content is manufacturer-specific. This field is also provided in the // Product Info area. Either or both fields may be null. 0xC1, // xx Additional custom Mfg. Info fields. Defined by manufacturing. Each // field must be preceded by a type/length byte // 1 C1h (type/length byte encoded to indicate no more info fields). // Y 00h - any remaining unused space (pad to a multiple of 8, including ) 0, 0, 0, 0, 0, 0, 0, 0xEF, // 1 Board Info Area Checksum (zero ) // (*) These areas are always encoded as if the Language Code were English }, { /*--- PRODUCT INFO AREA ---*/ 0x01, // 1 Product Area Format Version // 7:4 - reserved, write as 0000b // 3:0 - format version number = 1h for this specification 6, // 1 Product Area Length (in multiples of 8 bytes) 25, // 1 Language Code (See section 15) 0xC3, // 1 Manufacturer Name type/length byte // N Manufacturer Name bytes 'M', 'S', 'U', 0xCA, // 1 Product Name type/length byte // M Product Name bytes 'I', 'P', 'M', 'C', ' ', 's', 'h', 'e', 'l', 'f', 0xC5, // 1 Product Part/Model Number type/length byte // O Product Part/Model Number bytes 'I', 'C', 'A', 'R', 'E', 0xC2, // 1 Product Version type/length byte // R Product Version bytes 'V', '2', 0xCD, // 1 Product Serial Number type/length byte* // P Product Serial Number bytes* 'M', 'S', 'U', '-', 'I', 'P', 'M', 'C', '-', '2', '0', '1', '7', 0xC0, // 1 Asset Tag type/length byte // Q Asset Tag 0xC0, // 1 FRU File ID type/length byte // R FRU File ID bytes. The FRU File version field is a pre-defined field // provided as a manufacturing aid for verifying the file that was used // during manufacture or field update to load the FRU information. The // content is manufacturer-specific. This field is also provided in the // Board Info area. Either or both fields may be ~Qnull~R. 0xC1, // xx Custom product info area fields, if any (must be preceded with // type/length byte) // 1 C1h (type/length byte encoded to indicate no more info fields). // Y 00h - any remaining unused space 0, 0, 0, 0x40, // 1 Product Info Area Checksum (zero ) // (*) These fields are always encoded as if the Language Code were English. I.e. if the type/length code bits // 7:6=11b the serial number will always be interpreted as ASCII+Latin 1, not UNICODE }, { /*--- ADDRESS TABLE RECORD ---*/ { 0xC0, // Record Type ID. For all records defined in this specification a value of C0h (OEM) // shall be used. 0x2, // [3:0] record format version (2h for this definition) 0, // [6:4] Reserved, write as 0h 0, // [7] End of list. Set to one for the last record 75, // Record Length PICMG_ADDRESS_TABLE_RECORD_CHECKSUM_1, // Record Checksum. Holds the zero of the record data, including the following // activation and power management data records PICMG_ADDRESS_TABLE_HEADER_CHECKSUM_1, // Header Checksum. Holds the zero of the header // record data { // Manufacturer ID. LS Byte first. Write as the three byte // ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) shall be used. 0x5A, 0x31, 0x00, }, 0x10, // PICMG Record ID 0x00 // Record Format Version. For this specification, the value 0h shall be used }, 0, // 10 1 Shelf Address Type/Length Byte (FRU Information variant) // [7:6]- Type // [5:0] - Length (=000000b if Shelf Address is not configured) // 11 20 Shelf Address bytes as a fixed size field, with Length bytes of the Shelf // address, encoded according to the Shelf Address Type/Length Byte field in // byte 10. The values of the unused bytes of the fixed size field - // bytes (11 + Length) - 30 are undefined. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 16, // 31 1 Address Table Entries Count. Indicates the number of entries in the // Address Table Entries. // 32 N Address Table Entries. This is essentially an of Address Table // Entries. Each entry is formatted as shown in Table 3-8, "Address Table // Entry." N = (Address Table Entries Count x 3) // ADD (N) ADDRESS ENTRIES HEREAFTER - SHOULD FOLLOW IMMEDIATELY THIS INITIALIZERURE { { /*--- ADDRESS TABLE ENTRY ---*/ 0x41, // Hardware Address. This is the Hardware Address of the device. 1, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x42, // Hardware Address. This is the Hardware Address of the device. 2, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x43, // Hardware Address. This is the Hardware Address of the device. 3, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x44, // Hardware Address. This is the Hardware Address of the device. 4, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x45, // Hardware Address. This is the Hardware Address of the device. 5, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x46, // Hardware Address. This is the Hardware Address of the device. 6, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x47, // Hardware Address. This is the Hardware Address of the device. 7, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x48, // Hardware Address. This is the Hardware Address of the device. 8, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x49, // Hardware Address. This is the Hardware Address of the device. 9, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4a, // Hardware Address. This is the Hardware Address of the device. 10, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4b, // Hardware Address. This is the Hardware Address of the device. 11, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4c, // Hardware Address. This is the Hardware Address of the device. 12, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4d, // Hardware Address. This is the Hardware Address of the device. 13, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4e, // Hardware Address. This is the Hardware Address of the device. 14, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x4f, // Hardware Address. This is the Hardware Address of the device. 15, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, { /*--- ADDRESS TABLE ENTRY ---*/ 0x50, // Hardware Address. This is the Hardware Address of the device. 16, // Site Number. This is the number portion of the device´s Physical Address. 0x00 // Site Type. This is the type portion of the device´s Physical Address. }, }, }, { /*--- POWER DISTRIBUTION RECORD ---*/ { 0xC0, // Record Type ID. For all records defined in this specification a value of C0h (OEM) // shall be used. 0x2, // [3:0] record format version (2h for this definition) 0, // [6:4] Reserved, write as 0h 0, // [7] End of list. Set to one for the last record 44, // Record Length PICMG_SHELF_POWER_DISTRIBUTION_RECORD_CHECKSUM_1, // Record Checksum. Holds the zero of the record data, including the following // activation and power management data records PICMG_SHELF_POWER_DISTRIBUTION_HEADER_CHECKSUM_1, // Header Checksum. Holds the zero of the header // record data { // Manufacturer ID. LS Byte first. Write as the three byte // ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) shall be used. 0x5A, 0x31, 0x00, }, 0x11, // PICMG Record ID 0x00 // Record Format Version. For this specification, the value 0h shall be used }, 1, // Number of Power Feeds. This field specifies the number of power // Feeds (N) defined in this Shelf Power Distribution record. // Power Distribution Map. This table contains N variable sized Power // Distribution Maps, one for each Feed (see Table 3-76, "Power // Distribution Map"). { { /*--- POWER DISTRIBUTION MAP ENTRY ---*/ 0xF4, 0x01, // Maximum External Available Current, LS Byte first 0xFF, 0xFF, // Maximum Internal Current, LS Byte first 0x51, // Minimum Expected Operating Voltage in 1/2 V increments 16, // Feed-to-FRU Mapping Entries Count // Feed-to-FRU Mapping Entries. This describes all the FRUs that // are powered from this Feed. Each entry follows the format found in // Table 3-77, "Feed-to-FRU Mapping Entry," and is 2 bytes in size. { { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x41, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x42, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x43, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x44, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x45, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x46, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x47, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x48, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x49, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4a, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4b, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4c, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4d, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4e, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x4f, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, { /*--- FEED TO FRU MAPPING ENTRY ---*/ 0x50, // Hardware Address 0xfe // FRU Device ID. A value of FEh indicates that all FRU Device IDs at // the Hardware Address be considered as a unit. }, }, }, }, }, { /*--- SHELF ACTIVATION AND POWER MANAGEMENT RECORD ---*/ { 0xC0, // Record Type ID. For all records defined in this specification a value of C0h (OEM) // shall be used. 0x2, // [3:0] record format version (2h for this definition) 0, // [6:4] Reserved, write as 0h 0, // [7] End of list. Set to one for the last record 87, // Record Length PICMG_SHELF_ACTIVATION_AND_POWER_MGMT_RECORD_CHECKSUM_1, // Record Checksum. Holds the zero of the record data, including the following // activation and power management data records PICMG_SHELF_ACTIVATION_AND_POWER_MGMT_HEADER_CHECKSUM_1, // Header Checksum. Holds the zero of the header // record data // Manufacturer ID. LS Byte first. Write as the three byte // ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) shall be used. { 0x5A, 0x31, 0x00 }, 0x12, // PICMG Record ID 0x00 // Record Format Version. For this specification, the value 0h shall be used }, 0, // Allowance for FRU Activation Readiness in seconds 16, // FRU Activation and Power Descriptor Count. This contains a count of the number of entries (M) // in the FRU Activation and Power Descriptor Table. { { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x41, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x42, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x43, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x44, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x45, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x46, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x47, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x48, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x49, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4A, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4B, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4C, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4D, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4E, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x4F, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, { /*--- FRU ACTIVATION AND POWER DESCRIPTOR ---*/ 0x50, // byte 1 : hardware address 0xfe, // byte 2 : FRU device ID 48, // byte 3 : Maximum FRU Power Capability in Watts, LSB 0, // byte 4 : Maximum FRU Power Capability, MSB 0x40, // byte 5 : activation and power configuration parameters for the Hardware Address/FRU // Device ID location. // [7] Shelf Manager Controlled Deactivation. This flag determines if the Shelf Manager deactivates // the FRU residing at this location, when it reaches M5. // 1h = Disabled. The Shelf Manager does not deactivate this FRU. The // FRU waits in M5 until the System Manager decides to deactivate it. // 0h = Enabled. The Shelf Manager deactivates this FRU, and it proceeds to M6. // [6] Shelf Manager Controlled Activation. This flag determines if the Shelf Manager activates the // FRU residing at this location, when it reaches M2. // 0h = Disabled. The Shelf Manager does not activate this FRU. The // FRU waits in M2 until the System Manager decides to activate it. // 1h = Enabled. The Shelf Manager activates this FRU, and it proceeds to M3. // [5:0] Delay Before Next Power On. Tenths of a second to delay before powering up any other FRU // after powering this FRU. Note: for entries with FRU Device 10 set to FEh, this delay is // performed after powering on each FRU represented by a particular IPM Controller, // not just once after powering on the last FRU. }, }, }, { /*--- BACKPLANE POINT TO POINT CONNECTIVITY RECORD ---*/ { 0xC0, // Record Type ID. For all records defined in this specification a value of C0h (OEM) // shall be used. 0x2, // [3:0] record format version (2h for this definition) 0, // [6:4] Reserved, write as 0h 1, // [7] End of list. Set to one for the last record 101, // Record Length PICMG_BACKPLANE_P2P_CONNECTIVITY_RECORD_CHECKSUM_1, // Record Checksum. Holds the zero of the record data, including the following // activation and power management data records PICMG_BACKPLANE_P2P_CONNECTIVITY_HEADER_CHECKSUM_1, // Header Checksum. Holds the zero of the header // record data // Manufacturer ID. LS Byte first. Write as the three byte // ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) shall be used. { 0x5A, 0x31, 0x00 }, 0x04, // PICMG Record ID 0x00 // Record Format Version. For this specification, the value 0h shall be used }, { { /*--- POINT TO POINT SLOT DESCRIPTOR ---*/ 0x0B, // Point-to-Point Channel Type Indicates the type of point-to-point // connectivity described by this descriptor. 0x41, // Slot Address Indicates the Slot address for this Slot. // For PICMG® 3.0 systems, this is the Hardware Address. 15, // Point-to-Point Channel Count Indicates the number of // point-to-point Channels in this Slot of the type // specified in Point-to-Point Channel Type. { { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x42, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 2, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x43, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 3, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x44, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 4, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x45, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 5, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x46, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 6, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x47, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 7, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x48, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 8, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x49, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 9, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4A, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 10, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4B, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 11, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4C, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 12, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4D, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 13, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4E, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 14, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4F, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 15, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x50, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 1, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 16, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, }, }, { /*--- POINT TO POINT SLOT DESCRIPTOR ---*/ 0x0B, // Point-to-Point Channel Type Indicates the type of point-to-point // connectivity described by this descriptor. 0x42, // Slot Address Indicates the Slot address for this Slot. // For PICMG® 3.0 systems, this is the Hardware Address. 15, // Point-to-Point Channel Count Indicates the number of // point-to-point Channels in this Slot of the type // specified in Point-to-Point Channel Type. { { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x41, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 2, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x43, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 3, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x44, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 4, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x45, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 5, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x46, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 6, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x47, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 7, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x48, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 8, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x49, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 9, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4A, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 10, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4B, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 11, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4C, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 12, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4D, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 13, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4E, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 14, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x4F, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 15, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, { /*--- POINT TO POINT CHANNEL DESCRIPTOR ---*/ 0x50, // [7:0] Remote Slot In PICMG® 3.0 systems, this is the Hardware Address // of the remote Slot. 2, // [12:8] Remote Channel Indicates the Channel number within the remote Slot // to which this point-to-point connection is routed. 16, // [17:13] Local Channel Indicates the Channel number within the local Slot. 0 // [23:18] Reserved. Fixed to O. }, }, }, }, }, };