Startup configuration of the FLX712 firmware
                 to transmit the LHC clock to the Hub crates.
         (configuration for payload content, e.g. L1A, is not described here)

Rev: 23-Apr-2021


0) The FLX712 firmware should be loaded from flash at power up.


1) "ssh -Y" (for X-window) to the TTC computer with temporary name "msutcc"
  (which will eventually replace and be renamed hubttc)

  Philippe ~ % ssh -Y hubuser@msutcc.pa.msu.edu
  Warning: No xauth data; using fake authentication data for X11 forwarding.
  Last login: Fri Apr 23 10:05:00 2021 from 172.21.61.1
  Setting up FELIX (user)


2) Not required: check initial status - bottom says "LCLK fixed"

      [hubuser@msutcc ~]$ flx-info

   General information
   ----------------------------------
   FLX cards        : 2
   Card type        : FLX-712
   Reg Map version  : 4.a
   FW version date  : 20/11/16 10:50
   GIT tag          : rm-4.10
   GIT commit number: 367
   GIT hash         : 0x0000000067e759ab
   Firmware mode    : GBT

   Output of lspci: 
   06:00.0 Communication controller: CERN/ECP/EDU Device 0428
   07:00.0 Communication controller: CERN/ECP/EDU Device 0427

   Interrupts, descriptors & channels
   ----------------------------------
   Number of interrupts  : 8
   Number of descriptors : 2
   Number of channels    : 12

   Links and GBT settings
   ----------------------------------
   Number of channels    : 12
   GBT Wrapper generated : YES
   Optical transceivers  : 4

   Clock resources
   ----------------------------------
   MAIN clock source     : LCLK fixed
   Internal PLL Lock     : YES

   ADN2814 TTC Status    : ON


3) required: use the graphical program to switch to TTC clock
   (there may be a way to do this from the command line, but
   everything I tried from the documentation was not successful)

  [hubuser@msutcc ~]$ elinkconfig

see elinkconfig_0_start.png

  Click on "CLock..." at the top
  In pop-up window:
    switch from "Local" to "TTC"
    Click "OK"
  In main window
    Click "Quit"
    Note: we are not setting up the link payload in this description

see elinkconfig_1_clock_step1_select.png



4) Check status (again).  It should now say "TTC fixed"

   [hubuser@msutcc ~]$ flx-info

   General information
   ----------------------------------
   FLX cards        : 2
   Card type        : FLX-712
   Reg Map version  : 4.a
   FW version date  : 20/11/16 10:50
   GIT tag          : rm-4.10
   GIT commit number: 367
   GIT hash         : 0x0000000067e759ab
   Firmware mode    : GBT

   Output of lspci: 
   06:00.0 Communication controller: CERN/ECP/EDU Device 0428
   07:00.0 Communication controller: CERN/ECP/EDU Device 0427

   Interrupts, descriptors & channels
   ----------------------------------
   Number of interrupts  : 8
   Number of descriptors : 2
   Number of channels    : 12

   Links and GBT settings
   ----------------------------------
   Number of channels    : 12
   GBT Wrapper generated : YES
   Optical transceivers  : 4

   Clock resources
   ----------------------------------
   MAIN clock source     : TTC fixed
   Internal PLL Lock     : YES

   ADN2814 TTC Status    : ON


5) Not sure this is required but can't hurt: reset/initialize

   [hubuser@msutcc ~]$ flx-init
   Configuring Si5345
   Hard resetting the Si5345...
   Beginning configuration process....
   Configuration done...
   Enabling output...
   LOS register = 0x22
   Sticky LOS register = 0xff
   LOL register = 0x00
   Found lock in 1 seconds
   Sticky LOL register = 0x0d
   Performing GBT soft reset
   flx-init: warning: Not all channels align!
   flx-init: warning: 12 channels not aligned
   Resetting the RX and TX MiniPODs
   ERROR: 0xf written to address 0x5c of MINIPOD-TX3 but 0xff read back
   ERROR: 0xf written to address 0x5c of MINIPOD-TX4 but 0xff read back
   ERROR: 0xf written to address 0x5c of MINIPOD-RX3 but 0xff read back
   ERROR: 0xf written to address 0x5c of MINIPOD-RX4 but 0xff read back
   ERROR: 0 written to address 0x5d of MINIPOD-TX3 but 0xff read back
   ERROR: 0 written to address 0x5c of MINIPOD-TX3 but 0xff read back
   ERROR: 0 written to address 0x5d of MINIPOD-TX4 but 0xff read back
   ERROR: 0 written to address 0x5c of MINIPOD-TX4 but 0xff read back
   ERROR: 0 written to address 0x5d of MINIPOD-RX3 but 0xff read back
   ERROR: 0 written to address 0x5c of MINIPOD-RX3 but 0xff read back
   ERROR: 0 written to address 0x5d of MINIPOD-RX4 but 0xff read back
   ERROR: 0 written to address 0x5c of MINIPOD-RX4 but 0xff read back
   RX / TX MiniPODs reset done

   [hubuser@msutcc ~]$ flx-info

   General information
   ----------------------------------
   FLX cards        : 2
   Card type        : FLX-712
   Reg Map version  : 4.a
   FW version date  : 20/11/16 10:50
   GIT tag          : rm-4.10
   GIT commit number: 367
   GIT hash         : 0x0000000067e759ab
   Firmware mode    : GBT

   Output of lspci: 
   06:00.0 Communication controller: CERN/ECP/EDU Device 0428
   07:00.0 Communication controller: CERN/ECP/EDU Device 0427

   Interrupts, descriptors & channels
   ----------------------------------
   Number of interrupts  : 8
   Number of descriptors : 2
   Number of channels    : 12

   Links and GBT settings
   ----------------------------------
   Number of channels    : 12
   GBT Wrapper generated : YES
   Optical transceivers  : 4

   Clock resources
   ----------------------------------
   MAIN clock source     : TTC fixed
   Internal PLL Lock     : YES

   ADN2814 TTC Status    : ON


6) Not required: checking additional clock status info

   [hubuser@msutcc ~]$ flx-info Si5345
   Status of the SI5345
   --------------------
   Loss of lock (LOL): No
   Loss of signal (LOS) of input 1: No


   [hubuser@msutcc ~]$ flx-info ADN2814
   TTC Status: ON
   Loss of Signal Status: 0 
   Static Loss of Lock:   0 
   Loss of Lock Status:   0