!
!        TTCvi  Setup File  for the  Hub Tests at MSU
!       ----------------------------------------------
!
!                                            Initial Rev.  2-Nov-2018
!                                            Current Rev.  8-Nov-2018
!
!
!  This file is used to setup the TTC VME Crate in the MSU Hub/HTM
!  test stand.  This VME crate holds a slot 1 Bit-3 VME interface
!  card, a TTCvi card, and a 40.000 MHz version of the TTCvx card.
!
!  Because the TTCvx card has a 40.000 MHz reference our TTC
!  crate uses an external 40.0787 MHz ECL reference for the TTCvx.
!
!  All of the setup work is on the TTCvi card.  The TTCvx card
!  does not have a VME interface - it only gets its power from
!  the VME bus.
!
!  The goal is to setup the TTC VME Crate so that the optical
!  output from the TTCvx card has the following 4 components:
!
!    - 40.08 MHz Reference Clock
!
!    - L1As   for now set at a random 1 kHz rate
!
!    - Bunch Counter Reset   a once per turn Short Format,
!                            Synchronous,  Broadcast  Command
!                            with the value  0x01
!
!    - Event Counter Reset   For now sent out only in response
!                            to keyboard input from a human
!                            Short Format,  Non-Synchronous,
!                            Broadcast Command  with value  0x02
!
!
!  VME Operation Details:
!  ----------------------
!
!    There is only one Bit-3 interface in the system that controls
!    the TTC VME Crate  so we automatically default to VME Bit-3 #1.
!
!    The Bit-3 VME interface will default to its API mode.
!
!    This application will default to Supervisory Data Access Mode.
!
!    We can use  A24  access to all registers in the TTCvi.
!
!    We need to use both D16 and D32 data widths depending on
!    which register we are loading in the TTCvi module.
!
!
!  Commands for Initial VME Setup:
!  -------------------------------

Bit3_Adaptor:    0

Address_Space:  24

Data_Size:      16



!
!  Start the TTCvi setup with a Reset and initial
!  loads of Control Status Registers 1 and 2:
!  ----------------------------------------------

VME_Address: 0xC00084    ! Module Reset - caused by
                         ! VME Write with any data value
  Write_Value: 0xCAFE


VME_Address: 0xC00080    ! CSR1 - Reset does not over write CSR1
                         ! get things stopped, expect to read 0x0A60
  Write_Value: 0x0000


VME_Address: 0xC00082    ! CSR2 - Reset does not over write CSR2
                         ! zero it, then asset FIFO Resets, then set
                         ! all FIFOs for "Re-Transmission when Empty",
                         ! i.e. hold the Read Pointer,  see pg 7.
  Write_Value: 0x0000
  Write_Value: 0xF000
  Write_Value: 0x0000



!
!  Set the  TrigWord Size Sub-Address  register to
!  zero to block sending out Event/Orbit Counter
!  transfers following L1 Accepts:
!  -----------------------------------------------

VME_Address: 0xC000CA    ! TrigWord Size Sub-Address
                         ! register set to zero
  Write_Value: 0x0000



!
!  Set the  Inhibit<0>  Delay and Duration  registers
!  so that we can use the  B Channel Data <0> FIFO  to
!  send out the  Beam Crossing Counter Reset  signal.
!  Set the Delay to a reasonable value  0x0080
!    so that Delay is  128 x 25 nsec = 3.2 usec.
!  Set the Duration to be longer than the longest
!    possible Long-Format B Channel message  0x0040
!    so Duration is  64 x 25 nsec = 1.6 usec.
!  Beam Crossing Counter Reset  will be sent out
!  at the end of Duration which starts after Delay.
!  ---------------------------------------------------

VME_Address: 0xC00092    ! Inhibit<0> Delay register
                         ! load decimal 128
  Write_Value: 0x0080

VME_Address: 0xC00094    ! Inhibit<0> Duration register
                         ! load decimal  64
  Write_Value: 0x0040



!
!  Set the  B Go <0> Mode  register to:  Disable
!  the front panel input,  Synchronous Cycle,
!  Repetitive Mode,  Start when FIFO is Not Empty:
!  -----------------------------------------------

VME_Address: 0xC00090    ! B Go <0> Mode  register
                         ! Load  0x0005
  Write_Value: 0x0005



!
!  Load the  B Channel Data <0> FIFO  with the
!  Command value for  Beam Crossing Counter Reset
!  i.e. 0x01.  This is a Short-Format Command and
!  must be loaded into the non-byte-aligned bits
!  D30:D23  via a D32 write.   We should only need
!  1 but I will load 5 FIFO depths.  Note that this
!  is a write only FIFO.
!  ------------------------------------------------

Data_Size:   32

VME_Address: 0xC000B0    ! B Channel Data <0> FIFO
                         ! Load 0x0001 into D30:D23

  Write_Value: 0x00800000
  Write_Value: 0x00800000
  Write_Value: 0x00800000
  Write_Value: 0x00800000
  Write_Value: 0x00800000



!
!  Load  Control Status Register 1  for:
!    Select Orbit Counter,
!    Set 1 kHz Random Trigger (L1A) Rate,
!    Match the BC Delay read only data
!    Match the L1A FIFO read only data
!    Select an Internal Orbit Signal
!    Select a Random Source of L1A Trigger
!  ----------------------------------------------

Data_Size:      16

VME_Address: 0xC00080    ! Load the CSR1
                         ! with:  0xAA6D
  Write_Value: 0xAA6D