Analog Design for the CTFE Cards in Run II -------------------------------------------- Original Rev. 1-SEPT-1999 Current Rev. 16-MAY-2001 Utilizing the Full Analog Dynamic Range from the BLS Card Outputs to the Level 1 Calorimeter Trigger Inputs --------------------------------------------------------------------- Assume that the signals from the BLS cards can linearly swing 6 Volts differential. We break up eta into three ranges and then in each eta range we define a different scale for "Volts to GeV of E". These scales are picked so that the signal from the BLS can linearly swing far enough so that at the smallest eta in each range we can get enough E signal to give us 62 GeV of Et. Trig At smallest Tower L1 CT At smallest sin(eta), Volts Eta Input sin(eta), GeV Diff required Index E of E for to give Range sin(eta) Scale 62 GeV Et 62 GeV of Et ----- -------- ------- ----------- --------------- 1 0.9950 \ 2 Volts | diff = 146 GeV E 4.70 Volts 8 0.4259 / 62 GeV diff 9 0.3543 \ 2 Volts | diff = 465 GeV E 5.32 Volts 14 0.1332 / 175 GeV diff 15 0.1100 \ 2 Volts | diff = 1512 GeV E 5.40 Volts 19(20) 0.0410 / 560 GeV diff Note that the above table shows 19 as the highest Eta Index covered and that it has a sin(eta) of 0.0410. The same circuit is obviously going to be used at eta_index of 20. Here we expect that the signal to noise ratio will be a little worse because the gain at the input to the L1 Cal Trig will be turned down even further ( sin(eta) for eta_index 20 is about 0.0287) and we expect the eta_index 20 channels to saturate at about 43 GeV of Et. All other eta's will saturate at 62 GeV of Et. Block Diagram of the Analog Input to the L1 Cal Trig -------------------------------------------------------- Differential Receiver +---------+ |\ >--| Fixed |----| \ | Attn. | | >--. >--| x 0.37 |----| / | +---------+ |/ | | Diff Input | to L1 Cal Trig +----------+ +----------+ +--------+ from the BLS | | | | | Output | /-----+ | Variable | | Offset | | Stage | / Flash| | Gain |----| Summation|----| |----< ADC |--> | Cell | | | | x 1.75 | \ | +----------+ +----------+ +--------+ \-----+ | | +----------\ | | | Gain \ | | | Control >-------' | | DAC / | +----------/ | +------------\ | | Zero Energy \ | | Response >---' | DAC / +------------/ Then given the above Volts per Gev of E scales and the block level design of the analog input to the L1 Cal Trig, what do I do to think about the detailed design of this analog circuit ? For a given range of eta_index do the following: 1. For the highest eta_index in the range find the E signal in Volts diff that you need to make 62 Gev of Et at this eta_index. This is the largest input signal in volts diff that we will need to linearly process in this eta_index range. 2. Calculate the attenuation that you need to bring this signal down to 2.0 Volts diff which is the largest signal that the EL4451 can take at its input. The EL4451 is the I.C. that follows the fixed attenuator at the input to the L1 Cal Trig. 3. Given the above attenuation, calculate the required gain to give the correct E to Et conversion at the lowest eta_index of the range. We can count on a maximum gain of 1.9 coming from the variable gain cell and the rest must come from fixed gain in the output section of the EL4451. Note that you need to increase this fixed gain by 25% or so to give some head room for adjustment. 4. Given the fixed input attenuation and the fixed output stage gain calculate the actual gain required in the EL4451 variable gain stage at both the lowest and highest eta_index in this range. So what does all this make the input to the L1 Cal Trig look like ? 1. Over all the eta's we can use the same analog input to the L1 Cal Trig 2. The fixed input attenuator will have a gain of about 0.370 3. The fixed gain in the output stage will be about 1.75 which is about 25% more than what should be needed. 4. At the lowest eta in each range the variable gain cell will be set to a gain of about 1.54 At the highest eta in each range the variable gain cell will be set to a gain of about 0.572 5. The Gain Control DAC is 8 bits and can set the gain of the variable gain cell anywhere in the range 0 to 2.0 6. The Offset Control DAC is 12 bits and can swing the input to the Flash ADC through the range -1.25 Volt to +1.25 Volt. The actual input range to the flash converter is -1.0 volts to +1.0 Volts. The idea is to use this Offset Control both as a way to test the system and as a way to precisely set each L1 Cal Trig channel to its correct zero energy response. HD signals in the TT Eta Index range 1 through 8 ------------------------------------------------ The resistors picked for the BLS summing circuits in the TT Eta Index range 1 through 8 will provide only about 61% of the expected signal on the HD channels. The signal level for the EM channels should be as expected. The HD signal level will be low, i.e. for a given amount of GeV deposited in the Calorimeter we will see a smaller pickoff signal than expected. See notes from Maris, Reiner, and Bob from 2 and 3 May 2001. To compensate for this lower than expected signal level in the HD channels in this eta range we will change the attenuator at the input to the variable gain circuit. The standard value for this attenuator, and the value that will still be used for the EM channels is a gain of 0.37 For the HD channels we will make this a gain of 0.63 Original New EM HD -------- -------- Input Shunt Resistor 84.5 Ohm 84.5 Ohm Series Resistor 845 Ohm 499 Ohm Output Shunt Resistor 499 Ohm 845 Ohm Gain 0.371 0.629 Input Z 79.50 Ohm 79.50 Ohm So with this set of input attenuators, the HD channels will need only 59% as much input signal to send the same level signal into the variable gain stage. The specific changes in the HD channels are: R12, R13, R62, R63 changes from the original 845 Ohm to 499 Ohm for HD. R14, R15, R64, R65 changes from the original 499 Ohm to 845 Ohm for HD. [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][]] Background Material ----------------------- Review of the Geometry of the Trigger Towers -------------------------------------------- Version 12 Trigger Tower Data Table Trigger Tower Eta Indexs 1 through 20 North & South 12-JAN-1992 Eta Index EM Z EM Radius sin(theta) HD Z HD Radius sin(theta) ----- ------ --------- ---------- ------ --------- ---------- 1 9.198 91.65 0.9950 11.92 119.3 0.9950 2 27.96 91.65 0.9565 36.25 119.3 0.9568 3 47.85 91.65 0.8865 62.03 119.3 0.8872 4 69.65 91.65 0.7962 90.30 119.3 0.7973 5 94.26 91.65 0.6971 119.6 119.3 0.7062 6 118.7 91.65 0.6111 204.9 149.4 0.5892 7 178.2 95.30 0.4716 207.4 122.1 0.5073 8 178.9 84.22 0.4259 208.1 98.37 0.4274 9 178.9 67.77 0.3543 208.8 77.56 0.3482 10 178.9 54.85 0.2931 211.8 64.55 0.2915 11 178.9 44.56 0.2417 211.8 52.44 0.2403 12 178.9 36.30 0.1989 211.8 42.72 0.1977 13 178.9 29.62 0.1633 211.8 34.86 0.1624 14 178.9 24.22 0.1342 211.8 28.47 0.1332 15 178.9 19.80 0.1100 211.8 23.28 0.1093 16 178.9 16.19 0.0901 211.9 19.04 0.0895 17 178.9 13.18 0.0735 211.9 15.50 0.0730 18 178.9 10.30 0.0575 211.9 12.11 0.0571 19 179.0 7.556 0.0422 211.9 8.701 0.0410 20 0.01 150.0 0.---- 212.3 6.101 0.0287 D-Zero Notes from Run I ----------------------- D0 Note 1084 13-FEB-1991 "Summing Resistors for Central Calorimetry" D0 Note 1093 27-FEB-1991 "EC Contributions to Trigger Towers 1 thru 6" D0 Note 1159 22-JUL-1991 "EC Contributions to Trigger Towers 1 thru 6" D0 Note 1264 30-OCT-1991 "Summary of Calorimetry Summing Resistors" D0 Note 1306 18-DEC-1991 "Calorimeter Trigger Delays" D0 Note 1307 31-DEC-1991 "Level One Trigger Calibration from NWA to D0" D0 Note 1707 4-MAY-1993 "Scale and Saturation Solution" In the directory http://www.pa.msu.edu/hep/d0/ftp/run1/l1/caltrig/ see the files: energy_to_voltage.txt <--- this has sampling fraction stuff and information about what calorimeter element is in what trigger tower term_attns_in_use_jan_1993.txt In the directory http://www.pa.msu.edu/hep/d0/ftp/run1/l1/caltrig/cabling/ see the files: calorimeter_sector_to_bls_rack.txt calorimeter_sector_to_trigger_phi_index.txt central_bls_card_to_ctfe_card.txt end_cap_bls_card_to_ctfe_card.txt In the directory http://www.pa.msu.edu/hep/d0/ftp/run1/l1/drawings/ there are many L1 Cal Trig drawings from the Run I setup including the coordinate system in: calorimeter_coordinates.ps Zo of the BLS to L1 Cal Trig Cables From Ian Manning, "The old cable is 80 Ohm and the new 78 Ohm". Implementation of the II Term_Attn_Brd for the CTFE Cards in Run II ----------------------------------------------------------------------- For a Dual CTFE Channel Version the Dimensions Could Be: -------------------------------------------------------- The pitch between CTFE Channels is: 2.925" Dimensions of corners and CTFE pin #1's in inches. 0.000 +--------------------------------------+ 1.600 5.250 | | 5.250 | | | x x | | x x x x | | x x x x | | x 1 0.500 x x | CH #2 EM | 4.700 x x | | x x | | x x | | x x x x | CH #2 HD | x x x 1 | | x x | | x 1 0.500 1.500 | | 3.175 3.700 | | | | | | x x | | x x x x | | x x x x | | x 1 0.500 x x | CH #1 EM | 1.775 x x | | x x | | x x | | x x x x | CH #1 HD | x x x 1 | | x x | | x 1 0.500 1.500 | | 0.250 0.775 | | | 1.600 0,0 +--------------------------------------+ 0.000 This is looking through the Term-Attn Board as it would look plugged on to the CTFE. The pin "1" indicators are for the CTFE pin #1's. The unit cell for the Cal Trig crates is 0.700" inches, i.e. not 0.8". The Term-Attn-Brd would sit about 0.300" above the CTFE, i.e. 0.300" between the top surface of the CTFE and the bottom surface of the Term-Attn. The Term-Attn's components would go on its surface that faces the CTFE, i.e. its components would be between its pcb and the CTFE pcb. Now look from under the CTFE, throught the CTFE to see the component side of the Term-Attn-Brd. Recall that the Term-Attn-Brd will use normal rational pinout headers to plug into the CTFE's OpAmp and Term-Attn-Network sockets. 0.0, 1.600 5.250, 1.600 +-------------------------------------------------------------------------+ | | | xxxx xxxx xxxx xxxx | | | | 1xxx 1xxx 1xxx 1xxx | | | | 0.250, 1.775, 3.175, 4.700, | | 1.100 1.100 1.100 1.100 | | | | | | | | | | | | xxxxxxxx xxxxxxxx | | | | 1xxxxxxx 1xxxxxxx | | 0.850, 0.100 3.775, 0.100 | +-------------------------------------------------------------------------+ 0,0 5.250, 0.000 EM Ch#2 HD EM Ch#1 HD The above drawing is looking at the component surface of the Term-Attn-Brd Because the Term-Attn-Brd will use normal pinout headers to connect to the CTFE card we have to get the "what signal to what pin" correctly layed out. OpAmp Header Pinout Pin CTFE Num Function Term-Attn-Brd Function --- ----------------- --------------------------------------- 1 N.C. V- Power 2 - Input N.C. on the Term-Attn-Brd 3 + Input N.C. on the Term-Attn-Brd 4 V- Power N.C. on the Term-Attn-Brd 5 Gnd (after ECO) Gnd 6 OpAmp Output V+ Power 7 V+ Power Connection to the ADC Input Network 8 Gnd (after ECO) Gnd Term-Attn-Network Header Pinout Pin Num CTFE Function Term-Attn-Brd Function --- ------------------------ -------------------------------------- 1 Gnd Gnd 2 HD - Input to Network EM + Input 3 HD + Input to Network EM - Input 4 Gnd Gnd 5 Gnd Gnd 6 EM - Input to Network HD + Input 7 EM + Input to Network HD - Input 8 Gnd Gnd 9 EM + Output from Network N.C. on the Term-Attn-Brd 10 Gnd Gnd 11 Gnd Gnd 12 EM - Output from Network N.C. on the Term-Attn-Brd 13 HD + Output from Network N.C. on the Term-Attn-Brd 14 Gnd Gnd 15 Gnd Gnd 16 HD - Output from Network N.C. on the Term-Attn-Brd Term-Attn-Brd PCB Design Details -------------------- Use of Layers POWER_1 Vcc plane POWER_2 Vee plane POWER_3 GND plane DAM_1 Split in the Power plane DAM_2 Split in the Gnd and Power planes DENSITY_1 Trim Marks and board project label DENSITY-2 Substitute Silk Screen for Comp Side for Documentation Possible CTFE Power Issues: --------------------------- 1. The VA706 OpAmp that is being pulled out has a current draw of 7 typ 10 max mAmps. The EL4451C on the Term-Attn-Brd has a current draw of 15.5 typ 18 max mAmps. The DAC's take very little (1/2 mAmp). Generation of CBus Cycles: -------------------------- CBus Cycles are generated by TCC talking to an IRONICS Digital I/O card which is connected through a Paddle Board to a COMINT card. The byte wide registers on the IRONICS card that control the CBus Cycles are setup in the following way: IRONICS Ports COMINT Function ------- ------------- -------------------------------------------- 1 Port A (7:0) Mother Board Adrs (8:1) Ironics->Comint 2 Port B (15:8) Card Adrs (6:1), STRB, DIR Ironics->Comint 3 Port B (7:0) Function Adrs (8:1) Ironics->Comint 4 Port C (7:0) Write Data (8:1) Ironics->Comint 5 Port D (7:0) Read Data (8:1) Comint->Ironics So to perform a CBus write cycle, TCC does the following VME cycles to the Ironics Card: Setup the MBA Setup the CA with Strobe not asserted and Direction set to Write Setup the FA Setup the Write Data Hold CA and Direction while now asserting Strobe Return to Strobe not asserted while continuing to hold CA and Direstion So to generate a CBus write cycle it looks like TCC needs 6 VME cycles to the IRONICS Card. These VME cycles are about 2.5 usec each so it takes about 15 usec for TCC to complete a CBus write cycle. CBus Cycles to Shift Out Serial Data to DAC's --------------------------------------------- Doing the Writes to the Serial DAC's is a little different because we do not need to change the MBA or the CA or the FA. Once setup we just keep changing the serial data bit and the serial clock bit. It would look like this: Full 15 usec CBus Write Cycle during which we would setup the CS*'s to the DAC's Setup CBus data for: Serial Data "N" & Serial Clock NOT asserted. Hold CA and Direction while now asserting CBus Strobe Return to CBus Strobe not asserted continue to holding CA and Direstion Setup CBus data for: Serial Data "N" & Serial Clock Asserted. Hold CA and Direction while now asserting CBus Strobe Return to CBus Strobe not asserted continue to holding CA and Direstion Setup CBus data for: Serial Data "N+1" & Serial Clock NOT asserted. Hold CA and Direction while now asserting CBus Strobe Return to CBus Strobe not asserted continue to holding CA and Direstion Setup CBus data for: Serial Data "N+1" & Serial Clock Asserted. Hold CA and Direction while now asserting CBus Strobe Return to CBus Strobe not asserted continue to holding CA and Direstion Setup CBus data for: Serial Data "X" & Serial Clock NOT asserted. Hold CA and Direction while now asserting CBus Strobe Return to CBus Strobe not asserted continue to holding CA and Direstion Full 15 usec CBus Write Cycle during which we would clear the CS*'s to the DAC's So to shift out serial data it looks like it takes: 15 usec CS* setup + Number of Serial Bits x 15 usec + 7.5 usec to conclude serial data + 15 usec to clear the CS* This is: 37.5 usec + Number of Serial Bits x 15 usec If we setup the Term-Attn-Brd's with the 8 bit and 12 bit DAC's on sepparate serial strings then to load one CTFE card it takes: two passes of 4x16 bits of data plus four passes of 2x12 bits of data. This is 3.585 milsec to load 1 CTFE card or 1.147 sec to load the 320 CTFE's in the L1 Cal Trigger. This would all scale with 2.5 usec per VME cycle. If we setup all the DAC's on a sinle serial data chain then it takes four passes of 4x16 + 2x12 bits of data to load one CTFE card. This is 5.43 mil sec to load one CTFE card or 1.738 sec to load the whole L1 Cal Trig. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Everything below here is old development stuff ================================================ Variable Gain Blocks -------------------- AD835 limitations: +-1 Volt differential full scale input Large offset and drift over temperature marginally enough gain expensive $7.95 ea in 1k lot CLC522 limitations: Hard to understand what in the full scale input range is Looks great except that the single ended Vg input needs to swing -1V to +1V about $4.10 ea EL4451C limitations: No specification of settling time or pulse response characteristics: $3.15 ea at 1k lot Input Bias Current 9 typ 20 max uAmp Input offset voltage 7 typ 25 max mVolt So must keep input resistance down to 800 Ohms for Ibias x Risis <= V offset For Ibias x Risis x Gain <= 1/2% output swing then input resistance must be < 250 Ohm. Input Resistance 230 typ 100 min kOhms. So a 1 kOhm source is a 1% shift. Diff Input Range 1.8 min 2.0 typ Volts before "clipping" 1.3 type Volts before 0.2% non linearity So lets run with 1.5 Volts max Diff Input. Offset Voltage Drift 66 uVolt per Deg Cent typ So with a gain of 5 then it takes 24 Deg Cent to cause a 7.8 mVolt shift in output, i.e. a 1 LSB shift in the ADC Term-Attn-Brd Design Issues: ----------------------------- 2. How to do the layout. Would like the Term-Attn-Brd to be a right side up layout with standard pinout parts. So we must make up a special table of what is on what pin of the Input Connector and the OpAmp Connectors. 3. The male pin headers should have a seating plane about 0.100" above the Term-Attn-Brd. Try Samtec APO-308-G-H APO-316-G-H The seating height would be 70 mil 4. Possible DAC Parts: LTC1694 SMBus current source LTC1661 or LTC1663 DAC serial voltage out AD5312 MAX5250 MAX5158 Dual 10 bit Serial +5V supply Ext Ref $3.39 ea 1k up MAX5104 Dual 12 bit Serial +5V supply Ext Ref $3.75 ea 1k up MAX534 Quad 8 bit Serial +5V supply Ext Ref $2.80 ea 1k up MAX5250 Quad 10 bit Serial +5V supply Ext Ref $4.95 ea 1k up MAX525 Quad 12 bit Serial +5V supply Ext Ref $9.70 ea 1k up 5. Serial Data Connection of the 4x MAX5104 chips and 2x MAX534 chips will require only four lines. This will allow all 16 DAC's to be loaded up in two passes of 4x16 bits of data plus four passes of 2x12 bits of data. Assignment of the 4 control signals from the CTFE card could be the following: Data 2 pin 17 of U235 is the Data In to the first 2 DAC chip Data 3 pin 16 of U235 is the Serial Clock to the 6 DAC chips Data 4 pin 15 of U235 is the CS* to the 4x MAX5104 DAC chips Data 5 pin 14 of U235 is the CS* to the 2x MAX534 DAC chips Isolate these 4 digital input lines with 47 Ohm resistors or some thing like that to break the ground loops. Digital inputs are 1 uAmp max and 10 pFd max and need 3 Volts so must pull up. May also want to damp the serial clock signal.