Programming of the Analog Input Section of the Run II L1 Cal Trig --------------------------------------------------------------------- Original Rev. 8-JAN-2001 Current Rev. 5-SEPT-2001 Recall that a CTFE card services 4 Trigger Towers in Eta all at the same Phi. In the L1 Cal Trig Eta Phi coordinate system a CTFE card services for example eta's: 1:4, 17:20, -9:-12 The Pedestal Control DAC on the original CTFE cards (the DAC's controlled by the "Upper" Card Address with Function Addresses 0:7) are not used at all in the Run II setup. The following is the list of DAC's and ADC's used in the Run II setup of the CTFE cards. Gain Control DAC - this is a new DAC, 8 bits, serially controlled Zero Energy Response DAC - this is a new DAC, 12 bits, serially controlled Flash ADC - same as used in Run I, converts the Trigger Tower analog signal to 8 bit digital value. Can you see its output from the AM29525's ?? Block Diagram of the Analog Input to the Run II L1 Cal Trig ----------------------------------------------------------- Differential Receiver +---------+ |\ >--| Fixed |----| \ | Attn. | | >--. >--| x 0.37 |----| / | +---------+ |/ | | Diff Input | to L1 Cal Trig +----------+ +----------+ +--------+ from the BLS | | | | | Output | /-----+ | Variable | | Offset | | Stage | / Flash| | Gain |----| Summation|----| |----< ADC |--> | Cell | | | | x 1.75 | \ | +----------+ +----------+ +--------+ \-----+ | | +----------\ | | | Gain \ | | | Control >-------' | | DAC / | +----------/ | +------------\ | | Zero Energy \ | | Response >---' | DAC / +------------/ Interaction between the Gain and Zero Energy Response. There is likely to be a small interaction between the Gain and the Zero Energy Response of a channel. Changing the Zero Energy Response will not change the Gain but changing the Gain will make a small change in the Zero Energy Response. Swinging the Gain through it full range (gain of 0x through 2x) is likely to cause the Zero Energy Response coming out of the Flash ADC to move by typically 2 counts. As will be seen below, to compensate for this will require a move of about 26 counts in the Zero Energy Response DAC. This interaction is not a fixed known relationship. For some channels there may be zero interaction. For some other channels it could be positive and for others it could be negative. Controlling the new Serial Data DAC's -------------------------------------- On a given CTFE card all of the new Run II serial data DAC's are connected in one long series string. This series data string is controlled by a few spare bits in the CTFE's Board Control Status Register. The Board Control Status Register is at Function Address 80 decimal of the Upper Card Address used by the CTFE cards. There are 3 spare bits in this register that will be used to control the serial data DAC's. CTFE Board ------------ Board U235 CSR Pin Serial Data Term-Attn Board Bit Num DAC Function Pin Number ----- ---- --------------- --------------- 2 17 Chip Select * 1 3 16 Serial Data 3 4 15 Serial Clock 5 These three lines allow you shift serial data through a number of devices (each device has a Data_In and a Data_Out port) and then at some point, using the Chip Select * signal, you tell all the devices at once to absorb the data that is currently in their shift registers. So you start the loading process by asserting the Chip Select * signal that goes to all of the devices. On the devices this is a Voltage Low = asserted signal. Asserting this signal allows the devices to shift data through their shift registers. On these devices the Serial Data and Serial Clock signals are both active = Voltage High. You start with the Serial Clock line not asserted, put out the first data bit, the bit that goes the whole way to the end of the string, and then assert and then un-assert the Serial Clock line. You repeat this 88 times (decimal) to fill the 88 bits that are in the serial data devices that have been strung together on each CTFE card. The serial clock may run as fast as 10 MHz and these devices will keep up. You end the loading process by un-asserting the Chip Select * signal. This caused the information that is currently in a device's shift register to be loaded into that device and acted upon. Note that in one of these loads of 88 bits you only setup one of the two DAC's in a dual DAC device that controls the Zero Energy Response and setup only one of the four DAC's in a quad DAC device that controls Gain. Thus, starting from scratch, it requires 4 of these loads of 88 bits to setup all of the serial data DAC's on a given CTFE cards. This is a total of 16 DAC's (4 eta's x EM and HD x ZER and Gain). ZER is short hand for Zero Energy Response. Active Low Active Hi Inverters and all of that. Note that the DAC devices have a Chip Select signal that is active = Voltage Low while their Serial Data and Serial Clock signals are active = Voltage Hi. To add to the confusion there is an inverter between the register that TCC writes to and the actual DAC devices. This inverter with hysteresis is used to clean up the signals and bring them up to full CMOS levels before they go into the DAC's. So put this all together and what do you get: TCC writes a "0" to the bit #2 in the CTFE Board CSR causes the DAC device to see a Voltage Hi --> Chip Select is not active TCC writes a "1" to the bit #2 in the CTFE Board CSR causes the DAC device to see a Voltage Low --> Chip Select is active TCC writes a "0" to the bit #3 in the CTFE Board CSR causes the DAC device to see a Voltage Hi --> Serial Data = 1 TCC writes a "1" to the bit #3 in the CTFE Board CSR causes the DAC device to see a Voltage Low --> Serial Data = 0 TCC writes a "0" to the bit #4 in the CTFE Board CSR causes the DAC device to see a Voltage Hi --> Serial Clk = 1 = asserted. TCC writes a "1" to the bit #4 in the CTFE Board CSR causes the DAC device to see a Voltage Low --> Serial Clk = 0 = not-asserted. DAC's on a CTFE Card. The series string of serial data DAC's is setup as follows: ZER ZER Gain ZER ZER Gain DAC DAC DAC DAC DAC DAC Eta "N" --> Eta N+1 --> Eta N --> Eta N+2 --> Eta N+3 --> Eta N+2 EM & HD EM & HD & N+1 EM & HD EM & HD Eta N+3 TCC sends serial data into the left had side, Zero Energy Response DAC for Trig Towers Eta N and N+1, and it is shifted to the right. So in a load of 88 bits, the first thing that TCC sends out goes to the Gain DAC for Eta's N+2 and N+3. Detailed Description of the new Serial Data DAC's ------------------------------------------------- Gain Control DAC ---------------- One IC contains the 4 DAC's to provide gain control for both the EM and HD sections of 2 Trigger Towers. The 2 Trigger Towers that share this Quad 8 bit DAC are 2 adjacent Eta's for example: 1:2, 17:18, -11:-12. The IC used here is a Maxim MAX-534-BCEE. The documentation from Maxim refers to its 4 channels as "A", "B", "C", and "D". They are used in the following way: MAX-534 DAC Channel Used for ----------- -------------------------------- A EM of TT Eta "N" - (N is odd) B HD of TT Eta "N" C EM of TT Eta "N+1" D HD of TT Eta "N+1" The value that you load into one of these DAC's is in the range 0 to 255 decimal. This results in an output voltage in the range 0 to +2.500 Volts. This is offset by -250 mV to give a swing of -0.250 to +2.250 Volts which is applied to the "Variable Gain Cell" shown in the block diagram above. This controls the variable gain cell in the following way: 0 Volts (or negative Volts) --> a gain of 0 1 Volt --> a gain of 1 2 Volts --> a gain of 2 (i.e. it is just a multiplier, Volts = Gain) Being able to swing a little under 0 Volts and a little over 2.000 Volts guarantees that we have available the full range of gains 0 through 2 while still providing plenty of gain resolution in the vicinity of a gain of 1 where most of the channels will run. Trying to express the DAC Code vs Gain with algebra you have: Gain = / / Loaded DAC Code \ \ Gain = 1 | | --------------- x 2.500 Volts | - 0.250 Volts | x -------- \ \ 255 / / 1 Volt with the constraint that Gain is always 0 or positive. So some typical values of DAC_Code vs Gain are: DAC Resulting Code Gain ---------- ----------- <= 25.5 0.0 51.0 0.25 76.5 0.5 127.5 1.0 178.5 1.5 => 229.5 2.0 As described else where, part of the conversion from E to Et is accomplished by dividing the Eta range into 3 sections. Each of these sections has its own scale for Trigger Pickoff Volts to GeV of E. Based on this, and the desire to have the Et scale at the output of the Flash ADC be 1/4 GeV per count, you can calculate the approximate required gain vs TT Eta. This is: Est Req Est Req Est Req TT Eta Gain TT Eta Gain TT Eta Gain ------ ------- ------ ------- ------ ------- 1 1.54 9 1.53 15 1.49 2 1.48 10 1.26 16 1.22 3 1.37 11 1.05 17 0.99 4 1.24 12 0.87 18 0.77 5 1.08 13 0.70 19 0.57 6 0.93 14 0.57 20 0.39 7 0.76 8 0.66 Data is sent to the Max-534 quad DAC 12 bits at a time. Only one DAC is loaded at a time. There are 6 types of transfers from TCC that will be useful. D11 D10 D9 D8 D7 . . . D0 <-- 12 bit data from TCC, D11 comes out of TCC first 8 bit DAC Code \ --------------- | Function in the Max-534 A1 A0 C1 C0 D7 D6 ... D1 D0 / -- -- -- -- --------------- -------------------------------- 0 0 0 0 xxxx xxxx No Operation nothing changes 1 0 1 0 xxxx xxxx Force to "Default Mode" DOut update on falling edge of SCLK 0 0 1 1 8 bit DAC Code Load & Update DAC "A" 0 1 1 1 8 bit DAC Code Load & Update DAC "B" 1 0 1 1 8 bit DAC Code Load & Update DAC "C" 1 1 1 1 8 bit DAC Code Load & Update DAC "D" Because the serial data path for the Gain Control DAC's is in series with other serial DAC you might want to use the NOP instruction if you were changing just one of the other DAC's. The "Force Default Mode" instruction is needed only if control of the string of serial data DAC's were ever lost for some reason. Note that you would need to execute this 6 times - each time you would only be guaranteed of re-gaining control of the next DAC in the series string. Zero Energy Response DAC's -------------------------- The ZER DAC's are dual 12 bit IC's. One of these IC's controls the ZER of both the EM and HD section of a given Trigger Tower. The IC used here is a Maxim MAX-5104-CEE. The documentation from Maxim refers to its 2 channels as "A" and "B". They are used in the following way: MAX-5104 DAC Channel Used for ----------- ------------------- A HD of TT Eta "N" B EM of TT Eta "N" The value that you load into one of these DAC's is in the range 0 to 4095 decimal. This results in an output voltage in the range 0 to +2.500 Volts. This voltage is given a gain of about 0.56, inverted, offset, and given a final gain of about 1.75 before it reaches the input to the Flash ADC. It sounds crazy but all of this is done for good reasons. The result of this is that, with no signal coming from the BLS, the ZER DAC can swing the input signal to the Flash ADC through the range -1.225 to +1.225 Volts. Recall that the full scale input voltage range to the Flash ADC is -1 Volt to +1 Volt. Assuming that there is zero signal coming out of the BLS, the overall result is: Code Loaded Voltage Going into the ZER DAC into the Flash ADC Flash ADC Output ---------------- ------------------ ------------------ 4095 = $0fff -1.225 V $00 --> -2.00 GeV 3719 = $0e87 -1.000 V $00 --> -2.00 GeV 3706 = $0e7a -0.9922 V $01 --> -1.75 GeV 3614 = $0e1e -0.93725 V $08 --> 0.00 GeV 2054 = $07f9 -0.0039 V $7f --> 29.75 GeV 2041 = $0806 +0.0039 V $80 --> 30.00 GeV 389 = $0185 +0.9922 V $fe --> 61.50 GeV 376 = $0178 +1.000 V $ff --> 61.75 GeV 0 = $0000 +1.225 V $ff --> 61.75 GeV The increment is about 0.5983 mV per count to the ZER DAC. Thus it requires about a 13.109 count change to the ZER DAC to make a 1 count change in the Flash ADC output. The idea here is that we can swing a little under and a little over the full scale input range to the Flash ADC so we are guaranteed that we can explore its full range. With 13 bits of ZER DAC to 1 bit of Flash ADC we have plenty of resolution to accurately set the ZER of the Flash ADC. Data is sent to the Max-5104 dual DAC 16 bits at a time. Only one DAC is loaded at a time. There are 4 types of transfers from TCC that will be useful. D15 D14 D13 D12 ... D1 D0 <-- 16 bit data from TCC, D15 comes out of TCC first 12 bit DAC Code \ ---------------- | Function in the Max-534 A0 C1 C0 D11 D6 ... D1 D0 S0 / -- -- -- ---------------- -- ------------------------------- 0 0 0 000x xxxx xxxx 0 No Operation nothing changes 0 0 0 1000 xxxx xxxx 0 Force to "Default Mode" DOut update on falling edge of SCLK 0 1 0 12 bit DAC Code 0 Load & Update DAC "A" i.e. HD 1 1 0 12 bit DAC Code 0 Load & Update DAC "B" i.e. EM Because the serial data path for the ZER DAC's is in series with other serial DAC you might want to use the NOP instruction if you were changing just one of the other DAC's. The "Force Default Mode" instruction is needed only if control of the string of serial data DAC's was ever lost for some reason. Note that you would then need to execute this 6 times - each time you would only be guaranteed of re-gaining control of the next DAC in the series string. Possible Ideas for the Serial DAC Management Routines: ------------------------------------------------------ 1. Send out the "Force Default Mode" codes 6 times in a row to a given CTFE card. 2. Ask the operator for (or get from a data base) the 16 values that you want to load into the serial DAC's on a CTFE card. Use 4 loads of serial data to the string of DAC's to load all 16 of them. 3. Ask the operator for (or get from a data base) the "ID" of one DAC that you want to load and the value that you want to load into it. With just 1 load of serial data to the string of DAC's, and NOPing 5 of the 6 DAC IC's, load just the DAC that you want to. Flash ADC's ----------- Flash ADC input range full scale is -1.000 Volts to +1.000 Volts This is an 8 bit ADC, an increment is about 0.007843 Volts, the scale is 1 count = 0.25 GeV Et, with a Zero Energy Response code coming out of the Flash ADC of $08, so it looks like: Input Voltage Output Code GeV of Et ------------- ---------------------------------- ----------- -1.0000 V $00 "middle" of the $00 code -2.00 -0,9961 V boarder between codes $00 and $01 -0.9922 V $01 middle of the $01 code -1.75 -0.93725 V $08 middle of the $08 code 0.00 -0.0039 V $7f middle of the $7f code 29.75 0.0000 V boarder between codes $7f and $80 +0.0039 V $80 middle of the $80 code 30.00 +0.9922 V $fe middle of the $fe code 61.50 +0.9961 V boarder between codes $fe and $ff +1.0000 V $ff "middle" of the $ff code 61.75 ============================================================================ Below here is additional development information: Required Sin(eta) * Scale from BLS (e.g. 2 Volts = 175 GeV E) Gain Cell = --------------------------------------------------------- Gain Scale to the ( 2 Volts = ) * Input Attn * Output Gain Flash ADC ( 64 GeV Et ) i.e. 0.37 i.e. 1.75 The Molex Serial Data Connector has the following pin out: Board Molex Connector Wire U235 CSR Pin Number Color Function Pin Number BIT --------------- -------- ------------- ------------ ----- 1 Green Chip_Sel 17 2 2 Black GND 10 3 Yellow Serial_Data* 16 3 4 Black GND 10 5 Red Serial_Clock* 15 4 6 Black GND 10 The signal levels listed under "Function" indicate the signal levels at the output of U235 and on the cables connecting the CTFE to the Term-Attn_Brd's..