Distributor Cap Board Description ------------------------------------ Original: 28-APR-1999 Revised: 26-NOV-2001 Background ---------- For Run II, we need to use the Run I Distributor Cap (DC) cards. Certain changes will be required in the operation of these cards for Run II, including: - some "white wire" type ECO's - reprogramming some GAL's (recall that the GAL's on the DC are one-time programmable so we will need to purchase new replacements) - replacing the SPROM's which hold the ERPB FPGA programming This file describes these changes and other issues associated with using the Run I DC's in Run II. DC Hardware ----------- Unused Functionality -------------------- The DC had a considerable amount of functionality that was NOT used in Run I. Much of this functionality will again NOT be used in Run II. This unused functionality includes: - DC-to-DC Daisy-Chain connections, allowing use of only a single ERPB configuration SPROM - "MTG" Setup (vs. DIP-switch Setup) of DC Initiating Configuration of the FPGA's on the ERPB cards -------------------------------------------------------- This feature was used in Run I and will be used in Run II. The "standard" sequence of MTG signals to cause configuration is: MTG MTG MTG 9 8 7 --- --- --- Static quiesent value is: H H H # safest quiescent value 1st step to configure: H L L # then wait 3 usec. 2nd step to configure: L L L # then wait 3 usec. 3rd step to configure: H L L # then wait 3 usec. 4th step to configure: H L H # then wait 3 usec. 5th step to configure: L L H # then wait 3 usec. 6th step to configure: H L H # then wait 3 usec. Return to quiescent value: H H H # FPGA configuration has # started. It requires # 1 second to complete. I believe that this initiates FPGA configuration in the following way. MTG_8 and MTG_9 are used to generate a latch update clock to the "Main_MTG_Register" which is U12 a 74F574. To do this, MTG_8 must be low, and then on a low to high transition of MTG_9, and active update clock edge will go to the "Main_MTG_Register". MTG_9 should be left high. MTG_7 is the MSBit to U12 the "Main_MTG_Register". After passing through this register it becomes the "GLOB_CONF" signal. A change state of "GLOB_CONF" will cause the FPGA Configuration process to start. What is the safest quiescent value for MTG_(9:7) is all High. MTG_9 should be stored high. It will require a noise glitch of greater than 1 usec for this signal to make any difference in the Setup GAL 1. MTG_8 being High blocks any change that the Setup GAL 1 will generate and update clock to the "Main_MTG_Register". MTG_7 stored High means that even if the "Main_MTG_Register" did receive an update clock, nothing would happen because just the same data would appear at MTG_7 and thus on the "GLOB_CONF" signal so no stimulus would exist to cause configuration to start. The safest one of these signals to use for something else is MTG_8. Even if it is low, it is still very hard to generate an update clock to the "Main MTG Register" and even if you do, you will just clock in the same MTG_7 value, and nothing will happen. Note that MTG_8 on the DC also becomes: DIAG_DATA, DIAG_D0, DIAB, and then in the top ERPB this is: DIAA, DIAI, and finally DIAG_0. This stops at the top ERPB because the current ERPB designs does not pass this signal. In all FPGA's past the first one on the top ERPB this signal is just pulled high by a resistor. So for slow changes, (searching in the Lookback range) it should be safe to move MTG_8. Modification to the DC Board for Run II --------------------------------------- Receiving the XMIT_Trig Signal In the Run II setup the DC Board will will receive the XMIT Trig signal on its MTG-X input signal instead of on MTG-6 as it was originally setup to do. To accomplish this modification of the DC card do the following: Disconnect just the Transmit Logic Xmit_Trig input from MTG_6. Leave all other DC card connections to MTG_6 just as they are in etch. What we need to do is to disconnect GAL-4 pin 2 from MTG_6. On the component side of the DC card cut the 1 cm long trace leading away from U12 pin 8 to a via. Connect the Transmit Logic Xmit_Trig input to a TTL version of the MTG_X signal. Run a wire from the above via to U4 pin 1. Re-Work of the GAL2 the DC Selection PAL The Run I DC Selection GAL has not changed in function but it does nothing. The Xmit_Clk passes through it and there is the normal concern about what will hapen to this signal going through a PAL as it ramps up to 20 MHz. This PAL can be replaced by a jumper header. All signals should be happier and they are all still buffered before going off card. Run II DC Selection PAL Wire List Pin # 7 to Pin # 18 ! This takes LOC_XCLK to INU_XCLK Pin # 8 to Pin # 17 ! This takes LOC_PROG to INU_PROG Pin # 9 to Pin # 16 ! This takes LOC_CCLK to INU_CCLK Pin # 10 to Pin # 15 ! This takes LOC_DIN to INU_DIN Pin # 12 to Pin # 22 ! This takes GND to OUT_XCLK and to Pin # 21 ! and to OUT_PROG and to Pin # 20 ! and to OUT_CCLK and to Pin # 19 ! and to OUT_DIN =|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|= =|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|= More Understanding of the Distributor Cap ------------------------------------------- Original Section Rev. 18-JUNE-2003 Original Section Rev. 17-JULY-2003 Setup Switch Issues ------------------- The setting of the DC switches used in Run I are the following. This is in the log book for 28,29,30-APR-1999 Setup ID/Mode Eta Switch Switch Rack Coverage 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ---- -------- ---------------- ---------------- M103 +1...+4 d d d d d d d d d d d d d d d d M104 -1...-4 d d d d d d d U d d d U d d d d M105 +5...+8 d d d d d d d d d d U d d d d d M106 -5...-8 d d d d d d d U d d U U d d d d d --> the key is down --> the circuit is closed --> signal is low U --> the key is up --> the circuit if open --> signal is asserted The setting of the DC switches that we should us in Run II is the following: Setup ID/Mode Eta Switch Switch Racks Coverage 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -------------- -------- ---------------- ---------------- M103,5,7,9,11 positive d d d d d d d d U d d d d d d d M104,6,8,10,12 negative d d d d d d d U U d d d d d d d d --> the key is down --> the circuit is closed --> signal is low U --> the key is up --> the circuit if open --> signal is asserted ID/Mode Switch Keys 1:4 of the ID/Mode switch are signals DIST_N_3 through DIST_N_0 (yes in that order). These are the DC card ID switches. We do not ever want signals MTG_3 : MTG_0 to match this DC card ID because if there is a match then we may write to one of the MTG Alternate Registers. Setting these 4 keys as shown should mean that we never have a match. Key #1 DIST_N_3 Up --> DIST_N_3 is asserted Key #2 DIST_N_2 Down --> DIST_N_2 is negated Key #3 DIST_N_1 Down --> DIST_N_1 is negated Key #4 DIST_N_0 Down --> DIST_N_0 is negated Note that if we change the ERPB Lookback value then we need to re-thing what safe value to use for the DC card ID. Keys 5:7 of the ID/Mode switch are not used. Set them down, not asserted. Key #8 of the ID/Mode switch controls the state of the MTG_SETUP signal. This signal must never be asserted so this key must be down. Summary: Key #1 is Up Keys #2:#8 are Down Setup Switch Note: Setup Switch Key #1 controls the signal Setup_7 ... ... Setup Switch Key #8 controls the signal Setup_0 Key #1 controls the USE_LOC_C signal, i.e. when this signal is asserted --> use the local DC card as the source of ERPB LCA Configuration. With the jumper header installed at Selection GAL this does not have any effect. For labeling to fit the way the DC operates with the Selection GAL jumper this key should be UP. Key #2 controls the USE_MTG_C signal, i.e. when this signal is asserted --> use the MTG as the source of ERPB LCA Configuration. This key must be down. Key #3 controls the USE_ROM_1 signal, i.e. when this signal is asserted --> use ROM 1 instead of ROM 0 as the source of ERPB LCA Configuration. This must be down because we use ROM 0. Key #4 controls the USE_LOC_X signal, i.e. when this signal is asserted --> use the local Xmit Clock. With the jumper header installed at Selection GAL this does not have any effect. For labeling to fit the way the DC operates with the Selection GAL jumper this key should be UP. Key #5 controls the X_DISABLE, i.e. when this signal is asserted --> disable the DC from starting a readout sequence, i.e. the Xmit_Trig signal will not cause a readout sequence to start. The key must be down. Key #6 controls the F_DISABLE, i.e. in theory when this signal is asserted it sould disable the Fault Shift register. With the current Transmit GAL this signal does nothing so this key has not effect. For labeling to fit the way the DC operates with the current Transmit GAL this key should be UP. Key #7 controls the GP_1 signal. This signal is not used. Put key down. Key #8 controls the GP_0 signal which becomes the DST_2 signal on the parallel cable to the ERPB cards. On the ERPB this signal controls the positive eta vs negative eta readout. At positive eta this key must be down. At negative eta the key must be up. Summary: Keys 8:1 Although some keys should be up to make labeling match the function it is OK to operate the DC will all keys down except for key 8 which needs to be set to match the eta sign. Writting to the MTG Registers ----------------------------- The MTG can write to either: the MTG Main Register or to the MTG Alt 0 Reg or to the MTG Alt 1 Reg. You write to the MTG Main Reg by having MTG_8 Low and using MTG_9 as the register write clock. With MTG_8 Low you always write to the MTG Main Reg. However, if MTG_8 is asserted then you could end up writing to either the MTG Alt 0 or MTG Alt 1 register. Which of these two alternate registers you write to depends on whether or not the ALT_REG bit is set in the MTG Main Register. ALT_REG is controled by the state of MTG_4 when the MTG Main Register is written. To actually write to one of the alternate registers you also need to have either: MTG_3:MTG_0 must all be high the last time that the MTG Main Register was written to or MTG_3:MTG_0 must match DIST_N_3:DIST_N_0 the last time that the MTG Main Register was written to Because MTG_8 is used as a Lookback control line that is set asserted during normal operation we need to verify that we never (even accidentally) satisfy either of the conditions listed above for writting to one of the alternate MTG registers. The main concern is an accidental write to MTG Alt 1 which could cause a ERPB LCA re-configuration. Look at what MTG_3 through MTG_0 are used for and their state during normal operation. Is Which Is MTG Normal Compared Controlled Signal Is Used For State To By ------ ----------------- ------ -------- ---------- MTG_0 ERPB_Input_Clock Osc. DIST_N_0 Key #4 MTG_1 ERPB_EM/Total_Bar Osc. DIST_N_1 Key #3 MTG_2 ERPB_Lookback_0 either DIST_N_2 Key #2 MTG_3 ERPB_Lookback_1 Low DIST_N_3 Key #1 The normal state of MTG_3 is Low so that blocks the first of the two conditions listed above. By having DIST_N_3 asserted, i.e. Key #1 UP, you block the second of the conditions listed above. GAL Issues ---------- Setup GAL - GAL 1 - This GAL is more or less OK -------------------------------------------------- This part holds the clock line to the MTG Main Register HI most of the time. To get this clock line to go Low you need: MTG_8 to be low and you need MTG_9 to make a Low to HI transistion. MTG_9 must have been held Low for > 1 usec and must then be held HI for > 1 sec. Together these conditions will cause the MTG Main Reg clock line to go low for 1 usec. New data will be latched into the MTG Main Reg on the rising edge of its clock. Moving MTG_9 Low and keeping it Low for more than 1 usec causes the Xmit_Disable one-shot to fire for about 100 msec. This is a bit strange because it is the positive edge of MTG_9 that causes the MTG Main Register write. In addition it takes about 195 msec to Comfigure the LCA so this 100 msec XMit_Disable does not cover the full Configuration time anyway. Triggering the XMit_Disable and the MTG Main Register write could all be given more protection. Note that the TCC I/O cycles that change the MTG lines are currently spaced 10 msec. If this part is worked on we should just lock low the Alt_Reg_0_Clk and Alt_Reg_1_Clk lines. I wish that the alternate MTG registers would just go away. Selection GAL - GAL 2 ---------------------- This GAL was replaced by a jumper header at the beginning of Run IIA. Currently this addresses all issues with this part. Configuration GAL - GAL 3 - This GAL has problems ---------------------------------------------------- Currently this part thinks that it should start a Configuration process if it see *any* change on either Rack_Config or Global_Config. This part should stop looking at Rack_Config signal. This part should require Global_Config to go Low and stay Low for > 2 usec before it initiates the Configuration process. Currently this part thinks that it can use either local or MTG Configuration information. We do not need/want this. This part should stop looking at the Use_MTG_C signal and get rid of all the multiplexers and use only local data. Currently this part thinks that it can use either SCP1 or SCP2 data for Configuration. We do not need/want this. This part should stop looking at the Use_ROM_1_C signal and get rid of the multiplexers for SCP1 vs SCP2. You can make the original Configuration GAL a little safer to live with by pulling its Rack_Config pin, i.e. pin #11, out of the socket and connecting it to pin #12, i.e. GND. Transmit GAL - GAL 4 - This GAL has problems ------------------------------------------------ The big problem is the way that the original Transmit GAL generates the strobe signal that goes along with the data to the CRC (now Spark) card. The problems are: You can not properly adjust the timing of the strobe signal. The strobe for the first word of data in the event is short. There is an additional runt strobe pulse after the end of the data. We need to get rid of the Xmit_Disable stuff. That function does not really work and all that it can do is cause trouble In addition to these serious problems there are just too many options hanging on this part. Correct implementation issues include: have access to only Xmit_Clk and need Xmit_Clk* keep the Strobe to the CRC ahead of the data (22V10 vs ACT541) This needs to be rock solid and clean is we want to clean up the Spark and if we want to run this faster. Typical timing of some of the critical path parts. 74 ACT 541 Data in to Output 6 nsec 74 AC 574 Clock to Output 6 nsec GAL22V10B-7LP Input or I/O to combinatorial output 7.5 nsec Clock to output 5 nsec 100324 Data in to Output 2 to 3 nsec 100325 Data in to Output 1 to 4 nsec Fault Shift Register -------------------- Must insure that the outputs of the Fault Shift Register do not become enabled. That is U30 U31 U32 U33 all 74ACT299's must have their tri-state outputs remain disabled. Their G2* output enable bar pins must remain HI to keep their outputs disabled. This signal is SQ_FSR0_OEb and SQ_FSR1_OEb which comes from the 7C291 PROM at U23 which is not installed. The only reason that this currently works is because the floating inputs to U24 tend to drift HI. Need to install a header into U23 to pull all the PROM output lines HI. U23 is a 24 pin socket that has Vcc on pins: 18, 19, and 24. The PROM output pins that need to be pulled HI are: 9, 10, 11, 13, 14, 15, 16, and 17. State of the MTG_* lines at the end of Init_Post_Auxi_L1CT.rio --------------------------------------------------------------- Want MTG_7 left HI, i.e. the way that it was last written into the MTG Main Register. MTG_7 is used only by the Configuration Control logic so we can leave it in either state. Currently (June 2003) HI is the state of MTG_7 at the end of Init_Post_Auxi_Init.rio. Want MTG_8 left HI, i.e. so that the MTG Main Register is not selected. MTG_8 is shared by the Configuration Control Logic and the LookBack control. Luckily the LookBack control also wants MTG_8 left HI. Currently (June 2003) HI is the state of MTG_8 at the end of Init_Post_Auxi_Init.rio. Want MTG_9 must be left HI. Currently (June 2003) HI is the state of MTG_9 at the end of Init_Post_Auxi_Init.rio. If MTG_9 flaps around it could trigger Xmit_Disable. Other Concerns / Ideas about the Distributor Cap Circuit Board -------------------------------------------------------------- The DC has a number of 100325 receivers, so of which have floating inputs. For the 100325 this is OK, it has 50 k Ohm pull downs on its inputs. U18B, when triggered by its "A" input, is what actually starts the configuration process. U18B's "A" input is driven only by a Configuration GAL output through a 10k Ohm resistor, i.e. no solid drive. The "A" input is also connected, via a long trace, to a pushbutton, SW3. This trace runs for a long distance between the SPX_IN trace from U40 P3 to Transmit GAL pin 5 and the SETUP_7 trace from U8 P12 to the Selection GAL pin 13. Both of these traces are (should be) static and will act to shield the "A" input. Thus it is probably OK and we can hope that this "A" input does not pickup noise. It would be nice to clamp the "A" input to Gnd with a capacitor right at the U18B package but this would change the fall time of the "A" input signal and may cause U18B some trouble. This whole thing could be cleaned up. It would be nice to setup the Red LED to show when the LCA Configuration process takes place. Could drive this from an unused output of the Configuration GAL is that part is ever reworked. Could put an extra safety on the Configuration logic and the Transmit logic if these parts are ever reworked, i.e. a real exclusive mode bit. At any given time you are either: Enabled to be triggered to perform Xmit readout or else Enabled to be triggered to perform LCA Configuration. Dump all the Xmit_Disable oneshot junk. Use a currently unused output on the MTG Main Reg (e.g. MTG 5 or 6) as this mode bit. PROM's Currently in Use (June 2003) ------------------------------------ See the Log Book entries for 7:9-NOV-01 and 27:30-NOV-01 for a description of the U26 PROM currently in use in the DC and for a description of the current LCA Configuration Serial PROM. Currently (June 2003) U26 --------------------------- From the U26.now S9 record file S1130000 FE EF EF EF E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 4D S1130010 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 6C S1130020 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 5C S1130030 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 4C S1130040 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 3C S1130050 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 2C S1130060 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 1C S1130070 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 E7 0C S1130080 E7 E7 E7 E7 FE FE FE FE FE FE FE FE FE FE FE FE E8 S1130090 FE FE FE FE FE FE FE FE FE FE FE FE FE FE FE FE 7C S11300A0 FE FE FE FE FE FE FE FE FE FE FE FE FE FE FE FE 6C The correct description of this is the following. Note that there are mistakes in the log file description. D D D D D D D D 7 6 5 4 3 2 1 0 - - - - - - - - Adrs 0 is $FE 1 1 1 1 1 1 1 0 Adrs 1,2,3 $EF 1 1 1 0 1 1 1 1 Adrs 4:$83 $E7 1 1 1 0 0 1 1 1 Adrs $84:$FF $FE 1 1 1 1 1 1 1 0 D0 is the SQ_DDC0 signal PROM Adrs $0 is Low PROM Adrs $1:$83 are HI PROM Adrs $84:$ff are Low This is the "go" signal to the first ERPB down the cable. D2 is the SQ_ERPB_OE signal which is always HI This is the "output enable" signal to the first ERPB down the cable. D3 is the SQ_Clock_MASK signal PROM Adrs $0:$3 are HI PROM Adrs $4:$83 are Low PROM Adrs $84:$ff are HI This is the Low active enable to make the Strobe signal to the Spark. D4 is the SQ_FBACK0 signal PROM Adrs $0 is HI PROM Adrs $1:$83 are Low PROM Adrs $84:$ff are HI This is the Low active signal that enables the Transmit Sequencer PROM Address Counter to continue incrementing. U26 PROM note added on 26-SEPT-2003 ------------------------------------ The above description of the contents of U26 reflect what has been in use since the beginning of Run IIA. This also works fine with the Sept-2003 version of the Distributor Cap and its new Configure and Trans-Seq PAL's. But if we ever do need to change the contents of U26 here are some things to keep in mind. SQ_FBack_0 This could stay Low until 135 or 140 i.e. keep the Trans-Seq incrementing until 5 counts or so after the transfer has finished. This just makes things cleaner because it de-couples the end of the transfer from the stopping of the sequencer. This will not add any dead time because the VRBC-VRB is still doing stuff anyway. SQ_Clk_Mask No Change DDCB0 "Go" This could return Low sooner - 3 counts sooner I think. This would just start the tear down of the ERPB "Go" signals immediately after the last transfer - instead of waiting a couple of extra counts. Recall that the REOB from the LCA is delayed by 2 Xmit-Clk's so this let's you start the tear down sooner. The only advantages are that it is a bit cleaner and it does not leave the last ERPB with no inputs to its 74AC574 for as long. Note about the LCA_Program* Signal 7-JULY-2003 ---------------------------------- The LCA_Program* signal comes from the Configuration PAL on the Distributor Cap and goes to all the ERPB cards. LCA_Program* is carried to the ERPB cards on the Parallel Cable as signal DST_4. On the ERPB cards this signal is connected to the Program* pin, pin 55, on all the 4002A LCA's. A Low on the LCA_Program* signal is what tells the LCA's that they need to re-Configure. If pin 55 is Low for > 300 nsec then the LCA is guaranteed to understand that it needs to re-Configure. I do not know how short this signal can be, i.e. how sensitive is the LCA to a short glitch on its Program* pin ? Because the LCA may be sensitive to short glitch on its Program pin it is interesting to know what is on the Parallel Cable next to DST_4. DST_3 is currently not used in the design. DST_3 is driven by the SQ_Fault_Clk signal which comes from PROM U23 which is now a pull up header. So DST_3 should be very quiet. DST_5 is the LCA_CClk signal. This clock only runs during Configuration. So normally DST_5 should be very quiet. If the LCA Program pin is sensitive to short glitches then it would be nice to have local protection against accidental re-Configuration right on the ERPB instead of having all the protection up on the Distributor Cap. =.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.= .=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=. =.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.= September 2003 Version of the Distributor Cap ------------------------------------------------- Original Section Rev. 17-JULY-2003 Original Section Rev. 18-JULY-2003 The intent of this version is just to fix the things that absolutely must be fixed. We will not fix the other 10**9 things that it would be nice to clean up. These 4 things that will be fixed are: 1. Protect agains accidental re-Configuring of the ERPB LCA's. 2. Straighten out the data Strobe generation. 3. Implement modes of operation: Enb_Trans is asserted --> may send out data may not Configure Enb-Trans is not asserted --> may not send out data may Configure Enb_Confg is asserted --> may not send out data may Configure Enb-Confg is not asserted --> may send out data may not Configure 4. Pull off the stuff that is not in use - that could cause trouble and that is easy to get off. This September 2003 version of the Distributor Cap will require new version of the Configuration PAL (GAL3) and of the Sequencer PAL (GAL4). It may also require a small change in the Sequencer PROM U26. Mode Enable Signals ------------------- There are separate Enb_Trans and Enb_Confg signals. The signal MTG_2 which is latched in the MTG Main Register and becomes the signal DIST_S_2 is routed to the Enb_Trans pins on the new Sequencer and Configuration PAL's. The signal MTG_3 which is latched in the MTG Main Register and becomes the signal DIST_S_3 is routed to the Enb_Confg pins on the new Sequencer and Configuration PAL's. The source of these enable signals is the pad array for the unused U9. Board Work to implement the September 2003 Version of DC Work at IC U9 ------------- Pull off unused IC U9 and reflow the solder on its pads. GND the A=B output from U9 i.e. jump U9 pin 6 to U9 pin 8 U9 pin 14 which receives DIST_S_2 is the source of Enb_Trans U9 pin 1 which receives DIST_S_3 is the source of Enb_Confg Work at IC U10 -------------- Pull off unused IC U10 and reflow the solder on its pads. Work at IC U11 -------------- Pull off unused IC U11 and reflow the solder on its pads. GND the unused RACK_CONF signal from U11 i.e. jump U11 pin 12 to U11 pin 10 Connect Enb_Trans to MTG_DIN Note that MTG_DIN runs in trace to the Configuration PAL GAL3 pins 9 where it was called MTG_DIN and will now be called and used for Enb_Trans i.e. connect DIST_2 = Enb_Trans to MTG_DIN. junper U9 pin 14 to U11 pin 14 Connect Enb_Confg to MTG_CCLK Note that MTG_CCLK runs in trace to the Configuration PAL GAL3 pin 10 where it was called MTG_CCLK and will now be called and used for Enb_Confg i.e. connect DIST_3 = Enb_Confg to MTG_CCLK. junper U9 pin 1 to U11 pin 13 Work at U7 ---------- Pull off unused IC U7 and reflow the solder on its pads. Connect Setup_0 to its DIP control i.e. jump U7 pin 4 to U7 pin 2 Connect Setup_1 to its DIP control i.e. jump U7 pin 7 to U7 pin 5 Connect Enb_Trans to Setup_2 Note that Setup_2 runs in trace to the Sequencer PAL GAL4 pins 7 & 8 where it was called F_DISABLE and will not be called and used for Enb_Trans i.e. connect DIST_2 = Enb_Trans to Setup_2. junper U9 pin 14 to U7 pin 9 Connect Enb_Confg to Setup_3 Note that Setup_3 runs in trace to the Sequencer PAL GAL4 pin 9 where it was called X_DISABLE and will now be called and used for Enb_Confg i.e. connect DIST_3 = Enb_Confg to Setup_3. junper U9 pin 1 to U7 pin 12 Work at U8 ---------- Pull off unused IC U8 and reflow the solder on its pads. Connect Setup_4 to its DIP control i.e. jump U7 pin 4 to U7 pin 2 Connect Setup_5 to its DIP control i.e. jump U7 pin 7 to U7 pin 5 Connect Setup_6 to its DIP control i.e. jump U7 pin 9 to U7 pin 11 Connect Setup_7 to its DIP control i.e. jump U7 pin 12 to U7 pin 14 Work at U24 ----------- Pull off unused IC U24 and reflow the solder on its pads. Tie High the SQ_FAULT_CLK and SQ_FAULT_TOK signals. Do this by tying together U24 pins 18, 19, and 20. Add this www on the top side of the circuit board. Work at SCP2 ------------ On the bottom of the circuit board use a www to tie together pins: 1, 4, 5, 6. This ties to Gnd the unused ROM_Data_0 and ROM_CEO_0 signals from SCP2. Work at U30, U31, U32, U33, U35 ------------------------------- Pull off unused IC's U30, U31, U32, U33, U35 and reflow the solder on their pads. Work at U14 and U15 ------------------- Pull off unused IC's U14 and U15 and reflow the solder on their pads. Removed the socketed resistors RT1 and RL3. Wire Wrap Wire Work ------------------- Do not disturbe the white wire associated with the Run II Xmit_Trig modification. Disconnect GAL-4 pin 2 from MTG_6. On the component side of the DC card cut the 1 cm long trace leading away from U12 pin 8 to a via. Connect the Transmit Logic Xmit_Trig input to a TTL version of the MTG_X signal. Run a white wire from the above via to U4 pin 1. Remove the 2 wires and cut trace from the Run I data Strobe modification. Remove the black wire GAL4 pin 15 to U39 pin 21. Remove the black wire GAL4 pin 14 to Header H2 pin 2. Re-Connect the trace U39 pin 21 to Header H2 Connect LED_2 so that it shows when Configuration takes place. Run a www from the pad for R2 that is nearest CD32 to Spare20 S1 pin 3. Note that R2 is not installed. Install a 470 Ohm resistor from Spare20 S1 pin 3 to Spare20 S1 pin 8. Run a www from Spare20 S1 pin 8 to U18A pin 4. U18A will fire for as long as the Configuration Clock is running. Both www's are on top of the pcb. Clean up the INU_XCLK distribution. This currently runs all over the place and is the highest speed clock in the system. Cut and remove the trace from U17 pin 14. Cut and remove the trace from U39 pin 23. Cut and remove the trace from U41 pin 17. Install a direct clean www: U39 pin 23 - U17 pin 14 - U41 pin 17. Run this www on top of the PCB under the crystal oscillator sockets. Remove the separate Configuration Clock Domain. Remove the 8 MHz crystal oscillator from its socket X1. Run a www from U17 pin 13 to U16 pin 2. This will give us a 5 MHz bases for the Configuration Clock. This can be slowed down further if needed when Xmit_Clk speeds up. =.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.= .=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=. =.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.= Distributor Cap Parts that One Could/Should Remove --------------------------------------------------------- Original Section Rev. 17-JULY-2003 Original Section Rev. 17-JULY-2003 Fault Shift Register 1. Remove the unused Fault Shift Registers: U30, U31, U32, U33 74ACT299 No side effects. 2. Remove signal delay to Fault Shift Registers: U35 74HCT157 No side effects. 3. Remove Fault Shift Register Sequencer PROM Latch: U27 74F574 If Fault Shift Register is removed then the only side effect is that you need to tie U27 pins 18 and 19 either High or Low to give the unused signals SQ_Fault_Clk and SQ_Fault_TOK defined logic levels. 4. Remove the Fault Shift Register Sequencer PROM: U23 CY7C291 No side effects if the rest of the Fault Shift Register stuff is removed. subtotal remove 7 IC's Setup Logic 1. Remove card ID comparator: U9 74HCT85 No side effects. 2. Remove the Transmit Disable One Shot: U13 74HCT123 Tie pin 13 either High or Low to give the unused XDIS_PULSE signal a defined logic level. 3. Remove the Manual / MTG Setup Multiplexers: U7 and U8 74HCT157 Install jumpers to tie some of these mux outputs to defined logic levels. 4. Remove MTG Alternate Register #0: U10 74F574 No side effect of the Setup Multiplexers have been removed. subtotal remove 5 IC's Configuration Logic 1. Remove the DC to DC Receiver: U14 100325 No side effects. 2. Remove the DC to DC Driver: U15 100324 No side effects. 3. Remove DC to DC resistor packs: RT1 and RL3 No side effects. 4. Remove Selector PAL: GAL2 22V10 No side effect if the already developed jumper header is installed. 5. Remove Configuration crystal oscillator: X1 8 MHz 14 pin DIP Use 5 MHz tap on Transmit Oscillator for this function. To implement this connection, tie U17 pin 13 to U16 pin 2. 6. Remove unused Serial Configuration PROM: SCP2 XC1736 No side effect. 7. Connectors JD1 and JD2 could be removed but it is not worth the risk of damage to the circuit board. subtotal remove 5 IC's Daisy Chain Connector - no change Transmit Connector 1. Remove the auxiliary signal Receiver: U40 100325 Must tie U40 pin 3 the unused signal SPX_IN to a default logic level either High or Low. Must tie U40 pin 8 XMIT_CLK signal to a source of this clock which is U17 pin 14. (All the Xmit_Clk traces to the Selector PAL should be removed.) 2. Remove the auxiliary signal Driver: U39 100324 Of the 3 signals handled by U39 only the Strobe signal is still needed. This can be driven by a unused section of U38. Make a direct connection of the Strobe signal to U38 and remove the unused traces to U39. 3. Remove the now unused RT2 and RL7. subtotal remove 2 IC's MTG Connector - no change Parallel Connector 1. DST_0 : DST_2 Driver: U41 100324 is almost redundent. The signal DST_0 (XMIT_CLK) could be driven by an unused section of U42. The source of this signal sould be direct from U17 pin 14 and skip (remove) all the traces of Xmit_Clk to the Selector PAL. The signal DST_1 (SQ_DST_1) is not used - it just needs to be tied to default Differential ECL logic level. This is accomplished by the receiver for DST_1 on the ERPB which is a 100325 which has 50k Ohm pull downs. The signal DST_2 (Neg_Eta from Setup_0) could be driven by an unused section of U42. DST_2 is a static signal so its source wiring is not critical. 2. RL8 is not needed. subtotal remove 1 IC's Total removed IC's = 20. =|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|= =|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|=|= Everything below here is old material left over from the original version of this file. Much of it is NOT correct. 12-NOV-2001 Timing Signals -------------- In Run I, each DC received 10 "MTG" Timing signals on a 34-conductor cable, laid out in the following fashion: Cable pins Signal Name DC Use ----- ------------------- ------ 1,2 (unused) 3,4 MTG(0) 5,6 (unused) 7,8 MTG(1) 9,10 MTG(2) 11,12 MTG(3) 13,14 MTG(4) 15,16 (unused) 17,18 MTG(5) 19,20 (unused) 21,22 MTG(6) 23,24 MTG(7) DC_Config_FPGA's 25,26 MTG(8) DC_Altreg_Select 27,28 MTG(9) DC_Register_Clock 29,30 (MTG(x), unrouted on DC) 31,32 (MTG(y), unrouted on DC) 33,34 (unused) See the file MSUTRGROOT_II:[CAL_TRIG]ERPB_FPGA.TXT for details of how these signals are used on the ERPB. On the DC, only MTG(9:7) are used, for initiating the ERPB FPGA configuration (the others could be used for "MTG Setup" of the DC, a feature we do not use). The protocol for initiating this configuration is described in the ERPB and DC Project Record book (by Steve Pier), but is essentially as follows: Take MTG(7) and MTG(8) low, wait 3 us. Take MTG(9) low, wait 3 us. Take MTG(9) high, wait 3 us (clocks 0 into FPGA_Config trigger reg). Take MTG(7) high, wait 3 us. Take MTG(9) low, wait 3 us. Take MTG(9) high, wait 3 us (clocks 1 into FPGA_Config trigger reg). This is exactly the protocol used in Run I. Note that MTG(8) remains low during this entire protocol, perhaps we don't need to actually drive it but can hard-wire it low on the DC. Note that the configuration data for all ERPB's serviced by each DC comes from the "SCP1" SPROM on that DC. These SPROMs must be replaced for Run II with one containing the Run II ERPB FPGA configuration. Crystal Oscillators ------------------- For Run I, the ERPB contained two crystal oscillators: - 8 MHz, used for FPGA configuration (and other things) - 20 MHz, used for ERPB data transfer (and other things) in addition to the 10 "MTG"-generated Timing Signals. It is not obvious how these oscillator signals are used. Let's look at them in detail. First, 8 MHz: On the DC "LCA Configuration Logic" (DCONF.sch) sheet: X1 generates 8 MHz output. U16 divides to make CLK_250NS, CLK_500NS, CLK_1US, CLK_2US. GAL3 uses CLK_2US to generate ROM_CLK and LOC_CCLK. GAL2 uses select either LOC_CCLK (entering on pin 9) or REM_CCLK (from the DC-to-DC Daisy Chain, entering on pin 5) as INU_CCLK (exiting on pin 16). We will be setting up the DC to use LOC_CCLK. CLK_1US goes from the "LCA Configuration Logic" (DCONF.sch) sheet to the "Setup Logic" (DSET.sch) sheet. On the "Setup Logic" (DSET.sch) sheet: CLK_1US is used to clock GAL1, which in turn clocks the 3 "MTG" Registers. INU_CCLK goes from the "LCA Configuration Logic" (DCONF.sch) sheet to the "Parallel Connector" (DPARA.sch) sheet. On the "Parallel Connector" (DPARA.sch) sheet: U42 converts INU_CCLK to differential ECL (entering on pin 23 as DST_5, exiting on pins 4 and 5. The differential ECL version is pulled down in RL9, and sent to the Parallel Connector (JP1) as DST(5) on pins 11 and 12. This signal is received on the >>ERPB<< and is used as CCLK for FPGA configuration. This processing is essentially comprehensible and there is no reaon to change it for Run II. Then, 20 MHz: On the DC "LCA Configuration Logic" (DCONF.sch) sheet: X2 generates 20 MHz output. U17 divides by 2 to make LOC_XCLK (exiting on pin 14). GAL2 selects either LOC_XCLK (entering on pin 7) or REM_XCLK (from DC-to-DC Daisy Chain, entering on pin 3) as INU_XCLK (exiting on pin 18). We will set up the DC to use the LOC_XCLK. INU_XCLK goes from the "LCA Configuration Logic" (DCONF.sch) sheet to the "Transmit Connector" (DXCON.sch) sheet, and also to the "Parallel Connector" (DPARA.sch) sheet. On the "Parallel Connector" (DPARA.sch) sheet: U41 converts INU_XCLK to differential ECL (entering on pin 17 as DST_0, exiting on pins 9 and 10). The differential ECL version is pulled down in RL8, and sent to the Parallel Connector (JP1) as DST(0) on pins 19 and 20. This signal is received on the >>ERPB<< and used to clock the Transmit Logic, and (at 132 ns crossing rate only) the CTFE Input Logic. On the "Transmit Connector" (DXCON.sch) sheet: U39 converts INU_XCLK to differential ECL (entering on pin 23, exiting on pins 4 and 5). These signals are pulled down in RL7 (pins 4 and 11), and then converted BACK into TTL in U40 (entering on pins 15 and 16, exiting on pin 8), now called XMIT_CLK. XMIT_CLK is thus just INU_XCLK with a few ns of delay. Neither INU_XCLK or XMIT_CLK is sent to the CRC with the other signals on this schematic sheet. The delay was evidently done on this sheet for convenience rather than because the signals were actually used on this sheet. XMIT_CLK goes from the "Transmit Connector" (DXCON.sch) sheet to the "Transmit Logic" (DXLOG.sch) sheet, and also to the "Daisy Chain Connector" (DDASY.sch) sheet. On the "Transmit Logic" (DXLOG.sch) sheet: XMIT_CLK acts as the clock for counter chain U25, U28, U29 (entering on pin 2 of each IC). This counter chain produces the address delivered to a pair of ROMs (U23 and U26). The data from these ROMs is latched in U24 and U27 (74F574 latches), which are again clocked by XMIT_CLK. These ROMs are each 2K x 8 (i.e. 11 address bits, 8 data bits). They hold a control signal pattern, which may need to change between Run I and Run II. Of greater concern, the pattern may need to change between One Tick Readout and Two Tick Readout modes, and we need to figure out how to do that. XMIT_CLK also goes to GAL4, which uses it to generate X_STB (which is sent out the Transmit Connector to the CRC (Run I) or Bougie (Run II)). This generation is a bit strange. First, a copy of XMIT_CLK (P_CRC_CLK, exiting on pin 17) is made in GAL4. This is sent to U34 pin2, where it is delayed by a variable amount (depending on the jumper position in H2). This delayed copy of XMIT_CLK (DEL_XCLK) reenters the GAL on pin 14. The rising edge of X_STB is driven by DEL_XCLK, while the falling edge is driven by XMIT_CLK. X_STB exits the GAL on pin 15: _____ _____ XMIT_CLK _____| |_____| |_____ _____ _____ DEL_XCLK ________| |_____| |__ __ __ X_STB ________| |________| |_____ On the "Daisy Chain Connector" (DDASY.sch) sheet: XMIT_CLK is buffered by U19 (entering on pin 9, exiting on pin 11 as REG_CLK. REG_CLK is used to clock U20 and U21, the 74AC574's which receive data from the ERPB Daisy Chain. Recall that the >>ERPB<< which drives the data to this cable used DST(0), which runs slightly AHEAD of XMIT_CLK, to update its output. I hope that the delay of distributing DST(0) is enough to reliably put it BEHIND XMIT_CLK to avoid setup/hold problems on these latches. We want to replace the 20 MHz oscillator with an MTG channel, both to control its arrival at the ERPB (vs. the Input_Clk) and to control the data and strobe arrival at the Bougie. This could be done as follows (using MTG(4) as the source): - pull GAL2 pin 18 out of socket - wire U4 pin 10 to GAL2 (socket) pin 18 Moreover, this phase shift between XMIT_CLK and INU_XCLK is puzzling. It seems especially odd to delay INU_XCLK vs. XMIT_CLK, as that would seem to set up a race condition between the top ERPB emitting a new 16-bit word and the DC ingesting that word: _____ _____ _____ XMIT_CLK ___| |_____| |_____| |___ ____ ___________ ___________ ________ XDATA ____X___________X___________X________ _____ _____ _____ INU_XCLK _____| |_____| |_____| |_ Rather than the more desirable: _____ _____ _____ XMIT_CLK ___| |_____| |_____| |___ ____ ___________ ___________ ________ XDATA ____X___________X___________X________ _____ _____ _____ INU_XCLK _| |_____| |_____| |_____ with its greatly increased setup time (XDATA vs. INU_XCLK). We could remove much of this delay by NOT converting INU_XCLK to ECL and back again: - disconnect U40 pin 8 from the PCB - tie U39 pin 23 to U40 pin 8 (or some via connected to that net) There would still be some skew between various buffered and unbuffered versions of INU_XCLK (see above for details). PROMs ----- The DC contains a pair of 2K x 8 PROMs, followed by a pair of 74F574 latches. These PROMs generate a large number of control signals used on the DC and also distributed to the ERPB's via the Daisy Chain and Parallel Connectors. Following is a list of these signals: PROM U23: Bit Signal Goes to --- ------ ------- 0 SQ_FAULT_CLK U30-U33 (DXLOG.sch), ERPB's as DST(3) 1 SQ_FAULT_TOK U19 (DDASY.sch) 2 SQ_FSR0_S0 U30, U31 (DXLOG.sch) 3 SQ_FSR1_SO U32, U33 (DXLOG.sch) 4 SQ_FSR0_OE\ U30, U31 (via U35) (DXLOG.sch) 5 SQ_FSR1_OE\ U32, U33 (DXLOG.sch) 6 (unused) 7 (unused) PROM U26: Bit Signal Goes to --- ------ ------- 0 SQ_DDC0 ERPB's via Daisy Chain Connector 1 SQ_DDC1 ERPB's via Daisy Chain Connector 2 SQ_ERPB_OE ERPB's via Daisy Chain Connector 3 SQ_CLK_MASK GAL4 (DXLOG.sch) 4 SQ_FBACK0 GAL4 (DXLOG.sch) 5 SQ_FBACK1 GAL4 (DXLOG.sch) 6 SQ_DST_1 ERPB's as DST(1) via Parallel Connector 7 SQ_SPARE_OUT can be sent to CRC via Transmit Connector It is my current belief that we need NONE of the signals from PROM U23. They are all associated with transmitting Fault Data to the CRC's, which we did not do and do not plan to do in Run II. In the current PROM, some of the U23 outputs are always high and others are always low. None of these outputs change. What do the signal from PROM U26 do? They are defined in Steve Pier's documentation but only for the address range 0:255. I don't know what they do outside this range. 0. SQ_DDC0 This signal starts low at ROM Address 0, goes high at ROM Address 1, and remains high for 130 ticks (i.e. it goes low again at ROM Address 131). It remains low until ROM Address 255. It goes to the top ERPB to initiate its data transfer. 1: SQ_DDC1 Not used. Always HIGH. 2: SQ_ERPB_OE This signal is always HIGH. It goes to the top ERPB to set up its data output enable. 3: SQ_CLK_MASK This signal starts high at ROM Address 0, goes low at ROM Address 4, and remains low for 128 ticks (i.e. it goes high again at ROM Address 131). It remains high until ROM Address 255. It goes to GAL4 and is used to enable generation of X_STB to the CRC/THE Card. When this signal is LOW the DC is enabled to generate the "CRC" Strobe. 4: SE_FBACK0 This signal starts high at ROM Address 0, goes low at ROM Address 1, and remains low for 130 ticks (i.e. it goes high again at ROM Address 131). It is thus just exactly inverted from SQ_DDC0. It goes to GAL4 and is used to continue enabling the ROM Address Counters after the "MTG" XMIT_TRIG signal drops. While this signal is LOW the counters remain enabled. When the signal goes high (at ROM Address 131) the ROM Address counters are reset to 0 (note that this signal also remains HIGH at ROM Address 0). 5: SQ_FBACK1 Not used. Always HIGH. 6: SQ_DST_1 Not used. Always HIGH. 7: SQ_SPARE_OUT Not used. Always HIGH. So essentially only 4 signals are used from this ROM. Unfortunately, they appear to have an effective "word count" built in to them, limiting the transfer size to 128 16-bit words (also need to think about whether the extra IOB latch in the ERPB FPGA's alters this timing!). We want multiple "word counts" depending on Single Tick Readout Mode vs. Two Tick Readout Mode. There are 2 ways to get these modes: 1. Use Readout Mode as an upper order address bit to the ROMs, and hardcode the two length counts in the ROM pattern. This requires burning a new PROM for each DC and making some wire mods on each DC. 2. Lose the ROMs entirely and use an Up Daisy Chain signal to propagate the DDCO0 from the bottom ERPB back up to the top via the UDC0 or UDC1 path. This requires making some wire mods on each DC, making a new DC GAL4, and making a new Transmit GAL on each ERPB (because the current Transmit GAL doesn't propagate signals up the Daisy Chain) or making wire mods on each ERPB, and doing something special with either the Transmit GAL or wire mods (or just a jumper cable) on the bottom ERPB to "turn around" the DDCO0 signal. Technique 2 is the "right" solution, in that it eliminates the hardcoded word count, but it's more work, in that it involves touching the 80 ERPB's. Here are the wire mods required for solution 1: - cut trace U29 pin 12 to U26 pin 21 - wire U4 pin 9 (MTG(3)) to U26 pin 21 (will also go to U23 pin 21) -- this is the most significant address bit of each PROM - reprogram U26 (and U23?)