TITLE Distributor Cap CONFIGURATION PAL PATTERN Run IIA REVISION 2.0 AUTHOR Dan Edmunds COMPANY MSU HEP DATE 21-July-2003 ; This PAL on the Distributor Cap circuit board controls the Configuration ; of the LCA's on the ERPB cards. The PAL is installed in the socket ; labeled GAL3 on the DC circuit board. ; Notes: ; Note that the LCA's on the ERPB's are Configured using the Slave Serial ; Mode, i.e. LCA pins M0, M1, and M2 are are all High. In order to ; initiate Configuration the LCA Program* signal to pin #55 on the ; ERPB 4002A LCA's must be held Low for a minimum of 300 nsec. ; Note that pin #15 of this device which is an I/O pin is connected in ; trace on the DC circuit board to a 74-HCT output. Thus, even though ; pin #15 on this device is not used, it must be configured as an input. CHIP DC_Confg PAL22V10 ; Input Pins ; 1 2 3 4 5 Clk_2us Raw_1_Shot NC NC NC ; 6 7 8 9 10 NC ROM_Data ROM_CEO Enb_Trans Enb_Confg ; 11 12 13 NC GND Conf_Command ; Output Pins ; 14 15 16 17 18 Trg_1_Shot NC NU_Out_16 LCA_Conf_Data LCA_CClk ; 19 20 21 22 23 LCA_Prog ROM_OE ROM_Clk Verify Sync_1_Shot ; 24 "25" VCC GLOBAL ; Note that a 25th pin was defined to use in the global ; set/reset definition of all registers at power up. ; Input Signals ; Clk_2us This is the clock signal that is used by this PAL and is used to ; generate the ROM_Clk and LCA_Configuration_Clk at 1/2 of this frequency. ; Raw_1_Shot This is the input for the output of the 50 msec one-shot ; that is fired at the beginnig of the Configuration process. ; Enb_Trans is a High Active signal that enables the DC to perform ; readout cycles. If Enb_Trans is High then the Conf_Command signal has ; no effect. Enb_Trans must be Low for LCA Configuration to happen. ; Enb_Confg is a High Active signal that enables the DC to perform ; LCA Configuration. If Enb_Confg is Low then the Conf_Command signal ; has no effect. Enb_Confg must be High for LCA Configuration happen. ; ROM_Data This input receives the data from ROM SCP-1. ; ROM_CEO This input receives the Chip Enable Output from ROM SCP-1. ; Conf_Command This input receives the Configuration_Command signal ; from pin 12 of the MTG Main Register U12. The Configuration_Command ; signal must be High for > 2 periods of the Clk_2us before it will be ; recognized and the LCA Configuration process actually begins. ; It has been verified that all NC input pins to this device are connected ; to a sources of valid logic level which in most cases is a static line. EQUATIONS GLOBAL.RSTF = GND ; The following 2 equations control the triggering of the one shot that ; begins the LCA Configuration process. This one shot is triggered by a ; High to Low transition on its "A" input. These 2 equations protect ; against an accidental triggering of this one shot. ; In order for the Verify signal to become High, both Conf_Command and ; Enb_Confg must be high while Enb_Trans is Low. ; In order for Trg_1_Shot to go Low, all 3 signals Verify and Conf_Command ; and Enb_Confg must be High while Enb_Trans is Low. ; To make all this happen, the Configuration_Command signal must be ; High for > 2 usec. Verify := Conf_Command * Enb_Confg * /Enb_Trans Trg_1_Shot := /Conf_Command + /Verify + /Enb_Confg + Enb_Trans ; The following equation for Sync_1_Shot brings the raw output of the ; one shot into synchronization with the 2 usec Clock and provides more ; protection against accidentail Configuration. This protection comes ; from requiring the Enable_Configuration signal to be High and ; requiring the Enable_Transmit signal to be Low in order for the ; high active Sync_1_Shot output to be asserted. ; Note that this will normally block the action of the Configuration ; pushbutton on the DC because for normal operation these enable signals ; will not be in this state. Sync_1_Shot := Raw_1_Shot * Enb_Confg * /Enb_Trans ; The equation for ROM_Output_Enable will remain high as long as ; the Sync_1_Shot signal is high. This gives the Serial Configuration ; PROM the duration of the one shot period (about 50 usec) to initialize ; before this ROM's Output Enable pin returns to its active Low state. ROM_OE := Sync_1_Shot ; The next step in the configuration process is to tell the LCA's that ; they should stop running and get ready to receive new configuration ; data. A Low level on the LCA_Prog signal tells the LCA's to configure. ; We make a LCA_Program signal that is Low for 2 usec by "decoding" when ; Sync_1_Shot has risen (at the started of its one shot period) but ; ROM_OE has not yet risen. Protect this signal by requiring ; Enable_Configuration to be High and Enable_Transmit to be Low. ; Note that LCA_Prog is a registered output so it follows one clock behind. LCA_Prog := ROM_OE + /Sync_1_Shot + /Enb_Confg + Enb_Trans ; While the configuration process is actually under way we need the ; Configuration Clock to be running. This clock is used by both the ; Serial Configuration PROM and by the LCA's. This clock runs at 1/2 ; the speed of the 2 usec clock that enters this PAL on its pin #1. ; This clock train starts near the beginning of the configuration ; process when ROM_OE returns Low after the one shot has timed out. ; This clock train continues to run until the ROM_CEO signal goes Low ; (i.e. it runs until the end of the Serial PROM). When this clock ; train is not running it is in the High state. When this clock train ; starts its first transition is High to Low. The last transition of ; this train is Low to High. ROM_Clk := ROM_OE + /ROM_CEO + /ROM_Clk LCA_CClk = ROM_Clk ; The final equation is used to generate the LCA_Configuration_Data signal. ; The LCA Configuration Data comes from the Serial Configuration PROM that ; is labeled "SCP1" on the DC circuit board. This data is shifted so that ; it changes on the falling edge of the LCA Configuration Clock i.e. it ; is very nice and stable on the rising edge of the LCA Configuration ; Clock which is when the LCA's ingest this data. Once configuration has ; finished this line is forced Low by the ROM_CEO signal. LCA_Conf_Data := ROM_Data * ROM_CEO ; The following equation defines an unused output to a static Low level. NU_Out_16 = GND ; Static tied Low not used output SIMULATION TRACE_ON Conf_Command Enb_Confg Enb_Trans Verify Trg_1_Shot Raw_1_Shot Sync_1_Shot Clk_2us ROM_OE LCA_Prog ROM_CEO ROM_Clk LCA_CClk ROM_Data LCA_Conf_Data ; Setup some rational states for everything. SETF Enb_Confg Enb_Trans /Conf_Command /Raw_1_Shot /ROM_Data /ROM_CEO ; Setup normal state before requesting Configuration but with Enb_Trans ; High so Configuration will not startup anyway. SETF Enb_Confg Enb_Trans /Conf_Command CLOCKF Clk_2us CLOCKF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Setup normal state before requesting Configuration but with Enb_Config ; Low so Configuration will not startup anyway. SETF /Enb_Confg /Enb_Trans /Conf_Command CLOCKF Clk_2us CLOCKF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Now try starting a Configuration process with Enb_Config High and ; Enb_Transmit Low and check to verify what happens with each clock cycle. SETF Enb_Confg /Enb_Trans /Conf_Command SETF Conf_Command CLOCKF Clk_2us CHECK Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Check the next clock cycle to see that the one shot is triggered. CLOCKF Clk_2us CHECK Verify /Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Check that this state would persist. CLOCKF Clk_2us CHECK Verify /Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data CLOCKF Clk_2us CHECK Verify /Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Now stop trying to initiate Configuration, i.e. take Conf_Command ; back to its default Low. SETF /Conf_Command CLOCKF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Now let Raw_1_Shot go High and see that after the clock edge Sync_1_Shot ; also comes high. SETF Raw_1_Shot CLOCKF Clk_2us CHECK /Verify Trg_1_Shot Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; The next clock will bring LCA_Prog to its active Low state and ; ROM_OE to a High. Sync_1_Shot remains High. CLOCKF Clk_2us CHECK /Verify Trg_1_Shot Sync_1_Shot ROM_OE /LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; The next clock will return LCA_Prog to its not active High state ; and ROM_OE will remain High. Sync_1_Shot remains High. CLOCKF Clk_2us CHECK /Verify Trg_1_Shot Sync_1_Shot ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; This state will now persist as long as Raw_1_Shot Remains High. ; Note that ROM_CEO will become High during this process but for ; now that does not make any difference. CLOCKF Clk_2us SETF Raw_1_Shot ROM_CEO CLOCKF Clk_2us CLOCKF Clk_2us CHECK /Verify Trg_1_Shot Sync_1_Shot ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Raw_1_Shot now falls to its Low state and the action starts. ; Starting here walk the clock by hand to see the effects of its ; edges and levels. SETF /Raw_1_Shot ROM_CEO SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Now the 2nd positive edge of Clk_2us after Raw_1_Shot falls. ; This will cause ROM_OE to fall to its active Low state. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; Now the 3rd positive edge of Clk_2us after Raw_1_Shot falls. ; This will cause ROM_Clk & LCA_CClk to fall Low. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data ; Now the 4th positive edge of Clk_2us after Raw_1_Shot falls. ; This will cause ROM_Clk & LCA_CClk to return High. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; ROM Data --> LCA Configuration Data ; Now watch some ROM Data and LCA_Data. Data from the ROM will change ; right after a positive edge of ROM_Clk. Data to the LCA will be 1/2 ; cycle later and change right after the negative edge of LCA_Clk. ; 5th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data ; 6th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High. ; Let's assume that data from the ROM becomes High. SETF Clk_2us SETF ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 7th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA goes High following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data ; 8th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High. ; The LCA would now ingest the high configuration data. ; Let's assume that the next data from the ROM is Low. SETF Clk_2us SETF /ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data ; 9th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA goes Low following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data ; 10th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High ; The LCA would now ingest the Low configuration data. ; Let's assume that the next data from the ROM is High. SETF Clk_2us SETF ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 11th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA now goes High following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data ; 12th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High. ; The LCA would now ingest the High configuration data. ; Let's assume that the next data from the ROM is Low. SETF Clk_2us SETF /ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data ; 13th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA now goes Low following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data ; 14th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High ; The LCA would now ingest the Low configuration data. ; Let's assume that the next data from the ROM is also Low. SETF Clk_2us SETF /ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 15th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA remains Low following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk /LCA_Conf_Data ; 16th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High. ; The LCA would again ingest the Low configuration data. ; Let's assume that the next data from the ROM is High. SETF Clk_2us SETF ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 17th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA now goes High following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data ; 18th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High. ; The LCA would again ingest the High configuration data. ; Let's assume that the next data from the ROM is also High. SETF Clk_2us SETF ROM_Data ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data ; 19th positive edge of Clk_2us --> ROM_Clk & LCA_CClk fall Low. ; Configuration Data to the LCA remains High following the ROM data. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog /ROM_Clk /LCA_CClk LCA_Conf_Data ; Now with the ROM data and thus the Configuration data High, watch ; the end of the Configuration cycle when ROM_CEO falls LOW. ; End of Configuration will stop ROM_Clk & LCA_CClk High and ; then force configuration data to the LCA Low. ; 20th positive edge of Clk_2us --> ROM_Clk & LCA_CClk return High ; and ROM_CEO goes Low because it is the end of the Configuration ; PROM memory. SETF Clk_2us SETF ROM_Data /ROM_CEO CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk LCA_Conf_Data ; 21th positive edge of Clk_2us --> ROM_Clk & LCA_CClk *would* fall ; Low but ROM_CEO has gone Low because it is the end of the ; Configuration PROM memory and this will cause the ROM_Clk & LCA_CClk ; to stop at thier High level. ; In addition, even though the last ROM data was High, because ROM_CEO ; has gone Low at the end of Configuration, this will force the data ; to the LCA to go Low. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 22th positive edge of Clk_2us everything should now be static ; because Configuration is over. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data ; 23th positive edge of Clk_2us everythin should now be static ; because Configuration is over. SETF Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data SETF /Clk_2us CHECK /Verify Trg_1_Shot /Sync_1_Shot /ROM_OE LCA_Prog ROM_Clk LCA_CClk /LCA_Conf_Data TRACE_OFF