ERPB FPGA for Run II -------------------- Original: 13-APR-1999 Revised: 26-NOV-2001 Introduction ------------ All information is this document pertains to the the Run II version of the ERPB FPGA (sometimes called an LCA) and is quit different from the Run I setup of this part. Readout of Trigger Tower EM Et and Total Et data from the L1 Cal Trig occurs via the Run I ERPB system. The goal is to try to get all of the required functionality into the XC4002A FPGA's on these ERPB's. Each ERPB FPGA must: - receive the time-multiplexed 9-bit EM Et and Total Et data for each 132-ns tick for two Trigger Towers - pack these 9-bit quantities into 8-bit quantities, either modifying the energy scale by dropping the LSBit or maintaining the energy scale and saturating. - provide four, 32-stage, 8-bit wide, Beam Crossing History FIFOs, one for each of the 4 quantities (two Trigger Towers times EM Et and Total Et) handled by this FPGA - provide 4 Data Capture Registers, to hold each of the 4 quantities handled by this FPGA for two separate ticks - generation of FIFO read and write addresses and control for FIFO reading and writing. - readout this data to the Distributor Card, interfacing with the Transmit GAL, the Parallel Connector, and the Daisy Chain Connector - Readout State Engine to control which LCA source is providing data, which LCA is providing data, and to pass readout to the next ERPB card. Recall that there are 8 FPGA's on each ERPB card. Detailed Description of the ERPB FPGA ------------------------------------- The functionality of the ERPB FPGA can be broken up into individual modules, each of which I will describe below. 1. Parallel Timing Signal Input All ERPB FPGA's receive, in parallel, 16 Timing and Control Signals from the Distributor Card. 9 of these signals are provided to the DC from an external source--these are called MTG(8:0). The other 7 signals are generated on the DC itself--these are called DST(6:0). These signals are used to configure the FPGA's, and also to provide both static and dynamic timing and control signals to manage the data capture on these FPGA's. All of these signals, except for DST(5:4), are available for user logic in the ERPB FPGA. DST(5:4) are used only for configuring these FPGA's. Here is a table of the Parallel Timing Signals: Parallel ERPB Card Signal JP1 Pin ERPB LCA PC84 4002A Name Numbers Function Pin Num Pin Type Comment --------- --------- ------------ ------- -------- --------- MTG(0) 40-39 Input_Clock 13 PGCK1 MTG(1) 38-37 EM/Total_Bar 35 PGCK2 MTG(2) 36-35 Lookback(0) 10 SGCK1 but use ibuf MTG(3) 34-33 Lookback(1) 80 I/O MTG(4) 32-31 Lookback(2) 51 SGCK3 but use ibuf MTG(5) 30-29 Capture_Data 78 PGCK4 MTG(6) 28-27 Lookback(3) 3 I/O MTG(7) 26-25 -not_used- 4 I/O DC Config Ctrl MTG(8) 24-23 Lookback(4) 5 I/O Lookback(4) & DC Config Ctrl DST(0) 22-21 Xmit_Clk 57 PGCK3 DST(1) 20-19 -not_used- 6 I/O DST(2) 18-17 Negative_Eta 7 I/O DST(3) 16-15 -not_used- 8 I/O DST(4) 14-13 LCA Programming 55 PROG* DST(5) 12-11 LCA Programming 73 CCLK DST(6) 10-9 LCA Programming 71 Prog Data In NOTES: MTG(2) and MTG(4) connect to FPGA pins that can drive Global Clock lines but only ibuf are used at these inputs. MTG(6) had been the DC card Xmit_Trig signal. The DC card must be reworked to free up the MTG(6) signal. MTG(7) and MTG(8) are routed to the ERPB's but they are used by the DC card to control the Configuration Logic and thus MTG(7) and MTG(8) must only be used with extreme caution to control anything on the ERPB. 2. Two CTFE Channel Input Latches Each CTFE Channel provides 9 bits of time multiplexed Total Et and EM Et data. This data is latched on each Input_Clock FALLING edge (the FALLING edge is used to optimize timing within the LCA and takes into consideration thelevel-sensitive RAM's used in the xc4002A). During each tick, first the Total Et data is latched, then the EM Et data. Note that, as each tick is 7 (or 21) Accelerator Clock cycles long. The latches are in IOB FF's, this uses no CLB resources. 3. Two 9-to-8-bit Packing Blocks The 9-bit output of each Input Latch goes to a 9-to-8-bit Packing Block. The 9th bit of each Channel is OR-ed with each of the other 8 bits (i.e. any value of 256 or greater is "saturated" at 255). The output of the Packing Block is latched, using the RISING edge of the Input_Clock. Each of the two Packing Blocks uses 4 CLB's (for a total of 8 CLB's). 4. Four FIFO's and Data Capture Latches The 8-bit output of each Packing Block goes to a pair of FIFO's and Data Capture Latches. These FIFO's are 32 stages deep (to account for the L1 Accept latency). One FIFO in the pair holds EM Et data, and the other holds Total Et data. They are written to during alternate HIGH pulses of Input_Clock (the EM/Total_Bar signal is used to select which RAM is written to, see the description of the FIFO and Capture Control Block below). Note that because of the pipeline type structure that the CTFE data moves through, by the time it arrives at the FIFO data input, it is shifted so that Tot_Et data is actually written with the EM%Tot_Bar signal is HI. The 8-bit output of each FIFO goes to the Readout Data Capture Latches. These latches are clocked only when: Input_Clock goes high while the Capture_Data signal is high and EM%Tot_Bar signal is low. The Capture_Data signal only changes state at the time of the positive edges of the EM%Tot_Bar signal. The Capture_Date signal is generated by the CT_Readout_Helper in responce to an L1_Acpt to this Geo Section. Each 8-bit FIFO and 8-bit Data Capture Latch uses 8 CLB's (for a total of 32 CLB's, or 50% of the XC4002A device). Note that the outputs of these 4, 8-bit Data Capture Latches are grouped into 2, 16-bit combinations: EM Et and Total Et for Channel A EM Et and Total Et for Channel B These 2, 16-bit values are fed to a multiplexor (made of TBUF's and long lines, at a cost of zero CLB's). The output of this mux is fed to the XDATA_PAD output flip-flops. The mux and XDATA_PAD output enables are controlled by the Readout Control Logic, described below. 5. FIFO and Data Capture Control The FIFO and Data Capture Control logic is controlled by four signals: Input_Clock EM/Total_Bar Capture_Data Input_Clock, Capture_Data, and EM/Total_Bar are combined in logic gates to produce EM_WE and Tot_WE (the write-enables for the level-sensitive EM and Total FIFO's). Note that the xxx_WE signals are HIGH while Input_Clock is HIGH. The RAM cells in the xc4002A are such that the Address must be stable before, during, and after the high period of the Write Enable. In addition the data to be written into the FIFO must be stable before, at the time of, and after the falling edge of Write Enable. The address to the FIFO changes only on the rising edge of the EM%Tot_Bar signal. This may sound like a strage time to change it but the rising edge of this signal is at the completion of writing one full L1_Cal_Trig tick's worth of data (first Tot_Et and then EM_Et). Neither of the Write Enables is active at the time of the rising edge of the EM%Tot_Bar signal. Input_Clock, Capture_Data, and EM/Total_Bar are also used to generate the Capture_Clock signal, which is used as described above. See the timing diagram later in this file. This block also contains the FIFO Address generator, which uses a 5-bit counter to generate the FIFO Write Address. A 5-bit adder is used to add an offset to this Write Address to generate the FIFO Read Address. The value that you add is "32 complement" of the value that you want to look back. A 5-bit 2-to-1 mux selects either the Read or Write Address to send to the FIFO. The output of this FIFO Address Selector Mux goes through a latch that is clocked by the positive edge of EM%Tot_Bar before the selected address goes to the FIFO array. This 5-bit address counter also increments on the rising edge of EM%Tot_Bar as described above. The Write/Read Address Multiplexer is controlled by the Capture_Data signal which only changes states on the positive edge of the EM%Tot_Bar signal, i.e. when the address to the FIFO is changing anyway. The Read Address is obtained from the Write Address by adding a 5 bit "look back" value to the current Write Address. The actual value that you add is 32 - value_that_you_want_to_look_back. Note that this is the same as subtracting the value that you want to look back. The 5 bit look back value can be controlled from the CT_Readout_Helper card by a programmable register. Note that the Capture_Data signal must be asserted for 2 full cycles of the EM%Tot_Bar signal so that the Read Address is both generated, and makes it through the latch at the address selector mux output and reaches the FIFO array, i.e. the FIFO Address is pipelined. During a capture readout data cycle, the read address has a generous time to get setup and the selected FIFO data to make it to the Capture Latches. The full high time of EM%Tot_Bar signal plus the time from the falling edge of EM%Tot_Bar until the rising edge of Input_Clk is available for FIFO Read Address setup, FIFO data access and data setup at the Capture Data Latches. 6. Readout Control The 4 data elements (EM Et and Total Et for 2 Trigger Towers) stored in this FPGA are read out using the Daisy Chain Cable. There are 4 separate readout orders, depending on whether the ERPB is servicing Positive or Negative Eta and also on whether the ERPB is in the "normal" or "eccentric" slot in the Tier 1 Crate. Both the order of the elements in a single FPGA, and the order of the FPGA's themselves, varies. These readout orders are handled by having each of the 8 FPGA's track, with a counter, the readout of the entire card. Each FPGA knows its own ID number (provided on I/O pins) and the card's readout order (also provided on I/O pins), and provides data in the correct order at the correct time. The four readout orders are as follows: Normal Eccentric Normal Eccentric +ve Eta +ve Eta -ve Eta -ve Eta ------- --------- ------- --------- 0, A 2, A 1, B 3, B 0, B 2, B 1, A 3, A 1, A 3, A 0, B 2, B 1, B 3, B 0, A 2, A 2, A 4, A 3, B 5, B 2, B 4, B 3, A 5, A 3, A 5, A 2, B 4, B 3, B 5, B 2, A 4, A 4, A 6, A 5, B 7, B 4, B 6, B 5, A 7, A 5, A 7, A 4, B 6, B 5, B 7, B 4, A 6, A 6, A 0, A 7, B 1, B 6, B 0, B 7, A 1, A 7, A 1, A 6, B 0, B 7, B 1, B 6, A 0, A The Readout State Engine in FPGA #1 has the additional job of determining when all the data on "this" ERPB card has been sent up the Daisy Chain cable and then telling the next ERPB card down the Daisy Chain cable to start its readout. The protocol for controlling which ERPB card is reading out used the DDCA/B_0 and ROEA/B signals on the Daisy Chain cable. The protocol works as follows: The ERPB "above" passes DDCA_0 signal to "this" ERPB card via the Daisy Chain Cable. DDCA_0 is received and buffered and becomes DDCI_0 and is immediately sent to all 8 FPGA's as the GO_0 signal aka RI. All 8 Readout State Engine counters (one per FPGA) are taken out of reset On the next Xmit_Clk rising edge, all 8 counters increment from state 0 to state 1. Once they receive GO_0 they all begin incrementing in parallel on each positive edge of Xmit_Clk. On each FPGA, the Readout State Engine counter's 3 MSBits are compared to the 3 bit LCA ID (appropriately processed depending on the Pos/Neg Eta and the Normal_Position signals) to determine which FPGA should be driving the XDATA bus on the ERPB card. On each FPGA, the Readout State Engine counter's LSB is used to select which Capture Data Register should be the source of readout data. Note that the XDATA outputs on the FPGA are latched. The Output Enable is also delayed by one Xmit-Clk tick. Note also that the XDATA outputs are driven to the "Above" Daisy Chain Connector via 74AC574 latches. That is, they are delivered to this connector one Xmit_Clk phase later than when they exited the FPGA. So data actually leaves a given ERPB card 2 Xmit_Clk edges after the Readout State Engine counter was at the proper state to select that data. When the 8 counters reach Terminal Count, they halt (at the terminal count value which is 15 decimal) The Readout State Engine in FPGA #1 provides the control connections that pass the readout from the current ERPB card to the next ERPB card down the chain. In Run I these control signals passed through the "Transmit GAL". In Run II the Transmit GAL has been replaced with just a jumper plug. The two control signals from FPGA #1 that are used to pass the readout to the next ERPB card are: RO aka GI_3 Goes HI to Indicates that "this" State Engine is done and that the next positive edge of Xmit_Clk belongs to the "next" ERPB down the chain. This is the DDCB_0 signal to the next ERPB card. Dly_2_RO aka GI_1 Goes HI two positive edges of Xmit_Clk after "this" State Engine is done. This disables the LCA Data Buffer Outputs on "this" ERPB card and enables the outputs of the output latches on the next ERPB card down the chain. This is the ROEB signal to the next ERPB card. This logic requires about 8 CLB's. Programming Interface --------------------- These FPGA's have NO TCC-addressable registers. There are, however, jumpers and parallel control signals which modify the operation of these FPGA's: JMP(0): when HIGH, normal readout order when LOW, eccentric readout order JMP(1): not used but must be set HIGH. DST(2): when HIGH, Negative Eta readout order when LOW, Positive Eta readout order Timing Diagrams --------------- The timing diagrams are not yet included in this document. They are currently in the #4 FPGA Log Book. See pages 237, 249, 255. A Brief describtion of how this is setup follows. In the Tier 1 Crate, the EM/Tot select signal should follow when the CTFE cards actually outputs EM and Total data. The EM/Tot signal should be high when the CTFE card is sending out EM Et data. Data is clocked out of the CTFE on the positive edge of the X_Clock. So at the CMC the EM/Tot signal should change states at about the same time as the positive edge of the X_Clock or perhaps a little earlier to allow time for the EM/Tot signal to flow through the CT_Readout_Helper FPGA. The Write Address to the ERPB FIFO is incremented on the rising edge of the EM/Tot signal. The Input_Clk high period should be about centered in the high and low sections of the EM/Tot signal. Data is latched into the ERPB on the falling edge of the Input_Clk signal. The Write_Enables to the FIFO are active during the high period of the Input_Clk. Within the ERPB, data must make it through the 9->8 Packer and be setup in the latch at the end of the 8->9 Packer during the period that Input_Clk is low. That is, the Input Latch is clocked by the falling edge of Input_Clk and the latch at the output of the 8->9 Packer is clocked by the rising edge of the Input_Clk. Data must make it from the latch at the output of the 8->9 Packer and be setup in the FIFO during the time that Input_Clk is HI. FIFO Write Address must be stable before, during and after the period when Input_Clk is HI. Note that the operation of this is a bit funny if you think about a single isolated beam crossing's worth of CTFE data. You would need: a falling edge on Input_Clk to capture the CTFE's TOT Et output, then a pulse of Input_Clk to write this Tot Et data into the ERPB's FIFO, the falling edge of this pulse will capture the CTFE's EM Et output, and then finally a second pulse of Input_Clk to write this EM Et data into the ERPB's FIFO. So to capture a single isolated beam crossing of data from the CTFE you need 3 features of the ERPB Input_Clk to be in the right place. Once this gets running all is OK but infact it does have a problem at start up (actually at the start up of each Super Bunch). In practice this works out OK because the timing signals for a given Super Bunch start up early and cycle for one "fictional" BX before the first real Tevatron BX of the Super Bunch. So EM/Tot is high for 11 RF Buckets and low for 10 RF Buckets. Input_Clk will be asserted for 4 RF Buckets EM/Tot is shown on top with Input_Clk below. The scale is RF Buckets. +--------------------------------+ +--- | | | | | | ---+ +-----------------------------+ +-----------+ +-----------+ | | | | | | | | ---------------+ +-----------------+ +------------ | | | | | | | |<--- 4 --->|<--- 4 --->|<-- 3 ->|<-- 3 ->|<--- 4 --->|<-- 3 ->| | | | | | | | | | | | | | |<------------- 11 ------------->|<----------- 10 ------------>| | | | | | | | |<----------------------------- 21 --------------------------->| | | The number in time are: 1 RF Bucket equals 18.831 nsec 3 RF Buckets equals 56.49 nsec 4 RF Buckets equals 75.32 nsec 7 RF Buckets equals 131.82 nsec 21 RF Buckets equals 395.45 nsec ============================================================================= The information below here indicates some of the development work involved in making the current Run II design. This needs to be edited and included in the above "official" Run II ERPB description. Readout Control Between events the DDC_0 is low. At the end of an event this starts as the DC setting its DDC_0 low and this ripples down the chain. At each ERPB DDC_0 coming in low forces its Readout Counter to reset. This in turn: disables the 74AC574 latche outputs that send data up cable enables the 74ACT541 buffers that connect the LCA data to the latch inputs and sends DDC_0 down the calbe to the next ERPB. During readout as each ERPB finishes sending out its data, it sends a DDC_0 high to the next ERPB down the cable DDC_0 coming from above is buffered, passes through the Transmit GAL and becomes GO_0 to all the LCA's. The only GO_* that is actually used is GO_0. GO_0 becomes net "RI". When GO_0 aka RI goes high it takes the Readout Counter out of reset. When the readout counter reaches 15 it asserts "RO" ripple out which is inverted and tied to the counters Clock Enable to hold the counter at its terminal value. RO becomes GI_3 runs to the Transmit GAL where it is just jumpered to become DDCO_0 and then buffered by a 74ACT541 and sent to the next ERPB as DDCB_0. In the ERPB LCA RO is delayed by two FF which are clocked by XMIT_CLK and it then called Dly_2_RO. Dly_2_RO is GI_1 which runs to and jumpers through the Transmit GAL where it is called BUF_OE\ and is the OE\ signal on the 74ACT541 buffers that put the data from this ERPB card's LCA's into the 74AC574 latches at this cards output. GI_1 is also jumpered through the Transmit GAL to become ROEO. ROEO is buffered by a 74ACT541 and become ROEB and is sent down to the next ERPP where it enables its 74AC574 latche outputs to send data up. The Readout State Engine Counter 4 bits and runs 0:15. Signal RO_Ctr(0) Selects either the "A" or "B" channel depending on the state of the Negative_Eta signal. Signal RO_Ctr(3:1) Selects which counts of the Xmit_Clk this card will readout on depending on the LCA_ID(2:0) signal and the Negative_Eta signal and the Normal_Position signal. Things to Check: WRT XMIT_CLK when does the data mux in the ERPB FPGA output section change selections ? WRT XMIT_CLK when does the data at the output of the ERPB FPGA become valit ? WRT XMIT_CLK when does the latch at the output of the ERPB card update ? WRT XMIT_CLK when does the data latch on the DC update ? WRT XMIT_CLK when does the Data Strobe signal from the DC have an active edge ? Is it off by a whole integer ? The basic Run II cycle Writing into the FIFO: First write the Tot Et data and then the EM Et data into the FIFO. On the rising edge of EM/Tot_bar increment the Write Address Counter. The Tot_Write_Enable is asserted in the middle of the period with EM/Tot_bar high. The EM_Write_Enable is asserted in the middle of the period with EM/Tot_bar low. This sounds backwards but is correct because the data is shifted as it goes through the input latch and 9->8 packer. Neither of the Write_Enables is asserted if the Capture_Data signal is asserted. To capture data: Capture data will be asserted for two cycles of the EM/Tot_Bar signal. This is to give time for the Read Address to make it through the address selector mux and the latch at the output of the mux and to the FIFO array, i.e. the FIFO Address is pipelined. Capture_Data changes state only at the rising edge of EM/Tot_Bar signal. The state of the Capture_Data signal changes only at the time of the rising edge of the EM/Tot_bar signal, i.e. at the end of a complete write cycle for the L1 Cal Trig processing of a beam crossing. So on the rising edge of EM/Tot_bar when the Capture_Data becomes asserted, the Write Address Counter will increment. It is OK for the Write Address Counter to increment at this time because the FIFO Address Lines are changing state anyway (because the FIFO Address Mux is changing from write address to read address in responce to Capture_Data now being asserted). Neither of the Write_Enables are asserted at this time (or at any time during the period when the Capture_Data signal is asserted) so it is an OK time to change FIFO addresses lines. When the Capture_Data signal is asserted and the EM/Tot_bar signal is low, then the Input_Clock is gated through to the capture data latches and clocks data from the FIFO output into them. There has been plenty of time for the correct read address to setup before the capture data latches are clocked. Note that it is only during the 2nd EM/Tot cycle with Capture_Data asserted that the Read Address is actually present at the FIFO array. Re-Work of the U34 ERPB Transmit PAL The Run I Transmit GAL can not be used on the ERPB cards because it delays the "GO" to the next ERPB below by one tick of the Xmit_Clk. That was OK in Run I but now all of this is pipe-lined in the Readout State Engine to allow the whole system to run faster so this one Xmit_Clk delay must be removed from the PAL. This leaves basically nothing for this PAL to do so it will be replaced with just a wired header. The setup of this header is shown below. Note that Steve Pier did a nice job and all off card I/O to the LCA's will still go through buffer chips. ERPB Transmit PAL Wire List Pin # 5 to Pin # 19 ! This takes the LCA RO signal on GI_3 ! which arrives on pin #5 to pin #19 ! which is the DDCO_0 signal on its way ! to the below ERPB. Pin # 7 to Pin # 14 ! This takes the LCA Dly_2_RO signal on GI_1 and to Pin # 15 ! which arrives on pin #7 to pin #14 ! which is the Buf_OE\ signal on this ERPB ! and to pin # 15 which is the ROEO signal ! to the ERPB below. Pin # 8 to Pin # 23 ! This takes the DDCI_0 signal from the above ! ERPB to the GO_0 signal to the Readout ! State Engine on LCA #1 on this ERPB. Pin # 12 to Pin # 16 ! This takes GND to UDCO_1 and to Pin # 17 ! and to UDCO_0 and to Pin # 18 ! and to DDCO_1 and to Pin # 20 ! and to GO_3 and to Pin # 21 ! and to GO_2 and to Pin # 22 ! and to GO_1 ============================================================================ ============================================================================ ============================================================================ Old (no longer correct) stuff from the initial design of the Run II ERPB This is very different from what is described above. These diagrams do not represent how the system actually works. Following is the timing diagram for ERPB FPGA Data Capture at 132 ns: | Tick 1 | Tick 2 | Tick 3 | |<- 396 ns ->| 56.4 ns?->| |<- or |<- 132 ns ->| 18.8 ns ->| |<- _ _ _ _ Tick_Clock _____| |___________| |___________| |___________| |_______ _ _ _ _ _ _ _ _ Input_Clock _|E|_____|T|___|E|_____|T|___|E|_____|T|___|E|_____|T|___ ____ ____ ____ ____ ____ ____ ____ ____ CTFE_PAD X_E0_XXXX_T1_XX_E1_XXXX_T2_XX_E2_XXXX_T3_XX_E3_XXXX_T4_XX _____ _____ _____ _____ _ EM/Tot_Bar |_______| |_______| |_______| |_______| ___________________________ Capture_Data ___________________| |_________ --- signals generated internally --- ____ _______ _____ _______ _____ _______ _____ _______ __ EM_Tot_Unp T0__X_E0____X_T1__X_E1____X_T2__X_E2____X_T3__X_E3____X__ ____ _______ _____ _______ _____ _______ _____ _______ __ EM_Tot_Packed E-1_X_T0____X_E0__X_T1____X_E1__X_T2____X_E2__X_T3____X__ ____ _____________ _____________ _____________ ___ ______ Write_Addr _31_X___0_________X___1_________X___2_________X___3______ _ _ Tot_WE _________| |_______________________________________| |___ _ _ EM_WE _| |___________| |_______________________________________ ____ _____________ _____________ _____________ ___ ______ FIFO_Addr _31_X___0_________X_1-ofst_(TT)_X_2-ofst_(OT)_X___3______ _____________ Capture_Clock _____________________________| |_____________ (rising edge: Capture TT, falling edge: Capture OT) Note that this FPGA does not actually receive the Tick Clock, it is only shown for reference. Following is the timing diagram for the beginning of the ERPB FPGA Readout (example is FPGA #1, normal positive eta): |<- 132 ns ->| 18.8 ns ->| |<- _ _ _ _ _ _ _ _ Xmit_Clk _| |_____| |___| |_____| |___| |_____| |___| |_____| |___ ____________________________________________ RI (DDCI_0) ____________| --- signals generated internally --- ________________ _______ _____ _______ _____ _______ ____ RO_Ctr __0_____________X__1____X__2__X__3____X__4__X__5____X__6_ ________________ _____ ___ _____ ___ _____ __ XDATA __0_____________XXX_1___XXX_2_XXX_3___XXX_0_XXX_1___XXX_2 ________________________ _____ _______ _____ _______ ____ XDATA_Lat __0_____________________X__1__X__2____X__3__X__0____X__1_ ___________________________ XDATA_OE ________________| |____________ __ _____ __ __ __ ____ __ _ XDATA_PAD ZZZZZZZZZZZZZZZZ__0_____X__1__X__2____X__3_ZZZZZZZZZZZZZZ RO_Ctr_TC _________________________________________________________ RO _________________________________________________________ NE/TE_Bar _________________________________________________________ --- signals driven to the Above Daisy Chain Connector --- _____ _______ _____ _______ ____ DA XXXXXXXXXXXXXXXXXXXXXXXXX_1-0_X_1-1___X_1-2_X_1-3___X_2-0 (LCA # - Data Element #) --- signals driven to the Below Daisy Chain Connector --- DDCO_0 _________________________________________________________ --- signals received from the Below Daisy Chain Connector --- DB XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Following is the timing for the middle of the ERPB FPGA Readout (example is FPGA #2, normal positive eta): |<- 132 ns ->| 18.8 ns ->| |<- _ _ _ _ _ _ _ _ Xmit_Clk _| |_____| |___| |_____| |___| |_____| |___| |_____| |___ _________________________________________________________ RI --- signals generated internally --- __ _______ _____ _______ _____ _______ _____ _______ ____ RO_Ctr __X__3____X__4__X__5____X__6__X__7____X__8__X__9____X__10 __ _____ ___ _____ ___ _____ ___ _____ __ XDATA __XXX_3___XXX_0_XXX_1___XXX_2_XXX_3___XXX_0_XXX_1___XXX_2 __ _______ _____ _______ _____ _______ _____ _______ ____ XDATA_Lat __X__2____X__3__X__0____X__1__X__2____X__3__X__0____X__1_ ___________________________ XDATA_OE ________________| |____________ __ _____ __ __ __ ____ __ __ XDATA_PAD ZZZZZZZZZZZZZZZZ__0_____X__1__X__2____X__3__ZZZZZZZZZZZZZ RO_Ctr_TC _________________________________________________________ RO _________________________________________________________ NE/TE_Bar _________________________________________________________ --- signals driven to the Above Daisy Chain Connector --- __ _______ _____ _______ _____ _______ _____ _______ ____ DA __X_1-1___X_1-2_X_1-3___X_2-0_X_2-1___X_2-2_X_2-3___X_3-0 (LCA # - Data Element #) DDCO_0 _________________________________________________________ Following is the timing for the end of the ERPB FPGA Readout (example is FPGA #7, normal positive eta): |<- 132 ns ->| 18.8 ns ->| |<- _ _ _ _ _ _ _ _ Xmit_Clk _| |_____| |___| |_____| |___| |_____| |___| |_____| |___ _________________________________________________________ RI --- signals generated internally --- __ _______ _____ _______ _____ __________________________ RO_Ctr __X__27___X__28_X__29___X__30_X__31______________________ __ _____ ___ _____ ___ ________________________ XDATA __XXX_3___XXX_0_XXX_1___XXX_2_XXX_3______________________ __ _______ _____ _______ _____ _______ __________________ XDATA_Lat __X__2____X__3__X__0____X__1__X__2____X__3_______________ ___________________________ XDATA_OE ________________| |____________ __ _____ __ __ __ ____ __ __ XDATA_PAD ZZZZZZZZZZZZZZZZ__0_____X__1__X__2____X__3__ZZZZZZZZZZZZZ __________________________ RO_Ctr_TC ______________________________| __________________________ RO ______________________________| ____________ NE/TE_Bar ____________________________________________| --- signals driven to the Above Daisy Chain Connector --- __ _______ _____ _______ _____ _______ _____ _______ ____ DA __X_6-1___X_6-2_X_6-3___X_7-0_X_7-1___X_7-2_X_7-3___X_B1-0 (LCA # - Data Element #) --- signals driven to the Below Daisy Chain Connector --- ________________________ DDCO_0 ________________________________| --- signals received from the Below Daisy Chain Connector --- _______ ____ DB XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_B1-0__X_B1-1