Large Tile Operation in Run IIA ----------------------------------- Original Version: 3-DEC-2003 Current Version: 10-DEC-2003 The purpose of this file is to recall the details about how the Large Tile system works and to document how it has be re-setup for operation in Run IIA. Basic Large Tile Operation In order to operate the Large Tile system you need to do 2 lookups in the Momentum PROM's. The first lookup is for Px and Py and the second lookup is effectively for Total Et for the Large Tile calculation. The Tier 2 LTCC cards must capture the output from from the Tier 1 Momentum CAT2 cards when they are processing the second lookup data. Note that in the Momentum Adder Tree only the CTFE cards and the Tier 1 Momentum CAT2 cards need to process the two Momentum Lookups. The Momentum Tree Tier 2 and Tier 3 CAT cards and the FMLN card only need to process the first Momentum Lookup. Run I Documentation File to Review Include: www.pa.msu.edu/hep/d0/ftp/run1/l1/caltrig/cards/ ltcc_description.txt www.pa.msu.edu/hep/d0/ftp/run1/l1/caltrig/cabling/ large_tile_cables.txt large_tile_installation.txt large_tile_tier_3_to_and_or_terms.txt www.pa.msu.edu/hep/d0/ftp/run1/prog_dev/LTCC/ # 7 files # Large Tile Collection Card Review This card uses the following timing signals: T&SS A Write A/B T&SS B Latch-Shift T&SS C Read A/B T&SS H Input Latch Clock The LTCC Card uses 100328's for its signal latches. These chips have 3 control signals: OE, DIR, and LE. These are all ECL input level pins. They operate as follows: When OE is LOW then the ECL side is Cut-Off and the TTL side is Tri-State. When OE is HIGH then the output is enabled on the side selected by the DIR pin. When DIR is LOW then the ECL side is Input and the TTL side is Output. When DIR is HIGH then the TTL side is Input and the ECL side is Output. When LE is LOW the Latch is Transparent. When LE is HIGH the Latch holds the value that was setup when it made the transistion from Low to HIGH. But note that the circuit on the LTCC Card that receives T&SS H the Input Latch Clock inverts this Timing and Control Signal. Thus as a card it works as follows: When T&SS H is HIGH the Input Latch is Transparent. When T&SS H is LOW the Input Latch Holds. The Input Latch captures the value that was setup when T&SS H makes the HIGH to LOW transition. Timing and Control of the Large Tile System Run I CTMBD setup **** T2 Backplane WITH LTCC **** **** low ETA: Racks M105, M109 **** CAL. SPECIFIC TRIG. BACK MTG PLANE CHANNEL TIMING NUMBER SIGNAL FUNCTION ------- ------- --------------------------------------------------------- 15 TSS-A,B,C, D,E,F Count Operand Latch Clock Tier 2 used by Counter CAT2's 30 TSS-G,H Large Tile Latch Clock Tier 2 used by LTCC's 6 TSS-J Write A/B Control for 29525's used by LTCC's 5 TSS-K Latch/Shift 29525's used by LTCC's 4 TSS-L Read A/B Control for 29525's used by LTCC's -- TSS-M SPARE not routed 26 TSS-N,P Momentum Operand Latch Clock Tier 2 for Momentum CAT2's 18 TSS-R,S Energy Operand Latch Clock Tier 2 used on Energy CAT2's *** high ETA: Rack M111 *** CAL. SPECIFIC TRIG. BACK MTG PLANE CHANNEL TIMING NUMBER SIGNAL FUNCTION ------- ------- --------------------------------------------------------- 15 TSS-A,B Count Operand Latch Clock Tier 2 used by Counter CAT2's 30 TSS-C Large Tile Latch Clock Tier 2 used by LTCC's 6 TSS-J Write A/B Control for 29525's used by LTCC's 5 TSS-K Latch/Shift 29525's used by LTCC's 4 TSS-L Read A/B Control for 29525's used by LTCC's -- TSS-G SPARE routed to slot #3 -- TSS-H SPARE routed to slot #2 -- TSS-M SPARE not routed 26 TSS-N,P Momentum Operand Latch Clock Tier 2 for Momentum CAT2's 18 TSS-R Energy Operand Latch Clock Tier 2 used on Energy CAT2's **** T3 Backplane WITH LTCC **** CAL. SPECIFIC TRIG. BACK MTG PLANE CHANNEL TIMING NUMBER SIGNAL FUNCTION ------- ------- --------------------------------------------------------- 27 TSS-N Momentum Operand Latch Clock Tier 3 for Momentum CAT3's 28 TSS-E FMLN Clock used by the Final Momentum Logic Network 19 TSS-A,R Energy Operand Latch Clock Tier 3 1st Lookup Energy CAT3's 20 TSS-S Energy Operand Latch Clock Tier 3 2nd Lookup Energy CAT3's 21 TSS-G Energy Operand Latch Clock Tier 3 1st Lookup Total Et CAT3 22 TSS-H Energy Operand Latch Clock Tier 3 2nd Lookup Total 2nd CAT 16 TSS-B,C,D Count Operand Latch Clock Tier 3 used by Counter CAT2's 6 TSS-J Write A/B Control for 29525's used by LTCC 5 TSS-K Latch/Shift for 29525's used by LTCC 4 TSS-L Read A/B Control for 29525's used by LTCC 30 TSS-F Large Tile Latch Clock Tier 3 used by LTCC !! is MTG Ch #30 correct for Tier 3 LTCC Clk - shouldn't it be #31 ?? Backplane Cables for AM29525 Control The LTCC cards use 29525's to make their input data available for C-Bus readout. They need the stardard 29525 control signals: Write A/B Read A/B Latch/Shift. But these control signals are not a standard part of either the Run I Tier 2-3 crates or of the Run IIA Tier 2-3 Timing and Control signal bus cable. In the Tier 2-3 crates the Write A/B Read A/B Latch/Shift actually come off the CTMBD on one set of pins and are then jumpered to the correct backplane pins at the socket that holds the LTCC card(s). From the LTCC card document, " TSS-A, TSS-B, and TSS-C arrive on this card on J3 (via the CAT3 paddleboard) rather than on J4. Recall that a CTT2BP provides only TSS-H to each slot". For Run IIA we want to use the same Write A/B Read A/B Latch/Shift signals for the Tier 1 bus as for the Tier 2-3 bus. Run I Timing Setup for Large Tiles: From the Tier 1 Momentum CAT2 card updating its input latch with second lookup data to the Tier 2 LTCC input latch moving to Hold was 5 x 37.66 nsec = 188.3 nsec From the Tier 2 LTCC input latch moving to Hold to the Tier 3 LTCC input latch moving to Hold was 4x 37.66 nsec = 150.6 nsec. Run IIA Timing Signals for Large Tiles: The "Counter Tree Tier 3 Clock" looks just right for the Tier 3 LTCC Input Latch Clock. This is a once per 396 nsec clock that would cause the Tier 3 LTCC card to directly generate And-Or Terms with the correct timing to fit the "standard" L1 Cal Trig And-Or Input Term Strobe signal. The Tier 2 LTCC Input Latch Clock signal is a problem. To prevent a race with the Tier 3 LTCC the Tier 2 must not move to Transparent until after the Tier 3 LTCC moves to Hold. But by then the Tier 1 Momentum CAT2 cards are almost getting ready to have their input D Latches clocked. Cable Lenght and Timing Delta's See the following file for information about the cable length to the Tier 2-3 crates and the timing skew between Tier 1 and Tier 2-3. www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/timing/ cal_trig_momentum_tree_timing.txt I need to double check all of this. A good thing to measure would be the Tier 1 Energy Adder CAT2 Clock in the Tier 1 crates vs the Tier 2 Counter Tree CAT2 Clock in the Tier 2 crates. In the Tier 1 crates the Tier 1 Energy Adder CAT2 Clock is driven by CTMBD Backplane T&SS signal "P". In the Tier 2 crates the Tier 2 Counter Tree CAT2 Clock is driven by CTMBD Backplane T&SS signal "A,B,C,D,E,F" In the Tier 3 crate the Tier 2 Counter Tree CAT2 Clock is driven by CTMBD Backplane T&SS signal "N" Momentum PROM Lookup Page for Large Tile Operation Recall what is in the Run IIA CTFE Momentum PROM's +-------+-------+---------+--------+------+----------------------------------+ |TT |Zero |Symmetric|Transfer|Page |Page | |Eta |Energy |Energy |Slope |Number|Usage | |Magn |Resp |Cut | | | | |Range |[Count]|[GeV] |[float] |[0..7]| | +-------+-------+---------+--------+------+----------------------------------+ | (1:20)| 8 | None |Cos(Phi)| 0 |1st Lookup= Px - opt#1 | | | | | | | | | (1:16)| 8 | 1.00 |Cos(Phi)| 1 |1st Lookup= Px - opt#2 | |(17:18)| 8 | None | None | 1 |1st Lookup= Px - opt#2->No Contrib| |(19:20)| 8 | 1.00 |Cos(Phi)| 1 |1st Lookup= Px - opt#2 (ICD+MG)| | | | | | | | | (1:12)| 8 | 1.50 |Cos(Phi)| 2 |1st Lookup= Px - opt#3 | |(13:16)| 8 | 2.00 |Cos(Phi)| 2 |1st Lookup= Px - opt#3 | |(17:18)| 8 | None | None | 2 |1st Lookup= Px - opt#3->No Contrib| |(19:20)| 8 | 2.00 |Cos(Phi)| 2 |1st Lookup= Px - opt#3 (ICD+MG)| | | | | | | | | (1:12)| 8 | 2.00 |Cos(Phi)| 3 |1st Lookup= Px - opt#4 | |(13:16)| 8 | 3.00 |Cos(Phi)| 3 |1st Lookup= Px - opt#4 | |(17:18)| 8 | None | None | 3 |1st Lookup= Px - opt#4->No Contrib| |(19:20)| 8 | 3.00 |Cos(Phi)| 3 |1st Lookup= Px - opt#4 (ICD+MG)| +-------+-------+---------+--------+------+----------------------------------+ | (1:16)| 8 | None | 1.0 | 4 |2nd Lookup= LrgTile-opt#1 | |(17:18)| 8 | None | None | 4 |2nd Lookup= LrgTile-opt#1->NoContr| |(19:20)| 8 | None | 1.0 | 4 |2nd Lookup= LrgTile-opt#1 (ICD+MG)| | | | | | | | | (1:16)| 8 | 1.00 | 1.0 | 5 |2nd Lookup= LrgTile-opt#2 | |(17:18)| 8 | None | None | 5 |2nd Lookup= LrgTile-opt#2->NoContr| |(19:20)| 8 | 1.00 | 1.0 | 5 |2nd Lookup= LrgTile-opt#2 (ICD+MG)| +-------+-------+---------+--------+------+----------------------------------+ | (1:20)| 8 | None | None | 6 |Special/Diagnostics= constant 8's | | (1:20)| 8 | None | 1.0 | 7 |Special/Diagnostics= one-to-one | +-------+-------+---------+--------+------+----------------------------------+ Note that depending on what Momentum page we want to use for the first lookup (to do Missing Et) we may need to change the www on the Tier 1 CTMBD's so that we get the page that we want for the second lookup for Large Tiles. Currently 10-DEC-2003 Momentum Page Select Address Line MSBit is Low for the first lookup and Hi for the second lookup. The MidBit and LSBit are static and set by a Run I MTG. The strong guess is that we want Momentum page #5 for the Large Tile lookup. If we use Page #1 for the Missing Et lookup then everything is simple but it is likely that we may want page #2 or page #3 for the Missing Et lookup which would require www work on the Tier 1 CTMBD's. The test run of Mising Et trigger done in beam on 4-SEPT-2003 used Momentum Lookup Page #2 At this time 10-DEC-2003 just for tests without needing to change the www on the CTMBD we can run either: Momentum Page #0 for first lookup for Missing Et Momentum Page #4 for second lookup for Large Tiles or Momentum Page #1 for first lookup for Missing Et Momentum Page #5 for second lookup for Large Tiles We have 8 And-Or Input Terms assigned for Large Tiles, AOT 152:159 Recall that the Large Tile "Count Thresholds" are NOT programmable. At Tier 3, for each of the 8 Large Tile Ref Sets, there is a separate output for: >= 1 LT over threshold, >= 2 LT's over threshold, and >= 3 LT's over threshold. We have only 8 And-Or Term Inputs to use. So for now let's connect the >= 1 and the >= 2 comparator outputs for the first 4 Large Tile Ref Sets. Specifically: And-Or Term Comes from Tier 3 LTCC Card J8 Pins ----------- ---------------------------------------------------- 152 LT Ref Set #0 >= 1 LT over threshold Pins: 1-2 153 LT Ref Set #0 >= 2 LT over threshold Pins: 3-4 154 LT Ref Set #1 >= 1 LT over threshold Pins: 9-10 155 LT Ref Set #1 >= 2 LT over threshold Pins: 11-12 156 LT Ref Set #2 >= 1 LT over threshold Pins: 17-18 157 LT Ref Set #2 >= 2 LT over threshold Pins: 19-20 158 LT Ref Set #3 >= 1 LT over threshold Pins: 25-26 159 LT Ref Set #3 >= 2 LT over threshold Pins: 27-28