Trigger Tower Readout Hardware Path ----------------------------------- Original: 27-APR-1999 Latest: 27-APR-1999 Background ---------- The purpose of this file is to describe the hardware path used to read out Trigger Tower data from the L1 Cal Trig. The hardware components in this path are: - CTFE's which provide Trigger Tower data to the ERPB's - ERPB's, which store the Trigger Tower data until the L1 Accept - DC's, which provide timing and control signals to the ERPB's, and pass the Trigger Tower Data from the ERPB's to the Bougie - Bougie's, which convert the parallel copper data into serial fiberoptic data (G-link) and transmit this data to the VRB's. - VRB's, which receive this data and provide it to L2/L3 Below I will discuss each hardware component in more detail. Hardware Components ------------------- 1. CTFE's The Run I CTFE cards are carried forward into Run II. Their operation is described in detail in the Run I L1 Cal Trig documentation. This operation remains fundamentally the same during Run II. No changes in any programmable logic or the basic circuit board are planned. 2. ERPB's The Run I ERPB cards are also carried forward into Run II. No changes in the circuit boards are planned. The FPGA logic used for these cards must be changed from the Run I logic. The FPGA's themselves (XC4002A) are (barely) large enough to hold the new logic. The new logic is described in detail in the file: MSUTRGROOT_II:[CAL_TRIG]ERPB_FPGA.TXT The ERPB's contain two GAL's (U34 Transmit GAL, and U35 Fault GAL). The new FPGA logic is fully compatible with the current Transmit GAL, and the Fault logic is not used in Run II (just as it was not used in Run I). Therefore, the two GAL's DO NOT need to be modified. The ERPB's thus need NO physical modification for Run II. They need not be touched at all. 3. DC's The Run I DC cards are also carried forward into Run II. However, some number of circuit board modifications, as well as some new GAL logic, may be required. The details of this work are described in the file: MSUTRGROOT_II:[CAL_TRIG]DC_CARD_RUN_I_TO_RUN_II.TXT The biggest DC issue for Run II is how to deliver Timing Signals from Carmen/Calorimeter Helper to the DC. In Run I a large number of MTG channels were used. For Run II a different solution is required. Ideally the DC could "parasite" all necessary Timing Signals from the CTBP Tier 1 Backplane timing signals. Recall the Timing Signals required by the ERPB/DC: Signal Name "MTG" Source Needed for Note ----------- ----- ------ ---------- ---- INPUT_CLK 0 [Carmen] 396 ns running 1 XMIT_CLK [Carmen] 396 ns running 1 2X_Clock [Carmen] 132 ns running 1 EM/Total_Bar 1 [Carmen] 132 and 396 ns Capture_Data 2 [Helper] 132 and 396 ns Second_Tick 3 [Helper] 132 and 396 ns Two_Tick_Readout 4 [Helper] 132 and 396 ns 2 DC_Config_FPGAs 7 [Helper] 132 and 396 ns DC_Altreg_Select 8 [Helper] 132 and 396 ns 3 DC_Register_Clock 9 [Helper] 132 and 396 ns Notes: 1. Either 2X_Clock, or INPUT_CLK and XMIT_CLK are required. On the ERPB, XMIT_CLK or 2X_Clock must be distributed via DST(0). This will require modification on the DC (see above) to allow "MTG" type generation of this signal 2. This could in principle be a switch or register on the DC, as it does not change rapidly 3. I think we could always leave this LOW and not burn a Timing Signal This is between 7 and 9 Timing Signals. How many Timing Signals are unused in a CTBP Tier 1 Backplane? Signal Name CTBP Net Destination Note ----------- -------- ----------- ---- Write A/B A CTFE, CHTCR 1 Latch/Shift B CTFE, CHTCR 1 Read A/B C CTFE, CHTCR 1 Engy Map Sel LSB D CTFE Engy Map Sel MDB E CTFE X Clock F CTFE 2X Clock G CTFE ADC Clock H CTFE Engy Map Sel MSB J CTFE Mntm Map Sel LSB K CTFE Mntm Map Sel MDB L CTFE Mntm Map Sel MSB M CTFE Moment CAT2 Clock N CAT2 (Moment) Energy CAT2 Clock P CAT2 (Energy) CHTCR Input Clock R CHTCR Spare S CHTCR, CAT2 Notes: 1. These 3 signals are used only to control the 29525's on the CTFE and CHTCR. They can be freed up for other uses if the 29525's are not used. This still only looks like 1-4 available Timing Signals. So we don't have enough free Timing Signals on the CTBP to run the DC/ERPB. This means that we will need another Timing Signal path into the Cal Trig, which will need to be synchronized with the primary Cal Trig timing path (a non-trivial issue). 4. Bougies The Bougie is really just a Run II "Build A" AONM card with a special FPGA in the BSF site. The 16-bit data, plus a strobe, arrive on the P5 Global I/O connector on a 34-conductor cable. Note that the DC actually uses a 40-conductor output connector, but only pins 1-34 are actually used. The details of the Bougie FPGA are described in the file: MSUTRGROOT_II:[CAL_TRIG]BOUGIE_FPGA.TXT Ten Bougies will be required. They will be housed in the Cal Trig Readout Crate in M101 (?). This crate will require several P1 Timing Signals: BX_Rate Clock (e.g. Tick_Clock) Accelerator_Rate Clock (i.e. 53 MHz) The output of each Bougie is a G-link fiberoptic cable. These are routed to 3 VRB cards as follows: link link link link VRB 0/1 2/3 4/5 6/7 eta range --- ---- ---- ---- ---- --------- "A" ---- M112 M110 M108 -20 : -9 "B" M106 M104 M103 M105 -8 : +8 "C" M107 M109 M111 ---- +9 : +20