Timing and Control Signals to Run the Calorimeter Trigger Readout - Including Both ERPB Signals and M101 Mid Crate Signals ------------------------------------------------ Original Rev. 23-MAR-01 Current Rev. 13-NOV-03 Timing & Control Signals from the Master Clock to the M101 P1 Backplanes Selector-FanOut #4 distributes Master Clock Sequencer #1 timing signals to M101 Middle and M101 Bottom crates to support Calorimeter Trigger Readout. Note this is Sequencer #1. SFO #4 is setup for a rational set of Time Lines and P_Clk. The output from SFO #4 runs on two 26 conductor cables from it to TOM_PB's in the M101 Mid and M101 Bot crates, i.e. SFO #4 is makeing the P1_TS_0 : P1_TS_4 for these two crates. 26 Conductor Cables Carmen Master Clock to M101 TOM_PB's Slot #1 Selector Fanout #4 to the M101 Middle TOM_PB J2 Slot #1 Label: M101M Selector Fanout #4 to the M101 Bottom TOM_PB J2 Slot #1 Label: M101B This results in the following set of timing signals in these two crates: Selector FanOut Sequencer #1 Time Line Channel P1_TS -------------------------------- -------- ------- P_Clock 53 MHz PClk P1_TS_0 TL_3 Live Accel BX Marker 0 P1_TS_4 TL_2 Beginning of Turn Marker 1 P1_TS_3 TL_1 TRM Tick Clk 2 P1_TS_2 TL_0 Trig FW Tick Clk 3 P1_TS_1 In addition the the above Sequencer #1 timing signals, Sequencer #2 (the Calorimeter Trigger Sequencer) provides the following timing signals to just the M101 Middle crate. These two signals are carried on single signal twisted pair cables directly from the Sequencer #2 front panel to the M101 Middle Slot #1 TOM_PB. Can Be Used by Master Clock M101 Middle Enters M101 Distributed Quad-Term Sequencer #2 P1 Backplane Middle Crate to Main Array CTOM Time Line Timing Signal on TOM_PB on HQ_TS_ as ------------ ------------- ------------- ------------- ------- CMC_TL_16 P1_TS_6 J3 pins 11&12 HQ_TS_2 In_Clk CMC_TL_17 P1_TS_12 J4 pins 15&16 HQ_TS_1 Out_Clk Timing & Control Signals from the Cal_Trig_Readout_Helper to the M101 P1 Backplanes The Cal_Trig_Readout_Helper FPGA (on an FM card in slot 21 of M101 Middle) generates a number of timing & control signals that are distributed to M101 Middle and M101 Bottom P1 Backplanes. The Cal Trig Readout Helper is implemented as FPGA Site #4 on an FM card in Slot 21 of Crate M101 Middle. Front panel outputs from this FPGA are routed to the M101 P1 Backplanes as described in the following table. Cabling from the CT_Read_Helper Front Panel Output to the TOM_PB's in the M101 Middle and Bottom Crates ------------------------------------------------------- Source Destination CT_Read_Helper M101 Middle Signal Function Front_PB Slot #1 TOM_PB -------------------- --------------------- ------------------------ Trans_HSRO_Data MSA_Out_0 pins 1,2 P1_TS_8 J5 pins 7,8 Capture_HSRO_Data MSA_Out_1 pins 3,4 P1_TS_9 J4 pins 3,4 Capture_Monitor_Data MSA_Out_2 pins 5,6 P1_TS_10 J4 pins 7,8 Scaler_Reset MSA_Out_3 pins 7,8 P1_TS_15 J5 pins 15,16 Source Destination CT_Read_Helper M101 Bottom Signal Function Front_PB Slot #1 TOM_PB -------------------- --------------------- ------------------------ Trans_HSRO_Data MSA_Out_6 pins 13,14 P1_TS_8 J5 pins 7,8 Capture_HSRO_Data MSA_Out_7 pins 15,16 P1_TS_9 J4 pins 3,4 Capture_Monitor_Data MSA_Out_8 pins 17,18 P1_TS_10 J4 pins 7,8 Scaler_Reset MSA_Out_9 pins 19,10 P1_TS_15 J5 pins 15,16 Recall that the Cal_Trig_Readout_Helper has a number of other output signals that are routed to the Distributor_Cap and ERPB's. These Cal_Trig_Readout_Helper output signals are covered in the Cal_Trig_Readout_Helper documentation and the Distributor_Cap and ERPB documentation. Input signals to the Cal_Trig_Readout_Helper The Cal_Trig_Readout_Helper (FPGA Site #4 on an FM card in Slot 21 of Crate M101 Middle) has a number of input signals. The input signals to it come from 3 sources: SF0 #8 (Sequencer #1), the Trigger Framework, and Sequencer #2 (the Cal Trig Sequencer). Inputs to the Cal_Trig_Readout_Helper FPGA from Sequencer #1 The Cal_Trig_Readout_Helper receives the Helper_Clock from SFO #8 via a 26 conductor cable to a Rear_PB on P2 at the M101 Mid slot #21. SFO #8 is the "Helper B" Selector Fanout. The principal signal that the CT_Read_Helper receives from SF0 #8 is the Sequencer #1 Helper_Clock. The CT_Read_Helper receives Helper_Clock on its MSA_Input_51 input. The following table shows the full set of signals that are carried from SFO #8 to the Cal_Trig_Readout_Helper. Selector Fanout #8 "Helper B" to J5 of the Rear_PB on P2 at Slot #21 M101 Middle. Cable Label: M101_Help Selector Cal_Trig Sequencer #1 FanOut Readout Time Line Channel Helper ---------------------------- -------- --------- P_Clock 53 MHz (Disabled) PClk MSA_In_49 TL_4 Cosmic Gap Marker 0 MSA_In_57 TL_5 Sync Gap Marker 1 MSA_In_55 TL_6 Spare Marker 2 MSA_In_53 TL_7 Trig FW Helper Clock 3 MSA_In_51 Note MSA_In_51 is pin 239 on FPGA Site #4 which is a secondary clock net. Inputs to the Cal_Trig_Readout_Helper FPGA from Sequencer #2 The Cal_Trig_Readout_Helper receives the following two signals directly from the front panel of Sequencer #2. These two signals are carried on single signal twisted pair cables from Sequencer #2 front panel to the Rear_PB on P2 at M101 Middle Slot #21. Cal_Trig Sequencer #2 Time Line Readout Helper -------------------------------------- -------------- Sequencer #2 TL_20 ERPB_Input_Clock MSA_In_21 Sequencer #2 TL_21 ERPB_EM/Tot_Sel MSA_In_19 Note MSA_In_19 is pin 57 on FPGA Site #4 which is a secondary clock net Inputs to the Cal_Trig_Readout_Helper FPGA from the Trigger Framework These two signals are carried on single signal twisted pair cables from the Trigger Framework to the Rear_PB on P2 at M101 Middle Slot #21. Cal_Trig Signal from the Trigger Framework Readout Helper ------------------------------------- -------------- L1_Accept for Geographic Section 126 MSA_In_0 L1_Period MSA_In_1 Both the L1_Accept signal and the L1_Period come from the distribution box in the back of M123. The L1_Accept signal is just buffered in the distribution box. The L1_Period signal is just a buffered copy of L1_Fired_Strobe. \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\///////////////////////////// The following sections are background material which is generally up to date and correct. \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\///////////////////////////// Currently the M101 Bottom Crate is being used for the Routing Master. There are a number of private P1_TS_ in that crate that support the operation of the Routing Master. This is all covered in the Rounting Master documentation. see: www.pa.msu.edu/hep/d0/ftp/l1/framework/l3_interface/ ======================================================================== Sequence of Actions with each L1_Accept ---------------------------------------- The general idea is that when there is a L1_Acpt to the Cal Trig Readout we need the following to happen: Quicklyly send a Capture HSRO Data signal. This signalis used by the CTRO Cards in the standard way that the Capture HSRO Data signal is used by the cards in the Trigger Framework that do HSRO readout. The Capture HSRO Data signal used by the Spark cards as its "L1_Acpt" which starts them sending out their 6 words of Header data. The data from the ERPB can not arrive at the Spark before this Header information is completely sent out. Quickly send an ERPB Capture signal to the ERPB's via the Distributor Cap. This will cause the ERPB's to capture data at their FIFO output for transmission to the Sparks. The exact point in time when the ERPB Capture signal is issued controls which Beam Crossing's data will be readout. Issuing the ERPB Capture signal by the CT_Readout_Helper is controlled in the following general steps: L1_Period AND L1_Acpt_to_this_Geographic_Section --> L1_Accept L1_Accept clock in by BX_Clock --> ERPB_Capture ERPB_Capture sets a "1" that is picked up by the next ERPB_EM%Tot positive edge and makes --> ERPB_Capture_Pad ERPB_Capture_Pad remains asserted for 2 full cycles or ERPB_EM%Tot See the CT_Readout_Helper FPGA design for the full details of generating the ERPB Capture signal. Basically the L1_Acpt must be transfered from the BX_Clk domain (TFW clock domain) to the ERPB clock domain. This must be done in a way that always captures the correct Beam Crossing's data independent of wheather the L1_Acpt came before or after the timing jump that happens during the Gaps between Super Bunches. Remember that for a give Super Bunch some of the possible resulting L1_Acpt's come before the next Gap's timing jump and some of the L1_Acpt's come after the Gap's timing jump. After waiting ?? ticks delay, send a "Transmitt Trigger" signal to the Distributor Caps. This will cause the Distributor Caps to start the transport of their ERPB data to the Sparks's. This can not start immediately because we need to give the Spark''s time to send out their Header information before any ERPB data reaches the Spark's. The Header is 6 words of 16 bits so this can not take longer than 6 x 132 = 792 nsec i.e. 6 ticks. We also can not let the "Transmit Trigger" reach the Distributor Cap before the ERPB's have completed Capturing the data at the FIFO output. Capturing that data takes two cycles of the ERPB_EM/Tot_Sel. After waiting 2 ticks send out the Transport HSRO signal. This is used by the CTRO cards in the standard way that readout from the Trig FW works. A 2 tick spacing between Capture HSRO and Transport HSRO is used in the Trig FW. ======================================================================== P1_TS to HQ_TS and General setup of HSRO --------------------------------------------- The file that describes the P1_TS to HQ_TS and BSF internal signals mapping as used in the Trigger Framework is: http://www.pa.msu.edu/hep/d0/ftp/l1/framework/timing/ timing_signals_required_vs_fpga.txt The BSF FPGA description file explains what P1_TS_m can be routed to what HQ_TS_n. One constraint is that Transport_HSRO_Data must come from P1_TS_8 and Capture_HSRO_Data must come from P1_TS_9. Transport_HSRO_Data is used internally in the BSF FPGA. Capture_HSRO_Data is carried from the BSF to the Main Array FPGA's over a denticated trace, i.e. not over a HQ_TS_ trace. The best way to setup the Cal Trig readout is to have the crated in M101 mid and bot setup with the same P1_TS_ as are used in the Trigger Framework. Setup the BSF in the same way as the Trigger Framework. ======================================================================== Size of the L1 Cal Trig Data from each Rack ------------------------------------------- L1 Cal Trig HSRO Data Format 6 words of Header 128 words of TT data 8 words of EM Et Mask 8 words of Jet Et Mast 2 words of Trailer All words are 16 bit words. This is a total of 152 words or 19 alpha 128 bit objects. Recall that the Trig FW readout is: 2 words of Header 2 words from each of 16 Main Array FPGA's 4 words of Board Support FPGA data 2 words of Trailer All words are 16 bit words. This is a total of 40 words or 5 alpha 128 bit objects. So the L1 Cal Trig G-Links have about 4 times as much data to carry as the Trig FW G-Links. =========================================================================