Run II Calorimeter Trigger Timing Generation and Distribution ------------------------------------- Initial Rev. 19-JUL-1999 Current Rev. 24-APR-2001 Accurate generation and distribution of timing signals into the Calorimeter Trigger is a critical part in making the Cal Trig work in Run II. To properly sample the BLS Trigger Pick-Off signals the ADC clock timing must be very accurate. To complete the required logic operation every 132 nsec the timing of the various clock signals over the 10 rack size of the Cal Trig must be accurate. There is very little error budget for the timing signals. You can also think about the BLS Trigger Pickoff Signals being a 132 nsec long ramp so a 1 nsec jitter in the ADC Clock is a 1% jitter in the measurement of the Trigger Tower Energy. We should have a Carmen Sequencer to generate the basic timing signals for the Cal Trig. By itself this can make 1 copy each of 23 "Time Lines". These are provided in differential ECL on the front panel of the Sequencer. The basic plan is then to have a fanout and run a separate flat cable to each consumer of Cal Trig timing signals. The Fanout could be clocked to maintain the accuracy of the timing signals. Consumers of Cal Trig Time Signals: 20x Tier 1 Crates 3x Tier 2 Crates 1x Tier 3 Crate 1x Readout 9U Crate Bougie and CTRO (possible) 1x Timing Monitoring Connection In total it looks like we should be prepared to make 26 copies of the Cal Trig Timing Signals. Will all cables going to the consumers be the same ? i.e. same timing signal on the same twisted pair in the flat cable Could use the Run 1 Framework TLM cards to make a 1:4 timing fanout. These cards have some advantages and disadvantages. Advantages: They are a 1:4 Fanout They have a latch so the signals can be "re-timed" to keep them accurate. Some of these cards have their "H" series ECL gates replaced with standard series gates. We could house these cards in the Run I FW style backplane in the top of M103 along with the COMINT card. Disadvantages: These cards are an early (and very bad) 2 sided ECL layout. In places these cards have the ECL pull down terminators at the wrong end of the lines. TLM's at MSU 19-JUL-1999 02, 03, 04, 06, 13, 14, 16 None of these have their "H" parts replaced with standard series parts. TLM's that the Inventory book says have had their "H" parts replaced with standard series parts 01, 05, 07, 08, 12, 17, 18?, 21, 22, 23, 24 I believe that all of these also have Cu sheeting over the parallel distribution traces. MC10133 Setup time minimum 2.5 nsec Hold time minimum 1.5 nsec Delay through the Latch typ 2 nsec max 5.4 nsec Time Bus FanOut |---> \ |---> \ ----------+ | | |---> | | |---> | | | | |---> | |--- |---> | |--------------+ | ------+ |---> | | |--x |---> | | |--- | | | |---> | | | |---> | | ----------+ | Tier 1 20x Time Bus | |---> | |--- |---> | |--x | >----+ |---> | |--x |---> | |--- ----------+ | | | |---> | | | |---> | | | | | | |---> | | | |---> | | | -------+ | | |--- | |---> / | |------ |---> / ------+ |------ |---> \ |--- | |---> \ Tier 2 3x Time Bus | -------+ / | |---> / | |---> - Tier 3 1x Time Bus | | |--x | |--x ----------+ |---> - Readout Crate 1x Time Bus |---> - Monitor Port 1x Time Bus Time Bus FanOut uses 10 Run I TLM modules Layout Points ------------- To keep the very special lines quiet run them with guard pairs in between This is easy to do because there are only 24 (or 23) lines from Carmen's Sequencer and there are 32 physical lines in the Time Bus. To keep things quiet we could also cut off some of the lines in the TLM fanout so that only the signals necessary are carried on the long cables. Can use on of Julie's fanout bards to make multiple copies of the 53 MHz clock for the TLM board latches. This whole thing is going to take a lot of 32 pair flat cable. Need to save all the cables that we find. All cables to Tier 1 must be the same length. All cables to Tier 2 must be the same length. Could try to run the 53 MHz Latch Clock line as one of the normal 32 line. Just need to skip around its latch. We need the L1 Cal Trig to operate isochronously. But we do not want to make all the cables long enough to reach from M103 (where the timing distribution is likely to be) all the way down to M112. Making all the cables this long would require a lot of folded up cable. So can we make How to put the cards into a card file ------------------------------------- Side View Showing the Cards the the Cabling Slot Front of Card Back of Card ---- --------------- -------------- 1 |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x 1 |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x 1 |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x | 4 |------<--------------<----------------<----- | 5 |-----> TLM Card in the 2nd Tier of FanOut -->-- 6 |-----> TLM Card in the 2nd Tier of FanOut -->-- | | 7 | |------<--------------<----------------<----- | | 8 | |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x 9 | |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x 10 | |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x 11 | |-> TLM Card in the 3rd Tier of FanOut -->-----------> 4x | 12 ----------<--------------<----------------<----- | 13 Input 1x -> TLM Card in the 2nd Tier of FanOut -->-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Timing Signals Required by the Tier I CTFE and Their Structure -------------------------------------------------------------- Timing Signals to Operate the CTFE Card ------------------------------------------- Basic Design of the Timing Setup for the Beginning of Run II We will run with the 396 nsec basic clock. We will do this for as many BX's as practical, i.e. not just the 36x36 BX's. Classes of Timing Signsl: Master Clock: Stable, Accurate, samething every time Static: Change only at setup time, should be TCC controllible Could come from a Run I MTG or a new FPGA design for THE-Card. Special: Special sequences with possible modes, e.g. Read & Write A/B pipes in the 29525's. Could come from a Run I MTG or a new FPGA design for THE-Card. caltrg.dgn has the basic block diagrams of the Cal Trig cards and of combinations e.g. the trees and such and of the rack layouts in Cal Trig. run_ii_cal_trig_timing.dgn Common Levels Lv 1 is the Time Line Row Labels Lv 2 is the Column Labels Lv 4 is the Border Version from Run I has: Level 31 is the Cal Trig Level 45 is the cross hairs Level 55 is the L1.5 Cal Trig New Run II Version has: Level 10 Tier 1 external and internal Level 12 Backup copy of Level 10 Timing & Sync A is used to control which section of the 29525's is written into. When Timing and Sync Signal A is high then the A half of the 29525's is selected for writing into, and when the Timing and Sync Signal A is low than the B half of the 29525's is selected for writing data into. Timing & Sync B is used to LATCH & SHIFT the data in the 29525's. The data is LATCH & SHIFTED in the 29525's on the rising positive edge of Timing & Sync Signal B. This Timing & Sync Signal is also used to control the latch section of the 74F399 ADC Data Multiplexer-Latches. On the falling negative edge of this Timing & Sync Signal the ADC Data Multiplexer-Latches will update. The ADC Data Multiplexer-Latches may also be clocked by loading a bit in the Board Control Status Register. Timing & Sync Signal C is used to select which section of the AM29525 is read. When Timing & Sync Signal C is asserted then the A-half of the AM29525 is read. When the signal is negated then the B-half of the buffer is selected. Timing and PROM Device Sync. Signal Function Address Bit ------------ ---------------------------- ----------------- T&SS D Energy LUM Page Select LSB Address Bit 8 T&SS E Energy LUM Page Select MDB Address Bit 9 T&SS J Energy LUM Page Select MSB Address Bit 10 T&SS K Momentum LUM Page Select LSB Address Bit 0 T&SS L Momentum LUM Page Select MDB Address Bit 9 T&SS M Momentum LUM Page Select MSB Address Bit 10 NOTE: For details about the connections to the Momentum LUM Page Select address lines see the section below about CTFE Rev. B programmable parts. Timing & Sync Signal G is the 2X Clock Signal. The Energy Lookup Memory registered PROM's are clocked by the positive edges of the 2X Clock signal. Timing & Sync Signal F is the X Clock Signal. The Total Et Latches and EM Et Comparator Latches the are updated on the positive edge of the X Clock. Timing & Sync Signal H is used as the ADC Convert Clock Signal. A delayed version of this Timing & Sync Signal is used to Start the MC10319 ADC (the Converter Clock signal pin 18). On the rising edge of the ADC Clock line the data output latches are latched with existing data and the internal comparator latches are released to follow the input signal. While the ADC Clock line is high, the comparators track the input analog signal and the the output latches hold. When the ADC Clock line goes low, the comparators are latched with data that represents the value of the analog input signal about 4 nsec prior to the falling edge of the ADC Clock line. The output data latches are released and the output data lines represent the new sample within 20 nsec. While the ADC Clock line is low, the comparators remain latched and the output latches remain transparent. To generate the delay in the ADC Clock Signal the CTFE Card includes a delay line with multiple taps. The tap on this delay line is adjusted on each CTFE Card so the Peak of the Trigger Pick-off signals on the card and the falling edge of the ADC Clock occur at the same time. The Delay line has a total length of 100 nsec. and has 10 taps. X Clock Timing Signal Circuit The 74AS04 at U113 does nothing. We should remove it from its socket, but we do need to keep the jumper between pins 1 and 2 of its socket. The X_Clock signal originates from pin 5 of U22, its differential receiver, and runs only to pins 2 and 5 of U92, the 74AS08 that drives the Total_Et_Latch_Clk and the Comp_Latch_Clk signals. The X_Clock signal uses the jumper between pins 1 & 2 of U113 to get to pin 5 of U92. The 2x_Clock signal originates from pin 12 of U22 its differential receiver, and now runs only to pin 5 of U182 the 74ALS541 driver that sends the clock signal to the registered Energy Look Up PROM's. This signal used to be connected to pins 1 & 4 of U92 but it in the Feb-2001 ECO it was cut from these pins. For details see the Run II CTFE ReWork Document ======================================================== CRITICAL TIMING PATHS in the L1 CALORIMETER TRIGGER --------------------------------------------------------- CTFE Rev. B 13-FEB-2001 Receive TSS-B and get it to the F399's ---------------------------------------- DELAY DELAY Step - Function TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal B "Latch-Shift" 10H125 2 ns 4 ns Buffer and Invert 74 ALS 540 7 ns 12 ns OR 74 AS 32 4 ns 6 ns Buffer and Invert 74 ALS 540 7 ns 12 ns AND 74 AS 08 4 ns 6 ns -------- -------- Totals 24 ns 40 ns Receive TSS-H and get it to the ADC's MINIMUM Delay ---------------------------------------------------- DELAY DELAY Step - Function TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal B "Latch-Shift" 10H125 2 ns 4 ns Buffer 74 ALS 541 9 ns 14 ns -------- -------- Totals 11 ns 18 ns Receive TSS-H and get it to the ADC's MAXIMUM Delay ---------------------------------------------------- DELAY DELAY Step - Function TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal B "Latch-Shift" 10H125 2 ns 4 ns Buffer 74 ALS 541 9 ns 14 ns Delay Line 100 ns 100 ns Buffer 74 ALS 541 9 ns 14 ns -------- -------- Totals 120 ns 132 ns Receive TSS-G 2X Clk and get it to the CY7C245's -------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal G "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 ALS 541 9 ns 14 ns -------- -------- Totals 11 ns 18 ns Receive Map Select Adrs Line and get it to the PROM's ----------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal G "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 ALS 541 9 ns 14 ns -------- -------- Totals 11 ns 18 ns Receive TSS-F X Clk and get it to the Tot Et and Comp Latches --------------------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal F "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 AS 08 3 ns 6 ns -------- -------- Totals 5 ns 10 ns Clock 74F399 ADC Data Latch to Momentum Board Total Sum Driven Off Card ----------------------------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal B "Latch-Shift" 10H125 2 ns 4 ns Buffer and Invert 74 ALS 540 7 ns 12 ns OR 74 AS 32 4 ns 6 ns Buffer and Invert 74 ALS 540 7 ns 12 ns AND 74 AS 08 4 ns 6 ns Latch Clock to new data on outputs 74 F 399 7 ns 9 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns Memory Access Address to Data CY7C291A-35WC 35 ns 35 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns ADD LSB thru Carry to Carry to Bit out 3x 74 F 283 19 ns 30 ns Drive the Momentum Board Total Sum off card 10 H 124 2 ns 4 ns -------- -------- Totals 113 ns 158 ns Note that changing the Momentum LUM Page Select Address to getting the new data off card will be 13 nsec typical 22 nsec maximum less than the numbers shown above for F399 Clock to new Momentum data driven off card. 2x Clock to Energy Board Total Sum Driven off Card -------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal G "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 ALS 541 9 ns 14 ns Registered Memory Clock to new data CY7C245A-25WC 12 ns 12 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns ADD LSB thru Carry to Carry to Bit out 3x 74 F 283 19 ns 30 ns Drive the Energy Board Total Sum off card 10 H 124 2 ns 3 ns -------- -------- Totals 57 ns 83 ns X Clock to Trigger Tower "Total Et" Driven off Card -------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal F "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 AS 08 3 ns 6 ns TT Tot Et Latch Clk to new data 74 AS 821 4 ns 11 ns Drive the Energy Board Total Sum off card 10 H 124 2 ns 3 ns -------- -------- Totals 11 ns 24 ns X Clock to EM Et Comparator Outputs (from PAL Latches) Driven off Card ----------------------------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal F "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 AS 08 3 ns 6 ns EM Et Comp PAL Latch Clk to new data 22V10H-25 15 ns 15 ns -------- -------- Totals 20 ns 25 ns X Clock to Total Et Comparator Outputs (from PAL) Driven off Card ----------------------------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal F "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 AS 08 3 ns 6 ns Latch "update" clock to new data out 74 AS 821 4 ns 11 ns Tot Et Comparator data bits in to P>Q out 74 LS 684 24 ns 30 ns Total Et PAL Latch new data pass through 22V10H-25 25 ns 25 ns -------- -------- Totals 58 ns 76 ns CHTCR Input Latch Clk Falling Edge to the CHTCR AS573 Input Latches ------------------------------------------------------------------- DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal G "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 ALS 541 9 ns 14 ns -------- -------- Totals 11 ns 18 ns Note that the 74AS573 Input Latches on the CHTCR card require a minimum of 2 nsec setup and 3 nsec hold around the falling edge of their clock. While transparent the data fall through time is 3 nsec typ and 9 nsec max. ADC to the Data Register Latches -------------------------------- Falling Edge of the ADC Clock to Stable New Data at the ADC Outputs 19 nsec typ (no max given) Data Setup Time Before Falling Clock Edge at the F399 Inputs 3 nsec min The range over which you can delay the ADC Clock on board is 0 nsec to 110 nsec We choose to give a minimum of 40 nsec between the ADC seeing its clock and the F399 seeing its clock (the required minimum here to meet chip timing is 22 nsec). So, considereing the various on board clock delays we must generate the Falling Edge of the ADC Clock 188 nsec i.e. 10 RF buckets, before we generate the Falling Edge of Latch-Shift F399 Clock. This will result in a worst case minimum spacing between ADC Clk and F399 Clk at the chips of 80 nsec. --> Generate with 188 nsec skew 10 RF Buckets ADC Clock Falling Edge to Latch-Shift Falling Edge Data Register Update to Registered Energy Lookup Clock ------------------------------------------------------ Falling Edge of the F399 Clock to New Stable Data at its Outputs 9 nsec max New Address to Rising Edge of Clock on the CY7C245A-25WC 25 nsec min We choose to give the address at the Registered Energy Look-Up PROM's 50 nsec minimum of setup time before the PROM receives the 2x Clock So, considereing the various on board delays we must generate the 2x Clock Rising Edge 94 nsec i.e. 5 RF Buckets after we generate the Falling Edge of Latch-Shift F399 Clock. This gives a worst case set up at the CY7C245 of 56 nsec --> Generate with 94 nsec skew, 5 RF Buckets Latch-Shift F399 Falling Edge to the first 2X Clock Rising Edge How soon can we move the LUM Page Select Address Lines after the 2X Clock ------------------------------------------------------------------------- The on board delay of the 2X Clock and the Look-Up Memory Page Select Address Lines is exactly the same and there is a zero nsec hold time requirment for the CY7C245's. So 1 RF Bucket is fine. --> Generate with 19 nsec skew, 1 RF Bucket First 2X Clock Rising Edge to Change the LUM Page Select Address Lines to the 2nd Look-Up Energy Lookup Clock to Total Et - Comp Latch Clock -------------------------------------------------- Energy Look-Up Clock to new data at the Registered PROM Outputs 12 nsec max ADD 2x 8 bits to 9 bits using 2x 74 F 283 22 nsec max Data setup before Clock rising edge using 74AS821 6 nsec min or Energy Look-Up Clock to new data at the Registered PROM Outputs 12 nsec max Comparator data bits in to P>Q out 74 LS 684 30 nsec max Data setup before Clock PAL 22V10H-25 15 nsec min So how long we need to delay the X Clock rising edge after the first rising edge of the 2X Clock is clearly controlled by the Comparator path not the Trigger Tower Total Et adder path. We choose to have 40 nsec of setup at the Comparator Latch PAL's. So considering the various on board delays we must generate the X Clock rising edge 113 nsec 6 RF Buckets after the first rising edge of 2X Clock. This will give a worst case setup at the Comparator Latch PAL's of 58 nsec and a worst case setup at the TT Total Et Latch of 66 nsec. --> Generate with 113 nsec skew, 6 RF Buckets First 2X Clock Rising Edge to X Clock Rising Edge How soon after the X Clock rising edge can we make the Second 2X Clock rising edge ------------------------------------------------------------------------- Delaying the Second rising edge of the 2X Clock until 1 RF Bucket after the X Clock rising edge is enough to guarantee that the X Clock signal arrives at its destinations before the Second 2X Clock arrives at the CY7C245's and that the 2nd Look-Up Page Select Address Lines have had a worst case minumum of 106 nsec setup at the CY7C245's. So 1 RF Bucket is fine but it can be longer if this gives better balance. We will use 4 RF Buckets for balance. --> Generate with 75 nsec skew, 4 RF Bucket X Clock Rising Edge to Second 2X Clock Rising Edge Where is the 2nd Rising Edge of the X Clock ------------------------------------------- As shown above this should be no sooner than 6 RF Buckets after the 2nd rising edge of the 2X Clock. We will put it as late a possible i.e. 1 RF Bucket before the next Latch-Shift F399 falling edge to give a maximum time for the CHTCR to get comparator data from the first look-up and to give a good balance of EM Et and Total Et data to the ERPB. Non-Active Edges of Signals --------------------------- Guide lines Keeping signals 3 RF Buckets or longer makes them easy to see Keep the non-active edges away from important active edges of other signals. Keep everything in one 396 nsec cell. Reducing ADC Clock High time may reduce power consumption. ========================================================================== Timing to get the Trigger Pickoff Signal ---------------------------------------- Verified in a 5-MAY-1989 note from Ian Manning that the BLS to L1 Cal Trig cables are 130 ft, 150 ft, and 180 ft long. I would have guessed that the lengths were 120, 150, 180 ft. Anyway, assuming a velocity factor of 0.66 this gives about 1.54 nsec/ft. So these cables are 200 nsec 231 nsec and 277 nsec long. Deans 14-Feb-01 estimate for the delay from actual beam BX to peak of Trigger Pick Off signal that the BLS Crate Backplane is 340 nsec for a Central EM signal but it could be up to 50 nsec later. So, the tenative guess for a Central EM signal is that we get its peak about 571 nsec after the actual BX. This is about 30.3 RF Buckets of delay. Another way to think about this is the following. Lookup what the delay was in Run I. Lookup what the rise time of the Trigger Pickoff signal was in Run I. It was about 350 nsec. In Run II the rise time is about 150 nsec. This is a difference of 200 nsec. So the arrival time of the signals in Run II will be about 200 nsec earlier. =========================================================================== Run I Setup of Tier 1 MBD Tier 1 MBD Timing Signal Cable to Backplane Timing Bus Map Timing Cable Backplane Bus Bus Signal Function ------ ---------- ---------------------------------- 1 H ADC Clock signal 2 G 2X-Clock Registed Energy LUM clock 3 F X-Clock Tot Et and Comp Latch 4 C AM29525 Read A/B 5 B AM29525 Latch-Shift F399 Clock 6 A AM29525 WRITE A/B 7 R CHTCR Input Clock routed to Backplane Bus D 9 J Energy LUM Page Select MSB PROM Address Bit 10 10 E Energy LUM Page Select MDB PROM Address Bit 9 11 D Energy LUM Page Select LSB PROM Address Bit 8 12 M Momentum LUM Page Select MSB PROM Address Bit 10 13 L Momentum LUM Page Select MDB PROM Address Bit 9 14 K Momentum LUM Page Select LSB PROM Address Bit 0 17 P Tier 1 Energy Adder Tree CAT2 Clock routes to H 25 N Tier 1 Momentum Adder Tree CAT2 Clock routes to H 8 \ \ 15 | 16 | | 18 | 19 | 20 | 21 | No 22 | Tier 1 23 | MBD 24 | Connection | 26 | 27 | 28 | 29 | 30 | 31 / 32 / For the Tier 1 and the Tier 2-3 Backplanes I need to find out how the backplane bus timing signals get routed between the MBD slot and the slots where the CAT cards and such are. ============================================================================ Summary of Tier 2 and Tier 3 Timing in Run I -------------------------------------------- In Tier 1, 2, and 3 CAT cards the skew between first and second lookup is 10 RF Buckets or 188 nsec. The skew in the CAT clock signals, Tier 1 to Tier 2 and Tier 2 to Tier 3 is 8 RF Buckets or 151 nsec. The CAT Clock pulses were all high for 2 RF buckets. The skew from CTFE 2X-Clk to Tier 1 Energy CAT Clk was 12 RF buckets (226 nsec) for the first lookup and 8 RF buckets (151 nsec) for the second lookup. In Run I the generation of the ADC clock falling edge was about 715 nsec after the actual BX. Then there were the TS&S cables to run to MTG to MBD and the delay on the CTFE. ============================================================================ The Run I BBB and MBA addresses used in the L1 Cal Trig are: for Tier 1: 168 with MBA's 169, 172, 170, 175 200 with MBA's 201, 204, 202, 207 224 with MBA's 225, 228 for Tier 2: 176 with MBA's 177 208 with MBA's 209 248 with MBA's 249 for Tier 3: 152 with MBA's 153 168 = 10101 000 200 = 11001 000 169 = 10101 001 201 = 11001 001 170 = 10101 010 202 = 11001 010 172 = 10101 100 204 = 11001 100 175 = 10101 111 207 = 11001 111 224 = 11100 000 176 = 10110 000 225 = 11100 001 177 = 10110 001 228 = 11100 100 208 = 11010 000 209 = 11010 001 152 = 10011 000 248 = 11111 000 153 = 10011 001 249 = 11111 001 56 = 00111 000 128 = 10000 000 129 = 10000 001 64 = 01000 000 130 = 10000 010 65 = 01000 001 132 = 10000 100 66 = 01000 010 135 = 10000 111 68 = 01000 100 71 = 01000 111 152 = 10011 000 BBA's that have been used ------------------------- 56 = 00111 000 64 = 01000 000 128 = 10000 000 152 = 10011 000 168 = 10101 000 * 176 = 10110 000 200 = 11001 000 * 208 = 11010 000 224 = 11100 000 248 = 11111 000 8 = 00001 32 = 00100 56 = 00111 80 = 01010 104 = 01101 128 = 10000 152 = 176 = 200 = 224 = 248 = Setup for Run II Tier 1 BBA = 168 BBA = 200 -------------------------- -------------------------------- +1:+4 -1:-4 +5:+8 -5:-8 +9:+12 -9:-12 +13:+16 -13:-16 ----- ----- ----- ----- ------ ------ ------- ------- Phi 1:16 169 172 170 175 201 204 202 207 Phi 17:32 177 180 178 183 209 212 210 215 -------------------------- -------------------------------- BBA = 176 BBA = 208 BBA = 224 ------------------ +17:+20 -17:-20 ------- ------- Phi 1:16 225 228 Phi 17:32 226 231 ------------------ BBA = 224 Tier 2 Eta +8:-8 BBA = 152 MBA = 153 Eta +16:+9, -9:-16 BBA = 152 MBA = 154 Eta +20:+17, -17:-20 BBA = 152 MBA = 156 Tier 3 BBA = 152 MBA = 159 ============================================================================ Tier 1 MBD Timing Signal Cable to Backplane Timing Bus Map TSS Back Cable Plane Bus Bus Function Source ----- ----- -------------------------------------------------- --------- 1 H ADC Clock signal CMC TL_0 2 G 2X-Clock Registed Energy LUM clock CMC TL_2 3 F X-Clock Tot Et and Comp Latch CMC TL_3 4 C AM29525 Read A/B MTG FA=0 5 B AM29525 Latch-Shift F399 Clock CMC TL_1 6 A AM29525 WRITE A/B MTG FA=1 7 R CHTCR Input Clock routed to "D" CMC TL_6 9 J Energy LUM Page Select MSB PROM Address Bit 10 CMC TL_4 10 E Energy LUM Page Select MDB PROM Address Bit 9 MTG FA=2 11 D Energy LUM Page Select LSB PROM Address Bit 8 MTG FA=3 12 M Momentum LUM Page Select MSB PROM Address Bit 10 CMC TL_5 13 L Momentum LUM Page Select MDB PROM Address Bit 9 MTG FA=4 14 K Momentum LUM Page Select LSB PROM Address Bit 0 MTG FA=5 17 P Tier 1 Energy Adder Tree CAT2 Clock routed to H CMC TL_7 25 N Tier 1 Momentum Adder Tree CAT2 Clock routed to H CMC TL_8 Tier 1 MBD Timing Signal Cable to Backplane Timing Bus Map TSS Back Cable Plane Bus Bus Function Source ----- ----- -------------------------------------------------- --------- 15 A,B,C Tier 2 Counter Tree CAT2 Input Latch Clock CMC TL_11 D,E,F '''''''""'''""'''""'''""'''""'''""'''""'''""''""'''""'''""''""'''"'''""' The MTG is currently running at MBA = 208, CA = 53 It is running right off of a BBB, i.e. not from a MBD. It will move to some rational place at some time. Recall that in the MTG documents the channels are numbered 1:32 and are controlled from Function Addresses 0:31 decimal. All channels currently have BIT2 PAL's. To set the output HI write $19 to set the output LOW write $09. Bits 5:7 are not defined in a BIT2 PAL, Bits 0:4 are defined and should readback OK, i.e. mask = $1f. '''''''""'''""'''""'''""'''""'''""'''""'''""''""'''""'''""''""'''"'''""' Try to remember how the addressing of the various LUM pages worked in the Run I setup. I think this is right. What about the difference between EM and HD Energy PROM's, and what is in the Momentum PROM's ? PROM Lookup Memory Lookup Map Select Adrs Map ---------------- Selected MSB MDB LSB Descripton ----------- ---------------- -------------------------- 0 0 0 0 -Z Outer Region 1 0 0 1 -Z NT-NT Center Region 2 0 1 0 -Z Next to Center Region 3 0 1 1 Center Region 4 1 0 0 +Z Next to Center Region 5 1 0 1 +Z NT-NT Center Region 6 1 1 0 +Z Outer Region 7 1 1 1 In EM Energy PROM's I think this is a 1 to 1 page In HD Energy PROM's I think this is a page of zero or a page of the zero energy response. In momentum ??? So to switch between the "center" page and the "special" page you just need to move the MSB Address line from 0 to 1. ?????????????????????????????????????????????????????????????????????? So to startup a CTFE card, at the higher CA, the odd CA, you need to write a $01 to FA = 80 to select real ADC data instead of test register data, and you need to write a $ff to register FA = 81 to enable the clock to go to all the F399 registers. ````````````````````````````````````````````````````````````````````` Setting up the Tier 2 Counter Tree CAT2 Comparator Outputs Made a measurement of the CHTCR card and it apprears to be giving it new count output data in about 60 nsec after its input latches become transparent. Recall that its input latches go transparent when its input latch clock goes HI and its input latches move to hold when its input latch clock goes back LOW. Need to look up the parts and calculate what this should be. The path in the CHTCR is: Input Clock: Rec 10H125 Fanout buffer 74LS541 Date: Rec & Latch 74AS573 PROM 27S185 PROM 27S43 Output Driver 10H124 The calculated response of the CAT2 Card from positive edge of its input latch clock to new data at its comparator outputs is: 15 nsec min to 41 nsec max. The measured response is 31 nsec. ======================================================================= Timing Real D-Zero BX to Pickoff Signal at L1CT from log book 3:6-APR-01 Real BX Real BX Peak to Initial to Peak Height Rise of the Bump ------ ---------- ----------- 17 GeV 456 nsec 624 nsec 7 488 632 27 472 640 7 480 640 19 496 664 16 496 672 10 496 672 44 480 672 12 504 704 average 485 nsec 658 nsec difference = 173 nsec Real BX Center of D-Zero to Peak at L1CT 658 nsec Pickoff Peak to Latch-Shift Fall 138 nsec typ Latch-Shft Fall to Center Sub-System Strobe 885 nsec ------------- Real BX to Center Sub-System Strobe Total 1680 nsec From Real BX to L1_Acpt at SCL Receiver output is 27 ticks = 3559 nsec But SCL Hub to SCL Receiver output (with 44 ft cable) is about 410 nsec Trig FW output stable before the SCL Hub-End Ingests the data 65 nsec Trig FW Reads from the TRM Input FIFO before Its output stable 264 nsec ----------- Real BX center of D-Zero to Trig FW Reads from TRM Input FIFO 2820 nsec So for the L1 Cal Trig the TRM Input FIFO needs to store the L1CT's And-Or Terms for about 1140 nsec or about 8.64 ticks. =======================================================================