Generation and Distribution of the Run II Level 1 Calorimeter Trigger Timing and Control Signals -------------------------------------------------------- Original Rev. 16-APR-2002 Current Rev. 16-DEC-2003 Operation of the L1 Cal Trig in Run II was started in the winter/spring of 2001 with a temporary setup of the Timing and Control signal that are required to operate the L1 Cal Trig. This setup is described in: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/timing/ cal_trig_readout_and_m101_timing.txt and cal_trig_timing.txt As the work starts to implement the permanent Timing and Control Signal generation and distribution setup for Run II, instead of changing those files, we will start this new file. The current version of this file is always in: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/timing/ cal_trig_timing_generation_ii.txt Spring 2002 Implementation -------------------------- This file describes how the Generation and Distribution of the Timing and Control signals was setup in the spring of 2002. Some older reference information is at the end of this file. More details about the Distribution setup for these L1 Cal Trig signals can be found in the log book in the entries for: 4:8-JUNE-02 11:15-JUNE-02 19:21-JUNE-02 Use of Run I Bus Buffer Boards to distribute the Timing and Control Signals --------------------------------------------------------------------------- In the TSS section the BBB can buffer 32 signals, i.e. a full width cable packed from the pin #1 end TSS_1 : TSS_32. In the CBus section the BBB can straight buffer a number of signals packed from the pin #1 end: MBA_1 : MBA_8 (note MBA_8:4 have the BBB wake up logic on them) CA_6 : CA_1 FA_8 : FA_1 Note that the BBB's and MBD's use 10116 chips to receive signals - and that 10116's do not want floating inputs. So we will need to tie Vbb to one side of each unused input on those chips that are only partially used. Design for Tier 1 and DC-ERPB ----------------------------- There are 10 BBB's that are used to distribute the Timing & Control to the 10 Tier 1 racks. The TSS section of the BBB is used for this. This distribution is both the Tier 1 Timing_&_Control signals and the DC-ERPB Timing_&_Control signals. It is setup in the following way: BBB TSS section signals 1:15 are the DC-ERPB "MTG signals" 1:15. Note that it is OK that signal pairs 16 and 17 on the "MTG cable to the DC" are not driven because the DC's do not use these two pairs. The 17th pair is not cennected to anything. The 16th pair is received by a 100325 (which is OK with floating inputs) but the output from this section of the 100325 is not connected to anything. These 15 signals are just a direct 1:1 connection from the Cal_Trig_Readout_Helper to the DC "MTG" input. BBB TSS section signals 16:32 are used to carry 17 Tier 1 Timing and Control signals. This is the setup as shown in this table: BBB TSS MBD Pair Maps (Cable MBD this to Bus TSS Driven Backplane Tier 1 Backplane Buse Pair) Input by Bus Function ------- ----- -------- --------- ------------------------ 16 1 CMC_0 H ADC Clock 17 2 CMC_2 G 2X CTFE Clock 18 3 CMC_3 F X CTFE Clock 19 4 MTG FA_0 C Read A/B 20 5 CMC_1 B Latch/Shift 21 6 MTG FA_1 A Write A/B 22 7 CMC_6 R CHTCR Clock 23 8 MTG FA_6 Not used - static drive 24 9 CMC_4 E (INV) Energy MD Bit Adrs 25 10 MTG FA_2 J Energy MS Bit Adrs 26 11 MTG FA_3 D Energy LS Bit Adrs 27 12 CMC_5 M Momentum MS Bit Adrs 28 13 MTG FA_4 L Momentum MD Bit Adrs 29 14 MTG_FA_5 K Momentum LS Bit Adrs 30 15 MTG FA_7 S Not used - static drive 31 16 CMC_8 N Tier 1 Momentum CAT2 Clk 32 17 CMC_7 P Tier 1 Energy CAT2 Clk This is the 11-JUNE-2002 Tier 1 MBD mapping of TSS Cable Bus to Backplane Bus. It is slightly different than what was used in Run I Tier 1. To change what Lookup PROM pages are used, you need to make a change in this mapping of TSS Cable Bus to Backplane Bus on the MBD card. 10116 Buffer Chips on BBB and MBD --------------------------------- Note that both the BBB's and the MBD's use 10116 chips to buffer these Timing & Control signals. If any section of this chip is used, then all sections of this chip must be driven or biased. This is taken care of on the BBB by driving all 32 TSS channels. Where no useful signal is needed a static drive MTG signal is used. On the MBD there is one 10116 that we use 2 sections of but the 3rd section buffers the 18th cable pair that we are not connected to. To bias this section of this chip on the Tier 1 MBD we need to solder bridge U22 pins 11 and 12. Thus we have all sections of all 10116's on the Tier 1 MBD's either driven or biased. T&SS Input Connection to the 10 BBB's ------------------------------------- The T&SS inputs to the 10 BBB's that distribute Timing_&_Control to Tier 1 and to DC_ERPB are staggered along a flat cable so that the cable runs from these BBB's to the MBD's can be just their natural physical length and still have isochronous timing to all crates. Connection of the Timing & Control Signals to the 10 BBB's that Distribute these signals to Tier 1. ________________________[] Feed 2 sections to first BBB | | | ___________[] Termination 15 sectopms from feed | | | |__ | _____[] slot 18 feeds M103 13 sections | | | |_____ | _____[] slot 17 feeds M104 11 sections | | | |_____ | _____[] slot 16 feeds M105 10 sections | | | |_____ | _____[] slot 15 feeds M106 9 sections | | | |_____ | _____[] slot 14 feeds M107 8 sections | | | |_____ | _____[] slot 13 feeds M108 7 sections | | | |_____ | _____[] slot 10 feeds M109 5 sections | | | |_____ | _____[] slot 9 feeds M110 4 sections | | | |_____ | _____[] slot 8 feeds M111 3 sections | | | |_____ |______________[] slot 7 feeds M112 2 sections [] = connector to BBB or Feed or Termination The feed to this is the Top Left Hand connector at the top of M103. The termination on this is the Lower Left Hand connector at the top of M103. BBB to MBD Tier 1 and DC_ERPB Cables ------------------------------------ These 32 pair flat cables carry Timing_&_Control information to the DC-ERPB on pairs 1:15 and Timing_&_Control information to Tier 1 cards on pairs 12:32. Runs from the BBB's to the MBD's in the Tier 1 Crates Upper MBD Lower MBD --------- --------- from BBB's to M103 Upper Tier 1 is 6 section 9 section full length from BBB's to M104 Upper Tier 1 is 8 section 11 section full length from BBB's to M105 Upper Tier 1 is 9 section 12 section full length from BBB's to M106 Upper Tier 1 is 10 section 13 section full length from BBB's to M107 Upper Tier 1 is 11 section 14 section full length from BBB's to M108 Upper Tier 1 is 12 section 15 section full length from BBB's to M109 Upper Tier 1 is 14 section 17 section full length from BBB's to M110 Upper Tier 1 is 15 section 18 section full length from BBB's to M111 Upper Tier 1 is 16 section 19 section full length from BBB's to M112 Upper Tier 1 is 17 section 20 section full length To make the Tier 1 end of these new BBB to Tier 1 MBD cables: Split the cable into pair 1:15 and 16:32 Split this back through 3 and 1/2 twisted sections From the 1:15 bunch, cut off two sections. Install 34 pin connectors on the 1:15 bunch (cable pair 1 to connector pair 1, connector pair 16 and 17 are open). Install a connector at the end of the 1:15 bunch and install another connector one section up from the end. These connect to a DC and to a Terminator. Install 34 pin connectors on the 16:32 bunch (cable pair 16 to connector pair 1). Install a connector at the end of the 16:32 bunch and install another connector 3 sections up from the end. These connect to the upper and lower Tier 1 crates in a given rack. The feed to each DC has a terminator after the connection to the DC. In each Tier 1 rack, the MBD in the upper Tier 1 crate does not have terminator resistors on its T&SS inputs, the MBD in the lower Tier 1 crate does have terminator resistors on its T&SS inputs. Setup of the Tier 1 MBD's ------------------------- Post June 2002 Setup of Tier 1 MBD Timing Signal Cable to Backplane Timing Bus Map ------------------------------------------------------------------ TSS Back Cable Plane Bus Bus Function Source ----- ----- -------------------------------------------------- --------- 1 H ADC Clock signal CMC TL_0 2 G 2X-Clock Registed Energy LUM clock CMC TL_2 3 F X-Clock Tot Et and EM Comp Latch CMC TL_3 4 C AM29525 Read A/B MTG FA=0 5 B AM29525 Latch-Shift F399 Clock CMC TL_1 6 A AM29525 WRITE A/B MTG FA=1 7 R CHTCR Input Clock routed to "D" CMC TL_6 10 J Energy LUM Page Select MSB PROM Address Bit 10 MTG FA=2 9 INV E Energy LUM Page Select MDB PROM Address Bit 9 CMC TL_4 11 D Energy LUM Page Select LSB PROM Address Bit 8 MTG FA=3 12 M Momentum LUM Page Select MSB PROM Address Bit 10 CMC TL_5 13 L Momentum LUM Page Select MDB PROM Address Bit 9 MTG FA=4 14 K Momentum LUM Page Select LSB PROM Address Bit 0 MTG FA=5 15 S Just to bias S so all channels have a signal MTG FA=7 16 N Tier 1 Momentum Adder Tree CAT2 Clock routed to H CMC TL_8 17 P Tier 1 Energy Adder Tree CAT2 Clock routed to H CMC TL_7 This implements the following Energy and Momentum Lookup Page Selects Starting 4-JUNE-2002 we switch to running with the following setup so that we have no Symmetric Low Energy Cut for the initial studies of Pedestal and noise. Energy Page Adrs Momentum Page Adrs ---------------- ------------------ First LU 7 = 111 0 = 000 Second LU 5 = 101 4 = 100 For Energy, we need to make the Middle address line High during the first lookup and low during the second lookup. The LSBit and MSBit stay high. For Momentum we need the MSBit low for the first lookup and hi for the second lookup. The MDBit and LSBit are low for both. Starting 10-JULY-2003 we are using Momentum Page #2 for the first lookup to get a rational Symmetric Low Energy Cut for actually running a Missing Et trigger. There was NO change to the Pages used by the Energy Lookup PROM's. There was NO change to the wire wrap wires on the CTMBD's. The only change was to the default setup of the static Momentum Page Select Address Lines that come from the MTG. The MDBit and LSBit of the Momentum Page Select are static lines from the MTG. Thus Starting 10-JULY-2003 Momentum Page Adrs ------------------ First LU 2 = 010 Second LU 6 = 110 Design for Tier 2 ----------------- The Timing & Control fanout to the Tier 2 and Tier 3 crates is taken care of by the CBus Section of the 4 BBB cards in slots 7 through 10 of the Cal Trig Control Crate. The 8 MBA buffers and the 6 CA buffers and the 8 FA buffers and even perhaps the Stb and Dir buffers are used to fanout Timing_&_Control to the 3x Tier 2 crates and the 1x Tier 3 crate. The inputs to these BBB CBus sections are just feed in parallel so the runs from the BBB to the T2 and T3 crates must all be the same length to acheive isochronous timing. There are the same constraints as noted above about not letting both inputs to any section of a 10116 on the BBB or MBD "float" if any section of that 10116 is being used. The cable that feeds the fanout to T2 & T3 has the following signals in it. Cable Buffered Signal by CBus Pair Circuit Source Function ------ ------- --------- ------------------------------------- 1 MBA-1 none 2 MBA-2 none 3 MBA-3 none 4 MBA-4 none 5 MBA-5 none 6 MBA-6 none 7 MBA-7 none 8 MBA-8 none 9 CA-1 none 10 CA-2 MTG FA_11 static level 11 CA-3 CMC_15 Tier 2 Momentum Tree Input Clock 12 CA-4 MTG FA_12 static level 13 CA-5 CMC_14 Tier 3 Counter Tree Input Clock and FMLN Input Clock 14 CA-6 MTG FA_13 static level 15 FA-1 CMC_11 Tier 2 Counter Tree Input Clock and Tier 3 Momentum Tree Input Clock 16 FA-2 MTG FA_14 static level 17 FA-3 MTG FA_15 static level 18 FA-4 none 19 FA-5 none 20 FA-6 none 21 FA-7 none 22 FA-8 none Recall that the MTG Channels are numberede 1:32 while the control registers for the channels are FA_0 through FA_31. In the table above the MTG outputs are refered to by their FA numbers. For the mapping of T&SS Bus to the Backplane Bus for the Tier 2 and Tier 3 MBD's see the file: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/timing/ cal_trig_momentum_tree_timing.txt For a review of how this was setup in Run I see the file: www.pa.msu.edu/hep/d0/ftp/run1/l1/caltrig/cabling/ mbd_and_ctmbd_timing_signal_wiring.txt The T&SS cables that currently (DEC-2003) feed Tier 2 and Tier 3 are not all equal length. For a description of the timing skew caused by this and the current relative timing of Tier 1 wrt Tier 2-3 see the 11,12-DEC-2003 Log Book entry. Strobe and Gap Signals to the And-Or Terms ------------------------------------------ The outputs of the Tier 3 Count Comparators and FMLN are turned into blocks of And-Or Terms by adding the appropriate Strobe and Gap signals to them. For now these Strobe and Gap signals are coming directly from the Master Clock Sequencer #2. For now the Master Clock generates 2 copies of the GAP and 2 copies of the STROBE. For now these 2 copies are identical. The GAP and STROBE signals generated by the Master Clock Sequencer #2 are fanned out by channels of the MTG. This is done to make 4 copes of GAP and 4 copies of STROBE. This makes enough GAPs and STROBEs to drive all 4 blocks of 14 AOT's the the L1 Cal Trig has been assigned. The two copies of GAP and STROBE are generated by the #2 Sequencer using the following 4 Time Lines: TL # 9 Strobe copy 1 TL #12 Strobe copy 2 TL #10 Gap copy 1 TL #13 Gap copy 2 Details about the generation of the Strobe and Gap signals can be seen in the Sequencer #2 programming file in: www.pa.msu.edu/hep/d0/ftp/l1/framework/timing/clk_sequencer_2_DDMMMYY.txt We will continure to use these 2 copies of both GAP and STROBE just in case at some point in the future we need to make 2 flavors of GAP and STROBE. The fanout path is the following: TL # 9 Strobe feeds MTG Bit Inputs 21 and 22 TL #10 GAP feeds MTG Bit Inputs 17 and 18 TL #12 Strobe feeds MTG Bit Inputs 23 and 24 TL #13 GAP feeds MTG Bit Inputs 19 and 20 The MTG Bit Inputs are routed directly to the MTG outputs. These we now have 4 copies of GAP and 4 copies of STROBE. They are: MTG Output 17 is GAP #1 which comes from TL #10 MTG Output 18 is GAP #2 which comes from TL #10 MTG Output 19 is GAP #3 which comes from TL #13 MTG Output 20 is GAP #4 which comes from TL #13 MTG Output 21 is STROBE #1 which comes from TL # 9 MTG Output 22 is STROBE #2 which comes from TL # 9 MTG Output 23 is STROBE #3 which comes from TL #12 MTG Output 24 is STROBE #4 which comes from TL #12 MTG Card Output Polarity Recall that the output driver on the MTG card is "inverting", that is the Direct output pin on the driver is tied to the even pin number on the output connector and the Complement output pin of the driver is tied to the odd pin number of the output connector. This is all rational when the "L" type PAL is used in the MTG Channel. If you skip the PAL and just directly jumper the Bit Input to the Output then you need to invert either the differential input pair or output pair. Patch Panel Layout at the Top of M103 ------------------------------------- View from the front of M103 Terminate Feed to Feed to Tier 1 DC-ERPB Tier 1 DC-ERPB Tier 2 Tier 3 not used ============== ============== ============== ============== ============== ============== ============== ============== MTG Output not used not used not used Card Layout for Timing_&_Control Distribution in M103 ----------------------------------------------------- M103 TOP Timing and Control and CBus Distribution 20. COMINT -X-X-X-X- Cut 19. Skip 18. BBB BBA = 168 Tier 1 eta( 1:8 ) phi( 1:16) (middle backplane M103..M106) T&S Section is for Tier 1 and ERPB Timing & Control to M103 17. BBB BBA = 176 Tier 1 eta( 1:8 ) phi(17:32) (lower backplane M103..M106) T&S Section is for Tier 1 and ERPB Timing & Control to M104 16. BBB BBA = 200 Tier 1 eta( 9:16) phi( 1:16) (middle backplane M107..M110) T&S Section is for Tier 1 and ERPB Timing & Control to M105 15. BBB BBA = 208 Tier 1 eta( 9:16) phi(17:32) (lower backplane M107..M110) T&S Section is for Tier 1 and ERPB Timing & Control to M106 14. BBB BBA = 224 Tier 1 eta(17:20) phi( 1:32) (mid & low backpl M111, M112) T&S Section is for Tier 1 and ERPB Timing & Control to M107 13. BBB BBA = 152 Tier 2 and Tier 3 (upper backplane M105, M109, M111, M107) T&S Section is for Tier 1 and ERPB Timing & Control to M108 12. Skip -X-X-X-X- Cut 11. Skip 10. BBB CBus Section is for Tier 2 Timing and Control to M105 T&S Section is for Tier 1 and ERPB Timing & Control to M109 9. BBB CBus Section is for Tier 3 Timing and Control to M107 T&S Section is for Tier 1 and ERPB Timing & Control to M110 8. BBB CBus Section is for Tier 2 Timing and Control to M109 T&S Section is for Tier 1 and ERPB Timing & Control to M111 7. BBB CBus Section is for Tier 2 Timing and Control to M111 T&S Section is for Tier 1 and ERPB Timing & Control to M112 6. Skip -X-X-X-X- Cut 5. No Used -X-X-X-X- Cut 4. Not Used -X-X-X-X- Cut 3. Spare 2. MTG MBA = 120 CA = 53 Auxiliary Control Signals for L1 Cal Trig 1. MBD MBA = 120 Notes: This top crate in M103 is a Run I Trig Framework style card file and backplane. As viewed from the back, this type of backplane has 4 vertical columns of 64 pin connectors. Only the column on the left has any backplane traces connecting between the slots. The "-X-X-X-X- Cut" symbol in the table above shows where these traces have been cut between the slots. Slot #1 is a MBD that is used just to supply CBus control to the MTG card in slot #2. No BBB card is used in front of the MBD in slot #1. This backplane or cardfile has a lot of flex in it. It may be necessary to push from the back to get the card connectors to fully insert. Nothing is bent or out of alignment - just push the backplane to keep it flat and the card connectors will fully insert. Review the L1 Cal Trig Readout Helper setup ------------------------------------------- No change was made in the spring of 2002 to the setup of the L1 Cal Trig Readout Helper or its immediate cabling. Signals feeding the L1 Cal Trig Readout Helper ---------------------------------------------- CT Read Helper M101 Mid Slot 21 --------------------------------------- PClk and P1_TS_0 TL 0,1,2,3 Selector P1_TS_1 +--------> FanOut ---> P1_TS_2 ---> BSF FPGA #17 ---X | #4 P1_TS_3 | P1_TS_4 | Sequencer -+ #1 | | | Selector MSA_In_57 \ +--------> FanOut ---> MSA_In_55 \ TL 4,5,6,7 #8 MSA_In_53 | MSA_In_51 | | Main To |--> Array ---> Distrib Geo Section 126 L1_Acpt ---> MSA_In_0 | FPGA #4 ution Geo Section 126 L1_Period ---> MSA_In_1 | | | Sequencer TL_20 ERPB_In_Clk ---> MSA_In_21 / #2 TL_21 ERPB_EM/Tot ---> MSA_In_19 / Cal Trig Readout Helper Outputs ------------------------------- Source Destination CT_Read_Helper M101M Slot #1 Signal Function Front_PB TOM_PB -------------------- ----------------------- ------------------------ Trans_HSRO_Data MSA_Output_0 pins 1,2 P1_TS_8 J5 pins 7,8 Capture_HSRO_Data MSA_Output_1 pins 3,4 P1_TS_9 J4 pins 3,4 Capture_Monitor_Data MSA_Output_2 pins 5,6 P1_TS_10 J4 pins 7,8 Scaler_Reset MSA_Output_3 pins 7,8 P1_TS_15 J5 pins 15,16 Source Destination CT_Read_Helper M101B Slot #1 Signal Function Front_PB TOM_PB -------------------- ----------------------- ------------------------- Trans_HSRO_Data MSA_Output_6 pins 13,14 P1_TS_8 J5 pins 7,8 Capture_HSRO_Data MSA_Output_7 pins 15,16 P1_TS_9 J4 pins 3,4 Capture_Monitor_Data MSA_Output_8 pins 17,18 P1_TS_10 J4 pins 7,8 Scaler_Reset MSA_Output_9 pins 19,10 P1_TS_15 J5 pins 15,16 Output Signal Output MSA DC Label and Function ------------------ ------------- ----------------------- ERPB_Input_Clk_0 MSA Output 16 nc ERPB_Input_Clk_1 MSA Output 17 mtg-0 ERPB Input Clk ERPB_EMTot_Sel_0 MSA Output 18 nc ERPB_EMTot_Sel_1 MSA Output 19 mtg-1 ERPB EM/Tot Manual_Control_0 MSA Output 20 mtg-2 Lookback(0) Manual_Control_1 MSA Output 21 mtg-3 Lookback(1) Manual_Control_2 MSA Output 22 mtg-4 Lookback(2) CMD_Armed_0 MSA Output 23 nc ERPB_Capture_2 MSA Output 24 mtg-5 ERPB Capture Data CMD_Armed_1 MSA Output 25 nc Manual_Control_3 MSA Output 26 mtg-6 Lookback(3) Manual_Control_4 MSA Output 27 mtg-7 DC Config Control Manual_Control_5 MSA Output 28 mtg-8 Lookback(4) & DC Config Ctrl Manual_Control_6 MSA Output 29 mtg-9 DC Config Control DC_Transmit_2 MSA Output 30 mtg-x DC XMIT Trig Manual_Control_7 MSA Output 31 mtg-y no connection T&SS Added for Quadrant Term CTOM --------------------------------- Used by Master Clock M101 Middle Enters M101 Distributed Quad-Term Sequencer #2 P1 Backplane Middle Crate to Main Array CTOM Time Line Timing Signal on TOM_PB on HQ_TS_ as ------------ ------------- ------------- ------------- ------- CMC_TL_16 P1_TS_6 J3 pins 11&12 HQ_TS_2 In_Clk CMC_TL_17 P1_TS_12 J4 pins 15&16 HQ_TS_1 Out_Clk