Date:    13-SEPT-1999

         filename                         web description text
-------------------------------      ------------------------------

the_layout_L1_FW_cards.ps             L1 FW Cards  block diagram

the_layout_SF_FOM.ps                  Special Function FOM Cards

The_layout_exp_group_scalers.ps       Exposure Group Scalers Cards

the_layout_L2_FW_cards.ps             L2 FW Cards  block diagram

the_layout_MSU_Test_cards.ps          MSU Test Rack Cards




run_2_blk_L1_FW_Blk.ps                L1 FW Principal Connections Blk

the_layout_bunch_scaler.ps            Per Bunch Scaler Blk

the_layout_gated_scaler.ps            Gated Scaler Blk

the_layout_ma_readout.ps              Main Array Readout Blk

the_layout_THE_Card_readout.ps        THE Card Readout Blk

the_layout_hsro_path.ps               Readout to L3 Blk

the_layout_capture_monitor.ps         Capture Monitor HSRO Blk

run_2_L1_FW_system_timing.ps          L1 FW System Timing Diagram




the_layout_rack_Layout.ps             General Layout of Framework Racks

the_layout_L1_FW_rack_M123.ps         L1 Framework Rack M123 Layout

the_layout_Scaler_rack_M122.ps        Scaler Rack & L2 FW Rack M122 Layout

the_layout_SCL_Hub_rack_M124.ps    SCL Hub End Rack & Readout Rack M124 Layout

the_layout_CARMEN_rack.ps             Master Clock Rack M100 Layout

the_layout_MSU_Test_rack.ps           MSU Test Rack Layout




L2_FW_CARDS_AND_CABLES.GIF         Layout of the Cards and Cables in the L2 FW

L2_FW_AONM_MINUS.GIF               Block Diagram of the special AONM used for
                                   Programmable "ORing" and D-Latching in the
                                   L2 FW.