***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * And-Or Network Module * * * ***************************** Original: 2-MAY-1995 Latest: 27-OCT-1997 Introduction ------------ The And-Or Network Module (AONM) PCB is used in the Level 1 Trigger Framework to perform several functions: 1. And-Or Network Module functionality 2. Framework Output Module functionality The details of this card's operation for each function are provided below in this document. Each AONM has the following input and output connections (in addition to the VME, P1 Timing, and High-Speed Readout interfaces described in THE_CARD.TXT): 1. 128 Common Inputs, entering on P2/P3 and bussed to all 16 MSA FPGA's. These are differential ECL inputs. 2. 4 Outputs from each of the 16 MSA FPGA's, emerging on P4 (4 * 16 = 64 signals of this class). These are differential ECL outputs. Operation: General Comments --------------------------- The AONM PCB is used in all application which require all MSA Inputs to be bussed to all MSA FPGA's, and additionally require the MSA Outputs to be allocated equally to all MSA FPGA's (i.e. 4 MSA Outputs per MSA FPGA). As mentioned above, this includes the And-Or Network Module functionality and the Framework Output Module functionality. It is likely that other, "one-off" functionalities which require high input fan-in may also be built on the AONM PCB. Operation: And-Or Network Module -------------------------------- The And-Or Network Module configuration is used whenever a programmable "AND" of up to 128 of the MSA Inputs is required. This includes the Physics And-Or Input Term processing, and the Exposure Group And-Or Input Term processing. Note that, for Exposure Group And-Or Input Term processing, typically only two of the MSA FPGA's on the AONM are used (8 Exposure Groups / 4 MSA Outputs per FPGA = 2 MSA FPGA's). It is not yet clear how (or even if) the other MSA FPGA's on Exposure Group cards will be used. Recall what is meant by "programmable AND." The idea is that a coincidence of some subset of the MSA Inputs is performed to produce an MSA Output. As noted above, each MSA FPGA is responsible for producing 4 of these MSA Outputs. Within each MSA FPGA, the MSA Inputs which make up the programmable AND must be selected. Additionally, each selected MSA Input can be required either HIGH or LOW. Thus, two control bits are required for each of the 128 MSA Inputs which make up the programmable AND for each MSA Output, for a total of 2 bits * 128 MSA Inputs (And-Or Input Terms) * 4 MSA Outputs (Partial And-Or Fired) = 1024 control bits per MSA FPGA. Note that, if no And-Or Input Terms are selected for a given Partial And-Or Fired signal, that Partial And-Or Fired signal will always be set HIGH. The AONM signal flow is purely combinational, there are no latches on either the MSA Inputs or the MSA Outputs. The AONM does not provide any Data Block information, and so does not have High-Speed Readout. The AONM may have 32-bit scalers attached to each MSA Output signal (Partial And-Or Fired signal), which can be read out via the Monitor Readout path. These scalers are not necessary for the proper functioning of the L1 Trigger Framework, but rather correspond to scalers used in the Framework Output Module (see below). Operation: Framework Output Module ---------------------------------- FOM operation is very similar to AONM operation. Rather than combining the MSA Inputs in a "programmable AND," however, the FOM combines them in a "programmable OR." The MSA Inputs which contribute to the OR can again be required HIGH or LOW, leading to the same 1024 control bits per FPGA. The FOM does have some additional features. It has a 32-bit scaler attached to each MSA Output signal (again, 4 scalers per MSA FPGA), which can be read out via the Monitor Readout path. Via the High-Speed Readout path, the MSA Output states are available. The MSA Input states may also be available, but a special FPGA configuration may be required to provide these, as this readout is very expensive in CLB terms. Implementation Summary ---------------------- Table of specifics for the AONM species of THE Card Board Species ID MSB: 1 MSA FPGA Signal Mapping Chip Addr MSA Inputs MSA Outputs BG-I/O --------- ---------- ----------- ------ 1 127:0 3:0 none 2 127:0 7:4 none 3 127:0 11:8 none 4 127:0 15:12 none 5 127:0 19:16 none 6 127:0 23:20 none 7 127:0 27:24 none 8 127:0 31:28 none 9 127:0 35:32 none 10 127:0 39:36 none 11 127:0 43:40 none 12 127:0 47:44 none 13 127:0 51:48 none 14 127:0 55:52 none 15 127:0 59:56 none 16 127:0 63:60 none There are NO inter-MSA FPGA connections. ------------------------- CONNECTOR PIN ASSIGNMENTS ------------------------- ---------------------------------------------------------------------- P1: 160-pin E-style DIN connector for P1 VME and Timing ---------------------------------------------------------------------- See THE_CARD.TXT for a description of this connector, which is common to all species of THE Card. ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus ---------------------------------------------------------------------- (note: 0 <= n <= 1) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Isochronous And-Or Input Term 128*n + 0 COM INPUT MSA_In_000 B1 Isochronous And-Or Input Term 128*n + 0 DIR INPUT MSA_In_000 A2 Isochronous And-Or Input Term 128*n + 1 COM INPUT MSA_In_001 B2 Isochronous And-Or Input Term 128*n + 1 DIR INPUT MSA_In_001 A3 Isochronous And-Or Input Term 128*n + 2 COM INPUT MSA_In_002 B3 Isochronous And-Or Input Term 128*n + 2 DIR INPUT MSA_In_002 A4 Isochronous And-Or Input Term 128*n + 3 COM INPUT MSA_In_003 B4 Isochronous And-Or Input Term 128*n + 3 DIR INPUT MSA_In_003 A5 Isochronous And-Or Input Term 128*n + 4 COM INPUT MSA_In_004 B5 Isochronous And-Or Input Term 128*n + 4 DIR INPUT MSA_In_004 A6 Isochronous And-Or Input Term 128*n + 5 COM INPUT MSA_In_005 B6 Isochronous And-Or Input Term 128*n + 5 DIR INPUT MSA_In_005 A7 Isochronous And-Or Input Term 128*n + 6 COM INPUT MSA_In_006 B7 Isochronous And-Or Input Term 128*n + 6 DIR INPUT MSA_In_006 A8 Isochronous And-Or Input Term 128*n + 7 COM INPUT MSA_In_007 B8 Isochronous And-Or Input Term 128*n + 7 DIR INPUT MSA_In_007 A9 Isochronous And-Or Input Term 128*n + 8 COM INPUT MSA_In_008 B9 Isochronous And-Or Input Term 128*n + 8 DIR INPUT MSA_In_008 A10 Isochronous And-Or Input Term 128*n + 9 COM INPUT MSA_In_009 B10 Isochronous And-Or Input Term 128*n + 9 DIR INPUT MSA_In_009 A11 Isochronous And-Or Input Term 128*n + 10 COM INPUT MSA_In_010 B11 Isochronous And-Or Input Term 128*n + 10 DIR INPUT MSA_In_010 A12 Isochronous And-Or Input Term 128*n + 11 COM INPUT MSA_In_011 B12 Isochronous And-Or Input Term 128*n + 11 DIR INPUT MSA_In_011 A13 Isochronous And-Or Input Term 128*n + 12 COM INPUT MSA_In_012 B13 Isochronous And-Or Input Term 128*n + 12 DIR INPUT MSA_In_012 A14 Isochronous And-Or Input Term 128*n + 13 COM INPUT MSA_In_013 B14 Isochronous And-Or Input Term 128*n + 13 DIR INPUT MSA_In_013 A15 Isochronous And-Or Input Term 128*n + 14 COM INPUT MSA_In_014 B15 Isochronous And-Or Input Term 128*n + 14 DIR INPUT MSA_In_014 A16 Isochronous And-Or Input Term 128*n + 15 COM INPUT MSA_In_015 B16 Isochronous And-Or Input Term 128*n + 15 DIR INPUT MSA_In_015 A17 Isochronous And-Or Input Term 128*n + 16 COM INPUT MSA_In_016 B17 Isochronous And-Or Input Term 128*n + 16 DIR INPUT MSA_In_016 A18 Isochronous And-Or Input Term 128*n + 17 COM INPUT MSA_In_017 B18 Isochronous And-Or Input Term 128*n + 17 DIR INPUT MSA_In_017 A19 Isochronous And-Or Input Term 128*n + 18 COM INPUT MSA_In_018 B19 Isochronous And-Or Input Term 128*n + 18 DIR INPUT MSA_In_018 A20 Isochronous And-Or Input Term 128*n + 19 COM INPUT MSA_In_019 B20 Isochronous And-Or Input Term 128*n + 19 DIR INPUT MSA_In_019 A21 Isochronous And-Or Input Term 128*n + 20 COM INPUT MSA_In_020 B21 Isochronous And-Or Input Term 128*n + 20 DIR INPUT MSA_In_020 A22 Isochronous And-Or Input Term 128*n + 21 COM INPUT MSA_In_021 B22 Isochronous And-Or Input Term 128*n + 21 DIR INPUT MSA_In_021 A23 Isochronous And-Or Input Term 128*n + 22 COM INPUT MSA_In_022 B23 Isochronous And-Or Input Term 128*n + 22 DIR INPUT MSA_In_022 A24 Isochronous And-Or Input Term 128*n + 23 COM INPUT MSA_In_023 B24 Isochronous And-Or Input Term 128*n + 23 DIR INPUT MSA_In_023 A25 Isochronous And-Or Input Term 128*n + 24 COM INPUT MSA_In_024 B25 Isochronous And-Or Input Term 128*n + 24 DIR INPUT MSA_In_024 A26 Isochronous And-Or Input Term 128*n + 25 COM INPUT MSA_In_025 B26 Isochronous And-Or Input Term 128*n + 25 DIR INPUT MSA_In_025 A27 Isochronous And-Or Input Term 128*n + 26 COM INPUT MSA_In_026 B27 Isochronous And-Or Input Term 128*n + 26 DIR INPUT MSA_In_026 A28 Isochronous And-Or Input Term 128*n + 27 COM INPUT MSA_In_027 B28 Isochronous And-Or Input Term 128*n + 27 DIR INPUT MSA_In_027 A29 Isochronous And-Or Input Term 128*n + 28 COM INPUT MSA_In_028 B29 Isochronous And-Or Input Term 128*n + 28 DIR INPUT MSA_In_028 A30 Isochronous And-Or Input Term 128*n + 29 COM INPUT MSA_In_029 B30 Isochronous And-Or Input Term 128*n + 29 DIR INPUT MSA_In_029 A31 Isochronous And-Or Input Term 128*n + 30 COM INPUT MSA_In_030 B31 Isochronous And-Or Input Term 128*n + 30 DIR INPUT MSA_In_030 A32 Isochronous And-Or Input Term 128*n + 31 COM INPUT MSA_In_031 B32 Isochronous And-Or Input Term 128*n + 31 DIR INPUT MSA_In_031 C1 GROUND C2 +3.3V UPPER C3 GROUND C4 +3.3V UPPER C5 -2.0V UPPER C6 GROUND C7 +3.3V UPPER C8 GROUND C9 +5.0V UPPER C10 GROUND C11 +3.3V UPPER C12 GROUND C13 +3.3V UPPER C14 GROUND C15 -2.0V UPPER C16 GROUND C17 +3.3V UPPER C18 GROUND C19 +5.0V UPPER C20 +3.3V UPPER C21 GROUND C22 +3.3V UPPER C23 GROUND C24 -2.0V UPPER C25 GROUND C26 +3.3V UPPER C27 GROUND C28 +5.0V UPPER C29 +3.3V UPPER C30 GROUND C31 +3.3V UPPER C32 GROUND D1 Isochronous And-Or Input Term 128*n + 32 COM INPUT MSA_In_032 E1 Isochronous And-Or Input Term 128*n + 32 DIR INPUT MSA_In_032 D2 Isochronous And-Or Input Term 128*n + 33 COM INPUT MSA_In_033 E2 Isochronous And-Or Input Term 128*n + 33 DIR INPUT MSA_In_033 D3 Isochronous And-Or Input Term 128*n + 34 COM INPUT MSA_In_034 E3 Isochronous And-Or Input Term 128*n + 34 DIR INPUT MSA_In_034 D4 Isochronous And-Or Input Term 128*n + 35 COM INPUT MSA_In_035 E4 Isochronous And-Or Input Term 128*n + 35 DIR INPUT MSA_In_035 D5 Isochronous And-Or Input Term 128*n + 36 COM INPUT MSA_In_036 E5 Isochronous And-Or Input Term 128*n + 36 DIR INPUT MSA_In_036 D6 Isochronous And-Or Input Term 128*n + 37 COM INPUT MSA_In_037 E6 Isochronous And-Or Input Term 128*n + 37 DIR INPUT MSA_In_037 D7 Isochronous And-Or Input Term 128*n + 38 COM INPUT MSA_In_038 E7 Isochronous And-Or Input Term 128*n + 38 DIR INPUT MSA_In_038 D8 Isochronous And-Or Input Term 128*n + 39 COM INPUT MSA_In_039 E8 Isochronous And-Or Input Term 128*n + 39 DIR INPUT MSA_In_039 D9 Isochronous And-Or Input Term 128*n + 40 COM INPUT MSA_In_040 E9 Isochronous And-Or Input Term 128*n + 40 DIR INPUT MSA_In_040 D10 Isochronous And-Or Input Term 128*n + 41 COM INPUT MSA_In_041 E10 Isochronous And-Or Input Term 128*n + 41 DIR INPUT MSA_In_041 D11 Isochronous And-Or Input Term 128*n + 42 COM INPUT MSA_In_042 E11 Isochronous And-Or Input Term 128*n + 42 DIR INPUT MSA_In_042 D12 Isochronous And-Or Input Term 128*n + 43 COM INPUT MSA_In_043 E12 Isochronous And-Or Input Term 128*n + 43 DIR INPUT MSA_In_043 D13 Isochronous And-Or Input Term 128*n + 44 COM INPUT MSA_In_044 E13 Isochronous And-Or Input Term 128*n + 44 DIR INPUT MSA_In_044 D14 Isochronous And-Or Input Term 128*n + 45 COM INPUT MSA_In_045 E14 Isochronous And-Or Input Term 128*n + 45 DIR INPUT MSA_In_045 D15 Isochronous And-Or Input Term 128*n + 46 COM INPUT MSA_In_046 E15 Isochronous And-Or Input Term 128*n + 46 DIR INPUT MSA_In_046 D16 Isochronous And-Or Input Term 128*n + 47 COM INPUT MSA_In_047 E16 Isochronous And-Or Input Term 128*n + 47 DIR INPUT MSA_In_047 D17 Isochronous And-Or Input Term 128*n + 48 COM INPUT MSA_In_048 E17 Isochronous And-Or Input Term 128*n + 48 DIR INPUT MSA_In_048 D18 Isochronous And-Or Input Term 128*n + 49 COM INPUT MSA_In_049 E18 Isochronous And-Or Input Term 128*n + 49 DIR INPUT MSA_In_049 D19 Isochronous And-Or Input Term 128*n + 40 COM INPUT MSA_In_050 E19 Isochronous And-Or Input Term 128*n + 40 DIR INPUT MSA_In_050 D20 Isochronous And-Or Input Term 128*n + 51 COM INPUT MSA_In_051 E20 Isochronous And-Or Input Term 128*n + 51 DIR INPUT MSA_In_051 D21 Isochronous And-Or Input Term 128*n + 52 COM INPUT MSA_In_052 E21 Isochronous And-Or Input Term 128*n + 52 DIR INPUT MSA_In_052 D22 Isochronous And-Or Input Term 128*n + 53 COM INPUT MSA_In_053 E22 Isochronous And-Or Input Term 128*n + 53 DIR INPUT MSA_In_053 D23 Isochronous And-Or Input Term 128*n + 54 COM INPUT MSA_In_054 E23 Isochronous And-Or Input Term 128*n + 54 DIR INPUT MSA_In_054 D24 Isochronous And-Or Input Term 128*n + 55 COM INPUT MSA_In_055 E24 Isochronous And-Or Input Term 128*n + 55 DIR INPUT MSA_In_055 D25 Isochronous And-Or Input Term 128*n + 56 COM INPUT MSA_In_056 E25 Isochronous And-Or Input Term 128*n + 56 DIR INPUT MSA_In_056 D26 Isochronous And-Or Input Term 128*n + 57 COM INPUT MSA_In_057 E26 Isochronous And-Or Input Term 128*n + 57 DIR INPUT MSA_In_057 D27 Isochronous And-Or Input Term 128*n + 58 COM INPUT MSA_In_058 E27 Isochronous And-Or Input Term 128*n + 58 DIR INPUT MSA_In_058 D28 Isochronous And-Or Input Term 128*n + 59 COM INPUT MSA_In_059 E28 Isochronous And-Or Input Term 128*n + 59 DIR INPUT MSA_In_059 D29 Isochronous And-Or Input Term 128*n + 60 COM INPUT MSA_In_060 E29 Isochronous And-Or Input Term 128*n + 60 DIR INPUT MSA_In_060 D30 Isochronous And-Or Input Term 128*n + 61 COM INPUT MSA_In_061 E30 Isochronous And-Or Input Term 128*n + 61 DIR INPUT MSA_In_061 D31 Isochronous And-Or Input Term 128*n + 62 COM INPUT MSA_In_062 E31 Isochronous And-Or Input Term 128*n + 62 DIR INPUT MSA_In_062 D32 Isochronous And-Or Input Term 128*n + 63 COM INPUT MSA_In_063 E32 Isochronous And-Or Input Term 128*n + 63 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- (note: 0 <= n <= 1) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Isochronous And-Or Input Term 128*n + 64 COM INPUT MSA_In_064 B1 Isochronous And-Or Input Term 128*n + 64 DIR INPUT MSA_In_064 A2 Isochronous And-Or Input Term 128*n + 65 COM INPUT MSA_In_065 B2 Isochronous And-Or Input Term 128*n + 65 DIR INPUT MSA_In_065 A3 Isochronous And-Or Input Term 128*n + 66 COM INPUT MSA_In_066 B3 Isochronous And-Or Input Term 128*n + 66 DIR INPUT MSA_In_066 A4 Isochronous And-Or Input Term 128*n + 67 COM INPUT MSA_In_067 B4 Isochronous And-Or Input Term 128*n + 67 DIR INPUT MSA_In_067 A5 Isochronous And-Or Input Term 128*n + 68 COM INPUT MSA_In_068 B5 Isochronous And-Or Input Term 128*n + 68 DIR INPUT MSA_In_068 A6 Isochronous And-Or Input Term 128*n + 69 COM INPUT MSA_In_069 B6 Isochronous And-Or Input Term 128*n + 69 DIR INPUT MSA_In_069 A7 Isochronous And-Or Input Term 128*n + 70 COM INPUT MSA_In_070 B7 Isochronous And-Or Input Term 128*n + 70 DIR INPUT MSA_In_070 A8 Isochronous And-Or Input Term 128*n + 71 COM INPUT MSA_In_071 B8 Isochronous And-Or Input Term 128*n + 71 DIR INPUT MSA_In_071 A9 Isochronous And-Or Input Term 128*n + 72 COM INPUT MSA_In_072 B9 Isochronous And-Or Input Term 128*n + 72 DIR INPUT MSA_In_072 A10 Isochronous And-Or Input Term 128*n + 73 COM INPUT MSA_In_073 B10 Isochronous And-Or Input Term 128*n + 73 DIR INPUT MSA_In_073 A11 Isochronous And-Or Input Term 128*n + 74 COM INPUT MSA_In_074 B11 Isochronous And-Or Input Term 128*n + 74 DIR INPUT MSA_In_074 A12 Isochronous And-Or Input Term 128*n + 75 COM INPUT MSA_In_075 B12 Isochronous And-Or Input Term 128*n + 75 DIR INPUT MSA_In_075 A13 Isochronous And-Or Input Term 128*n + 76 COM INPUT MSA_In_076 B13 Isochronous And-Or Input Term 128*n + 76 DIR INPUT MSA_In_076 A14 Isochronous And-Or Input Term 128*n + 77 COM INPUT MSA_In_077 B14 Isochronous And-Or Input Term 128*n + 77 DIR INPUT MSA_In_077 A15 Isochronous And-Or Input Term 128*n + 78 COM INPUT MSA_In_078 B15 Isochronous And-Or Input Term 128*n + 78 DIR INPUT MSA_In_078 A16 Isochronous And-Or Input Term 128*n + 79 COM INPUT MSA_In_079 B16 Isochronous And-Or Input Term 128*n + 79 DIR INPUT MSA_In_079 A17 Isochronous And-Or Input Term 128*n + 80 COM INPUT MSA_In_080 B17 Isochronous And-Or Input Term 128*n + 80 DIR INPUT MSA_In_080 A18 Isochronous And-Or Input Term 128*n + 81 COM INPUT MSA_In_081 B18 Isochronous And-Or Input Term 128*n + 81 DIR INPUT MSA_In_081 A19 Isochronous And-Or Input Term 128*n + 82 COM INPUT MSA_In_082 B19 Isochronous And-Or Input Term 128*n + 82 DIR INPUT MSA_In_082 A20 Isochronous And-Or Input Term 128*n + 83 COM INPUT MSA_In_083 B20 Isochronous And-Or Input Term 128*n + 83 DIR INPUT MSA_In_083 A21 Isochronous And-Or Input Term 128*n + 84 COM INPUT MSA_In_084 B21 Isochronous And-Or Input Term 128*n + 84 DIR INPUT MSA_In_084 A22 Isochronous And-Or Input Term 128*n + 85 COM INPUT MSA_In_085 B22 Isochronous And-Or Input Term 128*n + 85 DIR INPUT MSA_In_085 A23 Isochronous And-Or Input Term 128*n + 86 COM INPUT MSA_In_086 B23 Isochronous And-Or Input Term 128*n + 86 DIR INPUT MSA_In_086 A24 Isochronous And-Or Input Term 128*n + 87 COM INPUT MSA_In_087 B24 Isochronous And-Or Input Term 128*n + 87 DIR INPUT MSA_In_087 A25 Isochronous And-Or Input Term 128*n + 88 COM INPUT MSA_In_088 B25 Isochronous And-Or Input Term 128*n + 88 DIR INPUT MSA_In_088 A26 Isochronous And-Or Input Term 128*n + 89 COM INPUT MSA_In_089 B26 Isochronous And-Or Input Term 128*n + 89 DIR INPUT MSA_In_089 A27 Isochronous And-Or Input Term 128*n + 90 COM INPUT MSA_In_090 B27 Isochronous And-Or Input Term 128*n + 90 DIR INPUT MSA_In_090 A28 Isochronous And-Or Input Term 128*n + 91 COM INPUT MSA_In_091 B28 Isochronous And-Or Input Term 128*n + 91 DIR INPUT MSA_In_091 A29 Isochronous And-Or Input Term 128*n + 92 COM INPUT MSA_In_092 B29 Isochronous And-Or Input Term 128*n + 92 DIR INPUT MSA_In_092 A30 Isochronous And-Or Input Term 128*n + 93 COM INPUT MSA_In_093 B30 Isochronous And-Or Input Term 128*n + 93 DIR INPUT MSA_In_093 A31 Isochronous And-Or Input Term 128*n + 94 COM INPUT MSA_In_094 B31 Isochronous And-Or Input Term 128*n + 94 DIR INPUT MSA_In_094 A32 Isochronous And-Or Input Term 128*n + 95 COM INPUT MSA_In_095 B32 Isochronous And-Or Input Term 128*n + 95 DIR INPUT MSA_In_095 C1 GROUND C2 +3.3V LOWER C3 GROUND C4 +3.3V LOWER C5 -4.5V LOWER C6 GROUND C7 +3.3V LOWER C8 GROUND C9 +5.0V LOWER C10 GROUND C11 +3.3V LOWER C12 GROUND C13 +3.3V LOWER C14 GROUND C15 -4.5V LOWER C16 GROUND C17 +3.3V LOWER C18 GROUND C19 +5.0V LOWER C20 +3.3V LOWER C21 GROUND C22 +3.3V LOWER C23 GROUND C24 -4.5V LOWER C25 GROUND C26 +3.3V LOWER C27 GROUND C28 +5.0V LOWER C29 +3.3V LOWER C30 GROUND C31 +3.3V LOWER C32 GROUND D1 Isochronous And-Or Input Term 128*n + 96 COM INPUT MSA_In_096 E1 Isochronous And-Or Input Term 128*n + 96 DIR INPUT MSA_In_096 D2 Isochronous And-Or Input Term 128*n + 97 COM INPUT MSA_In_097 E2 Isochronous And-Or Input Term 128*n + 97 DIR INPUT MSA_In_097 D3 Isochronous And-Or Input Term 128*n + 98 COM INPUT MSA_In_098 E3 Isochronous And-Or Input Term 128*n + 98 DIR INPUT MSA_In_098 D4 Isochronous And-Or Input Term 128*n + 99 COM INPUT MSA_In_099 E4 Isochronous And-Or Input Term 128*n + 99 DIR INPUT MSA_In_099 D5 Isochronous And-Or Input Term 128*n + 100 COM INPUT MSA_In_100 E5 Isochronous And-Or Input Term 128*n + 100 DIR INPUT MSA_In_100 D6 Isochronous And-Or Input Term 128*n + 101 COM INPUT MSA_In_101 E6 Isochronous And-Or Input Term 128*n + 101 DIR INPUT MSA_In_101 D7 Isochronous And-Or Input Term 128*n + 102 COM INPUT MSA_In_102 E7 Isochronous And-Or Input Term 128*n + 102 DIR INPUT MSA_In_102 D8 Isochronous And-Or Input Term 128*n + 103 COM INPUT MSA_In_103 E8 Isochronous And-Or Input Term 128*n + 103 DIR INPUT MSA_In_103 D9 Isochronous And-Or Input Term 128*n + 104 COM INPUT MSA_In_104 E9 Isochronous And-Or Input Term 128*n + 104 DIR INPUT MSA_In_104 D10 Isochronous And-Or Input Term 128*n + 105 COM INPUT MSA_In_105 E10 Isochronous And-Or Input Term 128*n + 105 DIR INPUT MSA_In_105 D11 Isochronous And-Or Input Term 128*n + 106 COM INPUT MSA_In_106 E11 Isochronous And-Or Input Term 128*n + 106 DIR INPUT MSA_In_106 D12 Isochronous And-Or Input Term 128*n + 107 COM INPUT MSA_In_107 E12 Isochronous And-Or Input Term 128*n + 107 DIR INPUT MSA_In_107 D13 Isochronous And-Or Input Term 128*n + 108 COM INPUT MSA_In_108 E13 Isochronous And-Or Input Term 128*n + 108 DIR INPUT MSA_In_108 D14 Isochronous And-Or Input Term 128*n + 109 COM INPUT MSA_In_109 E14 Isochronous And-Or Input Term 128*n + 109 DIR INPUT MSA_In_109 D15 Isochronous And-Or Input Term 128*n + 110 COM INPUT MSA_In_110 E15 Isochronous And-Or Input Term 128*n + 110 DIR INPUT MSA_In_110 D16 Isochronous And-Or Input Term 128*n + 111 COM INPUT MSA_In_111 E16 Isochronous And-Or Input Term 128*n + 111 DIR INPUT MSA_In_111 D17 Isochronous And-Or Input Term 128*n + 112 COM INPUT MSA_In_112 E17 Isochronous And-Or Input Term 128*n + 112 DIR INPUT MSA_In_112 D18 Isochronous And-Or Input Term 128*n + 113 COM INPUT MSA_In_113 E18 Isochronous And-Or Input Term 128*n + 113 DIR INPUT MSA_In_113 D19 Isochronous And-Or Input Term 128*n + 114 COM INPUT MSA_In_114 E19 Isochronous And-Or Input Term 128*n + 114 DIR INPUT MSA_In_114 D20 Isochronous And-Or Input Term 128*n + 115 COM INPUT MSA_In_115 E20 Isochronous And-Or Input Term 128*n + 115 DIR INPUT MSA_In_115 D21 Isochronous And-Or Input Term 128*n + 116 COM INPUT MSA_In_116 E21 Isochronous And-Or Input Term 128*n + 116 DIR INPUT MSA_In_116 D22 Isochronous And-Or Input Term 128*n + 117 COM INPUT MSA_In_117 E22 Isochronous And-Or Input Term 128*n + 117 DIR INPUT MSA_In_117 D23 Isochronous And-Or Input Term 128*n + 118 COM INPUT MSA_In_118 E23 Isochronous And-Or Input Term 128*n + 118 DIR INPUT MSA_In_118 D24 Isochronous And-Or Input Term 128*n + 119 COM INPUT MSA_In_119 E24 Isochronous And-Or Input Term 128*n + 119 DIR INPUT MSA_In_119 D25 Isochronous And-Or Input Term 128*n + 120 COM INPUT MSA_In_120 E25 Isochronous And-Or Input Term 128*n + 120 DIR INPUT MSA_In_120 D26 Isochronous And-Or Input Term 128*n + 121 COM INPUT MSA_In_121 E26 Isochronous And-Or Input Term 128*n + 121 DIR INPUT MSA_In_121 D27 Isochronous And-Or Input Term 128*n + 122 COM INPUT MSA_In_122 E27 Isochronous And-Or Input Term 128*n + 122 DIR INPUT MSA_In_122 D28 Isochronous And-Or Input Term 128*n + 123 COM INPUT MSA_In_123 E28 Isochronous And-Or Input Term 128*n + 123 DIR INPUT MSA_In_123 D29 Isochronous And-Or Input Term 128*n + 124 COM INPUT MSA_In_124 E29 Isochronous And-Or Input Term 128*n + 124 DIR INPUT MSA_In_124 D30 Isochronous And-Or Input Term 128*n + 125 COM INPUT MSA_In_125 E30 Isochronous And-Or Input Term 128*n + 125 DIR INPUT MSA_In_125 D31 Isochronous And-Or Input Term 128*n + 126 COM INPUT MSA_In_126 E31 Isochronous And-Or Input Term 128*n + 126 DIR INPUT MSA_In_126 D32 Isochronous And-Or Input Term 128*n + 127 COM INPUT MSA_In_127 E32 Isochronous And-Or Input Term 128*n + 127 DIR INPUT MSA_In_127 ---------------------------------------------------------------------- P4: 160-pin front-panel connector for card outputs ---------------------------------------------------------------------- (note: 0 <= n <= 1) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Partial And-Or Fired: Sp Trig 64*n + 63 DIR OUTPUT MSA_Out_63 B1 Partial And-Or Fired: Sp Trig 64*n + 63 COM OUTPUT MSA_Out_63 A2 Partial And-Or Fired: Sp Trig 64*n + 62 DIR OUTPUT MSA_Out_62 B2 Partial And-Or Fired: Sp Trig 64*n + 62 COM OUTPUT MSA_Out_62 A3 Partial And-Or Fired: Sp Trig 64*n + 61 DIR OUTPUT MSA_Out_61 B3 Partial And-Or Fired: Sp Trig 64*n + 61 COM OUTPUT MSA_Out_61 A4 Partial And-Or Fired: Sp Trig 64*n + 60 DIR OUTPUT MSA_Out_60 B4 Partial And-Or Fired: Sp Trig 64*n + 60 COM OUTPUT MSA_Out_60 A5 Partial And-Or Fired: Sp Trig 64*n + 59 DIR OUTPUT MSA_Out_59 B5 Partial And-Or Fired: Sp Trig 64*n + 59 COM OUTPUT MSA_Out_59 A6 Partial And-Or Fired: Sp Trig 64*n + 58 DIR OUTPUT MSA_Out_58 B6 Partial And-Or Fired: Sp Trig 64*n + 58 COM OUTPUT MSA_Out_58 A7 Partial And-Or Fired: Sp Trig 64*n + 57 DIR OUTPUT MSA_Out_57 B7 Partial And-Or Fired: Sp Trig 64*n + 57 COM OUTPUT MSA_Out_57 A8 Partial And-Or Fired: Sp Trig 64*n + 56 DIR OUTPUT MSA_Out_56 B8 Partial And-Or Fired: Sp Trig 64*n + 56 COM OUTPUT MSA_Out_56 A9 Partial And-Or Fired: Sp Trig 64*n + 55 DIR OUTPUT MSA_Out_55 B9 Partial And-Or Fired: Sp Trig 64*n + 55 COM OUTPUT MSA_Out_55 A10 Partial And-Or Fired: Sp Trig 64*n + 54 DIR OUTPUT MSA_Out_54 B10 Partial And-Or Fired: Sp Trig 64*n + 54 COM OUTPUT MSA_Out_54 A11 Partial And-Or Fired: Sp Trig 64*n + 53 DIR OUTPUT MSA_Out_53 B11 Partial And-Or Fired: Sp Trig 64*n + 53 COM OUTPUT MSA_Out_53 A12 Partial And-Or Fired: Sp Trig 64*n + 52 DIR OUTPUT MSA_Out_52 B12 Partial And-Or Fired: Sp Trig 64*n + 52 COM OUTPUT MSA_Out_52 A13 Partial And-Or Fired: Sp Trig 64*n + 51 DIR OUTPUT MSA_Out_51 B13 Partial And-Or Fired: Sp Trig 64*n + 51 COM OUTPUT MSA_Out_51 A14 Partial And-Or Fired: Sp Trig 64*n + 50 DIR OUTPUT MSA_Out_50 B14 Partial And-Or Fired: Sp Trig 64*n + 50 COM OUTPUT MSA_Out_50 A15 Partial And-Or Fired: Sp Trig 64*n + 49 DIR OUTPUT MSA_Out_49 B15 Partial And-Or Fired: Sp Trig 64*n + 49 COM OUTPUT MSA_Out_49 A16 Partial And-Or Fired: Sp Trig 64*n + 48 DIR OUTPUT MSA_Out_48 B16 Partial And-Or Fired: Sp Trig 64*n + 48 COM OUTPUT MSA_Out_48 A17 Partial And-Or Fired: Sp Trig 64*n + 47 DIR OUTPUT MSA_Out_47 B17 Partial And-Or Fired: Sp Trig 64*n + 47 COM OUTPUT MSA_Out_47 A18 Partial And-Or Fired: Sp Trig 64*n + 46 DIR OUTPUT MSA_Out_46 B18 Partial And-Or Fired: Sp Trig 64*n + 46 COM OUTPUT MSA_Out_46 A19 Partial And-Or Fired: Sp Trig 64*n + 45 DIR OUTPUT MSA_Out_45 B19 Partial And-Or Fired: Sp Trig 64*n + 45 COM OUTPUT MSA_Out_45 A20 Partial And-Or Fired: Sp Trig 64*n + 44 DIR OUTPUT MSA_Out_44 B20 Partial And-Or Fired: Sp Trig 64*n + 44 COM OUTPUT MSA_Out_44 A21 Partial And-Or Fired: Sp Trig 64*n + 43 DIR OUTPUT MSA_Out_43 B21 Partial And-Or Fired: Sp Trig 64*n + 43 COM OUTPUT MSA_Out_43 A22 Partial And-Or Fired: Sp Trig 64*n + 42 DIR OUTPUT MSA_Out_42 B22 Partial And-Or Fired: Sp Trig 64*n + 42 COM OUTPUT MSA_Out_42 A23 Partial And-Or Fired: Sp Trig 64*n + 41 DIR OUTPUT MSA_Out_41 B23 Partial And-Or Fired: Sp Trig 64*n + 41 COM OUTPUT MSA_Out_41 A24 Partial And-Or Fired: Sp Trig 64*n + 40 DIR OUTPUT MSA_Out_40 B24 Partial And-Or Fired: Sp Trig 64*n + 40 COM OUTPUT MSA_Out_40 A25 Partial And-Or Fired: Sp Trig 64*n + 39 DIR OUTPUT MSA_Out_39 B25 Partial And-Or Fired: Sp Trig 64*n + 39 COM OUTPUT MSA_Out_39 A26 Partial And-Or Fired: Sp Trig 64*n + 38 DIR OUTPUT MSA_Out_38 B26 Partial And-Or Fired: Sp Trig 64*n + 38 COM OUTPUT MSA_Out_38 A27 Partial And-Or Fired: Sp Trig 64*n + 37 DIR OUTPUT MSA_Out_37 B27 Partial And-Or Fired: Sp Trig 64*n + 37 COM OUTPUT MSA_Out_37 A28 Partial And-Or Fired: Sp Trig 64*n + 36 DIR OUTPUT MSA_Out_36 B28 Partial And-Or Fired: Sp Trig 64*n + 36 COM OUTPUT MSA_Out_36 A29 Partial And-Or Fired: Sp Trig 64*n + 35 DIR OUTPUT MSA_Out_35 B29 Partial And-Or Fired: Sp Trig 64*n + 35 COM OUTPUT MSA_Out_35 A30 Partial And-Or Fired: Sp Trig 64*n + 34 DIR OUTPUT MSA_Out_34 B30 Partial And-Or Fired: Sp Trig 64*n + 34 COM OUTPUT MSA_Out_34 A31 Partial And-Or Fired: Sp Trig 64*n + 33 DIR OUTPUT MSA_Out_33 B31 Partial And-Or Fired: Sp Trig 64*n + 33 COM OUTPUT MSA_Out_33 A32 Partial And-Or Fired: Sp Trig 64*n + 32 DIR OUTPUT MSA_Out_32 B32 Partial And-Or Fired: Sp Trig 64*n + 32 COM OUTPUT MSA_Out_32 C1 GROUND C2 +5.0V C3 GROUND C4 GROUND C5 GROUND C6 +3.3V C7 GROUND C8 GROUND C9 GROUND C10 -2.0V C11 GROUND C12 GROUND C13 GROUND C14 -4.5V C15 GROUND C16 GROUND C17 GROUND C18 GROUND C19 +5.0V C20 GROUND C21 GROUND C22 GROUND C23 +3.3V C24 GROUND C25 GROUND C26 GROUND C27 -2.0V C28 GROUND C29 GROUND C30 GROUND C31 -4.5V C32 GROUND D1 Partial And-Or Fired: Sp Trig 64*n + 31 DIR OUTPUT MSA_Out_31 E1 Partial And-Or Fired: Sp Trig 64*n + 31 COM OUTPUT MSA_Out_31 D2 Partial And-Or Fired: Sp Trig 64*n + 30 DIR OUTPUT MSA_Out_30 E2 Partial And-Or Fired: Sp Trig 64*n + 30 COM OUTPUT MSA_Out_30 D3 Partial And-Or Fired: Sp Trig 64*n + 29 DIR OUTPUT MSA_Out_29 E3 Partial And-Or Fired: Sp Trig 64*n + 29 COM OUTPUT MSA_Out_29 D4 Partial And-Or Fired: Sp Trig 64*n + 28 DIR OUTPUT MSA_Out_28 E4 Partial And-Or Fired: Sp Trig 64*n + 28 COM OUTPUT MSA_Out_28 D5 Partial And-Or Fired: Sp Trig 64*n + 27 DIR OUTPUT MSA_Out_27 E5 Partial And-Or Fired: Sp Trig 64*n + 27 COM OUTPUT MSA_Out_27 D6 Partial And-Or Fired: Sp Trig 64*n + 26 DIR OUTPUT MSA_Out_26 E6 Partial And-Or Fired: Sp Trig 64*n + 26 COM OUTPUT MSA_Out_26 D7 Partial And-Or Fired: Sp Trig 64*n + 25 DIR OUTPUT MSA_Out_25 E7 Partial And-Or Fired: Sp Trig 64*n + 25 COM OUTPUT MSA_Out_25 D8 Partial And-Or Fired: Sp Trig 64*n + 24 DIR OUTPUT MSA_Out_24 E8 Partial And-Or Fired: Sp Trig 64*n + 24 COM OUTPUT MSA_Out_24 D9 Partial And-Or Fired: Sp Trig 64*n + 23 DIR OUTPUT MSA_Out_23 E9 Partial And-Or Fired: Sp Trig 64*n + 23 COM OUTPUT MSA_Out_23 D10 Partial And-Or Fired: Sp Trig 64*n + 22 DIR OUTPUT MSA_Out_22 E10 Partial And-Or Fired: Sp Trig 64*n + 22 COM OUTPUT MSA_Out_22 D11 Partial And-Or Fired: Sp Trig 64*n + 21 DIR OUTPUT MSA_Out_21 E11 Partial And-Or Fired: Sp Trig 64*n + 21 COM OUTPUT MSA_Out_21 D12 Partial And-Or Fired: Sp Trig 64*n + 20 DIR OUTPUT MSA_Out_20 E12 Partial And-Or Fired: Sp Trig 64*n + 20 COM OUTPUT MSA_Out_20 D13 Partial And-Or Fired: Sp Trig 64*n + 19 DIR OUTPUT MSA_Out_19 E13 Partial And-Or Fired: Sp Trig 64*n + 19 COM OUTPUT MSA_Out_19 D14 Partial And-Or Fired: Sp Trig 64*n + 18 DIR OUTPUT MSA_Out_18 E14 Partial And-Or Fired: Sp Trig 64*n + 18 COM OUTPUT MSA_Out_18 D15 Partial And-Or Fired: Sp Trig 64*n + 17 DIR OUTPUT MSA_Out_17 E15 Partial And-Or Fired: Sp Trig 64*n + 17 COM OUTPUT MSA_Out_17 D16 Partial And-Or Fired: Sp Trig 64*n + 16 DIR OUTPUT MSA_Out_16 E16 Partial And-Or Fired: Sp Trig 64*n + 16 COM OUTPUT MSA_Out_16 D17 Partial And-Or Fired: Sp Trig 64*n + 15 DIR OUTPUT MSA_Out_15 E17 Partial And-Or Fired: Sp Trig 64*n + 15 COM OUTPUT MSA_Out_15 D18 Partial And-Or Fired: Sp Trig 64*n + 14 DIR OUTPUT MSA_Out_14 E18 Partial And-Or Fired: Sp Trig 64*n + 14 COM OUTPUT MSA_Out_14 D19 Partial And-Or Fired: Sp Trig 64*n + 13 DIR OUTPUT MSA_Out_13 E19 Partial And-Or Fired: Sp Trig 64*n + 13 COM OUTPUT MSA_Out_13 D20 Partial And-Or Fired: Sp Trig 64*n + 12 DIR OUTPUT MSA_Out_12 E20 Partial And-Or Fired: Sp Trig 64*n + 12 COM OUTPUT MSA_Out_12 D21 Partial And-Or Fired: Sp Trig 64*n + 11 DIR OUTPUT MSA_Out_11 E21 Partial And-Or Fired: Sp Trig 64*n + 11 COM OUTPUT MSA_Out_11 D22 Partial And-Or Fired: Sp Trig 64*n + 10 DIR OUTPUT MSA_Out_10 E22 Partial And-Or Fired: Sp Trig 64*n + 10 COM OUTPUT MSA_Out_10 D23 Partial And-Or Fired: Sp Trig 64*n + 9 DIR OUTPUT MSA_Out_09 E23 Partial And-Or Fired: Sp Trig 64*n + 9 COM OUTPUT MSA_Out_09 D24 Partial And-Or Fired: Sp Trig 64*n + 8 DIR OUTPUT MSA_Out_08 E24 Partial And-Or Fired: Sp Trig 64*n + 8 COM OUTPUT MSA_Out_08 D25 Partial And-Or Fired: Sp Trig 64*n + 7 DIR OUTPUT MSA_Out_07 E25 Partial And-Or Fired: Sp Trig 64*n + 7 COM OUTPUT MSA_Out_07 D26 Partial And-Or Fired: Sp Trig 64*n + 6 DIR OUTPUT MSA_Out_06 E26 Partial And-Or Fired: Sp Trig 64*n + 6 COM OUTPUT MSA_Out_06 D27 Partial And-Or Fired: Sp Trig 64*n + 5 DIR OUTPUT MSA_Out_05 E27 Partial And-Or Fired: Sp Trig 64*n + 5 COM OUTPUT MSA_Out_05 D28 Partial And-Or Fired: Sp Trig 64*n + 4 DIR OUTPUT MSA_Out_04 E28 Partial And-Or Fired: Sp Trig 64*n + 4 COM OUTPUT MSA_Out_04 D29 Partial And-Or Fired: Sp Trig 64*n + 3 DIR OUTPUT MSA_Out_03 E29 Partial And-Or Fired: Sp Trig 64*n + 3 COM OUTPUT MSA_Out_03 D30 Partial And-Or Fired: Sp Trig 64*n + 2 DIR OUTPUT MSA_Out_02 E30 Partial And-Or Fired: Sp Trig 64*n + 2 COM OUTPUT MSA_Out_02 D31 Partial And-Or Fired: Sp Trig 64*n + 1 DIR OUTPUT MSA_Out_01 E31 Partial And-Or Fired: Sp Trig 64*n + 1 COM OUTPUT MSA_Out_01 D32 Partial And-Or Fired: Sp Trig 64*n + 0 DIR OUTPUT MSA_Out_00 E32 Partial And-Or Fired: Sp Trig 64*n + 0 COM OUTPUT MSA_Out_00 ---------------------------------------------------------------------- P5: 34-pin front-panel connector for "global" signals ---------------------------------------------------------------------- Pin # Signal Description Dir Identifi ----- ------------------ --- -------- 1 P5 Global I/O Signal 0 DIR BIDIR P5_IO_00 2 P5 Global I/O Signal 0 COM BIDIR P5_IO_00 3 P5 Global I/O Signal 1 DIR BIDIR P5_IO_01 4 P5 Global I/O Signal 1 COM BIDIR P5_IO_01 5 P5 Global I/O Signal 2 DIR BIDIR P5_IO_02 6 P5 Global I/O Signal 2 COM BIDIR P5_IO_02 7 P5 Global I/O Signal 3 DIR BIDIR P5_IO_03 8 P5 Global I/O Signal 3 COM BIDIR P5_IO_03 9 P5 Global I/O Signal 4 DIR BIDIR P5_IO_04 10 P5 Global I/O Signal 4 COM BIDIR P5_IO_04 11 P5 Global I/O Signal 5 DIR BIDIR P5_IO_05 12 P5 Global I/O Signal 5 COM BIDIR P5_IO_05 13 P5 Global I/O Signal 6 DIR BIDIR P5_IO_06 14 P5 Global I/O Signal 6 COM BIDIR P5_IO_06 15 P5 Global I/O Signal 7 DIR BIDIR P5_IO_07 16 P5 Global I/O Signal 7 COM BIDIR P5_IO_07 17 P5 Global I/O Signal 8 DIR BIDIR P5_IO_08 18 P5 Global I/O Signal 8 COM BIDIR P5_IO_08 19 P5 Global I/O Signal 9 DIR BIDIR P5_IO_09 20 P5 Global I/O Signal 9 COM BIDIR P5_IO_09 21 P5 Global I/O Signal 10 DIR BIDIR P5_IO_10 22 P5 Global I/O Signal 10 COM BIDIR P5_IO_10 23 P5 Global I/O Signal 11 DIR BIDIR P5_IO_11 24 P5 Global I/O Signal 11 COM BIDIR P5_IO_11 25 P5 Global I/O Signal 12 DIR BIDIR P5_IO_12 26 P5 Global I/O Signal 12 COM BIDIR P5_IO_12 27 P5 Global I/O Signal 13 DIR BIDIR P5_IO_13 28 P5 Global I/O Signal 13 COM BIDIR P5_IO_13 29 P5 Global I/O Signal 14 DIR BIDIR P5_IO_14 30 P5 Global I/O Signal 14 COM BIDIR P5_IO_14 31 P5 Global I/O Signal 15 DIR BIDIR P5_IO_15 32 P5 Global I/O Signal 15 COM BIDIR P5_IO_15 33 P5 Global I/O Signal 16 DIR BIDIR P5_IO_16 34 P5 Global I/O Signal 16 COM BIDIR P5_IO_16