***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * AONM Electrical Tester * * * * FPGA Description * * * ***************************** Original: 23-SEP-1997 Latest: 13-OCT-1997 Introduction ------------ This file describes the And-Or Network Module "Electrical Tester" FPGA. It is used to test the following aspects of the AONM: - downloading FPGA configuration via VME - VME access of registers within an FPGA - VME access of RAM within an FPGA - interrupt propagation from FPGA to VME interface to VME to TCC - soldering of FPGA's - power consumption - ... Implementation -------------- The AONMET has the following features: 1. On-Card Bus/JTAG/High-Quality Timing Signal Interface This is a "component" from the MSU FPGA Common Block Library. 2. Chip-Level Condition/Status Register This is a 32-bit register, spread across 2 Register Addresses, used to control and monitor the operation of the FPGA (e.g. it contains interrupt-enable and interrupt-request bits). This component is specific to this FPGA (not part of the Common Block Library), but similar functionality will be required on other FPGA's. 3. Scratch Registers There are multiple 16-bit "scratch" registers in this FPGA. These scratch registers use CLB's configured as D flip-flops as memory elements, and are distributed in address space in such a way as to stress the register-address decoding logic, allowing us to verify that the decoding logic does not produce glitches which cause unintended register writes. Recall that the decoders and flip-flop memory elements are relatively inefficient in their CLB usage, so we can only afford to have around 16 of these registers (using around 128 CLB's). 4. Scratch RAM This FPGA also has some "scratch" RAM. This RAM uses CLB's configured as RAM as memory elements. Again this memory is distributed in address space in such a way as to stress the register-address decoding logic. The register address decoding logic for RAM-style memory is different from that for register-style memory so it is important to carefully test both types. Also recall that the decoders and RAM memory elements are relatively efficient in their CLB usage, so we can have many more RAM-style memory locations (compared to register-style). 5. 128 input pins This FPGA is configured with 128 "Main Signal" inputs. These 128 input signals are latched on the rising edge of the lowest High-Quality Timing Signal servicing its column (e.g. HQ_TS(0)), using D-latches. Their states are readable via VME. This allows testing of all the MSA Input solder joints on all MSA FPGA's (as well as much of the OCB solder joints), by simultaneously latching all MSA Inputs on all MSA FPGA's, and then slowly reading them out via VME. We can also experiment with the MSA Input setup time (vs. the clock) requirements. 6. 4 output pins This FPGA is configured with 4 "Main Signal" outputs, again as on the And-Or Network Module FPGA. This FPGA can drive all 4 outputs from each of the 16 MSA FPGA's. These 4 output signals are controlled by a read/write register, which is accessible via VME. 7. Power consumption logic Some fraction of the CLB's are configured simply to consume power. A single toggle flip-flop, toggling at a variable frequency, feeds a 192-stage shift register. The idea is that a toggling flip flop is a very good way to burn power. The flip flop toggle frequency is controllable via VME. The output of the last 4 stages of the shift register are available on the 4 MSA Output pins of the FPGA. The power burner looks like: .---------------------. | | | .---------------. | .-----------. | | 8-bit counter | | | 8-1 mux | | | | | | | .-------. HQ_TS(1) --+--|CLK Q(7:0)|--+--|D(7:0) Q|---| bufgs |----. | | | | `-------' | Ctr_Clk_Enb --|CE | | | | | | | E S(2:0) | | `---------------' `-----------' | | | | Mux_Enb -----------------------------' | | | | Mux_Sel ----------------------------------' | | | .-------------+-------------------------------------' | | | .------. | .---------------------------. | | FTC | | | 192-stage shift register | | | | | | | `--|C | `--|C | | | | | Toggle_Enb ----|T Q|------|D Q|--- Output `------' | | | | SR_Enb ---------------------|CE | `---------------------------' The power consumption can be controlled as follows: 1. Vary the incoming clock frequency on HQ_TS(1). If this clock is totally shut off, then the burner will burn effectively NO power. 2. Enable/disable the 8-bit counter. If the counter is disabled, the only power consumed will be the HQ_TS(1) clock distribution network 3. Vary the MUX control. The mux can be totally disabled, in which case the only power consumed will be the HQ_TS(1) clock distribution network and the 8-bit counter power. The mux also has 8 setings of "downstream" clock frequency: Mux sel "downstream clock freq" "toggle freq" ------- ----------------------- ------------- 000 HQ_TS(1) HQ_TS(1) / 2 001 HQ_TS(1) / 2 HQ_TS(1) / 4 010 HQ_TS(1) / 4 HQ_TS(1) / 8 011 HQ_TS(1) / 8 HQ_TS(1) / 16 100 HQ_TS(1) / 16 HQ_TS(1) / 32 101 HQ_TS(1) / 32 HQ_TS(1) / 64 110 HQ_TS(1) / 64 HQ_TS(1) / 128 111 HQ_TS(1) / 128 HQ_TS(1) / 256 By varying the "downstream" clock frequency, the power consumed by the downstream circuitry can be varied. 4. Enable/disable the toggle flip-flop. If the toggle flip-flop is disabled, the only power consumed will be the HQ_TS(1) clock distribution network, the 8-bit counter power, and the "downstream frequency" clock distribution network. 5. Enable/disable the shift register. If the shift register is disabled, the only power consumed will be the HQ_TS(1) clock distribution network, the 8-bit counter power, the "downstream frequncy" clock distribution network, and the toggle flip flop. With the shift register enabled, all circuitry is consuming power. The amount of power consumed can be varied as described in item 3. Other features which could be placed in this FPGA are: 1. High-Speed Readout Interface This would be extremely useful as a testbed for the High-Speed Readout Interface. Making a functional HSRO Interface requires both circuitry in this FPGA and circuitry in the Board Support Functions FPGA. The implementational details of this circuitry have not yet been finalized, but we should all review how this interface is intended to work, how it talks to the rest of the optical readout system, and what VME-based testing and control features we want/need for long-term support. 2. ... Programming Interface --------------------- The AONMET has the following VME-visible registers: VME Byte Address Offset (in HEX, Reg from card base Register Addr Access address) Contents ---- ------ -------------- -------- 0 R/W $000 Chip Control Status Register (LSW) 1 R/W $002 Chip Control Status Register (MSW) 4 R/W $008 Power Burner Control Status Register 8 R $010 Main Signal Input 15:0 Readback 9 R $012 Main Signal Input 31:16 Readback 10 R $014 Main Signal Input 47:32 Readback 11 R $016 Main Signal Input 63:48 Readback 12 R $018 Main Signal Input 79:64 Readback 13 R $01a Main Signal Input 95:80 Readback 14 R $01c Main Signal Input 111:96 Readback 15 R $01e Main Signal Input 127:112 Readback 16 R/W $020 Main Signal Output 3:0 32-47 R/W $040 - $05f RAM Bank 1 48-63 R/W $060 - $07f RAM Bank 2 128-129 R/W $100 - $101 Scratch Registers 144-145 R/W $120 - $121 Scratch Registers 160-161 R/W $140 - $141 Scratch Registers 176-177 R/W $160 - $161 Scratch Registers 192-193 R/W $180 - $181 Scratch Registers 208-209 R/W $1a0 - $1a1 Scratch Registers 224-225 R/W $1c0 - $1c1 Scratch Registers 240-241 R/W $1e0 - $1e1 Scratch Registers The bit allocation in most registers is straightforward. Within a single Main Signal Input or Output register, the least significant bit (e.g. Main Signal Input Bit 0 appears at D0 in register 8). The bit allocation in the Chip Status Register is as follows: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 unallocated The Chip Status Register MSW is currently unused. The Power Burner Control Status Register (Register Address 4) is allocated as follows: Bit Access Contents --- ------ -------- 0 R/W Counter Clock Enable ('1': 8-bit counter enabled) 1 R/W Mux Output Enable ('1': Mux output enabled) 2 R/W Toggle Enable ('1': Toggle enabled) 3 R/W Shift Register Clock Enable ('1': Shift Register Clock enabled) 6:4 R/W Mux Output Select 15:7 unallocated See the description of the power burning circuitry above for details of how these controls affect the power burning circuitry. The MSA Output Register (Register Address 16) is allocated as follows: Bit Access Contents --- ------ -------- 3:0 R/W MSA Output 3:0 Test Data 7:4 unallocated 11:8 R/W MSA Output 3:0 Toggle Output Enable ('1': Output driven from power burner)