***************************** * * * D-Zero Run II Upgrade * * * * Calorimeter Trigger * * * * Bougie FPGA * * * ***************************** Original: 5-MAY-1999 Latest: 6-DEC-2000 Introduction ------------ The Bougie FPGA is designed to be used in the BSF FPGA of a THE Card. It receives data from the Distributor Card (DC) and provides output via the HSROCB for both L2 and L3. Each Bougie FPGA has the following input and output connections: 1. On-Card Bus (EXCEPT for the High-Quality Timing Signals). 2. P1 Timing Signals 3. P5 Global I/O Signals Used as Inputs - 16 Input Data Terms and 1 Strobe 4. High-Speed Readout Operation--General Comments --------------------------- During data taking, the Bougie FPGA receives 128 words of Trigger Tower Et data in serial via the P5 Global I/O connector. Each word contains 8 bits of EM Et and 8 bits of Total Et for a given eta and phi and is accompanied by a strobe. As the data is received, it is compared to the Seed Reference Set and the result is stored in the Seed Mask Array. The Seed Reference Set accomodates 8 different reference values, one for each eta for both EM Et and Total Et. The 128 input words along with the Seed Mask Array and a header and trailer are provided to the HSROCB for readout. (See Data Format from L1 Cal Trig to L2 Cal_pp for more information on the input and output data formats.) The Bougie FPGA also has a second mode (selected via TCC) in which it must cope with data from two ticks. This mode is only for use during calibration, and the L2 Cal_pp will not use the output. In this mode, the seeds will be generated for all 256 input words; the additional words in the Seed Mask Array may or may not be readout. The Bougie FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Input Latch 3. Seed Mask Generator 4. Header and Trailer Generator, consisting of: A. Header Generator B. Trailer Generator C. Tick and Turn Counter 5. Transport Control 6. Data Source Selection and Output MUX Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. Input Latch The data is captured as it comes in. The strobe that accompanies the data is delayed, aligned with the Accelerator Clock, and sent back out as DAV*. The number of words received is counted and is available via TCC for error checking. 3. Seed Mask Generator The reference values are stored in dual port RAMS. There is one 8 bit RAM for the EM Et reference values and one for the Total Et reference values. Each RAM can store 4 values, one for each eta. The data is received in the following order: D15 D8 D7 D0 --------------------------------------------------------- EM Et eta = +1, phi = 1 Tot Et eta = +1, phi = 1 EM Et eta = +2, phi = 1 Tot Et eta = +2, phi = 1 EM Et eta = +3, phi = 1 Tot Et eta = +3, phi = 1 EM Et eta = +4, phi = 1 Tot Et eta = +4, phi = 1 EM Et eta = +1, phi = 2 Tot Et eta = +1, phi = 2 . . . EM Et eta = +4, phi = 32 Tot Et eta = +4, phi = 32 Thus, the read address for the RAMs must change every time a new word is received and repeat every 4 words. To accomplish this, the read address (which is the same for both RAMs) is determined by the lowest 2 bits of an 8 bit counter. The results of the comparisons, i.e. the sixteen, 16 bit words of the Seed Mask Array, are stored in a two identical sets of sixteen, 16 bit dual port RAMs (one set for EM Et and one for Tot Et). The Seed Mask Array is readout in the following order: D15 D8 D7 D0 --------------------------------------------------------- EM Et > L2 Seed EM Et Ref for eta = +1, Phi = 16:1 8 words EM Et > L2 Seed EM Et Ref for eta = +1, Phi = 32:17 of Em Et EM Et > L2 Seed EM Et Ref for eta = +2, Phi = 16:1 > Ref . . . EM Et > L2 Seed EM Et Ref for eta = +4, Phi = 32:17 Tot Et > L2 Seed Tot Et Ref for eta = +1, Phi = 16:1 8 words Tot Et > L2 Seed Tot Et Ref for eta = +1, Phi = 32:17 of Tot Et . > Ref . . Tot Et > L2 Seed Tot Et Ref for eta = +4, Phi = 32:17 If there are 256 Input Data Words, this may be repeated a second time. 6-Dec-2000 I think if 16 words for EM Et and 16 words for Tot Et are readout, all of the EM Et comes out first followed by the Tot Et (as opposed to 8 EM Et, 8 Tot Et, 8 more EM Et and 8 more Tot Et). Because the incoming data cycles through all etas for a given phi and the Seed Mask Array cycles through all of the phis for a given eta, the write addresses for the RAMs can not increment in a completely straightforward manner. Thus although the write addresses of the RAMs are determined by bits from the Seed Reference Set Counter, the bits must be reordered. Additionally, each of the 16 bits in a given word must be able to be written individually. To cope with this, each RAM will handle a single bit rather than a single readout word, e.g. RAM #0 for both the EM Et and Tot Et data contains bit 0 for all 8 readout words. The bits in the Seed Mask Array for either EM Et or Tot Et (they are written in parallel) are written in the following order: D15 D8 D7 D1 D0 --------------------------------------------------------- 5 1 68 65 6 2 69 66 7 3 70 67 64 8 4 Thus, RAM #0 will be written 4 consecutive times, then RAM #1 is written 4 consecutive times, etc. After all 16 RAMS have been written, the cycle is repeated with a different set of 4 write addresses for each RAM. Consequently, the RAM selection can be controlled by the decoded version of bits 5:2 of the Seed Reference Set Counter. Within a given RAM, address 0 is written first, followed by 2, 4, and 6. After the even addresses have been written for all RAMS, addresses 1, 3, 5, and 7 are written. This can be accomplished by using bit 6 of the Seed Reference Counter as bit 0 of the RAM write address and bits 0, 1, and 2 of the Counter as write address bits 1, 2, and 3 respectively. To accomodate the 256 word mode, bit 7 of the counter is used as write address bit 4, thus the Seed Mask Array for the second 128 words is written in the same order as for the first 128 words but in the second half of the RAMS. The read addresses of the RAMs are controlled by a separate counter which only increments after all the Trigger Tower data has been processed. The EM Et data is readout first, followed by the Tot Et data. The data in this case is accompanied by a DAV* based on a gated P1 Timing Signal. 4.A Header Generator As defined in the Data Format from L1 Cal Trig to L2 Cal_pp, the Header contains several words of static information (Header Length, Number of Objects, Header/Object Format, Object Length, Data Type, Algorithm Major and Minor Version, Status Bits, and Processor Specific Bits). This information is provided by TCC via a register. The Header also contains a Tick and a Turn Number provided by the local counter. The Header is of course readout before the data. Therefore, the readout of the Header is started upon the receipt of an L1 Accept; there must be sufficient time between the L1 Accept and the arrival of the first Input Data Word for the header to be completely readout. As with the Seed Mask Array, the words in the Header are accompanied by a DAV* based on a gated P1 Timing Signal. 4.B Trailer Generator The first word in the Trailer is a second copy of some of the information in the Header (Data Type and Tick Number). The final output word is the Longitudinal Parity. Each bit in the Longitudinal Parity word is set or not set depending on whether that bit was set an odd or even number of times respectively over the course of the event. The words in the Trailer are again accompanied by a DAV* based on a gated P1 Timing Signal. 4.C Tick and Turn Counter Both the Header and the Trailer call for a Tick and a Turn Number. Since the actual Tick and Turn are not available, they are simulated by a 24 bit counter which increments in some convenient fashion and does not roll over any faster than the actual Tick and Turn Numbers do. The counter should read the same for all 10 G-links. 5. Transport Control The readout in the Bougie is handled using a token ring. It is initiated by an L1 Accept and is completed when the final trailer word is been sent. 6. Data Source Selection and Output MUX The data and strobe from the various sources all pass through a final output multiplexer. The output of this multiplexer is selected by spying on the token ring. Programming Interface --------------------- The Bougie FPGA has the following VME-visible registers: NB In all cases, the number of words should be set assuming that first word is counted as word 0. That is, if there are 6 header words, the number of expected header words should be set to 5. Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 4 R/W Number of Input Data Words Expected 5 R Current Number of Input Words 8 R/W G-Link Control 16 R/W Data Type 17 R/W Header Word 0 18 R/W Header Word 1 19 R/W Header Word 2 20 R/W Header Word 5 21 R/W Number of Header Words 23 R/W Number of Trailer Words 24 R/W Tick Counter 25 R/W Turn Counter 32 R/W Reference Value RAM Program Address Register 33 R/W Reference Value 35 R/W Number of Seed Mask Words 36 R Token Ring Status The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Reference Value Program Enable ('1': enable programming of Reference Value RAMs '0': lock programming of Reference Value RAMs) 15:4 not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Tick 1 R/W Enable Timing Signal Reset for Turn 15:2 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Tick 1 R/W Force Reset for Turn 15:2 R/W not allocated Number of Input Data Words Expected Bit Access Contents --- ------ -------- 7:0 R/W Number of Words Expected 15:8 R/W not allocated Current Number of Input Words Bit Access Contents --- ------ -------- 7:0 R Number of Words Received 15:8 R not allocated G-Link Control Bit Access Contents --- ------ -------- 0 R/W RST* 1 R/W FF 2 R/W ED 3 R/W Flag 5:4 R/W Div(1:0) 6 R/W M20Sel 7 R/W FlagSel 8 R/W LoopEn 9 R/W CAV* 15:10 not allocated Data Type Bit Access Contents --- ------ -------- 7:0 R/W Data Type 15:8 R/W not allocated Number of Header Words Bit Access Contents --- ------ -------- 2:0 R/W Number of Header Words 15:3 R/W not allocated Number of Trailer Words Bit Access Contents --- ------ -------- 1:0 R/W Number of Trailer Words 15:2 R/W not allocated Reference Value RAM Program Address Register Bit Access Contents --- ------ -------- 1:0 R/W RAM Program Address(1:0) 15:2 R/W not allocated Reference Value Bit Access Contents --- ------ -------- 7:0 R/W Tot Et Reference Value 15:8 R/W EM Et Reference Value Number of Seed Mask Words Bit Access Contents --- ------ -------- 3:0 R/W Number of Seed Mask Words NB This is actually half the total number of words, i.e. it is the number of EM OR the number of Tot Seed Mask Words (it is assumed that these numbers are equal). That is, normally it should be set to 8. 6-Dec-2000 I think it should normally be set to 7 since the counting starts at 0. Kirsten 15:4 R/W not allocated Token Ring Status Bit Access Contents --- ------ -------- 0 R Transport Header (active low) 1 R Transport Data(active low) 2 R Transport Seed Mask (active low) 3 R Transport Trailer (active low) 4 R Transport Complete (active low) 15:5 R not allocated ============================================================================= Notes added from summer 2001 about the Bougie Data Source Sequence Control Start with Transport_Trailer_Out* aka Trans_Done* coming out of the Header/Trialer Generator module being not asserted. This goes to: Transport_Complete* in the Transport Control module Transport_Complete* in the Data Source Selection module L1_Acpt is asserted and goes to the Transport Control module where it causes Begin_Transport* aka Begin Trans* to be asserted. Begin_Transport* aka Begin Trans* goes to: DAV* Enable Transport_Header_In* in the Data Source Selection module Transport_Header_In* in the Head/Trail Generator module In the Data Source Selection module the asserted Transport_Header_In* signal causes: The Data_Src_Select_0 signal to be asserted (assuming that Transport_Data_In* is at its high voltage state, which it will be) In the Head/Trail Generator module the asserted Transport_Header_In* goes to: the Header Data module Transport_Header_In* pin where its falling to the low voltage state causes: Stop synchronously clearing a counter Stop force reseting a FF Enable an output gate In the Header Data module after n ticks of the BX_Clock the signal Transport_Header_Out* signal will be asserted. Where "n" is controlled by the value in the Number of Header Words register. Transport_Header_Data_Out* comes out of the Header Data module and then out of the Head/Trail Generator where and is then routed as Trans_Done* to the: Transport_Data_In* on the Data Source Selector module Transport_Data_In* on the Input Latch module Transport_Data_In* on the Seed Mask Generator module and to the Trailer Data module Begin_Trans* pin where its falling to the low voltage state causes: Stop force resetting a FF When this FF is released and then set by the first DAV it enables the Check Sum Generator to start cycling on every word as it is sent out to the G-Link. The Check Sum Generator is in the Trailer Data module. In the Data Source Selector module the asserted Transport_Data_In* signal causes: The Data_Src_Select_1 signal to be asserted (assuming that Transport_Mask_In* is at its high voltage state, which it will be) In the Input Latch module the asserted Transport_Data_In* signal causes: Transport_Data_In* falling to its low voltage asserted state stops force clearing a FF that was holding Transport_Data_Out* not asserted - voltage hi. Now after a programmable number of P5_Glb Input_Data_Strobes a counter output will equal a comparator threshold and the Transport_Data_Out* signal will be asserted - voltage low. Transport_Data_Out* comes out of the Input Latch module and then it is routed as Trans_Mask* to the: Transport_Mask_In* on the Data Source Selector module Transport_Mask_In* on the Seed Mask Generator module In the Seed Mask Generator module the asserted Transport_Data_In* signal causes: Transport_Data_In* falling to its low voltage asserted state stops force Async Clearing an 8 bit counter that is clock by P5_Glb Input_Data_Strobes and provides an address to a memory array in the Seed Mask Generator module. In the Data Source Selector module the asserted Transport_Mask_In* signal causes: The Data_Src_Select_2 signal to be asserted (assuming that Transport_Trailer_In* is at its high voltage state, which it will be) In the Seed Mask Generator module the asserted Transport_Mask_In* signal is routed to the L2_Seed_Mask_Array module. In the L2_Seed_Mask_Array module the signal Transport_Mask_In* falling to its low voltage asserted state stops force Async Clearing a number of FF's and counters and it stops forcing Transport_Mask_Out* to its inactive state. After a programmable number of BX_Clocks the Transport_Mask_Out* signal will go to it active voltage low state. Transport_Mask_Out* comes out of the L2_Seed_Mask_Array module and then out of the Seed_Mask_Generator module and is then routed as Trans_Trailer* to the: Transport_Trailer_In* on the Data Source Selector module Transport_Trailer_In* on the Header/Trailer Generator module