***************************** * * * D-Zero Run II Upgrade * * * * Calorimeter Trigger * * * * Cal Trig RO FPGA * * * ***************************** Original: 27-APR-1999 Latest: 6-DEC-2000 Introduction ------------ The Cal Trig RO (CTRO) FPGA can be used in any or all MSA FPGA locations on an AONM card. It provides HSRO and Monitor copies of the data and can also provide MSA outputs for use as AOIT to the L1 Framework. Each CTRO FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 128 MSA Inputs 3. 4 MSA Outputs Operation--General Comments --------------------------- The CTRO FPGA is designed to be a general purpose readout FPGA. It allows a subset of 32 of the 128 MSA inputs to be selected, put through a Beam Crossing History Shift Register (in this case, it is really a dual port RAM, hence BXHRAM), and then captured for High-Speed Readout and for Monitor Readout. Optionally, 4 of the 32 bits can be driven out as MSA Outputs prior to passing through the BXHRAM. Alternatively, 2 of the MSA Outputs can be driven by High Quality Timing Signals (HQ TS), allowing the FPGA to provide gap and strobe signals as required by the TRM. The CTRO FPGA is composed of the following elements: 1. On-Card Bus Interface 2. MSA Input Selection 3. Beam Crossing History Shift Register 4. Data Capture and Readout 5. MSA Output Selection Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. MSA Input Selection This is nothing more than a large multiplexer. The 128 MSA Inputs are grouped into 4 sets of 32 signals; TCC selects a set via a control register. 3. Beam Crossing History Shift Register Because of the number of bits and the large latency (up to 16 stages of the BXHRAM), it is impractical to implement the BXHRAM in the usual fashion. Instead it is similar to the BXHRAM in the ERPB. 4. Data Capture and Readout The standard Data Capture and Readout blocks from the MSU FPGA Common Block Library are used to handle both the HSRO and the Monitor Readout. Their operation is described elsewhere and will not be repeated here. 5. MSA Output Selection As with the Input Selection, this is nothing more than a multiplexer. The 32 Selected Inputs are divided into 8 groups of 4 signals. TCC can disable the MSA Outputs, select one of the 8 sets, or select the HQ TS, in which case 2 of the Outputs will be the gap and the strobe and 2 of the Outputs will be unused. The gap signal is expected on HQ TS(1) and the strobe on HQ TS (2). Programming Interface --------------------- The CTRO FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 8 R/W Input Selection MUX Control Register 16 R/W Output Selection MUX Control Register 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of Selected Data (LSB) 37 R Monitor Readout copy of Selected Data (MSB) The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 not allocated The Chip Status Register MSW is currently unused. Input Selection MUX Control Register Bit Access Contents --- ------ -------- 1:0 R/W Input Selection ('0': inputs 31:0 '1': inputs 63:32 '2': inputs 95:64 '3': inputs 127:96) 15:2 not allocated Output Selection MUX Control Register Bit Access Contents --- ------ -------- 0 R/W Enable Output 1 R/W Select Output ('0': data output '1': gap/strobe output) 3:2 not allocated 6:4 R/W Data Selection ('0': data bits 3:0 '1': data bits 7:4 '2': data bits 11:8 '3': data bits 15:12 '4': data bits 19:16 '5': data bits 23:20 '6': data bits 27:24 '7': data bits 31:28) 15:7 not allocated HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable HSRO_Data 15:3 not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Bit Access Contents --- ------ -------- 4:0 R/W Latency of data (Recall that capturing the data in essence adds 1 stage of delay. The data for the previous beam crossing will be captured for readout if a latency of 1 is selected.) 15:5 not allocated