CTOM FPGA Description ------------------------- Original Version: 19-NOV-2003 Current Version: 21-NOV-2003 The CTOM is eventually excexted to act as a full Calorimeter Trigger Output Module. For a first implementation in the fall of 2003 we need it for generation of the Quadrant Terms. We need to be able to do the logic to make the CHTCR "Hint" signals into Quadrant Terms and to set the timing of the Quadrant Term signals so it is appropriate for sending to the TFW as And-Or Terms. In the fullness of time it would be nice to send all of our L1 Cal Trig And-Or Terms to the TFW by sending them through the CTOM. This will require a some what fancier CTOM than what is being put together now in the fall of 2003. To enable the CTOM to handle any of the signals from the Cal Trig it will need to have some means to "age" data at its input before it is feed to the central "FOM" logic. The current idea is that the outputs from all of the CTOM's would be in sync and that the "Strobe and Gap" will be added to the CTOM output, external to the CTOM, and then sent to the TFW. One of the functions of the CTOM is to make the And-Or Terms from the Cal Trig visible, both as HSRO data from the Cal Trig, and as data from monitor registers. On one hand this will be straight forward because the CTOM will have HSRO and Monitor Data functions "for free". On the other hand it is a little complicated because: Cal Trig cycles at 396 nsec and the BX_Clk to the HSRO is 132 nsec, and because the input term latch to the CTOM is run by a clock that is appropriate for Cal Trig timing and then the data is handed off to the Beam Crossing History Shift Register and HSRO circuits that run on TFW BX_Clock. All of this should be workable with little trouble. On the THE-Cards that are used for CTOM we will also run 4 Miguel FPGA's to give assess to the input term data to the card. This will has the same issue of the Miguel sampling with BX_Clk at 3x the cycle time of the Cal Trig. CTOM was derived from the PT_ANOM (to pickup the cleanest representation of the central "FOM" logic), had its central logic changed to "ORing" instead of "ANDing", and had its input buffer changed to a 128 bit wide D-Latch input section (that was picked up from the DAVE FPGA). In addition the HQ_TS_ signals that operate the input and output latches were changed. The current setup of HQ timing signals to the Main Array is the following: Main Array HQ_TS_ Function - Name ---------- ------------------------- HQ_TS_0 Trig FW Tick Clk BX_Clk HQ_TS_2 CTOM Input Register Clk HQ_TS_1 CTOM Output Register Clk HQ_TS_3 Scaler Reset At some point a fancier input section may be added to allow adjustable aging of data. If this is added it will require additional control registers to setup the CTOM FPGA. For now the programming interface is the same as it is form "normal" AONM and FOM. CTOM Programming Interface -------------------------- The AONM FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W Input_Term(15:0), Channel(3:0) Programming information 17 R/W Input_Term(31:16), Channel(3:0) Programming information 18 R/W Input_Term(47:32), Channel(3:0) Programming information 19 R/W Input_Term(63:48), Channel(3:0) Programming information 20 R/W Input_Term(79:64), Channel(3:0) Programming information 21 R/W Input_Term(95:80), Channel(3:0) Programming information 22 R/W Input_Term(111:96), Channel(3:0) Programming information 23 R/W Input_Term(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord The bit allocation in each of these registers is: Chip Control Status Register LSW Register Address = 0 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Lookup Program Enable ('1': enable programming of lookup memories '0': lock programming of lookup memories) 15:4 --- not allocated The Chip Status Register MSW is currently unused Register Address = 1 Enable Timing Signal Reset Register Address = 2 Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 15:4 R/W not allocated Force Scaler Reset Register Address = 3 Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 15:4 R/W not allocated Lookup Programming Address Register Register Address = 8 Bit Access Contents --- ------ -------- 0 R/W AOIT 4*n + 0 Lookup Programming Address 1 R/W AOIT 4*n + 1 Lookup Programming Address 2 R/W AOIT 4*n + 2 Lookup Programming Address 3 R/W AOIT 4*n + 3 Lookup Programming Address 15:4 R/W not allocated Input_Term Programming Information Register Address = 16:23 (example for Input_Term(15:0), Channel(3:0) shown): Bit Access Contents --- ------ -------- 0 R/W Term(3:0) Channel(0) Stage 1 Partial And-Or Fired 1 R/W Term(3:0) Channel(1) Stage 1 Partial And-Or Fired 2 R/W Term(3:0) Channel(2) Stage 1 Partial And-Or Fired 3 R/W Term(3:0) Channel(3) Stage 1 Partial And-Or Fired 4 R/W Term(7:4) Channel(0) Stage 1 Partial And-Or Fired 5 R/W Term(7:4) Channel(1) Stage 1 Partial And-Or Fired 6 R/W Term(7:4) Channel(2) Stage 1 Partial And-Or Fired 7 R/W Term(7:4) Channel(3) Stage 1 Partial And-Or Fired 8 R/W Term(11:8) Channel(0) Stage 1 Partial And-Or Fired 9 R/W Term(11:8) Channel(1) Stage 1 Partial And-Or Fired 10 R/W Term(11:8) Channel(2) Stage 1 Partial And-Or Fired 11 R/W Term(11:8) Channel(3) Stage 1 Partial And-Or Fired 12 R/W Term(15:12) Channel(0) Stage 1 Partial And-Or Fired 13 R/W Term(15:12) Channel(1) Stage 1 Partial And-Or Fired 14 R/W Term(15:12) Channel(2) Stage 1 Partial And-Or Fired 15 R/W Term(15:12) Channel(3) Stage 1 Partial And-Or Fired The details of programming these registers and the use of the Lookup Programming Address register is the same as for the FOM cards in the TFW. HSRO State Register Address = 24 Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Register Address = 25 Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Register Address = 32 Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Monitor Readout copy of HSRO States Register Address = 36 Bit Access Contents --- ------ -------- 0 R Channel 0 Output: Triggered Tick - 1 1 R Channel 1 Output: Triggered Tick - 1 2 R Channel 2 Output: Triggered Tick - 1 3 R Channel 3 Output: Triggered Tick - 1 4 R Channel 0 Output: Triggered Tick 5 R Channel 1 Output: Triggered Tick 6 R Channel 2 Output: Triggered Tick 7 R Channel 3 Output: Triggered Tick 8 R Channel 0 Output: Triggered Tick + 1 9 R Channel 1 Output: Triggered Tick + 1 10 R Channel 2 Output: Triggered Tick + 1 11 R Channel 3 Output: Triggered Tick + 1 12 R Channel 0 Output: Triggered Tick + 2 13 R Channel 1 Output: Triggered Tick + 2 14 R Channel 2 Output: Triggered Tick + 2 15 R Channel 3 Output: Triggered Tick + 2