***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * Framework Output Module * * * * Plus - Plus * * * * FPGA Description * * * ***************************** Original: 1-DEC-1995 Latest: 20-NOV-2003 Introduction ------------ The FOM++ FPGA is very similar to the FOM FPGA but with additional functionality. In particular, its outputs can be 4 L1 qualifiers (one of which may be a hardware qualifier), 4 bits of the L3 transfer number, or 4 skip next N beam crossing signals. The programming interface is a superset of the programming interface for the FOM. Note that the first word provided for HSRO is the same as the Monitor Readout Copy of HSRO States. The second word provided for HSRO is the current (i.e. no BXHSR) L3 Xfer Number. Also note that the L3 Xfer number is always active, regardless of whether or not a particular FPGA makes use of the L3 Xfer Number. Output Logic ------------ Full History Shift Register and Logic HSRO +---> for 1st HSRO Word ----- 1st | Word | +-----------<----------- Bit 0 \ +---- Skip Next N ----------+ \ | Generator | \ | | \ | ____ \ | +-----| | \ FOM Type | | | \ Function i.e. ---+--- Mux to -----\-----------------| 4:1| | L1 Qualifiers +--- Pick Qual(3) \ | MUX| | | (HW or not) 0 MUX | | | Hardware ---+ <-----o--/------| 4 |----+----- MSA Qualifier 0 4 | Bit| Output Mux to / | | +--- Pick the 4 --/-----------------|____| | L3 Trn Num | to Output | | L3 Trans | Number -----/---+ Counter 16 | | Latch for +------- Monitor ---------------- Monitor Readout | Readout of | L3 Trn Num | | | Latch for +-------- HSRO 2nd ---------------- HSRO Readout Word 2nd Word data The "L1 Qual - L3 Trans Num" MUX is controlled by the "Send L2 Decision" signal which is P1_TS_14 in this crate; the other MUXs are controlled by TCC. The "Latch for the Monitor Readout of L3 Trans Num" is clocked by Tick_Clk enabled by Capture Monitor Data signal. The "Latch for the HSRO 2nd Word" is clocked by Tick_Clk enabled by Capture HSRO Data signal. The L3 Trans Num Counter is incremented by Tick_Clk enabled by the Increment L3 Trans Num signal. More information on the signals that cause the L3 Trans Num to increment, control the mux of this data to the MSA_Output of the FOM++, control the distribution of this number via the SCL, and control the latching and transport of this number to L3 via the L3 control path is available in: l1/framework/drawings/the_layout_sf_fom.gif l1/framework/drawings/the_layout_l2_fw_cards.gif l1/framework/hardware/helper_functions/l2_fw_helper_function_design.txt Control of the L3 Trans Num is described in text and in an ascii state diagram near the end of l2_fw_helper_function_design.txt Note that there is no guarantee that the value of the L3 Trans Num that is being HSROed will match the L3 Trans Num that is actually used to transport the event into L3. What is expected: At very slow running (i.e. never a L1_Accept N+1 before the L2_Accept for event N) they will match i.e. you capture the value of the L3 Trans Num Counter for HSRO at L1 Accept time you use this value in the L3 Trans Num Counter to issue the L2 Accept via SCL and send it to L3 via the L3 Control Path some ticks after the L2 Accept you increment the L3 Trans Num Counter to get ready for the next L2 Accept. Note that the first L3 XFer Number is 0 and so even in this situation, the L3 XFer Number will not agree with, for instance, the event number from the BSF or the Gated Scaler which is counting the number of L1 Accepts. Assuming that all of the scalers were reset to begin with and that only L2 Accepts are being issued and there are no L2 Rejects, the L3 Xfer number should be one behind the event number, etc. At high speed running (i.e. you have L1_Accept N and then issue L2_Accepts for events N-1 and maybe N-2 and N-3... before you issue the L2_Accept for event N) then the value of the L3 Trans Num in the HSRO will be behind (i.e. lower than) the value of the L3 Trans Num that is used to transport the event to L3. Running at a high rate with a lot of L2 Reject then this will tend to reduce the difference, e.g. you capture the value of the L3 Trans Num with L1_Accept N but before you issue the L2_Accept for event N you issue the L2 Decisions for events N-1 and maybe N-2 and N-3... But they are all L2 Reject so the L3 Trans Num does not increment between the time of the L1 Accept for event N and the L2_Accept for event N. The HSRO value of the L3 Trans Num inside the event should never be larger than the L3 Trans Num that was used to transport the event into L3. Note also that we want to count on never capturing smeared L3 Xfer Number data. Even if on the same Tick_Clk edge we both increment the L3 Trans Num counter and clock one of the capture latches, we want to capture all bits of the L3 Trans Num representing their before increment value. If on one Tick_Clk edge we increment the L3 Trans Num and on the next Tick_Clk edge we clock one of the latches, then we want to capture all bits of the L3 Trans Num representing their after increment value. Since both the L3 XFer Number counter and the capture latches are clocked by the Tick_Clk and only enabled by the Inc L3 Xfer Number, CMD, and Capture HSRO Data signals, there should be no problem with capturing correct, clean data. Programming Interface --------------------- The FOM++ FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W ST(15:0), Channel(3:0) Programming information 17 R/W ST(31:16), Channel(3:0) Programming information 18 R/W ST(47:32), Channel(3:0) Programming information 19 R/W ST(63:48), Channel(3:0) Programming information 20 R/W ST(79:64), Channel(3:0) Programming information 21 R/W ST(95:80), Channel(3:0) Programming information 22 R/W ST(111:96), Channel(3:0) Programming information 23 R/W ST(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord 48 R Monitor Copy of L3 Xfer Number Readout (16 bits) (captured when the Capture Monitor Data signal is asserted) 128 R/W L1 Qualifier, L3 Xfer Number, and Output Selection 130:129 R/W Skip Next N Control The bit allocation in each of these registers is: Chip Control Status Register LSW Register Address 0 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Lookup Program Enable ('1': enable programming of lookup memories '0': lock programming of lookup memories) 15:4 --- not allocated The Chip Status Register MSW is currently unused. Register Address 1 Enable Timing Signal Reset Register Address 2 Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 11:4 R/W not allocated 12 R/W Enable Timing Signal Reset for L3 Transfer Number 15:13 R/W not allocated Force Scaler Reset Register Address 3 Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 11:4 R/W not allocated 12 R/W Force Reset for L3 Transfer Number 15:13 R/W not allocated Lookup Programming Address Register Register Address 8 Bit Access Contents --- ------ -------- 0 R/W ST 4*n + 0 Lookup Programming Address 1 R/W ST 4*n + 1 Lookup Programming Address 2 R/W ST 4*n + 2 Lookup Programming Address 3 R/W ST 4*n + 3 Lookup Programming Address 15:4 R/W not allocated HSRO State Register Address 24 Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Register Address 25 Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Register Address 32 Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Monitor Readout Copy of HSRO States Register Address 36 Bit Access Contents --- ------ -------- 0 R Channel 0 Output: Triggered Tick - 1 1 R Channel 1 Output: Triggered Tick - 1 2 R Channel 2 Output: Triggered Tick - 1 3 R Channel 3 Output: Triggered Tick - 1 4 R Channel 0 Output: Triggered Tick 5 R Channel 1 Output: Triggered Tick 6 R Channel 2 Output: Triggered Tick 7 R Channel 3 Output: Triggered Tick 8 R Channel 0 Output: Triggered Tick + 1 9 R Channel 1 Output: Triggered Tick + 1 10 R Channel 2 Output: Triggered Tick + 1 11 R Channel 3 Output: Triggered Tick + 1 12 R Channel 0 Output: Triggered Tick + 2 13 R Channel 1 Output: Triggered Tick + 2 14 R Channel 2 Output: Triggered Tick + 2 15 R Channel 3 Output: Triggered Tick + 2 L1 Qualifier, L3 Xfer Number, and Output Selection Register Address 128 Bit Access Contents --- ------ -------- 0 R/W L1 Qualifier #3 selection (1 selects the hardware source) 2:1 R/W Select the group of L3 Xfer Number bits (0 for bits 3:0, 1 for bits 7:4 2 for bits 11:8, 3 for bits 15:12) 4:3 R/W MSA Output Selection (0: always L1 Qualifier 1: always L3 Xfer Number 2: L1 Qualifier or L3 Xfer depending on the state of the Send L2 Decision timing signal 3: always skip next N beam crossing signals) 15:5 R/W unallocated Skip Next N Comparator #0 Control Register Address 129 Bit Access Contents --- ------ -------- 15:0 R/W Stop Value for comparator 0 Skip Next N Comparator #1 Control Register Address 130 Bit Access Contents --- ------ -------- 15:0 R/W Stop Value for comparator 1 Notes about Skip Next N Comparators: The Stop Values should in fact be N-2, e.g. to skip the next 3 beam crossings, the Stop Value would be 1. Before August 2002 the Skip Next N Counter - Comparators were only 8 bits long and there were 4 of these Counter - Comparators implemented in the FPGA. In that design these same two 16 bit registers (Reg Adrs 129 and 130) were used to load the 8 bit long threshold values for all 4 comparators. Since August 2002 we have only 2 Skip Next N Counter - Comparators in the design. They are each 16 bits long and can thus provide a maximum Skip Next N time of 65k x 132 nsec = 8.65 mill seconds. 16 bit regesters at addresses 129 and 130 are used to load the Comparator threshold values as shown above. The MSA_Output signals for Skip Next N Comparators #2 and #3 are tied Low inside the FPGA.