How to program the FOM++ at Initialize Time: First, a reminder about what site performs what function (lifted from the "Special Functions" file under L1 FW AONM: FPGA Front Site Generates these Paddle MSA_Output Signals Numb MSA_Outputs Conn. Function and Destination ---- ----------------- ------ ---------------------------------- 1 MSA_Output(3:0) \ J 15:0 are the Multiplexed output 2 MSA_Output(7:4) | 15 of L1 Quals (set 0) and L3 3 MSA_Output(11:8) | :0 Transfer Number. This goes 4 MSA_Output(15:12) / to the SCL Hub End 5 MSA_Output(19:16) \ J 31:16 are the Multiplexed output 6 MSA_Output(23:20) | 31 of L1 Quals (set 1) and L3 7 MSA_Output(27:24) | :16 Transfer Number. This goes 8 MSA_Output(31:28) / to the SCL Hub-End. 9 MSA_Output(35:32) \ J 35:32 4 copies of Skip Next 10 MSA_Output(39:36) | 47 39:36 4 copies of L1 Trig Strobe 11 MSA_Output(43:40) | :32 43:40 4 Skip next N Programmable 12 MSA_Output(47:44) / 47:44 4 Diagnostic Scaler Control 13 MSA_Output(51:48) \ J 63:48 outputs are NOT used 14 MSA_Output(55:52) | 63 All 4 of these FPGA sites (13,14,15, 15 MSA_Output(59:56) | :48 16) are used for Miguel FPGA's to 16 MSA_Output(63:60) / readout the Spec Trig's Fired Mask. First, look at the 8 sites generating L1 Qualifiers. Here is how to program those sites (special programming different from FOM) at FW Initialize time: All registers with RA *below* 128 are just plain old FOM registers. The only differences are RA 128, 129, and 130: RA Contents -- -------- 128 sites 1, 5: 0x0010 ! L3 Xfr muxed with L1 Quals, sites 2, 6: 0x0012 ! the 0/2/4/6 variation selects sites 3, 7: 0x0014 ! which 4 L3 Xfr Number bits sites 4, 8: 0x0016 ! are sent... 129 0 ! these registers are used 130 0 ! for Skip Next BX control only Sites 9 and 10 make the L1 Accept Strobe and Skip Next BX signals (these are 2 names for the same signal...) They are programmed *exactly* like a standard FOM. Site 11 makes the 4 programmable "Skip Next N Ticks" signals. At Initialize time, let's not worry about the value of "N". Programming as follows: RA Contents -- -------- 128 0x0018 ! outputs are Skip Next N Tick 129 0 ! at Init time don't worry about 130 0 ! which Ticks we're skipping... One thing to note about Site 11: we're going to need a special FOM++ for this site, that latches its output on the Tick Clock *FALLING* edge, as required for producing And-Or Input Terms (like in the TTS and SCL Helper). I haven't yet made that FPGA. Sites 13 through 16 *should* contain Miguel FPGA's. They currently don't, instead they have FOM++ FPGA's. This is to make SCT work (note that we don't put Miguels in the Exp Group AONM's for the same reason). I'd like to switch to using Miguels in these locations. When not using Miguels, these sites are initialized like normal FOM's. When using Miguels, these sites are initialized as follows: RA Contents -- -------- 0 0 16 site 13: 0 ! reads MSA_In 31:0 site 14: 1 ! reads MSA_In 63:32 site 15: 2 ! reads MSA_In 95:64 site 16: 3 ! reads MSA_In 127:96 25 0 ! no HSRO data from Miguels 32 ??? ! which Ticks do we want to ! read out from Miguels? There ! was some issue about modifying ! which ones we read out to get ! a wider overall spread of Tick ! data? Note that the Exp Group AONM Miguels will be initialized just like these Miguels, except for (probably) RA 32 which needs to be tweaked due to 1st half/2nd half of FW pipeline issues. ----------------------------------------------------------------------- Trics Initialization of the FOM++ "Output Select Register" at FA 128 15-Sept-2003 This is a review of how Trics manages the FOM++ Output Select register in preparation for modifying the L1FW hardware to generate the "L2_UnbiasedSample" and the "Collect_Status" L1 qualifiers. The FOM++ FPGA needs to start using its "hardware input source" to generate this type of qualifier. From the FOM++ documentation: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/aonm/fompp_fpga_description.txt > L1 Qualifier, L3 Xfer Number, and Output Selection > > Bit Access Contents > --- ------ -------- > 0 R/W L1 Qualifier #3 selection > (1 selects the hardware source) > > 2:1 R/W Select the group of L3 Xfer Number bits > (0 for bits 3:0, 1 for bits 7:4 > 2 for bits 11:8, 3 for bits 15:12) > > 4:3 R/W MSA Output Selection > (0: always L1 Qualifier > 1: always L3 Xfer Number > 2: L1 Qualifier or L3 Xfer depending on the state > of the Send L2 Decision timing signal > 3: always skip next N beam crossing signals) > > 15:5 R/W unallocated Trics initializes each card in several phases, going from a generic FPGA level to a detailed level matching the identity of each particular resource. The FOM++ card initialization is a special case because the FOM++ card is special in two ways. (1) The FOM++ FPGA/Card is a superset of the FOM FPGA/Card, and is thus first handled as a generic FOM FPGA/card. (2) The FOM FPGA/Card is also a special case because Trics uses common AONM/FOM code as much as possible. There is even a third way that makes the FOM++ card special: the four upper FPGAs (#13-16) are Miguels, but this particularity is already handled by the common AONM/FOM code and does not affect this refister. The FOM++ card is first initialized as a generic AONM/FOM card but these initialization steps do not address register FA 128 which is a register specific to the FOM++ and which does not exist in the FOM. The FOM++ functionality itself is initialized in two steps: first at the generic FPGA level looped over each FOM++/Miguel FPGA, then at the FOM++ card level. After this card level initialization the functionality of the FOM++ within the L1FW trigger system has been configured. There is yet a higher level of initialization that can tune the operation of the FOM++ for a particular behavior. FA 128 is however not modified by this last step (this last step is where, for example, Trics programs the "N" for the first copy of the Skip Next N Ticks with the value 18-decimal which corresponds to a ~2.6 us delay). Functionality FPGA Init Card Init FPGA # 1 L1 Qual 00:03 1st copy 0x00 0x10 FPGA # 2 L1 Qual 04:07 1st copy 0x00 0x12 FPGA # 3 L1 Qual 08:11 1st copy 0x00 0x14 FPGA # 4 L1 Qual 12:15 1st copy 0x00 0x16 FPGA # 5 L1 Qual 00:03 2nd copy 0x00 0x10 FPGA # 6 L1 Qual 04:07 2nd copy 0x00 0x12 FPGA # 7 L1 Qual 08:11 2nd copy 0x00 0x14 FPGA # 8 L1 Qual 12:15 2nd copy 0x00 0x16 FPGA # 9 Skip Next Tick (4 copies) 0x00 ---- FPGA # 10 L1 Trigger Strobe (4 copies) 0x00 ---- FPGA # 11 Skip Next N (4 progr N) 0x00 0x18 FPGA # 12 Diagnostics Scalers (4 scalers) 0x00 ---- FPGA # 13 Miguel ---- ---- FPGA # 14 Miguel ---- ---- FPGA # 15 Miguel ---- ---- FPGA # 16 Miguel ---- ---- After system initialization, Trics does not have to address FA 128 ever again. It is thus safe to modify the programming of this FOM++ control register from within Init_Post_Auxi_L1FW.rio. We may in fact prefer to live that way and make the specificity of which L1 Qualifiers use the "hardware input source" something that Trics never knows about. The advantage is that we won't need new code when this allocation changes. On the other hand, one advantage of making Trics aware of this allocation would be to make Trics able to complain back to COOR if a configuration were to request a L1 Qualifier that is using its hardware input source instead of the FOM functionality to generate L1 Qualifiers. This round of implementation includes the L2_UnbiasedSample flag which is L1 Qualifier #3 and the CollectStatus flag which is L1Qualifier #7. This means that the Output Select Register of FPGA #1, #2, #5, and #6 need to have their LSBit set. We can leave the other 2 sets of potential hardware input terms untouched at the moment. Init_Post_AuxiL1FW.rio FPGA # 1 L1 Qual 00:03 1st copy 0x11 FPGA # 2 L1 Qual 04:07 1st copy 0x13 FPGA # 3 L1 Qual 08:11 1st copy ---- FPGA # 4 L1 Qual 12:15 1st copy ---- FPGA # 5 L1 Qual 00:03 2nd copy 0x11 FPGA # 6 L1 Qual 04:07 2nd copy 0x13 FPGA # 7 L1 Qual 08:11 2nd copy ---- FPGA # 8 L1 Qual 12:15 2nd copy ---- This translates into the following RIO commands: Vertical_Master: 1 ! M123 Vertical_Slave: 1 ! Middle Crate Slot: 16 ! FOM++ Register_Address: 128 ! all IOs are to the "Output Select Register" ! Program L1 Qualifier #3 to use its hardware input. ! This is the L2UnbiasedSample Flag, i.e. the grand OR of all individual SpTrg ! L2Unbiased countdown scaler flags ! The L1 Qualifiers 0:3 are also programmed to present ! the L3 Transfer Number bits 0:3 during L2 decision SCL frames Chip_Address: 1 Write_Value: 0x0011 ! and there are two copies of each L1 Qualifier Chip_Address: 5 Write_Value: 0x0011 ! Program L1 Qualifier #7 to use its hardware input. ! This is the CollectStatus Flag, i.e. monit info to be captured for this event ! The L1 Qualifiers 4:7 are also programmed to present ! the L3 Transfer Number bits 4:7 during L2 decision SCL frames Chip_Address: 2 Write_Value: 0x0013 Chip_Address: 6 Write_Value: 0x0013