***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * And-Or Network Module * * * * FPGA Description * * * ***************************** Original: 12-SEP-1995 Latest: 6-MAY-2003 Introduction ------------ This description of the Level 1 And-Or FPGA is for the version that includes the Pseudo-Term functionality. The And-Or FPGA is used in all MSA FPGA locations on the And-Or Network Module cards. Each And-Or FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 128 Input Terms (these are Main Signal Array (MSA) Input Signals). 3. 4 Output Terms (these are MSA Output Signals). Operation --------- The And-Or FPGA is used to perform the And-Or Fired processing and the Exposure Group (And-Or Input Term) processing. The And-Or FPGA is composed of the following elements: 1. On-Card Bus Interface 2. "Hardwired" Pseudo And-Or Input Term (P-Term) Generation 3. Four Separate Processing Channels, each consisting of: A. Programmable "AND" processing of H-Terms and P-Terms B. 32-bit Scaler with Monitor Data readout C. HSRO Data Capture and Readout D. Monitor Data Capture and Readout Each element is described below: 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. "Hardwired" Pseudo And-Or Input Term (P-Term) Generation The AONM FPGA contains "hardwired" logic for generating up to 48 Pseudo And-Or Input Terms (P-Terms). P-Terms are combinations of a number of the 128 Hardware And-Or Input Terms (H-Terms) serviced by a single AONM FPGA. There are some "rule of thumb" limitations on the complexity of P-Terms. Each P-Term can be composed of up to 32 H-Terms. The logic should be "no too complicated," such that it can be performed in no more than about 3 tiers of CLB's. This is best judged by expanding the logic and trying to sketch out the gates required to implement it, but often a quick perusal of the definition is all that is required. All Specific Triggers have access to the same set of P-Terms (i.e. all of the Physics AOIT Processing FPGA's are identical). P-Terms must be defined as logical combination of H-Terms. Note that the H-Terms used in P-Term processing must be LOCKED to particular AOIT Input Term numbers. A detailed assessment of the CLB usage, and delay, associated with the generation of each P-Term must be performed as part of the "feasibility study" of each P-Term. For each Specific Trigger the Trigger List then contains the P-Terms and H-Terms used by that Specific Trigger. The P-Term and H-Term used by a given Specific Trigger are programmed by TCC before each run, as discussed below. 3. Four Separate Processing Channels All four Processing Channels on this FPGA are identical, and are composed of the following elements: A. Programmable "AND" processing B. 32-bit Scaler C. Monitor Data Capture and Readout A single Processing Channel services a single Specific Trigger. 3.A Programmable "AND" Processing The And-Or Requirements for a given Channel can be thought of as four arrays of boolean flags: (1) INCLUDE (Hardware And-Or Input Term "H-Term") (128 bits) (2) INCLUDE (Pseudo And-Or Input Term "P-Term) ( 48 bits) If this flag is true, the H-Term (or P-Term) is INCLUDED in the logic for this Channel. If this flag is false, the H-Term (or P-Term) is IGNORED for this Channel. (3) VETO (Hardware And-Or Input Term "H-Term) (128 bits) (4) VETO (Pseudo And-Or Input Term "P-Term") ( 48 bits) This flag is only meaningful if the H-Term (or P-Term) is INCLUDED for this Channel. If this flag is false, the H-Term (or P-Term) is required to be HIGH. If this flag is true, the H-Term (or P-Term) is required to be LOW (i.e. this H-Term or P-Term acts as a VETO for this channel). Conceptually, then, the logic works as follows: .-----. H-Term 0 -----| | .-----. | XOR |-----| | .-------. VETO HT 0 ----| | | OR |---| | `-----' .-o| | | | | `-----' | | INCLUDE HT 0 ----------' | 176- | . | input | . | AND | . | | .-----. | | H-Term 127 ---| | .-----. | | | XOR |-----| | | | VETO HT 127 --| | | OR |---| | `-----' .-o| | | | | `-----' | | INCLUDE HT 127 --------' | | | |---- Channel Partial .-----. | | And-Or Fired P-Term 0 -----| | .-----. | | | XOR |-----| | | | VETO PT 0 ----| | | OR |---| | `-----' .-o| | | | | `-----' | | INCLUDE PT 0 ----------' | | . | | . | | . | | .-----. | | P-Term 47 ----| | .-----. | | | XOR |-----| | | | VETO PT 47 ---| | | OR |---| | `-----' .-o| | `-------' | `-----' INCLUDE PT 47 ---------' In terms of CLB requirement, physically implementing the logic in this way is prohibitively expensive. Instead, for both the P-Terms and the H-Terms, the INCLUDE and VETO flags are encoded as the data stored in 16x1 dual-port SRAM's within the FPGA's. Each group of 4 H-Terms or P-Terms serves as the "read" address of the SRAM's, while the "write" address of the SRAM's comes from a special programming register. The "read" data of the SRAM's go to a tree of AND gates, while the "write" data of the SRAM's comes from TCC. Note that each 16x1 dual-port SRAM occupies a single CLB, thus the flag storage and processing logic for FOUR H-Terms or P-Terms fits in a single CLB. The physical implementation of the logic (write address and write data omitted for clarity) is shown below: .-----------. |A 16 D| H-Term ---/---|D x1 A|---/--- (3:0) 4 |D SRAM T| 1 |R A| `-----------' . . (32 such blocks) . .-----------. |A 16 D| H-Term ---/---|D x1 A|---/--- (127:124) 4 |D SRAM T| 1 |R A| `-----------' (total of 44 signals) .-----------. |A 16 D| P-Term ---/---|D x1 A|---/--- (3:0) 4 |D SRAM T| 1 |R A| `-----------' . . (12 such blocks) . .-----------. |A 16 D| P-Term ---/---|D x1 A|---/--- (47:44) 4 |D SRAM T| 1 |R A| `-----------' The 44 output signals are then ANDed together. One possible arrangement for this 44-input AND tree is a single 5-input AND gate, fed by 4 9-input AND gates and one 8-input AND gate. Other arrangements exist, but at least 2 tiers of "post-lookup" logic, and approximately 6 CLB's, are required for all reasonable layouts. Each Channel's programmable AND logic uses: 44 16x1 SRAM's @ 1 CLB each = 44 CLB's 1 "post-lookup" AND tree @ 6 CLB's = 6 CLB's For a total of 50 CLB's arranged in 3 tiers. Note that each of the 128 H-Terms, and each of the 48 P-Terms, must be fed in parallel to 4 16x1 dual-port SRAM's (one per Channel). 3.B 32-bit Scaler For each Channel, the Partial And-Or Fired acts as the gate of a 32-bit Scaler. The clock of this Scaler is the Tick Clock. This scaler can be read as monitoring data. The synchronous reset for each Scaler is controlled by an individual reset signal. The Scaler Reset can come from a High-Quality Timing Signal or from a VME-visible register. The High-Quality Timing Signal reset must be enabled by TCC, but the register reset can be used to force a scaler reset at any time. The Scaler Reset passes through the Beam Crossing History Shift Register with the same latency as the data which is being scaled. 3.C HSRO Data Capture and Readout For each Channel, the following HSRO data is captured: Partial And-Or Fired State for the Triggered, Triggered - 1, Triggered + 1, and Triggered + 2 ticks. The latency (delay from Triggered tick to the Capture Monitor/HSRO Data signals) is programmable by TCC (within a limited range, currently the FPGA supports latencies between 3 and 7 ticks). Note that these 16 bits of data fill a single 16-bit HSRO data word. 3.D Monitor Data Capture and Readout For each Channel, the following Monitoring data is captured: Partial And-Or Fired State (the same state information captured for HSRO) Partial And-Or Fired Scaler The Monitor Data Capture and Readout is done in the normal fashion, such that the state and scaler information captured on all cards comes from the same tick. Programming Interface --------------------- The AONM FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W H-Term(15:0), Channel(3:0) Programming information 17 R/W H-Term(31:16), Channel(3:0) Programming information 18 R/W H-Term(47:32), Channel(3:0) Programming information 19 R/W H-Term(63:48), Channel(3:0) Programming information 20 R/W H-Term(79:64), Channel(3:0) Programming information 21 R/W H-Term(95:80), Channel(3:0) Programming information 22 R/W H-Term(111:96), Channel(3:0) Programming information 23 R/W H-Term(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord 48 R/W P-Term(15:0), Channel(3:0) Programming information 49 R/W P-Term(31:16), Channel(3:0) Programming information 50 R/W P-Term(47:32), Channel(3:0) Programming information NOTE: H-Term = Hardware And-Or Input Term, relative to card base H-Term The bit allocation in each of these registers is: Chip Control Status Register LSW Register Address = 0 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Lookup Program Enable ('1': enable programming of lookup memories '0': lock programming of lookup memories) 15:4 --- not allocated The Chip Status Register MSW is currently unused Register Address = 1 Enable Timing Signal Reset Register Address = 2 Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 15:4 R/W not allocated Force Scaler Reset Register Address = 3 Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 15:4 R/W not allocated Lookup Programming Address Register Register Address = 8 Bit Access Contents --- ------ -------- 0 R/W AOIT 4*n + 0 Lookup Programming Address 1 R/W AOIT 4*n + 1 Lookup Programming Address 2 R/W AOIT 4*n + 2 Lookup Programming Address 3 R/W AOIT 4*n + 3 Lookup Programming Address 15:4 R/W not allocated H-Term (or P-Term) Programming Information Register Address = 16:23 (example for H-Term(15:0), Channel(3:0) shown): Bit Access Contents --- ------ -------- 0 R/W H-Term(3:0) Channel(0) Stage 1 Partial And-Or Fired 1 R/W H-Term(3:0) Channel(1) Stage 1 Partial And-Or Fired 2 R/W H-Term(3:0) Channel(2) Stage 1 Partial And-Or Fired 3 R/W H-Term(3:0) Channel(3) Stage 1 Partial And-Or Fired 4 R/W H-Term(7:4) Channel(0) Stage 1 Partial And-Or Fired 5 R/W H-Term(7:4) Channel(1) Stage 1 Partial And-Or Fired 6 R/W H-Term(7:4) Channel(2) Stage 1 Partial And-Or Fired 7 R/W H-Term(7:4) Channel(3) Stage 1 Partial And-Or Fired 8 R/W H-Term(11:8) Channel(0) Stage 1 Partial And-Or Fired 9 R/W H-Term(11:8) Channel(1) Stage 1 Partial And-Or Fired 10 R/W H-Term(11:8) Channel(2) Stage 1 Partial And-Or Fired 11 R/W H-Term(11:8) Channel(3) Stage 1 Partial And-Or Fired 12 R/W H-Term(15:12) Channel(0) Stage 1 Partial And-Or Fired 13 R/W H-Term(15:12) Channel(1) Stage 1 Partial And-Or Fired 14 R/W H-Term(15:12) Channel(2) Stage 1 Partial And-Or Fired 15 R/W H-Term(15:12) Channel(3) Stage 1 Partial And-Or Fired Note that the VME Address specifies which 16x1 SRAMs are to be programmed (or read back), and the VME Data specifies the data written (or read). The individual address within the SRAM is specified using the Lookup Programming Address Control register. A full programming (or readback) cycle of the AONM FPGA requires 16 accesses to each of the 11 Programming Information Register Addresses, for a total of 176 accesses, plus the additional accesses needed to vary the SRAM Address Control Register. The data written during each programming access should be the desired Stage 1 Partial And-Or Fired for the Terms stored in the SRAM Programming Address Register. As an example, consider H-Term(3:0) for all 4 Channels on this card. If the desired programming is: Channel And-Or Input Term Number 3 2 1 0 -------- -------------------------------------------- 0 REQ TRUE REQ TRUE REQ TRUE REQ TRUE 1 REQ FALSE REQ FALSE REQ FALSE REQ FALSE 2 IGNORE IGNORE IGNORE INGORE 3 REQ TRUE REQ FALSE IGNORE REQ TRUE Then the 4 LSB's of the data written to the AOIT(3:0) Programming Information address of this card, while varying the SRAM Programming Address Register as shown below, must be: Lookup Prog VME Data(3:0) Add Reg (binary) -------- ------------- 0000 0110 0001 0100 0010 0100 0011 0100 0100 0100 0101 0100 0110 0100 0111 0100 1000 0100 1001 1100 1010 0100 1011 1100 1100 0100 1101 0100 1110 0100 1111 0101 Note that, if all Terms for a given Channel (Specific Trigger) on a card are IGNORED, the corresponding Partial And-Or Fired output will be set HIGH always. HSRO State Register Address = 24 Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Register Address = 25 Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Register Address = 32 Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Monitor Readout copy of HSRO States Register Address = 36 Bit Access Contents --- ------ -------- 0 R Channel 0 Output: Triggered Tick - 1 1 R Channel 1 Output: Triggered Tick - 1 2 R Channel 2 Output: Triggered Tick - 1 3 R Channel 3 Output: Triggered Tick - 1 4 R Channel 0 Output: Triggered Tick 5 R Channel 1 Output: Triggered Tick 6 R Channel 2 Output: Triggered Tick 7 R Channel 3 Output: Triggered Tick 8 R Channel 0 Output: Triggered Tick + 1 9 R Channel 1 Output: Triggered Tick + 1 10 R Channel 2 Output: Triggered Tick + 1 11 R Channel 3 Output: Triggered Tick + 1 12 R Channel 0 Output: Triggered Tick + 2 13 R Channel 1 Output: Triggered Tick + 2 14 R Channel 2 Output: Triggered Tick + 2 15 R Channel 3 Output: Triggered Tick + 2