Description of the L1 Hardware Qualifiers ------------------------------------------- Original Rev. 30-JAN-2002 Current Rev. 21-NOV-2003 The following part of this write up is from 31-JAN-2002. The L1_Qualifiers are outputs from the FOM++ card. Once set of FOM++ outputs carries both the L1_Qualifiers and the L3_Tranfer_Number. During most ticks these outputs present L1_Qualifiers. Only when the Trigger Framework is issuing an L2_Decision do these outputs present the L3_Transfer_Number data. There are two types of L1 Qualifiers the "Standard" type and the "Hardware" type. A Standard L1_Qualifier is asserted for a given event if any one of a defined subset of the 128 L1 Specific Triggers fired for that event. The "defined subset" of L1 Specific Triggers for each of the 12 Standard L1_Qualifiers is setup by COOR at the COOR to Trig FW trigger download time, i.e. their meaning is dynamic and can be moved by COOR to fit the user's requirements. A Hardware L1_Qualifier is asserted for a given event if its electrical control input signal is asserted when the FOM++ card is processing data for that event.. These control inputs are hard wired so they can not be moved about by COOR. The FOM++ can actually source 2 sets of 16 L1_Qualifiers but for now both of these sets are always programmed in exactly the same way so it is better to think of this as 2 copies of one set of 16 Li_Qualifiers. The following table lists the 16 L1_Qualifiers, which type each one is, which FOM++ FPGA site generates each copy of it, and what MSA_Output signals these are on. Level 1 Qualifier Type Generated by Output On ------------------- ------ ------------ --------- L1_Qual_0 is the "Standard" type \ L1_Qual_1 is the "Standard" type | FPGA #1 MSA_Output(3:0) L1_Qual_2 is the "Standard" type | FPGA #5 MSA_Output(19:16) L1_Qual_3 is the "Hardware" type / L1_Qual_4 is the "Standard" type \ L1_Qual_5 is the "Standard" type | FPGA #2 MSA_Output(7:4) L1_Qual_6 is the "Standard" type | FPGA #6 MSA_Output(23:20) L1_Qual_7 is the "Hardware" type / L1_Qual_8 is the "Standard" type \ L1_Qual_9 is the "Standard" type | FPGA #3 MSA_Output(11:8) L1_Qual_10 is the "Standard" type | FPGA #7 MSA_Output(27:24) L1_Qual_11 is the "Hardware" type / L1_Qual_12 is the "Standard" type \ L1_Qual_13 is the "Standard" type | FPGA #4 MSA_Output(15:12) L1_Qual_14 is the "Standard" type | FPGA #8 MSA_Output(31:28) L1_Qual_15 is the "Hardware" type / We currently have 2 of the 4 Hardware type L1_Qualifiers defined. These are: L1_Qual_3 is "Hardware" type and is controlled by the "OR" of the outputs of the 128 MFP_Counters (one associated with each L1 Specific Trigger). L1_Qual_7 is "Hardware" type and is controlled by a signal that indicates whether or not the Trigger Framework captured Monitoring data when the L1_accept for this event was issued. L1_Qual_11 is "Hardware" type and is currently not connected L1_Qual_15 is "Hardware" type and is currently not connected Description of the Signal Path for L1_Qualifier #3 the Mark and Force Pass Qualifier This L1_Qualifier is asserted if for this L1_Accept any one of the L1 Triggers that fired also had it 24 bit Mark and Force Pass Counter reach Terminal Count on this event. The signal path starts on the TDM card in one of the TDM Main Array FPGA's. Each one of the TDM Main Array FPGA's handles one L1 Specific Trigger. The TDM Main Array FPGA contains the 24 bit MFP Counter. This counter is enabled by the Specific Trigger Fired signal and clocked by the BX Clock. The terminal count output from the MFP Counter is ANDed with the Specific Trigger Fired signal and this forms the "MP_Flag" output on pin 31 from a TDM main array FPGA. Each main array site FPGA on the TDM has its pin 31 connected to a different one of the TDM pcb "Board Global IO" lines. These 16 "Board Global IO" lines (15:0) all arrive at the TDM BSF site on pins in the range 65:82. In the TDM BSF FPGA the Board Global IO lines run through pad buffers that can be enabled for either input or output. For this application the input buffers would need to be enabled. BG_IO(15:0) are then ORed and presented to a pad driver that can send a signal to P5_IO_16. For this application, this pad driver needs to be enabled which also sets the direction and enables the P5 17th pair ECL transceiver. This gets the TDM_MFP signal off the TDM card for these 16 Specific Triggers. This TDM card's MFP signal is routed in front panel cable to the FOM++ module's front panel P5 connector the 1st through 8th pin pairs, i.e. P5_IO(7:0). In the FOM++ BSF it needs to have its first 8 P5 IO lines setup as inputs. This will bring P5_IO(7:0), i.e. the MFP signals from the 8 TDM modules, into the BSF logic. Here P5_IO(7:0) are ORed and this forms the signal called FOMPP_Hardware_L1_Qual(0). This signal comes out of the BSF FPGA on its pin 4. Now add to this description of the FOM++ BSF processing of the other 3 Hardware Qualifiers. The 2nd Hardware Qualifier, L1_Qualifier_7, comes in to P5_IO_8 loops through the FOM++ BSF FPGA and comes back out on pin 238. The 3rd Hardware Qualifier, L1_Qualifier_11, comes in to P5_IO_9 loops through the FOM++ BSF FPGA and comes back out on pin 237. The 4th Hardware Qualifier, L1_Qualifier_15, comes in to P5_IO_10 loops through the FOM++ BSF FPGA and comes back out on pin 236. Summary of the FOM++ BSF's L1_Qualifier outputs FOMPP_Hardware_L1_Qual_PAD(0) is on Pin 4 which runs to via J26 FOMPP_Hardware_L1_Qual_PAD(1) is on Pin 238 whcih runs to via J27 FOMPP_Hardware_L1_Qual_PAD(2) is on Pin 237 which runs to via J28 FOMPP_Hardware_L1_Qual_PAD(3) is on Pin 236 which runs to via J29 From these vias at the output of the FOM++ BSF the 4 Hardware Qualifiers need to run down to the FOM++ Main Array FPGA's. There are no traces for this so it is done in wire wrap wire. These wires are described in www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/the_card/ the_card_customization.txt www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/aonm/ special_functions_fom.txt The Hardware Qualifier signals run to via RA8 which connects to Pin 157. on the FOM++ Main Array. Once inside the FOM++ Main Array FPGA this signal becomes HW_L1_Qual_PAD. A multiplexer allows one to select either HW_L1_Qual_PAD or a Standard FOM signal as the 4th (out of 4) L1_Qualifiers that are sourced by this FOM++ Main Array FPGA. The output of this first multiplexer goes to another multiplexer which selects either L1_Qualifier or L3_Tran_Num to be the actual output. This second multiplexer is controlled by the Send_L2_Decision control signal. (((((((((((((((((((((((((((((((((((()))))))))))))))))))))))))))))))))))) The following is additional information was added in November 2003 when the modifications were done to actually implement the first two Hardware Input L1 Qualifiers. Understanding this mapping of these signals involved: Find MFP_Counters in the TDM FPGA schematic and find the logical name of the output signal that comes from this logic. Use this logical name and the TDM ucf file to find the physical pin number. Use the schematic of the TDM printed circuit board to trace this signal to a physical pin on the TDM BSF. Use the TDM BSF ucf file to get a logical name for this signal. Trace this through the logic in the TDM's BSF FPGA schematic and find the logical name of the output signal. Back to the TDM BSF ucf file to get a physical pin number for this signal. Back to the schematic of the TDM printed circuit board and trace this signal to a pin pair on the front panel P5 I/O driver. Use cabling document to get this signal to the FOM++ front panel P5 connector. Use the schematic of the AONM printed circuit board to trace this signal to a FOM++ BSF physical pin. Use the FOM++ BSF ucf file to get a logical name. Trace this signal through the logic in the FOM++ BSF and find the logical name of its output. Back to the FOM++ BSF ucf file to get a physical pin number. Back to the schematic of the AONM printed circuit board to trace this signal to a physical pin in the FOM++ main array FPGA's. Use the FOM++ ucf file to get a logical name for this signal. Use the FOM++ FPGA schematic to find where in the 4 bits of L1_Qualifier - L3_Transfer_Number this signal gets muxed. Which Hardware Input L1_Qualifier is which ? This is from reading the 8-MAY-2003 version of Jim's list. For L1_Qualifiers numbered 0:15 we need: L2_Unbiased_Sample to be L1_Qualifier #3 Collect_Status to be L1_Qualifier #7 Not used "Hardware Input L1 Qualifiers" are #11 and #15. On the TDM Cards everything should be all set. From each TDM Mains Signal Array FPGA comes the MFP signal for one Specific Trigger. These signals come out of the TDM Main Array FPGA on pin #31 and are carried to the BSF FPGA on the Board_Global_IO lines - a separate line for each Main Array FPGA. In the BSF FPGA these 16 Board_Global_IO signals (15:0) are "ORed" and buffered and then sent out the P5_IO_16 (note, not 15 but 16). TDM Main Array FPGA site #1 MFP signal is connected to the BSF via Board_Global_IO(0) TDM Main Array FPGA site #16 MFP signal is connected to the BSF via Board_Global_IO(15) I do not know what connects to the BSF Board_Global_IO(16) input. This is pin #84 on the BSF FPGA. Modifications to the FOM++ Start by fully understanding: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/aonm/ special_functions_fom.txt FPGA Front Site Generates these Paddle MSA_Output Signals Numb MSA_Outputs Conn. Function and Destination ---- ----------------- ------ ---------------------------------- 1 MSA_Output(3:0) \ J 15:0 are the Multiplexed output 2 MSA_Output(7:4) | 15 of the L1 Qualifier Set 0 3 MSA_Output(11:8) | :0 and L3 Transfer Number. This 4 MSA_Output(15:12) / goes to the SCL Hub End. 5 MSA_Output(19:16) \ J 31:16 are the Multiplexed output 6 MSA_Output(23:20) | 31 of the L1 Qualifier Set 1 7 MSA_Output(27:24) | :16 and L3 Transfer Number. This 8 MSA_Output(31:28) / goes to the SCL Hub-End. FOM++ P5 Global I/O Signals The Hardware Source L1 Qualifiers are received on this FOM card via the P5 Global I/O connector. P5 Signal Signal - Function - Source --------- ---------------------------------------------------------- P5(7:0) These pins are used to receive a Mark_&_Force_Pass signal from each of the 8 TDM cards. These 8 Signals are "ORed" before they become the Harware_Source_L1_Qualifier signal that goes to FPGA sites #1 and # 5. In these FPGA's this "ORed" signal can be selected as L1_Qualifier #3. These FPGA site's make L1_Qualifiers 3:0 P5-8 This pin is used to receive the Hardware_Source_L1_Qualifier that goes to FPGA sites #2 and #6 where it can be selected as L1_Qualifier #7. These FPGA sites make L1_Qualifiers 7:4. Via's to pins on the FOM++ Main Array sites on the FOM++ (AONM) Card In the FOM++ Main Array FPGA the hardware qualifier input signal is called HW_L1_Qual_PAD. This signal is mux'ed with PAOF(3) to become L1_Qual(3). In the ucf file HW_L1_Qual_PAD is located on pin #157. On the AONM circuit board, pin #157 at each Main Array FPGA site is connected to a near by WRAP33 via. At FPGA site #1 the via is J10100. At FPGA site #2 the via is J10200. At all FPGA sites this is the via between the silk screen labels "RA8" and "VIA". Via's to pins on the BSF FPGA on the FOM++ (AONM) Card The "OR" of P5_IO(7:0) comes out of the BSF FPGA on Pin #4. On the pcb this is routed to via J26 which is directly adjacent to BSF FPGA pin #4 P5_IO(8) comes out of the BSF FPGA on Pin #238. On the pcb this is routed to via J27 which is directly adjacent to BSF FPGA pin #240. In the row of 3 via's adjacent to pin #240 it is the closest via to the FPGA. P5_IO(9) comes out of the BSF FPGA on Pin #237. On the pcb this is routed to via J28 which is adjacent to BSF FPGA pin #240. This via is the middle one in the row of 3 via's adjacent to pin #240. P5_IO(10) comes out of the BSF FPGA on Pin #236. On the pcb this is routed to via J29 which is adjacent to BSF FPGA pin #240. In the row of 3 via's adjacent to pin #240 it is the furthest via to the FPGA. Jumper Wires on the FOM++ (AONM) Card L2_Unbiased_Sample (aka Mark and Force Pass) needs to be L1_Qualifier #3 (and #19) This siganl comes from via J26 which connects to pin #4 of the BSF FPGA and must we wired to the via connected to pin #157 on Main Array FPGA's #1 and #5. Collect Status needs to be L1_Qualifier #7 (and #23) This siganl comes from via J27 which connects to pin #238 of the BSF FPGA and must we wired to the via connected to pin #157 on Main Array FPGA's #2 and #6. Spare Hardware Input Qualifier needs to be L1_Qualifier #11 (and #27) This siganl comes from via J28 which connects to pin #237 of the BSF FPGA and must we wired to the via connected to pin #157 on Main Array FPGA's #3 and #7. Spare Hardware Input Qualifier needs to be L1_Qualifier #15 (and #31) This siganl comes from via J29 which connects to pin #236 of the BSF FPGA and must we wired to the via connected to pin #157 on Main Array FPGA's #4 and #8. Collect Status Signal Source I think that the source of the Capture Monitor Data Armed signal is Connector #15 on the timing signal distribution box in the back of M122 pins #15 & #16 for CMD_Armed_Signal_0 pins #17 & #18 for CMD_Armed_Signal_1 See: www.pa.msu.edu/hep/d0/ftp/l1/framework/timing/ timing_signal_generation_distribution.txt in about the middle of the file. Most of this work is covered in the 6:7-Nov-2003 log book entry.