***************************** * * * D-Zero Run II Upgrade * * * * Level 2 Trigger Framework * * * * L2 And-Or Network Module * * * * FPGA Description * * * ***************************** Original: 5-APR-2000 Latest: 5-APR-2000 Introduction ------------ The L2 And-Or FPGA is used in all MSA FPGA locations on the And-Or Network Module cards. Each And-Or FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 128 Input Terms (these are Main Signal Array (MSA) Input Signals). 3. 4 Output Terms (these are MSA Output Signals). Operation --------- The L2 And-Or FPGA is used to convert the L2 Answers from the L2 Global Processor into L2 Accept and L2 Reject signals per Specific Trigger. It is based on the L1 And-Or FPGA Design. The L2 And-Or FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Four Separate Processing Channels, each consisting of: A. Programmable "AND" processing of H-Terms and P-Terms B. 32-bit Scaler C. HSRO Data Capture and Readout D. Monitor Data Capture and Readout Each element is described below: 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 3. Four Separate Processing Channels All four Processing Channels on this FPGA are identical, and are composed of the following elements: A. Programmable "AND" processing B. 32-bit Scaler C. Monitor Data Capture and Readout A single Processing Channel services a single Specific Trigger. 3.A Programmable "AND" Processing The And-Or Requirements for a given Channel can be thought of as two arrays of boolean flags: (1) INCLUDE (Hardware And-Or Input Term "H-Term") (128 bits) If this flag is true, the H-Term is INCLUDED in the logic for this Channel If this flag is false, the H-Term is IGNORED for this Channel. (2) VETO (Hardware And-Or Input Term "H-Term") (128 bits) This flag is only meaningful if the H-Term is INCLUDED for this Channel. If this flag is false, the H-Term is required to be HIGH. If this flag is true, the H-Term is required to be LOW (i.e. this H-Term acts as a VETO for this channel). Note that in L2 applications, the VETO functionality of the AONM is not used. Conceptually, then, the logic works as follows: .-----. H-Term 0 -----| | .-----. | XOR |-----| | .-------. VETO HT 0 ----| | | OR |---| | `-----' .-o| | | | | `-----' | | INCLUDE HT 0 ----------' | 128- | . | input | . | AND |--- Channel AO Fired . | | .-----. | | H-Term 127 ---| | .-----. | | | XOR |-----| | | | VETO HT 127 --| | | OR |---| | `-----' .-o| | | | | `-----' | | INCLUDE HT 127 --------' | | | | `-------' Physically implementing the logic in this fashion is prohibitively expensive in CLB terms, however. Instead, for the H-Terms, the INCLUDE and VETO flags are encoded as the data stored in 16x1 dual-port SRAM's within the FPGA's. Each group of 4 H-Terms serves as the "read" address of the SRAM's, while the "write" address of the SRAM's comes from a special programming register. The "read" data of the SRAM's go to a tree of AND gates, while the "write" data of the SRAM's comes from TCC. Note that each 16x1 dual-port SRAM occupies a single CLB, thus the flag storage and processing logic for FOUR H-Terms or P-Terms fits in a single CLB. The physical implementation of the logic (write address and write data omitted for clarity) is shown below: .-----------. |A 16 D| H-Term ---/---|D x1 A|---/--- (3:0) 4 |D SRAM T| 1 |R A| `-----------' . . (32 such blocks) . .-----------. |A 16 D| H-Term ---/---|D x1 A|---/--- (127:124) 4 |D SRAM T| 1 |R A| `-----------' The 32 output signals are then ANDed together. Note that each of the 128 H-Terms must be fed in parallel to 4 16x1 dual-port SRAM's (one per Channel). 3.B 32-bit Scaler For each Channel, the And-Or Fired acts as the gate of a 32-bit Scaler. The clock of this Scaler is the Tick Clock. The synchronous reset for each Scaler is controlled by an individual reset signal. The Scaler Reset can come from a High-Quality Timing Signal or from a VME-visible register. The High-Quality Timing Signal reset must be enabled by TCC, but the register reset can be used to force a scaler reset at any time. The And-Or Fired signal is qualified by a HQ_Timing signal (HQ_TS(2)) which is active for only one tick in each L2 Cycle. In this way the scaler increments at most once for each L2 Cycle. 3.C HSRO Data Capture and Readout For each Channel, the following HSRO data is captured: And-Or Fired State for the Current L2 Cycle and the 3 Previous L2 Cycles The And-Or Fired signals pass through a L2 Cycle History Shift Register, which shifts only once per L2 Cycle. The latency of this shift register is programmable, but must be set to "0" for proper functionality. Note that these 16 bits of data fill a single 16-bit HSRO data word. Note additionally that the HSRO Data Readout is not currently planned to be used in the L2 Framework. 3.D Monitor Data Capture and Readout For each Channel, the following Monitoring data is captured: Partial And-Or Fired State (the same state information captured for HSRO) Partial And-Or Fired Scaler The Monitor Data Capture and Readout is done in the normal fashion, such that the state and scaler information captured on all cards comes from the same tick. Programming Interface --------------------- The AONM FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W H-Term(15:0), Channel(3:0) Programming information 17 R/W H-Term(31:16), Channel(3:0) Programming information 18 R/W H-Term(47:32), Channel(3:0) Programming information 19 R/W H-Term(63:48), Channel(3:0) Programming information 20 R/W H-Term(79:64), Channel(3:0) Programming information 21 R/W H-Term(95:80), Channel(3:0) Programming information 22 R/W H-Term(111:96), Channel(3:0) Programming information 23 R/W H-Term(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord NOTE: H-Term = Hardware And-Or Input Term, relative to card base H-Term The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Lookup Program Enable ('1': enable programming of lookup memories '0': lock programming of lookup memories) 15:4 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 15:4 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 15:4 R/W not allocated Lookup Programming Address Register Bit Access Contents --- ------ -------- 0 R/W AOIT 4*n + 0 Lookup Programming Address 1 R/W AOIT 4*n + 1 Lookup Programming Address 2 R/W AOIT 4*n + 2 Lookup Programming Address 3 R/W AOIT 4*n + 3 Lookup Programming Address 15:4 R/W not allocated H-Term Programming Information (example for H-Term(15:0), Channel(3:0) shown): Bit Access Contents --- ------ -------- 0 R/W H-Term(3:0) Channel(0) Stage 1 Partial And-Or Fired 1 R/W H-Term(3:0) Channel(1) Stage 1 Partial And-Or Fired 2 R/W H-Term(3:0) Channel(2) Stage 1 Partial And-Or Fired 3 R/W H-Term(3:0) Channel(3) Stage 1 Partial And-Or Fired 4 R/W H-Term(7:4) Channel(0) Stage 1 Partial And-Or Fired 5 R/W H-Term(7:4) Channel(1) Stage 1 Partial And-Or Fired 6 R/W H-Term(7:4) Channel(2) Stage 1 Partial And-Or Fired 7 R/W H-Term(7:4), Channel(3) Stage 1 Partial And-Or Fired 8 R/W H-Term(11:8), Channel(0) Stage 1 Partial And-Or Fired 9 R/W H-Term(11:8), Channel(1) Stage 1 Partial And-Or Fired 10 R/W H-Term(11:8), Channel(2) Stage 1 Partial And-Or Fired 11 R/W H-Term(11:8), Channel(3) Stage 1 Partial And-Or Fired 12 R/W H-Term(15:12), Channel(0) Stage 1 Partial And-Or Fired 13 R/W H-Term(15:12), Channel(1) Stage 1 Partial And-Or Fired 14 R/W H-Term(15:12), Channel(2) Stage 1 Partial And-Or Fired 15 R/W H-Term(15:12), Channel(3) Stage 1 Partial And-Or Fired Note that the VME Address specifies which 16x1 SRAMs are to be programmed (or read back), and the VME Data specifies the data written (or read). The individual address within the SRAM is specified using the Lookup Address Control register. Thus, a full programming (readback) cycle of the AONM FPGA requires 16 accesses to each of the 11 Programming Information Register Addresses, for a total of 176 accesses, plus an additional 16 accesses to vary the SRAM Address Control Register. The data written during each programming access should be the desired Stage 1 Partial And-Or Fired for the Terms stored in the SRAM Programming Address Register. As an example, consider H-Term(3:0) for all 4 Channels on this card. If the desired programming is: Channel And-Or Input Term Number 3 2 1 0 -------- -------------------------------------------- 0 REQ TRUE REQ TRUE REQ TRUE REQ TRUE 1 REQ FALSE REQ FALSE REQ FALSE REQ FALSE 2 IGNORE IGNORE IGNORE INGORE 3 REQ TRUE REQ FALSE IGNORE REQ TRUE Then the 4 LSB's of the data written to the AOIT(3:0) Programming Information address of this card, while varying the SRAM Programming Address Register as shown below, must be: Lookup Prog VME Data(3:0) Add Reg (binary) -------- ------------- 0000 0110 0001 0100 0010 0100 0011 0100 0100 0100 0101 0100 0110 0100 0111 0100 1000 0100 1001 1100 1010 0100 1011 1100 1100 0100 1101 0100 1110 0100 1111 0101 Note that, if all Terms for a given Channel (Specific Trigger) on a card are IGNORED, the corresponding Partial And-Or Fired output will be set HIGH always. HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR (note: must be programmed to 0) 15:3 R/W unallocated Monitor Readout copy of HSRO States Bit Access Contents --- ------ -------- 0 R Channel 0 Output: NT NT Previous L2 Cycle 1 R Channel 1 Output: NT NT Previous L2 Cycle 2 R Channel 2 Output: NT NT Previous L2 Cycle 3 R Channel 3 Output: NT NT Previous L2 Cycle 4 R Channel 0 Output: Next to Previous L2 Cycle 5 R Channel 1 Output: Next to Previous L2 Cycle 6 R Channel 2 Output: Next to Previous L2 Cycle 7 R Channel 3 Output: Next to Previous L2 Cycle 8 R Channel 0 Output: Previous L2 Cycle 9 R Channel 1 Output: Previous L2 Cycle 10 R Channel 2 Output: Previous L2 Cycle 11 R Channel 3 Output: Previous L2 Cycle 12 R Channel 0 Output: Current L2 Cycle 13 R Channel 1 Output: Current L2 Cycle 14 R Channel 2 Output: Current L2 Cycle 15 R Channel 3 Output: Current L2 Cycle