***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * Framework Output Module * * * * FPGA Description * * * ***************************** Original: 1-DEC-1995 Latest: 6-APR-2000 Introduction ------------ The L2_FOM FPGA is a copy of the L2_AONM FPGA with the AND logic replaced by OR logic. The programming interface is the same but is repeated here for convenience. Programming Interface --------------------- The L2_FOM FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W ST(15:0), Channel(3:0) Programming information 17 R/W ST(31:16), Channel(3:0) Programming information 18 R/W ST(47:32), Channel(3:0) Programming information 19 R/W ST(63:48), Channel(3:0) Programming information 20 R/W ST(79:64), Channel(3:0) Programming information 21 R/W ST(95:80), Channel(3:0) Programming information 22 R/W ST(111:96), Channel(3:0) Programming information 23 R/W ST(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Lookup Program Enable ('1': enable programming of lookup memories '0': lock programming of lookup memories) 15:4 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 15:4 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 15:4 R/W not allocated Lookup Programming Address Register Bit Access Contents --- ------ -------- 0 R/W ST 4*n + 0 Lookup Programming Address 1 R/W ST 4*n + 1 Lookup Programming Address 2 R/W ST 4*n + 2 Lookup Programming Address 3 R/W ST 4*n + 3 Lookup Programming Address 15:4 R/W not allocated HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR (note: must be programmed to 0) 15:3 R/W unallocated Monitor Readout copy of HSRO States Bit Access Contents --- ------ -------- 0 R Channel 0 Output: NT NT Previous L2 Cycle 1 R Channel 1 Output: NT NT Previous L2 Cycle 2 R Channel 2 Output: NT NT Previous L2 Cycle 3 R Channel 3 Output: NT NT Previous L2 Cycle 4 R Channel 0 Output: Next to Previous L2 Cycle 5 R Channel 1 Output: Next to Previous L2 Cycle 6 R Channel 2 Output: Next to Previous L2 Cycle 7 R Channel 3 Output: Next to Previous L2 Cycle 8 R Channel 0 Output: Previous L2 Cycle 9 R Channel 1 Output: Previous L2 Cycle 10 R Channel 2 Output: Previous L2 Cycle 11 R Channel 3 Output: Previous L2 Cycle 12 R Channel 0 Output: Current L2 Cycle 13 R Channel 1 Output: Current L2 Cycle 14 R Channel 2 Output: Current L2 Cycle 15 R Channel 3 Output: Current L2 Cycle