***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * L2 Busy Answer Delay * * * * FPGA Description * * * ***************************** Original: 30-NOV-1999 Latest: 4-MAY-2000 Introduction ------------ The L2 Busy Answer Delay (L2Bad) FPGA can be used on either And-Or Network Module (AONM) cards or on Framework Output Module (FOM) cards. Each L2Bad FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 64 L2 Accept Signals (on P2) 3. 64 L2 Busy Signals (on P3) 4. 4 Copies of the Global L2 Busy Delay Signal Operation --------- The L2Bad is used to check whether or not there is a L2 Accept for a geographic section which is currently busy. The output is a global OR of these Individual L2 Busy Delays. The L2Bad FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Busy Check 3. Monitor Data Capture and Readout A. States B. Scalers Each element is described below: 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. Busy Check Each of the 64 L2 Busy signals can be independently enabled, disabled, or forced high. These signals are then ANDed with the corresponding L2 Accepts to produce 64 Individual L2 Busy Delays. These 64 Busy Delays are ORed to produce the Global L2 Busy Delay that is then fanned out to all 4 outputs. For testing, the Global L2 Busy Delay output can also be forced high. Note that this programming must be repeated on all 16 MSA FPGA's on each of the 2 L2BAD cards, otherwise the scalers (described below) will not be correct. 3. Monitor Data Capture and Readout This FPGA provides a normal Monitor Data Capture and Readout mechanism for its input states, output states, and a number of scalers. This FPGA does not include a History Shift Register, therefore only information from the current L2 Cycle is available for Monitor Readout. 3.A States All 128 inputs and the Global L2 Busy Delay outputs are available for readout via TCC. Note that the L2 Busy states captured are AFTER the gating logic described above in section 2. L2 Busy inputs which are forced high or low will reflect that in the captured state data. The same is true for the L2 Delay output. 3.B Scalers Each L2BAD FPGA includes 3 separate scalers for each of 4 Geographic Sections. TCC must program a mux in each L2BAD FPGA to select which 4 Geographic Sections are serviced by these scalers. By using all 16 MSA FPGA's on both L2BAD cards, all 128 Geographic Sections are serviced by L2BAD scalers. Each scaler can be reset via the normal scaler reset mechanisms. The scalers determine the following quantities: - "Raw" L2 Busy input rate This scaler increments once during each 132 ns tick for which the Geographic Section is holding its L2 Busy input high. This scaler is BEFORE the gating logic described above in section 2, allowing us to examine the L2 Busy rates of Geo Sections which are not currently participating in the L2 Trigger processing. To determine a percentage rate from this scaler, divide by the L2 Beam Crossing scaler (in the L2 Helper). - L2 Busy AND L2 Accept Clock Time This scaler is intended to show how much "clock time" is consumed by each individual Geographic Section contributing to delaying the L2 Answer. The gate to this scaler is: L2_Busy AND L2_Accept AND Currently_Waiting The L2_Busy input here is AFTER the gating described above in section 2. The Currently_Waiting input comes from the L2 Helper FPGA and is distributed on P1 Timing Signal 9. In the L2BAD FPGA, this is mapped to Capture HSRO Data in the standard OCB_Interface library component. As the L2 Framework does not use HSRO, this is acceptable. This scaler increments once per 132 ns tick while the gate is high. To determine a percentage rate from this scaler, divide by the L2 Busy Delay Beam Crossing Scaler (in the L2 Helper). - L2 Busy AND L2 Accept L2 Cycles This scaler is intended to show how many L2 Cycles were affected by each individual Geographic Section contributing to delaying the L2 Answer. The gate to this scaler is: L2_Busy AND L2_Accept AND First_Tick_Waiting The L2_Busy input here is AFTER the gating described above in section 2. First_Tick_Waiting is derived from the Currently_Waiting input by logic in the L2BAD FPGA. It is active for only the FIRST 132 ns of the Currently_Waiting envelope. This scaler thus increments only once for each L2 Cycle which was delayed by this Geographic Section. Programming Interface --------------------- The L2Bad FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W L2 Busy(15:0) Control (LSW) 9 R/W L2 Busy(15:0) Control (MSW) 10 R Monitor Data: L2 Accept(15:0) 11 R Monitor Data: L2 Busy(15:0) 12 R/W L2 Busy(31:16) Control (LSW) 13 R/W L2 Busy(31:16) Control (MSW) 14 R Monitor Data: L2 Accept(31:16) 15 R Monitor Data: L2 Busy(31:16) 16 R/W L2 Busy(47:32) Control (LSW) 17 R/W L2 Busy(47:32) Control (MSW) 18 R Monitor Data: L2 Accept(47:32) 19 R Monitor Data: L2 Busy(47:32) 20 R/W L2 Busy(63:48) Control (LSW) 21 R/W L2 Busy(63:48) Control (MSW) 22 R Monitor Data: L2 Accept(63:48) 23 R Monitor Data: L2 Busy(63:48) 24 R Monitor Data: Output 26 R/W Force Output 129:128 R Geo Sect 0 Raw L2 Busy Scaler MSW:LSW 131:130 R Geo Sect 1 Raw L2 Busy Scaler MSW:LSW 133:132 R Geo Sect 2 Raw L2 Busy Scaler MSW:LSW 135:134 R Geo Sect 3 Raw L2 Busy Scaler MSW:LSW 137:136 R Geo Sect 0 L2 Delay Clock Time Scaler MSW:LSW 139:138 R Geo Sect 1 L2 Delay Clock Time Scaler MSW:LSW 141:140 R Geo Sect 2 L2 Delay Clock Time Scaler MSW:LSW 143:142 R Geo Sect 3 L2 Delay Clock Time Scaler MSW:LSW 145:144 R Geo Sect 0 L2 Delay L2 Cycles Scaler MSW:LSW 157:146 R Geo Sect 1 L2 Delay L2 Cycles Scaler MSW:LSW 159:148 R Geo Sect 2 L2 Delay L2 Cycles Scaler MSW:LSW 151:150 R Geo Sect 3 L2 Delay L2 Cycles Scaler MSW:LSW 152 R/W Scaler Geo Section Range Select Mux The bit allocation in each of these registers is given below. Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 15:3 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable TS Reset for GS 0 Raw L2 Busy Scaler 1 R/W Enable TS Reset for GS 1 Raw L2 Busy Scaler 2 R/W Enable TS Reset for GS 2 Raw L2 Busy Scaler 3 R/W Enable TS Reset for GS 3 Raw L2 Busy Scaler 4 R/W Enable TS Reset for GS 0 L2 Delay Clock Time Scaler 5 R/W Enable TS Reset for GS 1 L2 Delay Clock Time Scaler 6 R/W Enable TS Reset for GS 2 L2 Delay Clock Time Scaler 7 R/W Enable TS Reset for GS 3 L2 Delay Clock Time Scaler 8 R/W Enable TS Reset for GS 0 L2 Delay L2 Cycles Scaler 9 R/W Enable TS Reset for GS 1 L2 Delay L2 Cycles Scaler 10 R/W Enable TS Reset for GS 2 L2 Delay L2 Cycles Scaler 11 R/W Enable TS Reset for GS 3 L2 Delay L2 Cycles Scaler 15:12 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for GS 0 Raw L2 Busy Scaler 1 R/W Force Reset for GS 1 Raw L2 Busy Scaler 2 R/W Force Reset for GS 2 Raw L2 Busy Scaler 3 R/W Force Reset for GS 3 Raw L2 Busy Scaler 4 R/W Force Reset for GS 0 L2 Delay Clock Time Scaler 5 R/W Force Reset for GS 1 L2 Delay Clock Time Scaler 6 R/W Force Reset for GS 2 L2 Delay Clock Time Scaler 7 R/W Force Reset for GS 3 L2 Delay Clock Time Scaler 8 R/W Force Reset for GS 0 L2 Delay L2 Cycles Scaler 9 R/W Force Reset for GS 1 L2 Delay L2 Cycles Scaler 10 R/W Force Reset for GS 2 L2 Delay L2 Cycles Scaler 11 R/W Force Reset for GS 3 L2 Delay L2 Cycles Scaler 15:12 R/W not allocated L2 Busy Control (LSW) Bit Access Contents --- ------ -------- 1:0 R/W Enable, Disable, Force FEBZ(0+n*16) High (0: Disable 1: Enable 2: Force FEBZ(0+n*16) High) 3:2 R/W Enable, Disable, Force FEBZ(1+n*16) High (0: Disable 1: Enable 2: Force FEBZ(1+n*16) High) 5:4 R/W Enable, Disable, Force FEBZ(2+n*16) High (0: Disable 1: Enable 2: Force FEBZ(2+n*16) High) 7:6 R/W Enable, Disable, Force FEBZ(3+n*16) High (0: Disable 1: Enable 2: Force FEBZ(3+n*16) High) 9:8 R/W Enable, Disable, Force FEBZ(4+n*16) High (0: Disable 1: Enable 2: Force FEBZ(4+n*16) High) 11:10 R/W Enable, Disable, Force FEBZ(5+n*16) High (0: Disable 1: Enable 2: Force FEBZ(5+n*16) High) 13:12 R/W Enable, Disable, Force FEBZ(6+n*16) High (0: Disable 1: Enable 2: Force FEBZ(6+n*16) High) 15:14 R/W Enable, Disable, Force FEBZ(7+n*16) High (0: Disable 1: Enable 2: Force FEBZ(7+n*16) High) L2 Busy Control (MSW) Bit Access Contents --- ------ -------- 1:0 R/W Enable, Disable, Force FEBZ(8+n*16) High (0: Disable 1: Enable 2: Force FEBZ(8+n*16) High) 3:2 R/W Enable, Disable, Force FEBZ(9+n*16) High (0: Disable 1: Enable 2: Force FEBZ(9+n*16) High) 5:4 R/W Enable, Disable, Force FEBZ(10+n*16) High (0: Disable 1: Enable 2: Force FEBZ(10+n*16) High) 7:6 R/W Enable, Disable, Force FEBZ(11+n*16) High (0: Disable 1: Enable 2: Force FEBZ(11+n*16) High) 9:8 R/W Enable, Disable, Force FEBZ(12+n*16) High (0: Disable 1: Enable 2: Force FEBZ(12+n*16) High) 11:10 R/W Enable, Disable, Force FEBZ(13+n*16) High (0: Disable 1: Enable 2: Force FEBZ(13+n*16) High) 13:12 R/W Enable, Disable, Force FEBZ(14+n*16) High (0: Disable 1: Enable 2: Force FEBZ(14+n*16) High) 15:14 R/W Enable, Disable, Force FEBZ(15+n*16) High (0: Disable 1: Enable 2: Force FEBZ(15+n*16) High) Monitor Data: Output Bit Access Contents --- ------ -------- 0 R Global L2 Busy Delay Output (NOTE: this is after the force high/low described below) 1 R Global L2 Busy Delay Internal (NOTE: this is before the force high/low described below) 15:2 not allocated Monitor Data: L2 Accept/L2 Busy Bit Access Contents --- ------ -------- 15:0 R L2 Accept/L2 Busy 16*n+15:16*n:0 ('0': corresponding input not asserted '1': corresponding input is asserted NOTE: for the L2 Busy inputs, this is BEFORE the gating described above) Force Output Bit Access Contents --- ------ -------- 0 R/W Force Output (0: Do not force output 1: Force output high) 15:1 R/W not allocated Scaler Geo Section Range Select Mux Bit Access Contents --- ------ -------- 3:0 R/W Scaler Geo Section Range Select ('0000': Select Geo Sect 64*n + 3 : 64*n + 0 '0001': Select Geo Sect 64*n + 7 : 64*n + 4 '0010': Select Geo Sect 64*n + 11 : 64*n + 8 '0011': Select Geo Sect 64*n + 15 : 64*n + 12 '0100': Select Geo Sect 64*n + 19 : 64*n + 16 '0101': Select Geo Sect 64*n + 23 : 64*n + 20 '0110': Select Geo Sect 64*n + 27 : 64*n + 24 '0111': Select Geo Sect 64*n + 31 : 64*n + 28 '1000': Select Geo Sect 64*n + 35 : 64*n + 32 '1001': Select Geo Sect 64*n + 39 : 64*n + 36 '1010': Select Geo Sect 64*n + 43 : 64*n + 40 '1011': Select Geo Sect 64*n + 47 : 64*n + 44 '1100': Select Geo Sect 64*n + 51 : 64*n + 48 '1101': Select Geo Sect 64*n + 55 : 64*n + 52 '1110': Select Geo Sect 64*n + 59 : 64*n + 56 '1111': Select Geo Sect 64*n + 63 : 64*n + 60)