***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * Miguel Module * * * * FPGA Description * * * ***************************** Original: 23-APR-1998 Latest: 12-OCT-2000 Introduction ------------ The Miguel FPGA can be used on either And-Or Network Module (AONM) cards or on Framework Output Module (FOM) cards. Each Miguel FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 128 Input Terms (these are Main Signal Array (MSA) Input Signals). Operation --------- The Miguel FPGA is used to read out 32 of the 128 Input Terms for the triggered tick and for 3 additional ticks which are contiguous with the triggered tick. The Miguel FPGA is composed of the following elements: 1. On-Card Bus Interface 2. High-Speed Readout Interface 3. Input Term Multiplexer 4. Readout Data Source, consisting of A. Beam Crossing History Shift Register B. High-Speed Data Capture and Readout C. Monitor Data Capture and Readout Each element is described below: 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. High-Speed Readout Interface This is the standard High-Speed Readout (HSRO) Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 3. Input Term Multiplexer The Input Term Multiplexer is controlled via TCC and selects which subset of 32 Input Terms will be read out. 4. Readout Data Source The Readout Data Source includes A. Beam Crossing History Shift Register B. High-Speed Data Capture and Readout C. Monitor Data Capture and Readout 4.A Beam Crossing History Shift Register The basic principle of the Beam Crossing History Shift Register (BXHSR) is to hold the information, in this case the Input Terms, to be readout from the time it arrives until the readout signal arrives. The Input Terms are fed to a 32 bit wide shift register which is clocked by the BX Clock. At the moment, the BXHSR in the Miguel is the standard BXHSR from the FPGA library. 4.B High-Speed Data Capture and Readout The selected 32 Input Terms are captured for high-speed readout in the usual fashion. Note that the oldest data is the first to be readout. (The HSRO data has the same format as the Monitor data - see Programming Interface below.) 4.C Monitor Data Capture and Readout As for the high-speed readout, 32 Input Terms are captured for monitor readout. The Monitor Data Capture and Readout is done in the normal fashion. Programming Interface --------------------- The Miguel FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 16 R/W Input Term Selection 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Shift Register Latency 33 R Monitor Data: Previous-2 Tick Input Term (15:0) 34 R Monitor Data: Previous-2 Tick Input Term (31:16) 35 R Monitor Data: Previous-1 Tick Input Term (15:0) 36 R Monitor Data: Previous-1 Tick Input Term (31:16) 37 R Monitor Data: Previous Tick Input Term (15:0) 38 R Monitor Data: Previous Tick Input Term (31:16) 39 R Monitor Data: Triggered Tick Input Term (15:0) 40 R Monitor Data: Triggered Tick Input Term (31:16) The bit allocation in each of these registers is given below. The Chip Control Status Register is currently unused. Input Term Selection Bit Access Contents --- ------ -------- 1:0 R/W Select Input Term Subset (S0 and S1) (0: select terms 31:0 1: select terms 63:32 2: select terms 95:64 3: select terms 127:96) 15:2 R/W unallocated HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Shift Register Latency Bit Access Contents --- ------ -------- 2:0 R/W Select BXHSR Latency (values 0 to 7 are allowed) 15:3 R/W unused